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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.07 99.33 95.61 100.00 98.40 99.51 47.58


Total test records in report: 426
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T133 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.980992091 Aug 25 02:16:04 AM UTC 24 Aug 25 02:35:24 AM UTC 24 501847942487 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.2288470929 Aug 25 02:17:20 AM UTC 24 Aug 25 02:17:22 AM UTC 24 490105466 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.366259667 Aug 25 02:17:20 AM UTC 24 Aug 25 02:17:22 AM UTC 24 487652761 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2680186368 Aug 25 02:17:20 AM UTC 24 Aug 25 02:17:22 AM UTC 24 491217918 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.1968739723 Aug 25 02:17:20 AM UTC 24 Aug 25 02:17:24 AM UTC 24 456914061 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.3325237389 Aug 25 02:17:23 AM UTC 24 Aug 25 02:17:25 AM UTC 24 518485578 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.474823993 Aug 25 02:17:22 AM UTC 24 Aug 25 02:17:26 AM UTC 24 1038999025 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2469149705 Aug 25 02:17:23 AM UTC 24 Aug 25 02:17:26 AM UTC 24 465252148 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2796677723 Aug 25 02:17:23 AM UTC 24 Aug 25 02:17:26 AM UTC 24 1324842645 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1628269815 Aug 25 02:17:23 AM UTC 24 Aug 25 02:17:28 AM UTC 24 647726110 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.1629052765 Aug 25 02:17:26 AM UTC 24 Aug 25 02:17:29 AM UTC 24 482483300 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1675178281 Aug 25 02:17:26 AM UTC 24 Aug 25 02:17:29 AM UTC 24 323378853 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2711856757 Aug 25 02:17:24 AM UTC 24 Aug 25 02:17:29 AM UTC 24 477423813 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.893935416 Aug 25 02:17:26 AM UTC 24 Aug 25 02:17:29 AM UTC 24 390087521 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1192060173 Aug 25 02:17:27 AM UTC 24 Aug 25 02:17:30 AM UTC 24 1234545477 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.2816266523 Aug 25 02:17:29 AM UTC 24 Aug 25 02:17:32 AM UTC 24 547409713 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2041069120 Aug 25 02:17:30 AM UTC 24 Aug 25 02:17:32 AM UTC 24 470423437 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.3258573975 Aug 25 02:17:43 AM UTC 24 Aug 25 02:17:48 AM UTC 24 577976016 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3951583642 Aug 25 02:17:26 AM UTC 24 Aug 25 02:17:33 AM UTC 24 4835222281 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.3141497159 Aug 25 02:17:31 AM UTC 24 Aug 25 02:17:33 AM UTC 24 516828054 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.257705355 Aug 25 02:17:30 AM UTC 24 Aug 25 02:17:33 AM UTC 24 458467804 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4117554006 Aug 25 02:17:31 AM UTC 24 Aug 25 02:17:33 AM UTC 24 786118023 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4111518784 Aug 25 02:17:31 AM UTC 24 Aug 25 02:17:33 AM UTC 24 368714335 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.1078908496 Aug 25 02:17:31 AM UTC 24 Aug 25 02:17:33 AM UTC 24 473464903 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4234815055 Aug 25 02:17:30 AM UTC 24 Aug 25 02:17:34 AM UTC 24 640888730 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.2407602827 Aug 25 02:17:32 AM UTC 24 Aug 25 02:17:35 AM UTC 24 499737150 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.132249460 Aug 25 02:17:34 AM UTC 24 Aug 25 02:17:36 AM UTC 24 560799271 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1617620403 Aug 25 02:17:30 AM UTC 24 Aug 25 02:17:37 AM UTC 24 2557935337 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.292565638 Aug 25 02:17:34 AM UTC 24 Aug 25 02:17:37 AM UTC 24 607708619 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.1105973122 Aug 25 02:17:34 AM UTC 24 Aug 25 02:17:37 AM UTC 24 318715881 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2777952893 Aug 25 02:17:35 AM UTC 24 Aug 25 02:17:37 AM UTC 24 447501893 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3749837456 Aug 25 02:17:35 AM UTC 24 Aug 25 02:17:37 AM UTC 24 272268864 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.765766974 Aug 25 02:17:35 AM UTC 24 Aug 25 02:17:37 AM UTC 24 852671551 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.2888152140 Aug 25 02:17:35 AM UTC 24 Aug 25 02:17:38 AM UTC 24 517438085 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2029227242 Aug 25 02:17:35 AM UTC 24 Aug 25 02:17:38 AM UTC 24 3936847764 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2508999905 Aug 25 02:17:36 AM UTC 24 Aug 25 02:17:38 AM UTC 24 737342114 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.970555531 Aug 25 02:17:30 AM UTC 24 Aug 25 02:17:39 AM UTC 24 8183528970 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.1244828872 Aug 25 02:17:36 AM UTC 24 Aug 25 02:17:39 AM UTC 24 438839246 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1222598289 Aug 25 02:17:37 AM UTC 24 Aug 25 02:17:40 AM UTC 24 430659651 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2539859728 Aug 25 02:17:38 AM UTC 24 Aug 25 02:17:40 AM UTC 24 386707492 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.1177461197 Aug 25 02:17:38 AM UTC 24 Aug 25 02:17:40 AM UTC 24 529955897 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.3550279309 Aug 25 02:17:38 AM UTC 24 Aug 25 02:17:40 AM UTC 24 530710123 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2871877486 Aug 25 02:17:34 AM UTC 24 Aug 25 02:17:41 AM UTC 24 1145450550 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.392123743 Aug 25 02:17:39 AM UTC 24 Aug 25 02:17:41 AM UTC 24 453299323 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.4067609281 Aug 25 02:17:38 AM UTC 24 Aug 25 02:17:41 AM UTC 24 307977751 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.2536712950 Aug 25 02:17:37 AM UTC 24 Aug 25 02:17:42 AM UTC 24 496855946 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1752270908 Aug 25 02:17:38 AM UTC 24 Aug 25 02:17:42 AM UTC 24 670238076 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.546580333 Aug 25 02:17:40 AM UTC 24 Aug 25 02:17:42 AM UTC 24 496426239 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2011107924 Aug 25 02:17:30 AM UTC 24 Aug 25 02:17:42 AM UTC 24 13143759971 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3305386721 Aug 25 02:17:33 AM UTC 24 Aug 25 02:17:43 AM UTC 24 7423579538 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.2176324405 Aug 25 02:17:40 AM UTC 24 Aug 25 02:17:43 AM UTC 24 643841269 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.120747070 Aug 25 02:17:41 AM UTC 24 Aug 25 02:17:43 AM UTC 24 582210694 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.888301026 Aug 25 02:17:41 AM UTC 24 Aug 25 02:17:43 AM UTC 24 477251533 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.1412885310 Aug 25 02:17:42 AM UTC 24 Aug 25 02:17:44 AM UTC 24 343938115 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.484158105 Aug 25 02:17:41 AM UTC 24 Aug 25 02:17:44 AM UTC 24 1978710604 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.1540248279 Aug 25 02:17:42 AM UTC 24 Aug 25 02:17:44 AM UTC 24 500759790 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.2504732773 Aug 25 02:17:41 AM UTC 24 Aug 25 02:17:44 AM UTC 24 511161328 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2347976736 Aug 25 02:17:41 AM UTC 24 Aug 25 02:17:45 AM UTC 24 4254584784 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.1863648523 Aug 25 02:17:41 AM UTC 24 Aug 25 02:17:45 AM UTC 24 446110654 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.2905083279 Aug 25 02:17:43 AM UTC 24 Aug 25 02:17:46 AM UTC 24 283198706 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.194127485 Aug 25 02:17:42 AM UTC 24 Aug 25 02:17:46 AM UTC 24 497374186 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.733058065 Aug 25 02:17:44 AM UTC 24 Aug 25 02:17:47 AM UTC 24 409695860 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.3962581909 Aug 25 02:17:43 AM UTC 24 Aug 25 02:17:47 AM UTC 24 535016529 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3923599239 Aug 25 02:17:40 AM UTC 24 Aug 25 02:17:47 AM UTC 24 7945302892 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1815226957 Aug 25 02:17:40 AM UTC 24 Aug 25 02:17:47 AM UTC 24 2195372965 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3304869179 Aug 25 02:17:20 AM UTC 24 Aug 25 02:17:48 AM UTC 24 7727876712 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.3475309264 Aug 25 02:17:46 AM UTC 24 Aug 25 02:17:48 AM UTC 24 464083559 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2759040197 Aug 25 02:17:45 AM UTC 24 Aug 25 02:17:48 AM UTC 24 311874843 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.367373271 Aug 25 02:17:42 AM UTC 24 Aug 25 02:17:48 AM UTC 24 1229147326 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.4000669196 Aug 25 02:17:46 AM UTC 24 Aug 25 02:17:48 AM UTC 24 490446238 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.2506323605 Aug 25 02:17:44 AM UTC 24 Aug 25 02:17:48 AM UTC 24 526022933 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.262288479 Aug 25 02:17:46 AM UTC 24 Aug 25 02:17:48 AM UTC 24 445564929 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4097462098 Aug 25 02:17:37 AM UTC 24 Aug 25 02:17:48 AM UTC 24 2271678497 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3061711366 Aug 25 02:17:44 AM UTC 24 Aug 25 02:17:48 AM UTC 24 1900530390 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.189272555 Aug 25 02:17:45 AM UTC 24 Aug 25 02:17:49 AM UTC 24 485149508 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.1440702876 Aug 25 02:17:45 AM UTC 24 Aug 25 02:17:49 AM UTC 24 462313081 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.1990925288 Aug 25 02:17:47 AM UTC 24 Aug 25 02:17:49 AM UTC 24 433790321 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.1410769448 Aug 25 02:17:47 AM UTC 24 Aug 25 02:17:49 AM UTC 24 428100340 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2426385098 Aug 25 02:17:43 AM UTC 24 Aug 25 02:17:49 AM UTC 24 4569133526 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2765995517 Aug 25 02:17:39 AM UTC 24 Aug 25 02:17:49 AM UTC 24 10546623459 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.2008867863 Aug 25 02:17:45 AM UTC 24 Aug 25 02:17:49 AM UTC 24 975780999 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3959083839 Aug 25 02:17:37 AM UTC 24 Aug 25 02:17:49 AM UTC 24 4543939768 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.644004950 Aug 25 02:17:23 AM UTC 24 Aug 25 02:17:50 AM UTC 24 12715148270 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.1780243912 Aug 25 02:17:48 AM UTC 24 Aug 25 02:17:50 AM UTC 24 490438695 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1541560624 Aug 25 02:17:47 AM UTC 24 Aug 25 02:17:50 AM UTC 24 326794763 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3991531968 Aug 25 02:17:48 AM UTC 24 Aug 25 02:17:50 AM UTC 24 523225881 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.2555911838 Aug 25 02:17:48 AM UTC 24 Aug 25 02:17:50 AM UTC 24 416781547 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3754089927 Aug 25 02:17:45 AM UTC 24 Aug 25 02:17:51 AM UTC 24 4807203997 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.4269959346 Aug 25 02:17:48 AM UTC 24 Aug 25 02:17:51 AM UTC 24 610039575 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3627056932 Aug 25 02:17:47 AM UTC 24 Aug 25 02:17:51 AM UTC 24 4122968133 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3813400447 Aug 25 02:17:48 AM UTC 24 Aug 25 02:17:51 AM UTC 24 2302866876 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3373376877 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:01 AM UTC 24 391247828 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.2547602657 Aug 25 02:17:49 AM UTC 24 Aug 25 02:17:51 AM UTC 24 549518920 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.335435270 Aug 25 02:17:50 AM UTC 24 Aug 25 02:17:52 AM UTC 24 303028013 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2721010523 Aug 25 02:17:49 AM UTC 24 Aug 25 02:17:52 AM UTC 24 612144994 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4027897695 Aug 25 02:17:46 AM UTC 24 Aug 25 02:17:52 AM UTC 24 2499507900 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2330457156 Aug 25 02:17:49 AM UTC 24 Aug 25 02:17:52 AM UTC 24 298205195 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3022064521 Aug 25 02:17:45 AM UTC 24 Aug 25 02:17:53 AM UTC 24 1474295674 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3919992343 Aug 25 02:17:50 AM UTC 24 Aug 25 02:17:53 AM UTC 24 417289692 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2835398935 Aug 25 02:17:51 AM UTC 24 Aug 25 02:17:53 AM UTC 24 531273422 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.2766685892 Aug 25 02:17:49 AM UTC 24 Aug 25 02:17:53 AM UTC 24 507258701 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.4212813078 Aug 25 02:17:51 AM UTC 24 Aug 25 02:17:53 AM UTC 24 306226797 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.898136502 Aug 25 02:17:50 AM UTC 24 Aug 25 02:17:53 AM UTC 24 491592317 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3379235127 Aug 25 02:17:50 AM UTC 24 Aug 25 02:17:54 AM UTC 24 369001639 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2052075879 Aug 25 02:17:51 AM UTC 24 Aug 25 02:17:54 AM UTC 24 422995130 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2657328982 Aug 25 02:17:48 AM UTC 24 Aug 25 02:17:54 AM UTC 24 4257845939 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.2652495050 Aug 25 02:17:52 AM UTC 24 Aug 25 02:17:54 AM UTC 24 306613452 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1992168861 Aug 25 02:17:49 AM UTC 24 Aug 25 02:17:55 AM UTC 24 4308199929 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1542619245 Aug 25 02:17:51 AM UTC 24 Aug 25 02:17:55 AM UTC 24 505632003 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.910167169 Aug 25 02:17:52 AM UTC 24 Aug 25 02:17:55 AM UTC 24 508974930 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.3189088991 Aug 25 02:17:52 AM UTC 24 Aug 25 02:17:55 AM UTC 24 395181011 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4070866112 Aug 25 02:17:45 AM UTC 24 Aug 25 02:17:55 AM UTC 24 8066100986 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.2272895259 Aug 25 02:17:53 AM UTC 24 Aug 25 02:17:55 AM UTC 24 352097263 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.419143715 Aug 25 02:17:51 AM UTC 24 Aug 25 02:17:55 AM UTC 24 386504934 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3826237688 Aug 25 02:17:52 AM UTC 24 Aug 25 02:17:55 AM UTC 24 323851716 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1411202253 Aug 25 02:17:49 AM UTC 24 Aug 25 02:17:56 AM UTC 24 1325567891 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4207040590 Aug 25 02:17:50 AM UTC 24 Aug 25 02:17:56 AM UTC 24 4348664217 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.112576681 Aug 25 02:17:54 AM UTC 24 Aug 25 02:17:56 AM UTC 24 434106902 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.185314003 Aug 25 02:17:54 AM UTC 24 Aug 25 02:17:56 AM UTC 24 439044065 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.493990303 Aug 25 02:17:51 AM UTC 24 Aug 25 02:17:56 AM UTC 24 761150466 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.648737122 Aug 25 02:17:54 AM UTC 24 Aug 25 02:17:57 AM UTC 24 2070253148 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2711409284 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:01 AM UTC 24 292172155 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4221283784 Aug 25 02:17:52 AM UTC 24 Aug 25 02:17:57 AM UTC 24 1665694184 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.2468737401 Aug 25 02:17:54 AM UTC 24 Aug 25 02:17:57 AM UTC 24 407106480 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.2115174950 Aug 25 02:17:55 AM UTC 24 Aug 25 02:17:57 AM UTC 24 296031035 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.2902479525 Aug 25 02:17:52 AM UTC 24 Aug 25 02:17:57 AM UTC 24 493524553 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.547317778 Aug 25 02:17:54 AM UTC 24 Aug 25 02:17:57 AM UTC 24 418116684 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.1853763699 Aug 25 02:17:55 AM UTC 24 Aug 25 02:17:57 AM UTC 24 452208115 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1339924567 Aug 25 02:17:54 AM UTC 24 Aug 25 02:17:58 AM UTC 24 584050159 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.1468945353 Aug 25 02:17:54 AM UTC 24 Aug 25 02:17:58 AM UTC 24 292054216 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1432704962 Aug 25 02:17:56 AM UTC 24 Aug 25 02:17:58 AM UTC 24 531689974 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.713940795 Aug 25 02:17:55 AM UTC 24 Aug 25 02:17:58 AM UTC 24 541672544 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3997954752 Aug 25 02:17:54 AM UTC 24 Aug 25 02:17:58 AM UTC 24 2812541158 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.3963804524 Aug 25 02:17:55 AM UTC 24 Aug 25 02:17:58 AM UTC 24 405942830 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.3148285147 Aug 25 02:17:56 AM UTC 24 Aug 25 02:17:58 AM UTC 24 310308152 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.719042394 Aug 25 02:17:51 AM UTC 24 Aug 25 02:17:58 AM UTC 24 1837183275 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.505733956 Aug 25 02:17:51 AM UTC 24 Aug 25 02:17:59 AM UTC 24 8474755947 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.802200348 Aug 25 02:17:57 AM UTC 24 Aug 25 02:17:59 AM UTC 24 526378979 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.561281085 Aug 25 02:17:57 AM UTC 24 Aug 25 02:17:59 AM UTC 24 514710371 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.2555904172 Aug 25 02:17:55 AM UTC 24 Aug 25 02:17:59 AM UTC 24 511660255 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.2964861000 Aug 25 02:17:57 AM UTC 24 Aug 25 02:17:59 AM UTC 24 460241757 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3544077057 Aug 25 02:17:56 AM UTC 24 Aug 25 02:17:59 AM UTC 24 1296717086 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.3439553467 Aug 25 02:17:57 AM UTC 24 Aug 25 02:17:59 AM UTC 24 420151937 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.851078926 Aug 25 02:17:55 AM UTC 24 Aug 25 02:17:59 AM UTC 24 460549989 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.2443393647 Aug 25 02:17:57 AM UTC 24 Aug 25 02:17:59 AM UTC 24 508774911 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1520828534 Aug 25 02:17:49 AM UTC 24 Aug 25 02:17:59 AM UTC 24 1439750826 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.3925323238 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:00 AM UTC 24 298739399 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1328418742 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:00 AM UTC 24 478827350 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.2412093469 Aug 25 02:17:57 AM UTC 24 Aug 25 02:18:00 AM UTC 24 503183735 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3324000867 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:00 AM UTC 24 448884394 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.3337501032 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:01 AM UTC 24 547133499 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.801258819 Aug 25 02:17:51 AM UTC 24 Aug 25 02:18:01 AM UTC 24 3960942179 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2649097921 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:01 AM UTC 24 487145163 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.1892575631 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:01 AM UTC 24 268613915 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.3492504593 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:01 AM UTC 24 399588111 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.419545557 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:01 AM UTC 24 500012937 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.3649473266 Aug 25 02:17:58 AM UTC 24 Aug 25 02:18:01 AM UTC 24 377801146 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.961823325 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:02 AM UTC 24 415676544 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4213626655 Aug 25 02:17:51 AM UTC 24 Aug 25 02:18:02 AM UTC 24 2558258591 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.809090754 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:02 AM UTC 24 348100274 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2212275447 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:02 AM UTC 24 427448290 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.1550020210 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:02 AM UTC 24 568716030 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.3582451321 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:02 AM UTC 24 384650643 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.1227453854 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:02 AM UTC 24 517401115 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.4239712957 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:02 AM UTC 24 490928576 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.1697313715 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:02 AM UTC 24 518907639 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2180316056 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:02 AM UTC 24 294089212 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1213372834 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:03 AM UTC 24 425907509 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.1999621409 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:03 AM UTC 24 461976255 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.3418399682 Aug 25 02:18:00 AM UTC 24 Aug 25 02:18:03 AM UTC 24 491817279 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4193235291 Aug 25 02:17:54 AM UTC 24 Aug 25 02:18:04 AM UTC 24 8034449711 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4103622434 Aug 25 02:17:55 AM UTC 24 Aug 25 02:18:06 AM UTC 24 8382421810 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3516258441 Aug 25 02:17:52 AM UTC 24 Aug 25 02:18:07 AM UTC 24 8070405562 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3253766764 Aug 25 02:17:55 AM UTC 24 Aug 25 02:18:08 AM UTC 24 2379483417 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2066268797 Aug 25 02:17:55 AM UTC 24 Aug 25 02:18:20 AM UTC 24 7952427230 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3847400641 Aug 25 02:17:36 AM UTC 24 Aug 25 02:18:25 AM UTC 24 9209407987 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.1657776805
Short name T3
Test name
Test status
Simulation time 575587078 ps
CPU time 1.25 seconds
Started Aug 25 02:15:03 AM UTC 24
Finished Aug 25 02:15:06 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657776805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1657776805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.121616668
Short name T11
Test name
Test status
Simulation time 1482837354 ps
CPU time 12.33 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:12 AM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=121616668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.aon_timer_stress_all_with_rand_reset.121616668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.619429608
Short name T43
Test name
Test status
Simulation time 9450216628 ps
CPU time 29.62 seconds
Started Aug 25 02:15:13 AM UTC 24
Finished Aug 25 02:15:45 AM UTC 24
Peak memory 215536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=619429608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.aon_timer_stress_all_with_rand_reset.619429608
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1628269815
Short name T50
Test name
Test status
Simulation time 647726110 ps
CPU time 3.53 seconds
Started Aug 25 02:17:23 AM UTC 24
Finished Aug 25 02:17:28 AM UTC 24
Peak memory 203332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628269815 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.1628269815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.2642977758
Short name T92
Test name
Test status
Simulation time 15968978417 ps
CPU time 47.79 seconds
Started Aug 25 02:16:30 AM UTC 24
Finished Aug 25 02:17:19 AM UTC 24
Peak memory 215388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2642977758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 34.aon_timer_stress_all_with_rand_reset.2642977758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.1734874495
Short name T24
Test name
Test status
Simulation time 8079065562 ps
CPU time 7.39 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:25 AM UTC 24
Peak memory 231292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734874495 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1734874495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.4281517981
Short name T110
Test name
Test status
Simulation time 52332899297 ps
CPU time 95.61 seconds
Started Aug 25 02:15:36 AM UTC 24
Finished Aug 25 02:17:14 AM UTC 24
Peak memory 200912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281517981 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.4281517981
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.1980128604
Short name T91
Test name
Test status
Simulation time 16320986281 ps
CPU time 41.91 seconds
Started Aug 25 02:15:12 AM UTC 24
Finished Aug 25 02:15:58 AM UTC 24
Peak memory 211912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1980128604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 7.aon_timer_stress_all_with_rand_reset.1980128604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.1812896197
Short name T96
Test name
Test status
Simulation time 4006234624 ps
CPU time 41.02 seconds
Started Aug 25 02:16:36 AM UTC 24
Finished Aug 25 02:17:19 AM UTC 24
Peak memory 214980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1812896197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 35.aon_timer_stress_all_with_rand_reset.1812896197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.1527435447
Short name T47
Test name
Test status
Simulation time 12987045183 ps
CPU time 33.74 seconds
Started Aug 25 02:15:19 AM UTC 24
Finished Aug 25 02:15:55 AM UTC 24
Peak memory 215424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1527435447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.aon_timer_stress_all_with_rand_reset.1527435447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.1533716089
Short name T93
Test name
Test status
Simulation time 10536404271 ps
CPU time 46.19 seconds
Started Aug 25 02:16:01 AM UTC 24
Finished Aug 25 02:16:49 AM UTC 24
Peak memory 214744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1533716089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 25.aon_timer_stress_all_with_rand_reset.1533716089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.3353252356
Short name T129
Test name
Test status
Simulation time 11867949490 ps
CPU time 62.61 seconds
Started Aug 25 02:15:25 AM UTC 24
Finished Aug 25 02:16:29 AM UTC 24
Peak memory 215592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3353252356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 12.aon_timer_stress_all_with_rand_reset.3353252356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.578849975
Short name T102
Test name
Test status
Simulation time 67177505906 ps
CPU time 88.64 seconds
Started Aug 25 02:15:56 AM UTC 24
Finished Aug 25 02:17:26 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578849975 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.578849975
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/22.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.3287736044
Short name T104
Test name
Test status
Simulation time 266467617459 ps
CPU time 133.18 seconds
Started Aug 25 02:16:46 AM UTC 24
Finished Aug 25 02:19:01 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287736044 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.3287736044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/38.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.4262944467
Short name T114
Test name
Test status
Simulation time 182864912431 ps
CPU time 232.13 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:19:12 AM UTC 24
Peak memory 200760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262944467 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.4262944467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.2041748382
Short name T88
Test name
Test status
Simulation time 17964555588 ps
CPU time 71.94 seconds
Started Aug 25 02:17:18 AM UTC 24
Finished Aug 25 02:18:32 AM UTC 24
Peak memory 212096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2041748382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 49.aon_timer_stress_all_with_rand_reset.2041748382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.2582677280
Short name T151
Test name
Test status
Simulation time 27723273145 ps
CPU time 60.72 seconds
Started Aug 25 02:16:40 AM UTC 24
Finished Aug 25 02:17:42 AM UTC 24
Peak memory 221108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2582677280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 36.aon_timer_stress_all_with_rand_reset.2582677280
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.2365165821
Short name T136
Test name
Test status
Simulation time 4382458827 ps
CPU time 45.97 seconds
Started Aug 25 02:16:42 AM UTC 24
Finished Aug 25 02:17:30 AM UTC 24
Peak memory 201104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2365165821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 37.aon_timer_stress_all_with_rand_reset.2365165821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.2096694752
Short name T95
Test name
Test status
Simulation time 6423249275 ps
CPU time 47.62 seconds
Started Aug 25 02:15:52 AM UTC 24
Finished Aug 25 02:16:41 AM UTC 24
Peak memory 206744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2096694752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 21.aon_timer_stress_all_with_rand_reset.2096694752
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.1982419559
Short name T98
Test name
Test status
Simulation time 526551380600 ps
CPU time 279.51 seconds
Started Aug 25 02:15:20 AM UTC 24
Finished Aug 25 02:20:03 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982419559 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.1982419559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.1999120245
Short name T121
Test name
Test status
Simulation time 196331224692 ps
CPU time 126.89 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:17:18 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999120245 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.1999120245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.1147352058
Short name T116
Test name
Test status
Simulation time 149344434953 ps
CPU time 172.13 seconds
Started Aug 25 02:16:41 AM UTC 24
Finished Aug 25 02:19:36 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147352058 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.1147352058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/36.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.1247969613
Short name T119
Test name
Test status
Simulation time 69751409964 ps
CPU time 96.4 seconds
Started Aug 25 02:15:18 AM UTC 24
Finished Aug 25 02:16:57 AM UTC 24
Peak memory 200824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247969613 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.1247969613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.2347313133
Short name T145
Test name
Test status
Simulation time 200719601031 ps
CPU time 132.13 seconds
Started Aug 25 02:15:53 AM UTC 24
Finished Aug 25 02:18:08 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347313133 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.2347313133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/21.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.1671308441
Short name T137
Test name
Test status
Simulation time 6412894263 ps
CPU time 66.28 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:16:24 AM UTC 24
Peak memory 206744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1671308441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.aon_timer_stress_all_with_rand_reset.1671308441
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.307407097
Short name T101
Test name
Test status
Simulation time 7460590801 ps
CPU time 46.49 seconds
Started Aug 25 02:16:00 AM UTC 24
Finished Aug 25 02:16:48 AM UTC 24
Peak memory 214024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=307407097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 24.aon_timer_stress_all_with_rand_reset.307407097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2029227242
Short name T38
Test name
Test status
Simulation time 3936847764 ps
CPU time 2.52 seconds
Started Aug 25 02:17:35 AM UTC 24
Finished Aug 25 02:17:38 AM UTC 24
Peak memory 205432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029227242 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.2029227242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.1459859074
Short name T100
Test name
Test status
Simulation time 250705421193 ps
CPU time 502.14 seconds
Started Aug 25 02:15:58 AM UTC 24
Finished Aug 25 02:24:27 AM UTC 24
Peak memory 204144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459859074 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.1459859074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/23.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.314848813
Short name T105
Test name
Test status
Simulation time 148718863024 ps
CPU time 90.19 seconds
Started Aug 25 02:15:43 AM UTC 24
Finished Aug 25 02:17:16 AM UTC 24
Peak memory 200824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314848813 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.314848813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.1817046936
Short name T138
Test name
Test status
Simulation time 176337743076 ps
CPU time 327.59 seconds
Started Aug 25 02:15:01 AM UTC 24
Finished Aug 25 02:20:46 AM UTC 24
Peak memory 200888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817046936 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.1817046936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.3509195987
Short name T118
Test name
Test status
Simulation time 16667874611 ps
CPU time 36.61 seconds
Started Aug 25 02:17:14 AM UTC 24
Finished Aug 25 02:17:52 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509195987 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.3509195987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/47.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.31114644
Short name T21
Test name
Test status
Simulation time 53060293987 ps
CPU time 25.72 seconds
Started Aug 25 02:15:12 AM UTC 24
Finished Aug 25 02:15:42 AM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31114644 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.31114644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.836980712
Short name T77
Test name
Test status
Simulation time 4196231625 ps
CPU time 19.79 seconds
Started Aug 25 02:16:49 AM UTC 24
Finished Aug 25 02:17:10 AM UTC 24
Peak memory 215312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=836980712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.aon_timer_stress_all_with_rand_reset.836980712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.3988108031
Short name T7
Test name
Test status
Simulation time 619039370 ps
CPU time 1.14 seconds
Started Aug 25 02:15:07 AM UTC 24
Finished Aug 25 02:15:10 AM UTC 24
Peak memory 199248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988108031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3988108031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.287367927
Short name T127
Test name
Test status
Simulation time 142718803672 ps
CPU time 99 seconds
Started Aug 25 02:15:26 AM UTC 24
Finished Aug 25 02:17:11 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287367927 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.287367927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.2600245569
Short name T165
Test name
Test status
Simulation time 16641281174 ps
CPU time 61.75 seconds
Started Aug 25 02:16:08 AM UTC 24
Finished Aug 25 02:17:11 AM UTC 24
Peak memory 206708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2600245569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 28.aon_timer_stress_all_with_rand_reset.2600245569
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.3536163861
Short name T90
Test name
Test status
Simulation time 300752708371 ps
CPU time 745.33 seconds
Started Aug 25 02:16:27 AM UTC 24
Finished Aug 25 02:29:02 AM UTC 24
Peak memory 204064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536163861 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.3536163861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/33.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.960462412
Short name T128
Test name
Test status
Simulation time 114982956205 ps
CPU time 76.09 seconds
Started Aug 25 02:17:08 AM UTC 24
Finished Aug 25 02:18:26 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960462412 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.960462412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/45.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.2628284360
Short name T94
Test name
Test status
Simulation time 68556748006 ps
CPU time 81.69 seconds
Started Aug 25 02:16:05 AM UTC 24
Finished Aug 25 02:17:29 AM UTC 24
Peak memory 200892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628284360 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.2628284360
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/27.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.2409654181
Short name T117
Test name
Test status
Simulation time 10635622103 ps
CPU time 45.63 seconds
Started Aug 25 02:15:07 AM UTC 24
Finished Aug 25 02:15:56 AM UTC 24
Peak memory 217484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2409654181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 6.aon_timer_stress_all_with_rand_reset.2409654181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.859233505
Short name T41
Test name
Test status
Simulation time 6458925939 ps
CPU time 22.09 seconds
Started Aug 25 02:15:00 AM UTC 24
Finished Aug 25 02:15:41 AM UTC 24
Peak memory 215388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=859233505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 3.aon_timer_stress_all_with_rand_reset.859233505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.2821395152
Short name T112
Test name
Test status
Simulation time 6305681582 ps
CPU time 20.04 seconds
Started Aug 25 02:17:14 AM UTC 24
Finished Aug 25 02:17:35 AM UTC 24
Peak memory 205880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2821395152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 47.aon_timer_stress_all_with_rand_reset.2821395152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.2346519545
Short name T120
Test name
Test status
Simulation time 116046304091 ps
CPU time 111.78 seconds
Started Aug 25 02:17:16 AM UTC 24
Finished Aug 25 02:19:10 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346519545 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.2346519545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/48.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.2197814707
Short name T146
Test name
Test status
Simulation time 437275710 ps
CPU time 1.42 seconds
Started Aug 25 02:15:34 AM UTC 24
Finished Aug 25 02:15:37 AM UTC 24
Peak memory 199248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197814707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2197814707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.2259845270
Short name T15
Test name
Test status
Simulation time 4626096256 ps
CPU time 14.57 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:32 AM UTC 24
Peak memory 206620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2259845270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 1.aon_timer_stress_all_with_rand_reset.2259845270
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.2048697185
Short name T134
Test name
Test status
Simulation time 203157296475 ps
CPU time 235.33 seconds
Started Aug 25 02:15:33 AM UTC 24
Finished Aug 25 02:19:32 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048697185 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.2048697185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.2649754572
Short name T124
Test name
Test status
Simulation time 10076934621 ps
CPU time 37.02 seconds
Started Aug 25 02:15:34 AM UTC 24
Finished Aug 25 02:16:13 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2649754572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 16.aon_timer_stress_all_with_rand_reset.2649754572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.3009120587
Short name T131
Test name
Test status
Simulation time 43219764021 ps
CPU time 57.94 seconds
Started Aug 25 02:15:43 AM UTC 24
Finished Aug 25 02:16:43 AM UTC 24
Peak memory 221536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3009120587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 18.aon_timer_stress_all_with_rand_reset.3009120587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.462659153
Short name T149
Test name
Test status
Simulation time 8250279404 ps
CPU time 64.7 seconds
Started Aug 25 02:15:18 AM UTC 24
Finished Aug 25 02:16:25 AM UTC 24
Peak memory 206752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=462659153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 9.aon_timer_stress_all_with_rand_reset.462659153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.3171635406
Short name T135
Test name
Test status
Simulation time 63876682536 ps
CPU time 89.05 seconds
Started Aug 25 02:15:23 AM UTC 24
Finished Aug 25 02:16:55 AM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171635406 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.3171635406
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.4242481667
Short name T155
Test name
Test status
Simulation time 190236944903 ps
CPU time 185.79 seconds
Started Aug 25 02:16:42 AM UTC 24
Finished Aug 25 02:19:51 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242481667 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.4242481667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/37.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.179881031
Short name T79
Test name
Test status
Simulation time 3417606573 ps
CPU time 30.51 seconds
Started Aug 25 02:17:11 AM UTC 24
Finished Aug 25 02:17:43 AM UTC 24
Peak memory 213952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=179881031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 46.aon_timer_stress_all_with_rand_reset.179881031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.2563153839
Short name T107
Test name
Test status
Simulation time 171261019319 ps
CPU time 107.75 seconds
Started Aug 25 02:16:32 AM UTC 24
Finished Aug 25 02:18:22 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563153839 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.2563153839
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/34.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.3479048303
Short name T113
Test name
Test status
Simulation time 138563590551 ps
CPU time 312.67 seconds
Started Aug 25 02:15:46 AM UTC 24
Finished Aug 25 02:21:03 AM UTC 24
Peak memory 202064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479048303 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.3479048303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.2230968281
Short name T125
Test name
Test status
Simulation time 73640027812 ps
CPU time 38.13 seconds
Started Aug 25 02:16:00 AM UTC 24
Finished Aug 25 02:16:39 AM UTC 24
Peak memory 200892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230968281 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.2230968281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/24.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.2446947727
Short name T142
Test name
Test status
Simulation time 326861302237 ps
CPU time 297.24 seconds
Started Aug 25 02:16:01 AM UTC 24
Finished Aug 25 02:21:03 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446947727 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.2446947727
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/25.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.980992091
Short name T133
Test name
Test status
Simulation time 501847942487 ps
CPU time 1146.08 seconds
Started Aug 25 02:16:04 AM UTC 24
Finished Aug 25 02:35:24 AM UTC 24
Peak memory 204264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980992091 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.980992091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/26.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.3343530033
Short name T106
Test name
Test status
Simulation time 274301460993 ps
CPU time 129.52 seconds
Started Aug 25 02:16:14 AM UTC 24
Finished Aug 25 02:18:26 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343530033 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.3343530033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/30.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.4143458771
Short name T109
Test name
Test status
Simulation time 287337155718 ps
CPU time 141.4 seconds
Started Aug 25 02:16:37 AM UTC 24
Finished Aug 25 02:19:01 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143458771 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.4143458771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/35.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2796677723
Short name T36
Test name
Test status
Simulation time 1324842645 ps
CPU time 1.73 seconds
Started Aug 25 02:17:23 AM UTC 24
Finished Aug 25 02:17:26 AM UTC 24
Peak memory 201904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796677723 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.2796677723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.3760685049
Short name T169
Test name
Test status
Simulation time 398301145257 ps
CPU time 204.31 seconds
Started Aug 25 02:15:49 AM UTC 24
Finished Aug 25 02:19:17 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760685049 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.3760685049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/20.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.1584999354
Short name T89
Test name
Test status
Simulation time 456398221769 ps
CPU time 252.92 seconds
Started Aug 25 02:16:08 AM UTC 24
Finished Aug 25 02:20:25 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584999354 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.1584999354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/28.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.3067487288
Short name T158
Test name
Test status
Simulation time 8988775603 ps
CPU time 47.24 seconds
Started Aug 25 02:16:45 AM UTC 24
Finished Aug 25 02:17:33 AM UTC 24
Peak memory 214924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3067487288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 38.aon_timer_stress_all_with_rand_reset.3067487288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.17723017
Short name T150
Test name
Test status
Simulation time 169172452532 ps
CPU time 167.91 seconds
Started Aug 25 02:16:58 AM UTC 24
Finished Aug 25 02:19:49 AM UTC 24
Peak memory 200552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17723017 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.17723017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/42.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.417131205
Short name T75
Test name
Test status
Simulation time 9662730642 ps
CPU time 43.02 seconds
Started Aug 25 02:16:04 AM UTC 24
Finished Aug 25 02:16:49 AM UTC 24
Peak memory 215388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=417131205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.aon_timer_stress_all_with_rand_reset.417131205
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.3568675770
Short name T99
Test name
Test status
Simulation time 116333053256 ps
CPU time 88.43 seconds
Started Aug 25 02:16:18 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568675770 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.3568675770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/31.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.3152733528
Short name T123
Test name
Test status
Simulation time 19616940409 ps
CPU time 57.02 seconds
Started Aug 25 02:16:18 AM UTC 24
Finished Aug 25 02:17:16 AM UTC 24
Peak memory 215428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3152733528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 31.aon_timer_stress_all_with_rand_reset.3152733528
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.1519982819
Short name T156
Test name
Test status
Simulation time 7983204787 ps
CPU time 27.04 seconds
Started Aug 25 02:15:46 AM UTC 24
Finished Aug 25 02:16:14 AM UTC 24
Peak memory 215060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1519982819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 19.aon_timer_stress_all_with_rand_reset.1519982819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.3297868021
Short name T2
Test name
Test status
Simulation time 424495968 ps
CPU time 1.22 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:00 AM UTC 24
Peak memory 199248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297868021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3297868021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.3648871174
Short name T153
Test name
Test status
Simulation time 4029014569 ps
CPU time 25.48 seconds
Started Aug 25 02:16:11 AM UTC 24
Finished Aug 25 02:16:38 AM UTC 24
Peak memory 211912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3648871174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.aon_timer_stress_all_with_rand_reset.3648871174
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.1398886670
Short name T111
Test name
Test status
Simulation time 392141039 ps
CPU time 2.13 seconds
Started Aug 25 02:16:16 AM UTC 24
Finished Aug 25 02:16:19 AM UTC 24
Peak memory 200576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398886670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1398886670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/31.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.3355847522
Short name T122
Test name
Test status
Simulation time 663557301 ps
CPU time 1.01 seconds
Started Aug 25 02:16:25 AM UTC 24
Finished Aug 25 02:16:27 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355847522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3355847522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/33.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.1334851197
Short name T159
Test name
Test status
Simulation time 24960195367 ps
CPU time 19.91 seconds
Started Aug 25 02:17:01 AM UTC 24
Finished Aug 25 02:17:22 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334851197 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.1334851197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/43.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.2724369280
Short name T157
Test name
Test status
Simulation time 82135874582 ps
CPU time 192.22 seconds
Started Aug 25 02:15:29 AM UTC 24
Finished Aug 25 02:18:44 AM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724369280 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.2724369280
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.2873629832
Short name T97
Test name
Test status
Simulation time 86740414523 ps
CPU time 66.3 seconds
Started Aug 25 02:16:49 AM UTC 24
Finished Aug 25 02:17:57 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873629832 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.2873629832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/39.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.276540408
Short name T78
Test name
Test status
Simulation time 6602804355 ps
CPU time 18.95 seconds
Started Aug 25 02:16:52 AM UTC 24
Finished Aug 25 02:17:12 AM UTC 24
Peak memory 217556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=276540408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 40.aon_timer_stress_all_with_rand_reset.276540408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.3235818570
Short name T103
Test name
Test status
Simulation time 415418183 ps
CPU time 1.03 seconds
Started Aug 25 02:17:11 AM UTC 24
Finished Aug 25 02:17:14 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235818570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3235818570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/46.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.3954493151
Short name T152
Test name
Test status
Simulation time 189036550446 ps
CPU time 297.43 seconds
Started Aug 25 02:17:11 AM UTC 24
Finished Aug 25 02:22:13 AM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954493151 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.3954493151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/46.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.3233433140
Short name T48
Test name
Test status
Simulation time 535242085 ps
CPU time 1.3 seconds
Started Aug 25 02:15:22 AM UTC 24
Finished Aug 25 02:15:24 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233433140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3233433140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.3233334284
Short name T108
Test name
Test status
Simulation time 462106273 ps
CPU time 2.18 seconds
Started Aug 25 02:15:54 AM UTC 24
Finished Aug 25 02:15:58 AM UTC 24
Peak memory 200652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233334284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3233334284
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/22.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.2277757615
Short name T31
Test name
Test status
Simulation time 444028581 ps
CPU time 1.17 seconds
Started Aug 25 02:15:00 AM UTC 24
Finished Aug 25 02:15:19 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277757615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2277757615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.1631498888
Short name T183
Test name
Test status
Simulation time 23802864381 ps
CPU time 52.97 seconds
Started Aug 25 02:16:52 AM UTC 24
Finished Aug 25 02:17:46 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631498888 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.1631498888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/40.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.3809351155
Short name T115
Test name
Test status
Simulation time 455203579 ps
CPU time 1.64 seconds
Started Aug 25 02:17:18 AM UTC 24
Finished Aug 25 02:17:21 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809351155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3809351155
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/49.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.2146535470
Short name T22
Test name
Test status
Simulation time 80568654093 ps
CPU time 58.52 seconds
Started Aug 25 02:15:03 AM UTC 24
Finished Aug 25 02:16:04 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146535470 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.2146535470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.4253451222
Short name T33
Test name
Test status
Simulation time 515214889 ps
CPU time 1.73 seconds
Started Aug 25 02:15:19 AM UTC 24
Finished Aug 25 02:15:22 AM UTC 24
Peak memory 199248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253451222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4253451222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.1028573334
Short name T171
Test name
Test status
Simulation time 6223341547 ps
CPU time 26.13 seconds
Started Aug 25 02:15:56 AM UTC 24
Finished Aug 25 02:16:23 AM UTC 24
Peak memory 215256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1028573334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 22.aon_timer_stress_all_with_rand_reset.1028573334
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.3525244728
Short name T130
Test name
Test status
Simulation time 3784223293 ps
CPU time 25.4 seconds
Started Aug 25 02:15:57 AM UTC 24
Finished Aug 25 02:16:24 AM UTC 24
Peak memory 215044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3525244728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 23.aon_timer_stress_all_with_rand_reset.3525244728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.2994153324
Short name T180
Test name
Test status
Simulation time 2991691651 ps
CPU time 27.9 seconds
Started Aug 25 02:16:05 AM UTC 24
Finished Aug 25 02:16:34 AM UTC 24
Peak memory 214384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2994153324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 27.aon_timer_stress_all_with_rand_reset.2994153324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.3219806232
Short name T87
Test name
Test status
Simulation time 426895959 ps
CPU time 1.96 seconds
Started Aug 25 02:16:30 AM UTC 24
Finished Aug 25 02:16:33 AM UTC 24
Peak memory 199220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219806232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3219806232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/34.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.3141584652
Short name T141
Test name
Test status
Simulation time 418168323 ps
CPU time 1.48 seconds
Started Aug 25 02:17:08 AM UTC 24
Finished Aug 25 02:17:11 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141584652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3141584652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/45.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.3987883230
Short name T176
Test name
Test status
Simulation time 2518993348 ps
CPU time 27.12 seconds
Started Aug 25 02:17:08 AM UTC 24
Finished Aug 25 02:17:37 AM UTC 24
Peak memory 217024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3987883230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 45.aon_timer_stress_all_with_rand_reset.3987883230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.1827326987
Short name T160
Test name
Test status
Simulation time 30217300999 ps
CPU time 32.37 seconds
Started Aug 25 02:17:20 AM UTC 24
Finished Aug 25 02:17:53 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827326987 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.1827326987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/49.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.512843559
Short name T26
Test name
Test status
Simulation time 581352165 ps
CPU time 2.67 seconds
Started Aug 25 02:15:13 AM UTC 24
Finished Aug 25 02:15:18 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512843559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.512843559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.679418000
Short name T32
Test name
Test status
Simulation time 556287611 ps
CPU time 2.8 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:20 AM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679418000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.679418000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.2079939453
Short name T144
Test name
Test status
Simulation time 122288751748 ps
CPU time 101.2 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:17:00 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079939453 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.2079939453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.590886705
Short name T139
Test name
Test status
Simulation time 423602345 ps
CPU time 1.99 seconds
Started Aug 25 02:16:40 AM UTC 24
Finished Aug 25 02:16:43 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590886705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.590886705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/36.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.2405696392
Short name T168
Test name
Test status
Simulation time 4501084672 ps
CPU time 51.89 seconds
Started Aug 25 02:17:05 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 211908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2405696392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 44.aon_timer_stress_all_with_rand_reset.2405696392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.577612711
Short name T10
Test name
Test status
Simulation time 467486863 ps
CPU time 1.27 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:11 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577612711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.577612711
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.1760253577
Short name T132
Test name
Test status
Simulation time 519480149 ps
CPU time 2.67 seconds
Started Aug 25 02:15:26 AM UTC 24
Finished Aug 25 02:15:33 AM UTC 24
Peak memory 200652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760253577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1760253577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.4122540838
Short name T126
Test name
Test status
Simulation time 458795322 ps
CPU time 2.55 seconds
Started Aug 25 02:15:38 AM UTC 24
Finished Aug 25 02:15:42 AM UTC 24
Peak memory 200652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122540838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.4122540838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.2249025955
Short name T143
Test name
Test status
Simulation time 592337404 ps
CPU time 1.38 seconds
Started Aug 25 02:16:01 AM UTC 24
Finished Aug 25 02:16:04 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249025955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2249025955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/25.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.2108099119
Short name T20
Test name
Test status
Simulation time 14499388638 ps
CPU time 13.4 seconds
Started Aug 25 02:15:00 AM UTC 24
Finished Aug 25 02:15:32 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108099119 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.2108099119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.3908666287
Short name T14
Test name
Test status
Simulation time 2438896135 ps
CPU time 9.32 seconds
Started Aug 25 02:15:01 AM UTC 24
Finished Aug 25 02:15:25 AM UTC 24
Peak memory 215340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3908666287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 4.aon_timer_stress_all_with_rand_reset.3908666287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.2255290148
Short name T172
Test name
Test status
Simulation time 2898966591 ps
CPU time 39.54 seconds
Started Aug 25 02:16:54 AM UTC 24
Finished Aug 25 02:17:36 AM UTC 24
Peak memory 215592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2255290148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 41.aon_timer_stress_all_with_rand_reset.2255290148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.280446402
Short name T42
Test name
Test status
Simulation time 1362287677 ps
CPU time 10.76 seconds
Started Aug 25 02:15:26 AM UTC 24
Finished Aug 25 02:15:41 AM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=280446402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.aon_timer_stress_all_with_rand_reset.280446402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.2395180952
Short name T197
Test name
Test status
Simulation time 475698638 ps
CPU time 1.65 seconds
Started Aug 25 02:15:27 AM UTC 24
Finished Aug 25 02:15:31 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395180952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2395180952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.1554402392
Short name T154
Test name
Test status
Simulation time 82197891101 ps
CPU time 208.88 seconds
Started Aug 25 02:15:42 AM UTC 24
Finished Aug 25 02:19:14 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554402392 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.1554402392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.19009010
Short name T81
Test name
Test status
Simulation time 527952466 ps
CPU time 2.49 seconds
Started Aug 25 02:15:43 AM UTC 24
Finished Aug 25 02:15:47 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19009010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.19009010
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.2261908976
Short name T173
Test name
Test status
Simulation time 1869722066 ps
CPU time 11.32 seconds
Started Aug 25 02:15:49 AM UTC 24
Finished Aug 25 02:16:02 AM UTC 24
Peak memory 206556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2261908976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 20.aon_timer_stress_all_with_rand_reset.2261908976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.442780273
Short name T192
Test name
Test status
Simulation time 423528581 ps
CPU time 2.35 seconds
Started Aug 25 02:16:00 AM UTC 24
Finished Aug 25 02:16:03 AM UTC 24
Peak memory 200648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442780273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.442780273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/24.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.104975869
Short name T147
Test name
Test status
Simulation time 446609445 ps
CPU time 2.53 seconds
Started Aug 25 02:16:04 AM UTC 24
Finished Aug 25 02:16:07 AM UTC 24
Peak memory 200648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104975869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.104975869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/26.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.386391826
Short name T148
Test name
Test status
Simulation time 501382840 ps
CPU time 2.47 seconds
Started Aug 25 02:16:06 AM UTC 24
Finished Aug 25 02:16:10 AM UTC 24
Peak memory 200580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386391826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.386391826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/28.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.3035512845
Short name T167
Test name
Test status
Simulation time 463503053 ps
CPU time 2.3 seconds
Started Aug 25 02:16:13 AM UTC 24
Finished Aug 25 02:16:17 AM UTC 24
Peak memory 200780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035512845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3035512845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/30.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.3292085795
Short name T76
Test name
Test status
Simulation time 7822392481 ps
CPU time 41.81 seconds
Started Aug 25 02:16:13 AM UTC 24
Finished Aug 25 02:16:57 AM UTC 24
Peak memory 206772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3292085795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.aon_timer_stress_all_with_rand_reset.3292085795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.3321732075
Short name T195
Test name
Test status
Simulation time 530801577 ps
CPU time 2.15 seconds
Started Aug 25 02:16:21 AM UTC 24
Finished Aug 25 02:16:24 AM UTC 24
Peak memory 200580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321732075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3321732075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/32.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.3265844813
Short name T174
Test name
Test status
Simulation time 2094904858 ps
CPU time 23.93 seconds
Started Aug 25 02:16:23 AM UTC 24
Finished Aug 25 02:16:48 AM UTC 24
Peak memory 211836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3265844813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 32.aon_timer_stress_all_with_rand_reset.3265844813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.2420668478
Short name T74
Test name
Test status
Simulation time 1714993912 ps
CPU time 14.07 seconds
Started Aug 25 02:16:26 AM UTC 24
Finished Aug 25 02:16:41 AM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2420668478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 33.aon_timer_stress_all_with_rand_reset.2420668478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.1325442880
Short name T188
Test name
Test status
Simulation time 405199576 ps
CPU time 1.85 seconds
Started Aug 25 02:16:42 AM UTC 24
Finished Aug 25 02:16:45 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325442880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1325442880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/37.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.3552750857
Short name T198
Test name
Test status
Simulation time 533063284 ps
CPU time 2.62 seconds
Started Aug 25 02:16:49 AM UTC 24
Finished Aug 25 02:16:53 AM UTC 24
Peak memory 200608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552750857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3552750857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/39.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.599782287
Short name T4
Test name
Test status
Simulation time 369567006 ps
CPU time 1.81 seconds
Started Aug 25 02:15:03 AM UTC 24
Finished Aug 25 02:15:07 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599782287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.599782287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.1032031557
Short name T44
Test name
Test status
Simulation time 6782810965 ps
CPU time 39.97 seconds
Started Aug 25 02:15:03 AM UTC 24
Finished Aug 25 02:15:45 AM UTC 24
Peak memory 209992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1032031557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 5.aon_timer_stress_all_with_rand_reset.1032031557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.69866140
Short name T177
Test name
Test status
Simulation time 93504103514 ps
CPU time 161.09 seconds
Started Aug 25 02:15:08 AM UTC 24
Finished Aug 25 02:17:53 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69866140 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.69866140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.118470767
Short name T28
Test name
Test status
Simulation time 469962121 ps
CPU time 2.56 seconds
Started Aug 25 02:15:11 AM UTC 24
Finished Aug 25 02:15:18 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118470767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.118470767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.3545479211
Short name T164
Test name
Test status
Simulation time 96428812164 ps
CPU time 56.98 seconds
Started Aug 25 02:15:13 AM UTC 24
Finished Aug 25 02:16:13 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545479211 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.3545479211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4193235291
Short name T202
Test name
Test status
Simulation time 8034449711 ps
CPU time 8.77 seconds
Started Aug 25 02:17:54 AM UTC 24
Finished Aug 25 02:18:04 AM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193235291 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.4193235291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.1475497144
Short name T45
Test name
Test status
Simulation time 7032776202 ps
CPU time 21.51 seconds
Started Aug 25 02:15:22 AM UTC 24
Finished Aug 25 02:15:46 AM UTC 24
Peak memory 215384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1475497144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 11.aon_timer_stress_all_with_rand_reset.1475497144
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.1657782628
Short name T185
Test name
Test status
Simulation time 424221835 ps
CPU time 1.43 seconds
Started Aug 25 02:15:24 AM UTC 24
Finished Aug 25 02:15:27 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657782628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1657782628
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.3638276643
Short name T175
Test name
Test status
Simulation time 5936575086 ps
CPU time 30.86 seconds
Started Aug 25 02:15:27 AM UTC 24
Finished Aug 25 02:16:01 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3638276643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 14.aon_timer_stress_all_with_rand_reset.3638276643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.4036394422
Short name T166
Test name
Test status
Simulation time 577288861 ps
CPU time 0.99 seconds
Started Aug 25 02:15:33 AM UTC 24
Finished Aug 25 02:15:35 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036394422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4036394422
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.1118881560
Short name T191
Test name
Test status
Simulation time 559179678 ps
CPU time 2.77 seconds
Started Aug 25 02:15:52 AM UTC 24
Finished Aug 25 02:15:56 AM UTC 24
Peak memory 200652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118881560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1118881560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/21.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.2657866450
Short name T182
Test name
Test status
Simulation time 490592591 ps
CPU time 1.21 seconds
Started Aug 25 02:16:09 AM UTC 24
Finished Aug 25 02:16:11 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657866450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2657866450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/29.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.3820993686
Short name T178
Test name
Test status
Simulation time 564035985 ps
CPU time 1.72 seconds
Started Aug 25 02:16:36 AM UTC 24
Finished Aug 25 02:16:39 AM UTC 24
Peak memory 199056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820993686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3820993686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/35.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.1902685838
Short name T163
Test name
Test status
Simulation time 154055959901 ps
CPU time 162.93 seconds
Started Aug 25 02:16:54 AM UTC 24
Finished Aug 25 02:19:41 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902685838 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.1902685838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/41.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.2074664457
Short name T187
Test name
Test status
Simulation time 453326363 ps
CPU time 2.15 seconds
Started Aug 25 02:16:57 AM UTC 24
Finished Aug 25 02:17:00 AM UTC 24
Peak memory 200716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074664457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2074664457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/42.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.596097754
Short name T179
Test name
Test status
Simulation time 466776271 ps
CPU time 2 seconds
Started Aug 25 02:17:00 AM UTC 24
Finished Aug 25 02:17:03 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596097754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.596097754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/43.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.813330967
Short name T194
Test name
Test status
Simulation time 559844763 ps
CPU time 1.28 seconds
Started Aug 25 02:17:12 AM UTC 24
Finished Aug 25 02:17:15 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813330967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.813330967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/47.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.240283174
Short name T170
Test name
Test status
Simulation time 365514879 ps
CPU time 1.21 seconds
Started Aug 25 02:15:17 AM UTC 24
Finished Aug 25 02:15:20 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240283174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.240283174
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.3525303617
Short name T73
Test name
Test status
Simulation time 2334438609 ps
CPU time 18.96 seconds
Started Aug 25 02:15:40 AM UTC 24
Finished Aug 25 02:16:00 AM UTC 24
Peak memory 206556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3525303617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 17.aon_timer_stress_all_with_rand_reset.3525303617
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.3082666900
Short name T86
Test name
Test status
Simulation time 623163082 ps
CPU time 1.17 seconds
Started Aug 25 02:15:49 AM UTC 24
Finished Aug 25 02:15:52 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082666900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3082666900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/20.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.1251249730
Short name T193
Test name
Test status
Simulation time 690696797 ps
CPU time 0.98 seconds
Started Aug 25 02:15:57 AM UTC 24
Finished Aug 25 02:15:59 AM UTC 24
Peak memory 199248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251249730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1251249730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/23.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.3367367421
Short name T186
Test name
Test status
Simulation time 533228253 ps
CPU time 1.78 seconds
Started Aug 25 02:16:05 AM UTC 24
Finished Aug 25 02:16:08 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367367421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3367367421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/27.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.697489230
Short name T27
Test name
Test status
Simulation time 448972555 ps
CPU time 2.52 seconds
Started Aug 25 02:15:01 AM UTC 24
Finished Aug 25 02:15:18 AM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697489230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.697489230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.1628251217
Short name T190
Test name
Test status
Simulation time 662726620 ps
CPU time 0.84 seconds
Started Aug 25 02:17:15 AM UTC 24
Finished Aug 25 02:17:17 AM UTC 24
Peak memory 199004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628251217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1628251217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/48.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.1117821091
Short name T184
Test name
Test status
Simulation time 7326984306 ps
CPU time 36.93 seconds
Started Aug 25 02:17:16 AM UTC 24
Finished Aug 25 02:17:54 AM UTC 24
Peak memory 218968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1117821091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 48.aon_timer_stress_all_with_rand_reset.1117821091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.644004950
Short name T63
Test name
Test status
Simulation time 12715148270 ps
CPU time 25.19 seconds
Started Aug 25 02:17:23 AM UTC 24
Finished Aug 25 02:17:50 AM UTC 24
Peak memory 205648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644004950 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.644004950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.474823993
Short name T40
Test name
Test status
Simulation time 1038999025 ps
CPU time 2.61 seconds
Started Aug 25 02:17:22 AM UTC 24
Finished Aug 25 02:17:26 AM UTC 24
Peak memory 203252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474823993 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.474823993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2469149705
Short name T35
Test name
Test status
Simulation time 465252148 ps
CPU time 1.39 seconds
Started Aug 25 02:17:23 AM UTC 24
Finished Aug 25 02:17:26 AM UTC 24
Peak memory 206100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2469149705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_csr_mem_rw_with_rand_reset.2469149705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.3325237389
Short name T34
Test name
Test status
Simulation time 518485578 ps
CPU time 1.03 seconds
Started Aug 25 02:17:23 AM UTC 24
Finished Aug 25 02:17:25 AM UTC 24
Peak memory 201772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325237389 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3325237389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.366259667
Short name T291
Test name
Test status
Simulation time 487652761 ps
CPU time 1.23 seconds
Started Aug 25 02:17:20 AM UTC 24
Finished Aug 25 02:17:22 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366259667 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.366259667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2680186368
Short name T292
Test name
Test status
Simulation time 491217918 ps
CPU time 1.11 seconds
Started Aug 25 02:17:20 AM UTC 24
Finished Aug 25 02:17:22 AM UTC 24
Peak memory 199856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680186368 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.2680186368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.2288470929
Short name T290
Test name
Test status
Simulation time 490105466 ps
CPU time 0.84 seconds
Started Aug 25 02:17:20 AM UTC 24
Finished Aug 25 02:17:22 AM UTC 24
Peak memory 200540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288470929 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.2288470929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.1968739723
Short name T293
Test name
Test status
Simulation time 456914061 ps
CPU time 3.03 seconds
Started Aug 25 02:17:20 AM UTC 24
Finished Aug 25 02:17:24 AM UTC 24
Peak memory 205928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968739723 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1968739723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3304869179
Short name T200
Test name
Test status
Simulation time 7727876712 ps
CPU time 26.45 seconds
Started Aug 25 02:17:20 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 206060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304869179 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.3304869179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4234815055
Short name T54
Test name
Test status
Simulation time 640888730 ps
CPU time 3.31 seconds
Started Aug 25 02:17:30 AM UTC 24
Finished Aug 25 02:17:34 AM UTC 24
Peak memory 203332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234815055 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.4234815055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2011107924
Short name T58
Test name
Test status
Simulation time 13143759971 ps
CPU time 11.51 seconds
Started Aug 25 02:17:30 AM UTC 24
Finished Aug 25 02:17:42 AM UTC 24
Peak memory 205592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011107924 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.2011107924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1192060173
Short name T51
Test name
Test status
Simulation time 1234545477 ps
CPU time 1.85 seconds
Started Aug 25 02:17:27 AM UTC 24
Finished Aug 25 02:17:30 AM UTC 24
Peak memory 201784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192060173 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.1192060173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.257705355
Short name T216
Test name
Test status
Simulation time 458467804 ps
CPU time 2.15 seconds
Started Aug 25 02:17:30 AM UTC 24
Finished Aug 25 02:17:33 AM UTC 24
Peak memory 205432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=257705355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_time
r_csr_mem_rw_with_rand_reset.257705355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.2816266523
Short name T52
Test name
Test status
Simulation time 547409713 ps
CPU time 2.74 seconds
Started Aug 25 02:17:29 AM UTC 24
Finished Aug 25 02:17:32 AM UTC 24
Peak memory 203384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816266523 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2816266523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.1629052765
Short name T294
Test name
Test status
Simulation time 482483300 ps
CPU time 1.27 seconds
Started Aug 25 02:17:26 AM UTC 24
Finished Aug 25 02:17:29 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629052765 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1629052765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1675178281
Short name T295
Test name
Test status
Simulation time 323378853 ps
CPU time 1.33 seconds
Started Aug 25 02:17:26 AM UTC 24
Finished Aug 25 02:17:29 AM UTC 24
Peak memory 199856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675178281 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.1675178281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.893935416
Short name T297
Test name
Test status
Simulation time 390087521 ps
CPU time 1.73 seconds
Started Aug 25 02:17:26 AM UTC 24
Finished Aug 25 02:17:29 AM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893935416 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.893935416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1617620403
Short name T67
Test name
Test status
Simulation time 2557935337 ps
CPU time 5.86 seconds
Started Aug 25 02:17:30 AM UTC 24
Finished Aug 25 02:17:37 AM UTC 24
Peak memory 205424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617620403 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.1617620403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2711856757
Short name T296
Test name
Test status
Simulation time 477423813 ps
CPU time 3.54 seconds
Started Aug 25 02:17:24 AM UTC 24
Finished Aug 25 02:17:29 AM UTC 24
Peak memory 206968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711856757 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2711856757
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3951583642
Short name T37
Test name
Test status
Simulation time 4835222281 ps
CPU time 5.24 seconds
Started Aug 25 02:17:26 AM UTC 24
Finished Aug 25 02:17:33 AM UTC 24
Peak memory 206772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951583642 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.3951583642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3991531968
Short name T343
Test name
Test status
Simulation time 523225881 ps
CPU time 1.24 seconds
Started Aug 25 02:17:48 AM UTC 24
Finished Aug 25 02:17:50 AM UTC 24
Peak memory 206240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3991531968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_ti
mer_csr_mem_rw_with_rand_reset.3991531968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.1410769448
Short name T339
Test name
Test status
Simulation time 428100340 ps
CPU time 1.21 seconds
Started Aug 25 02:17:47 AM UTC 24
Finished Aug 25 02:17:49 AM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410769448 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1410769448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.1990925288
Short name T338
Test name
Test status
Simulation time 433790321 ps
CPU time 1.19 seconds
Started Aug 25 02:17:47 AM UTC 24
Finished Aug 25 02:17:49 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990925288 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1990925288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3813400447
Short name T348
Test name
Test status
Simulation time 2302866876 ps
CPU time 2.37 seconds
Started Aug 25 02:17:48 AM UTC 24
Finished Aug 25 02:17:51 AM UTC 24
Peak memory 205624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813400447 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.3813400447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1541560624
Short name T342
Test name
Test status
Simulation time 326794763 ps
CPU time 2.24 seconds
Started Aug 25 02:17:47 AM UTC 24
Finished Aug 25 02:17:50 AM UTC 24
Peak memory 207036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541560624 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1541560624
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3627056932
Short name T347
Test name
Test status
Simulation time 4122968133 ps
CPU time 3.37 seconds
Started Aug 25 02:17:47 AM UTC 24
Finished Aug 25 02:17:51 AM UTC 24
Peak memory 206816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627056932 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.3627056932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2721010523
Short name T352
Test name
Test status
Simulation time 612144994 ps
CPU time 1.49 seconds
Started Aug 25 02:17:49 AM UTC 24
Finished Aug 25 02:17:52 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2721010523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_ti
mer_csr_mem_rw_with_rand_reset.2721010523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.2555911838
Short name T344
Test name
Test status
Simulation time 416781547 ps
CPU time 1.21 seconds
Started Aug 25 02:17:48 AM UTC 24
Finished Aug 25 02:17:50 AM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555911838 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2555911838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.1780243912
Short name T341
Test name
Test status
Simulation time 490438695 ps
CPU time 0.95 seconds
Started Aug 25 02:17:48 AM UTC 24
Finished Aug 25 02:17:50 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780243912 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1780243912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1411202253
Short name T370
Test name
Test status
Simulation time 1325567891 ps
CPU time 5.39 seconds
Started Aug 25 02:17:49 AM UTC 24
Finished Aug 25 02:17:56 AM UTC 24
Peak memory 203448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411202253 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.1411202253
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.4269959346
Short name T346
Test name
Test status
Simulation time 610039575 ps
CPU time 1.93 seconds
Started Aug 25 02:17:48 AM UTC 24
Finished Aug 25 02:17:51 AM UTC 24
Peak memory 206952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269959346 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.4269959346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2657328982
Short name T361
Test name
Test status
Simulation time 4257845939 ps
CPU time 5.13 seconds
Started Aug 25 02:17:48 AM UTC 24
Finished Aug 25 02:17:54 AM UTC 24
Peak memory 206904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657328982 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.2657328982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3919992343
Short name T356
Test name
Test status
Simulation time 417289692 ps
CPU time 2.3 seconds
Started Aug 25 02:17:50 AM UTC 24
Finished Aug 25 02:17:53 AM UTC 24
Peak memory 205364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3919992343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_ti
mer_csr_mem_rw_with_rand_reset.3919992343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2330457156
Short name T354
Test name
Test status
Simulation time 298205195 ps
CPU time 1.85 seconds
Started Aug 25 02:17:49 AM UTC 24
Finished Aug 25 02:17:52 AM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330457156 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2330457156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.2547602657
Short name T350
Test name
Test status
Simulation time 549518920 ps
CPU time 0.96 seconds
Started Aug 25 02:17:49 AM UTC 24
Finished Aug 25 02:17:51 AM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547602657 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2547602657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1520828534
Short name T398
Test name
Test status
Simulation time 1439750826 ps
CPU time 8.82 seconds
Started Aug 25 02:17:49 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 203576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520828534 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.1520828534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.2766685892
Short name T357
Test name
Test status
Simulation time 507258701 ps
CPU time 2.78 seconds
Started Aug 25 02:17:49 AM UTC 24
Finished Aug 25 02:17:53 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766685892 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2766685892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1992168861
Short name T363
Test name
Test status
Simulation time 4308199929 ps
CPU time 4.11 seconds
Started Aug 25 02:17:49 AM UTC 24
Finished Aug 25 02:17:55 AM UTC 24
Peak memory 206392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992168861 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.1992168861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2052075879
Short name T360
Test name
Test status
Simulation time 422995130 ps
CPU time 2.21 seconds
Started Aug 25 02:17:51 AM UTC 24
Finished Aug 25 02:17:54 AM UTC 24
Peak memory 205500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2052075879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti
mer_csr_mem_rw_with_rand_reset.2052075879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.898136502
Short name T64
Test name
Test status
Simulation time 491592317 ps
CPU time 2.51 seconds
Started Aug 25 02:17:50 AM UTC 24
Finished Aug 25 02:17:53 AM UTC 24
Peak memory 203384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898136502 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.898136502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.335435270
Short name T351
Test name
Test status
Simulation time 303028013 ps
CPU time 1.04 seconds
Started Aug 25 02:17:50 AM UTC 24
Finished Aug 25 02:17:52 AM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335435270 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.335435270
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4213626655
Short name T411
Test name
Test status
Simulation time 2558258591 ps
CPU time 9.92 seconds
Started Aug 25 02:17:51 AM UTC 24
Finished Aug 25 02:18:02 AM UTC 24
Peak memory 205752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213626655 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.4213626655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3379235127
Short name T359
Test name
Test status
Simulation time 369001639 ps
CPU time 2.99 seconds
Started Aug 25 02:17:50 AM UTC 24
Finished Aug 25 02:17:54 AM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379235127 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3379235127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4207040590
Short name T371
Test name
Test status
Simulation time 4348664217 ps
CPU time 4.99 seconds
Started Aug 25 02:17:50 AM UTC 24
Finished Aug 25 02:17:56 AM UTC 24
Peak memory 206068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207040590 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.4207040590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1542619245
Short name T364
Test name
Test status
Simulation time 505632003 ps
CPU time 2.38 seconds
Started Aug 25 02:17:51 AM UTC 24
Finished Aug 25 02:17:55 AM UTC 24
Peak memory 205424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1542619245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_ti
mer_csr_mem_rw_with_rand_reset.1542619245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2835398935
Short name T65
Test name
Test status
Simulation time 531273422 ps
CPU time 1.14 seconds
Started Aug 25 02:17:51 AM UTC 24
Finished Aug 25 02:17:53 AM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835398935 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2835398935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.4212813078
Short name T358
Test name
Test status
Simulation time 306226797 ps
CPU time 1.18 seconds
Started Aug 25 02:17:51 AM UTC 24
Finished Aug 25 02:17:53 AM UTC 24
Peak memory 199688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212813078 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.4212813078
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.719042394
Short name T389
Test name
Test status
Simulation time 1837183275 ps
CPU time 6.37 seconds
Started Aug 25 02:17:51 AM UTC 24
Finished Aug 25 02:17:58 AM UTC 24
Peak memory 203384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719042394 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.719042394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.419143715
Short name T368
Test name
Test status
Simulation time 386504934 ps
CPU time 2.98 seconds
Started Aug 25 02:17:51 AM UTC 24
Finished Aug 25 02:17:55 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419143715 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.419143715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.505733956
Short name T201
Test name
Test status
Simulation time 8474755947 ps
CPU time 6.72 seconds
Started Aug 25 02:17:51 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 207032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505733956 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.505733956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3826237688
Short name T369
Test name
Test status
Simulation time 323851716 ps
CPU time 1.9 seconds
Started Aug 25 02:17:52 AM UTC 24
Finished Aug 25 02:17:55 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3826237688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti
mer_csr_mem_rw_with_rand_reset.3826237688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.3189088991
Short name T60
Test name
Test status
Simulation time 395181011 ps
CPU time 1.43 seconds
Started Aug 25 02:17:52 AM UTC 24
Finished Aug 25 02:17:55 AM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189088991 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3189088991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.2652495050
Short name T362
Test name
Test status
Simulation time 306613452 ps
CPU time 1.21 seconds
Started Aug 25 02:17:52 AM UTC 24
Finished Aug 25 02:17:54 AM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652495050 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2652495050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4221283784
Short name T377
Test name
Test status
Simulation time 1665694184 ps
CPU time 3.79 seconds
Started Aug 25 02:17:52 AM UTC 24
Finished Aug 25 02:17:57 AM UTC 24
Peak memory 203576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221283784 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.4221283784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.493990303
Short name T374
Test name
Test status
Simulation time 761150466 ps
CPU time 4.34 seconds
Started Aug 25 02:17:51 AM UTC 24
Finished Aug 25 02:17:56 AM UTC 24
Peak memory 207040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493990303 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.493990303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.801258819
Short name T404
Test name
Test status
Simulation time 3960942179 ps
CPU time 8.4 seconds
Started Aug 25 02:17:51 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 205428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801258819 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.801258819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.185314003
Short name T373
Test name
Test status
Simulation time 439044065 ps
CPU time 1.55 seconds
Started Aug 25 02:17:54 AM UTC 24
Finished Aug 25 02:17:56 AM UTC 24
Peak memory 207008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=185314003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_tim
er_csr_mem_rw_with_rand_reset.185314003
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.2272895259
Short name T367
Test name
Test status
Simulation time 352097263 ps
CPU time 1.2 seconds
Started Aug 25 02:17:53 AM UTC 24
Finished Aug 25 02:17:55 AM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272895259 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2272895259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.910167169
Short name T365
Test name
Test status
Simulation time 508974930 ps
CPU time 1.18 seconds
Started Aug 25 02:17:52 AM UTC 24
Finished Aug 25 02:17:55 AM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910167169 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.910167169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3997954752
Short name T386
Test name
Test status
Simulation time 2812541158 ps
CPU time 3.21 seconds
Started Aug 25 02:17:54 AM UTC 24
Finished Aug 25 02:17:58 AM UTC 24
Peak memory 205496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997954752 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.3997954752
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.2902479525
Short name T379
Test name
Test status
Simulation time 493524553 ps
CPU time 3.74 seconds
Started Aug 25 02:17:52 AM UTC 24
Finished Aug 25 02:17:57 AM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902479525 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2902479525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3516258441
Short name T424
Test name
Test status
Simulation time 8070405562 ps
CPU time 13.5 seconds
Started Aug 25 02:17:52 AM UTC 24
Finished Aug 25 02:18:07 AM UTC 24
Peak memory 206896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516258441 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.3516258441
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.547317778
Short name T380
Test name
Test status
Simulation time 418116684 ps
CPU time 2.11 seconds
Started Aug 25 02:17:54 AM UTC 24
Finished Aug 25 02:17:57 AM UTC 24
Peak memory 205688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=547317778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_tim
er_csr_mem_rw_with_rand_reset.547317778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.2468737401
Short name T378
Test name
Test status
Simulation time 407106480 ps
CPU time 2.24 seconds
Started Aug 25 02:17:54 AM UTC 24
Finished Aug 25 02:17:57 AM UTC 24
Peak memory 203180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468737401 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2468737401
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.112576681
Short name T372
Test name
Test status
Simulation time 434106902 ps
CPU time 1.01 seconds
Started Aug 25 02:17:54 AM UTC 24
Finished Aug 25 02:17:56 AM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112576681 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.112576681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.648737122
Short name T375
Test name
Test status
Simulation time 2070253148 ps
CPU time 1.98 seconds
Started Aug 25 02:17:54 AM UTC 24
Finished Aug 25 02:17:57 AM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648737122 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.648737122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.1468945353
Short name T383
Test name
Test status
Simulation time 292054216 ps
CPU time 2.94 seconds
Started Aug 25 02:17:54 AM UTC 24
Finished Aug 25 02:17:58 AM UTC 24
Peak memory 207104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468945353 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1468945353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.713940795
Short name T385
Test name
Test status
Simulation time 541672544 ps
CPU time 1.64 seconds
Started Aug 25 02:17:55 AM UTC 24
Finished Aug 25 02:17:58 AM UTC 24
Peak memory 203940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=713940795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_tim
er_csr_mem_rw_with_rand_reset.713940795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.2115174950
Short name T66
Test name
Test status
Simulation time 296031035 ps
CPU time 0.99 seconds
Started Aug 25 02:17:55 AM UTC 24
Finished Aug 25 02:17:57 AM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115174950 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2115174950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.1853763699
Short name T381
Test name
Test status
Simulation time 452208115 ps
CPU time 1.17 seconds
Started Aug 25 02:17:55 AM UTC 24
Finished Aug 25 02:17:57 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853763699 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1853763699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3253766764
Short name T425
Test name
Test status
Simulation time 2379483417 ps
CPU time 11.2 seconds
Started Aug 25 02:17:55 AM UTC 24
Finished Aug 25 02:18:08 AM UTC 24
Peak memory 205496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253766764 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.3253766764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1339924567
Short name T382
Test name
Test status
Simulation time 584050159 ps
CPU time 2.56 seconds
Started Aug 25 02:17:54 AM UTC 24
Finished Aug 25 02:17:58 AM UTC 24
Peak memory 206996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339924567 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1339924567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2066268797
Short name T426
Test name
Test status
Simulation time 7952427230 ps
CPU time 23.71 seconds
Started Aug 25 02:17:55 AM UTC 24
Finished Aug 25 02:18:20 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066268797 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.2066268797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1432704962
Short name T384
Test name
Test status
Simulation time 531689974 ps
CPU time 1.38 seconds
Started Aug 25 02:17:56 AM UTC 24
Finished Aug 25 02:17:58 AM UTC 24
Peak memory 205892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1432704962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti
mer_csr_mem_rw_with_rand_reset.1432704962
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.2555904172
Short name T392
Test name
Test status
Simulation time 511660255 ps
CPU time 2.54 seconds
Started Aug 25 02:17:55 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 201132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555904172 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2555904172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.3963804524
Short name T387
Test name
Test status
Simulation time 405942830 ps
CPU time 1.69 seconds
Started Aug 25 02:17:55 AM UTC 24
Finished Aug 25 02:17:58 AM UTC 24
Peak memory 199852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963804524 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3963804524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3544077057
Short name T394
Test name
Test status
Simulation time 1296717086 ps
CPU time 2.7 seconds
Started Aug 25 02:17:56 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 203576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544077057 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.3544077057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.851078926
Short name T396
Test name
Test status
Simulation time 460549989 ps
CPU time 2.97 seconds
Started Aug 25 02:17:55 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851078926 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.851078926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4103622434
Short name T423
Test name
Test status
Simulation time 8382421810 ps
CPU time 9.23 seconds
Started Aug 25 02:17:55 AM UTC 24
Finished Aug 25 02:18:06 AM UTC 24
Peak memory 206968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103622434 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.4103622434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.292565638
Short name T304
Test name
Test status
Simulation time 607708619 ps
CPU time 2.55 seconds
Started Aug 25 02:17:34 AM UTC 24
Finished Aug 25 02:17:37 AM UTC 24
Peak memory 203200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292565638 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.292565638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3305386721
Short name T62
Test name
Test status
Simulation time 7423579538 ps
CPU time 8.37 seconds
Started Aug 25 02:17:33 AM UTC 24
Finished Aug 25 02:17:43 AM UTC 24
Peak memory 205664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305386721 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.3305386721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4117554006
Short name T53
Test name
Test status
Simulation time 786118023 ps
CPU time 1.16 seconds
Started Aug 25 02:17:31 AM UTC 24
Finished Aug 25 02:17:33 AM UTC 24
Peak memory 201784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117554006 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.4117554006
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.132249460
Short name T303
Test name
Test status
Simulation time 560799271 ps
CPU time 1.34 seconds
Started Aug 25 02:17:34 AM UTC 24
Finished Aug 25 02:17:36 AM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=132249460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_time
r_csr_mem_rw_with_rand_reset.132249460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.2407602827
Short name T55
Test name
Test status
Simulation time 499737150 ps
CPU time 1.2 seconds
Started Aug 25 02:17:32 AM UTC 24
Finished Aug 25 02:17:35 AM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407602827 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2407602827
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.3141497159
Short name T300
Test name
Test status
Simulation time 516828054 ps
CPU time 0.89 seconds
Started Aug 25 02:17:31 AM UTC 24
Finished Aug 25 02:17:33 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141497159 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3141497159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4111518784
Short name T301
Test name
Test status
Simulation time 368714335 ps
CPU time 1.28 seconds
Started Aug 25 02:17:31 AM UTC 24
Finished Aug 25 02:17:33 AM UTC 24
Peak memory 199856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111518784 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.4111518784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.1078908496
Short name T302
Test name
Test status
Simulation time 473464903 ps
CPU time 1.47 seconds
Started Aug 25 02:17:31 AM UTC 24
Finished Aug 25 02:17:33 AM UTC 24
Peak memory 199908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078908496 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.1078908496
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2871877486
Short name T68
Test name
Test status
Simulation time 1145450550 ps
CPU time 6.22 seconds
Started Aug 25 02:17:34 AM UTC 24
Finished Aug 25 02:17:41 AM UTC 24
Peak memory 203312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871877486 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.2871877486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2041069120
Short name T298
Test name
Test status
Simulation time 470423437 ps
CPU time 1.68 seconds
Started Aug 25 02:17:30 AM UTC 24
Finished Aug 25 02:17:32 AM UTC 24
Peak memory 207068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041069120 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2041069120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.970555531
Short name T39
Test name
Test status
Simulation time 8183528970 ps
CPU time 7.66 seconds
Started Aug 25 02:17:30 AM UTC 24
Finished Aug 25 02:17:39 AM UTC 24
Peak memory 207004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970555531 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.970555531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.3148285147
Short name T388
Test name
Test status
Simulation time 310308152 ps
CPU time 1.73 seconds
Started Aug 25 02:17:56 AM UTC 24
Finished Aug 25 02:17:58 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148285147 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3148285147
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/20.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.561281085
Short name T391
Test name
Test status
Simulation time 514710371 ps
CPU time 1.12 seconds
Started Aug 25 02:17:57 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561281085 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.561281085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/21.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.2964861000
Short name T393
Test name
Test status
Simulation time 460241757 ps
CPU time 1.42 seconds
Started Aug 25 02:17:57 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964861000 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2964861000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/22.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.3439553467
Short name T395
Test name
Test status
Simulation time 420151937 ps
CPU time 1.58 seconds
Started Aug 25 02:17:57 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439553467 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3439553467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/23.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.2412093469
Short name T401
Test name
Test status
Simulation time 503183735 ps
CPU time 2.5 seconds
Started Aug 25 02:17:57 AM UTC 24
Finished Aug 25 02:18:00 AM UTC 24
Peak memory 201124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412093469 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2412093469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/24.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.2443393647
Short name T397
Test name
Test status
Simulation time 508774911 ps
CPU time 1.62 seconds
Started Aug 25 02:17:57 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443393647 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2443393647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/25.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.802200348
Short name T390
Test name
Test status
Simulation time 526378979 ps
CPU time 0.85 seconds
Started Aug 25 02:17:57 AM UTC 24
Finished Aug 25 02:17:59 AM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802200348 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.802200348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/26.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1328418742
Short name T400
Test name
Test status
Simulation time 478827350 ps
CPU time 1.26 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:00 AM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328418742 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1328418742
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/27.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.3925323238
Short name T399
Test name
Test status
Simulation time 298739399 ps
CPU time 1.02 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:00 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925323238 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3925323238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/28.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.3649473266
Short name T409
Test name
Test status
Simulation time 377801146 ps
CPU time 1.92 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 199404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649473266 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3649473266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/29.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2508999905
Short name T56
Test name
Test status
Simulation time 737342114 ps
CPU time 1.39 seconds
Started Aug 25 02:17:36 AM UTC 24
Finished Aug 25 02:17:38 AM UTC 24
Peak memory 201784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508999905 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.2508999905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3847400641
Short name T61
Test name
Test status
Simulation time 9209407987 ps
CPU time 47.74 seconds
Started Aug 25 02:17:36 AM UTC 24
Finished Aug 25 02:18:25 AM UTC 24
Peak memory 205416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847400641 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.3847400641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.765766974
Short name T308
Test name
Test status
Simulation time 852671551 ps
CPU time 1.53 seconds
Started Aug 25 02:17:35 AM UTC 24
Finished Aug 25 02:17:37 AM UTC 24
Peak memory 201780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765766974 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.765766974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1222598289
Short name T311
Test name
Test status
Simulation time 430659651 ps
CPU time 1.72 seconds
Started Aug 25 02:17:37 AM UTC 24
Finished Aug 25 02:17:40 AM UTC 24
Peak memory 204012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1222598289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_csr_mem_rw_with_rand_reset.1222598289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.1244828872
Short name T310
Test name
Test status
Simulation time 438839246 ps
CPU time 2.41 seconds
Started Aug 25 02:17:36 AM UTC 24
Finished Aug 25 02:17:39 AM UTC 24
Peak memory 203192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244828872 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1244828872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3749837456
Short name T307
Test name
Test status
Simulation time 272268864 ps
CPU time 1.53 seconds
Started Aug 25 02:17:35 AM UTC 24
Finished Aug 25 02:17:37 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749837456 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3749837456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2777952893
Short name T306
Test name
Test status
Simulation time 447501893 ps
CPU time 1.37 seconds
Started Aug 25 02:17:35 AM UTC 24
Finished Aug 25 02:17:37 AM UTC 24
Peak memory 199856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777952893 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.2777952893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.2888152140
Short name T309
Test name
Test status
Simulation time 517438085 ps
CPU time 1.76 seconds
Started Aug 25 02:17:35 AM UTC 24
Finished Aug 25 02:17:38 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888152140 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.2888152140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4097462098
Short name T72
Test name
Test status
Simulation time 2271678497 ps
CPU time 9.61 seconds
Started Aug 25 02:17:37 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 205688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097462098 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.4097462098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.1105973122
Short name T305
Test name
Test status
Simulation time 318715881 ps
CPU time 2.48 seconds
Started Aug 25 02:17:34 AM UTC 24
Finished Aug 25 02:17:37 AM UTC 24
Peak memory 207092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105973122 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1105973122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.1892575631
Short name T406
Test name
Test status
Simulation time 268613915 ps
CPU time 1.64 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892575631 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1892575631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/30.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.3492504593
Short name T407
Test name
Test status
Simulation time 399588111 ps
CPU time 1.8 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 199408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492504593 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3492504593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/31.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3373376877
Short name T349
Test name
Test status
Simulation time 391247828 ps
CPU time 2.09 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 201200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373376877 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3373376877
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/32.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2649097921
Short name T405
Test name
Test status
Simulation time 487145163 ps
CPU time 1.28 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649097921 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2649097921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/33.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2711409284
Short name T376
Test name
Test status
Simulation time 292172155 ps
CPU time 1.72 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711409284 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2711409284
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/34.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.419545557
Short name T408
Test name
Test status
Simulation time 500012937 ps
CPU time 1.57 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419545557 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.419545557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/35.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3324000867
Short name T402
Test name
Test status
Simulation time 448884394 ps
CPU time 1.09 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:00 AM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324000867 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3324000867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/36.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.3337501032
Short name T403
Test name
Test status
Simulation time 547133499 ps
CPU time 1.03 seconds
Started Aug 25 02:17:58 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337501032 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3337501032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/37.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.4239712957
Short name T417
Test name
Test status
Simulation time 490928576 ps
CPU time 1.57 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:02 AM UTC 24
Peak memory 199696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239712957 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4239712957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/38.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.1999621409
Short name T421
Test name
Test status
Simulation time 461976255 ps
CPU time 2.27 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:03 AM UTC 24
Peak memory 201116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999621409 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1999621409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/39.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.392123743
Short name T315
Test name
Test status
Simulation time 453299323 ps
CPU time 1.24 seconds
Started Aug 25 02:17:39 AM UTC 24
Finished Aug 25 02:17:41 AM UTC 24
Peak memory 201780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392123743 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.392123743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2765995517
Short name T59
Test name
Test status
Simulation time 10546623459 ps
CPU time 9.55 seconds
Started Aug 25 02:17:39 AM UTC 24
Finished Aug 25 02:17:49 AM UTC 24
Peak memory 205852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765995517 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.2765995517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1752270908
Short name T317
Test name
Test status
Simulation time 670238076 ps
CPU time 2.81 seconds
Started Aug 25 02:17:38 AM UTC 24
Finished Aug 25 02:17:42 AM UTC 24
Peak memory 203260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752270908 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.1752270908
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.546580333
Short name T318
Test name
Test status
Simulation time 496426239 ps
CPU time 1.58 seconds
Started Aug 25 02:17:40 AM UTC 24
Finished Aug 25 02:17:42 AM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=546580333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_time
r_csr_mem_rw_with_rand_reset.546580333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.4067609281
Short name T57
Test name
Test status
Simulation time 307977751 ps
CPU time 1.7 seconds
Started Aug 25 02:17:38 AM UTC 24
Finished Aug 25 02:17:41 AM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067609281 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4067609281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.1177461197
Short name T313
Test name
Test status
Simulation time 529955897 ps
CPU time 1.01 seconds
Started Aug 25 02:17:38 AM UTC 24
Finished Aug 25 02:17:40 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177461197 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1177461197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2539859728
Short name T312
Test name
Test status
Simulation time 386707492 ps
CPU time 1.07 seconds
Started Aug 25 02:17:38 AM UTC 24
Finished Aug 25 02:17:40 AM UTC 24
Peak memory 199856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539859728 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.2539859728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.3550279309
Short name T314
Test name
Test status
Simulation time 530710123 ps
CPU time 1.14 seconds
Started Aug 25 02:17:38 AM UTC 24
Finished Aug 25 02:17:40 AM UTC 24
Peak memory 199160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550279309 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.3550279309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1815226957
Short name T70
Test name
Test status
Simulation time 2195372965 ps
CPU time 6.79 seconds
Started Aug 25 02:17:40 AM UTC 24
Finished Aug 25 02:17:47 AM UTC 24
Peak memory 205752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815226957 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.1815226957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.2536712950
Short name T316
Test name
Test status
Simulation time 496855946 ps
CPU time 3.82 seconds
Started Aug 25 02:17:37 AM UTC 24
Finished Aug 25 02:17:42 AM UTC 24
Peak memory 207100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536712950 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2536712950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3959083839
Short name T205
Test name
Test status
Simulation time 4543939768 ps
CPU time 11.07 seconds
Started Aug 25 02:17:37 AM UTC 24
Finished Aug 25 02:17:49 AM UTC 24
Peak memory 206644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959083839 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.3959083839
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.961823325
Short name T410
Test name
Test status
Simulation time 415676544 ps
CPU time 0.93 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:02 AM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961823325 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.961823325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/40.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.809090754
Short name T412
Test name
Test status
Simulation time 348100274 ps
CPU time 1.03 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:02 AM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809090754 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.809090754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/41.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2180316056
Short name T419
Test name
Test status
Simulation time 294089212 ps
CPU time 1.62 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:02 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180316056 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2180316056
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/42.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2212275447
Short name T413
Test name
Test status
Simulation time 427448290 ps
CPU time 1.08 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:02 AM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212275447 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2212275447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/43.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1213372834
Short name T420
Test name
Test status
Simulation time 425907509 ps
CPU time 1.95 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:03 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213372834 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1213372834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/44.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.1227453854
Short name T416
Test name
Test status
Simulation time 517401115 ps
CPU time 1.2 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:02 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227453854 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1227453854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/45.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.3418399682
Short name T422
Test name
Test status
Simulation time 491817279 ps
CPU time 2.14 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:03 AM UTC 24
Peak memory 201124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418399682 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3418399682
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/46.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.1550020210
Short name T414
Test name
Test status
Simulation time 568716030 ps
CPU time 0.97 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:02 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550020210 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1550020210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/47.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.3582451321
Short name T415
Test name
Test status
Simulation time 384650643 ps
CPU time 0.99 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:02 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582451321 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3582451321
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/48.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.1697313715
Short name T418
Test name
Test status
Simulation time 518907639 ps
CPU time 1.2 seconds
Started Aug 25 02:18:00 AM UTC 24
Finished Aug 25 02:18:02 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697313715 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1697313715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/49.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.120747070
Short name T320
Test name
Test status
Simulation time 582210694 ps
CPU time 1.46 seconds
Started Aug 25 02:17:41 AM UTC 24
Finished Aug 25 02:17:43 AM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=120747070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_time
r_csr_mem_rw_with_rand_reset.120747070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.2504732773
Short name T324
Test name
Test status
Simulation time 511161328 ps
CPU time 2.37 seconds
Started Aug 25 02:17:41 AM UTC 24
Finished Aug 25 02:17:44 AM UTC 24
Peak memory 201400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504732773 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2504732773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.888301026
Short name T321
Test name
Test status
Simulation time 477251533 ps
CPU time 1.58 seconds
Started Aug 25 02:17:41 AM UTC 24
Finished Aug 25 02:17:43 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888301026 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.888301026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.484158105
Short name T69
Test name
Test status
Simulation time 1978710604 ps
CPU time 2.36 seconds
Started Aug 25 02:17:41 AM UTC 24
Finished Aug 25 02:17:44 AM UTC 24
Peak memory 205364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484158105 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.484158105
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.2176324405
Short name T319
Test name
Test status
Simulation time 643841269 ps
CPU time 2.63 seconds
Started Aug 25 02:17:40 AM UTC 24
Finished Aug 25 02:17:43 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176324405 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2176324405
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3923599239
Short name T199
Test name
Test status
Simulation time 7945302892 ps
CPU time 6.21 seconds
Started Aug 25 02:17:40 AM UTC 24
Finished Aug 25 02:17:47 AM UTC 24
Peak memory 207064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923599239 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.3923599239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.194127485
Short name T327
Test name
Test status
Simulation time 497374186 ps
CPU time 2.55 seconds
Started Aug 25 02:17:42 AM UTC 24
Finished Aug 25 02:17:46 AM UTC 24
Peak memory 206184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=194127485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_time
r_csr_mem_rw_with_rand_reset.194127485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.1540248279
Short name T323
Test name
Test status
Simulation time 500759790 ps
CPU time 1.19 seconds
Started Aug 25 02:17:42 AM UTC 24
Finished Aug 25 02:17:44 AM UTC 24
Peak memory 201772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540248279 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1540248279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.1412885310
Short name T322
Test name
Test status
Simulation time 343938115 ps
CPU time 1.09 seconds
Started Aug 25 02:17:42 AM UTC 24
Finished Aug 25 02:17:44 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412885310 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1412885310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.367373271
Short name T71
Test name
Test status
Simulation time 1229147326 ps
CPU time 4.49 seconds
Started Aug 25 02:17:42 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 203324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367373271 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.367373271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.1863648523
Short name T325
Test name
Test status
Simulation time 446110654 ps
CPU time 2.99 seconds
Started Aug 25 02:17:41 AM UTC 24
Finished Aug 25 02:17:45 AM UTC 24
Peak memory 207040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863648523 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1863648523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2347976736
Short name T203
Test name
Test status
Simulation time 4254584784 ps
CPU time 2.43 seconds
Started Aug 25 02:17:41 AM UTC 24
Finished Aug 25 02:17:45 AM UTC 24
Peak memory 206744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347976736 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.2347976736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.733058065
Short name T328
Test name
Test status
Simulation time 409695860 ps
CPU time 2 seconds
Started Aug 25 02:17:44 AM UTC 24
Finished Aug 25 02:17:47 AM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=733058065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_time
r_csr_mem_rw_with_rand_reset.733058065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.3962581909
Short name T329
Test name
Test status
Simulation time 535016529 ps
CPU time 2.36 seconds
Started Aug 25 02:17:43 AM UTC 24
Finished Aug 25 02:17:47 AM UTC 24
Peak memory 203180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962581909 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3962581909
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.2905083279
Short name T326
Test name
Test status
Simulation time 283198706 ps
CPU time 1.21 seconds
Started Aug 25 02:17:43 AM UTC 24
Finished Aug 25 02:17:46 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905083279 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2905083279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3061711366
Short name T335
Test name
Test status
Simulation time 1900530390 ps
CPU time 3.58 seconds
Started Aug 25 02:17:44 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 205360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061711366 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.3061711366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.3258573975
Short name T299
Test name
Test status
Simulation time 577976016 ps
CPU time 3.35 seconds
Started Aug 25 02:17:43 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 206964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258573975 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3258573975
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2426385098
Short name T204
Test name
Test status
Simulation time 4569133526 ps
CPU time 4.79 seconds
Started Aug 25 02:17:43 AM UTC 24
Finished Aug 25 02:17:49 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426385098 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.2426385098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2759040197
Short name T331
Test name
Test status
Simulation time 311874843 ps
CPU time 1.27 seconds
Started Aug 25 02:17:45 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 204012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2759040197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim
er_csr_mem_rw_with_rand_reset.2759040197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.189272555
Short name T336
Test name
Test status
Simulation time 485149508 ps
CPU time 2.4 seconds
Started Aug 25 02:17:45 AM UTC 24
Finished Aug 25 02:17:49 AM UTC 24
Peak memory 203320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189272555 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.189272555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.1440702876
Short name T337
Test name
Test status
Simulation time 462313081 ps
CPU time 2.39 seconds
Started Aug 25 02:17:45 AM UTC 24
Finished Aug 25 02:17:49 AM UTC 24
Peak memory 203176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440702876 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1440702876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3022064521
Short name T355
Test name
Test status
Simulation time 1474295674 ps
CPU time 6.14 seconds
Started Aug 25 02:17:45 AM UTC 24
Finished Aug 25 02:17:53 AM UTC 24
Peak memory 203576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022064521 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.3022064521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.2506323605
Short name T333
Test name
Test status
Simulation time 526022933 ps
CPU time 3.18 seconds
Started Aug 25 02:17:44 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 207164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506323605 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2506323605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3754089927
Short name T345
Test name
Test status
Simulation time 4807203997 ps
CPU time 4.32 seconds
Started Aug 25 02:17:45 AM UTC 24
Finished Aug 25 02:17:51 AM UTC 24
Peak memory 206496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754089927 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.3754089927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.262288479
Short name T334
Test name
Test status
Simulation time 445564929 ps
CPU time 1.22 seconds
Started Aug 25 02:17:46 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=262288479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_time
r_csr_mem_rw_with_rand_reset.262288479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.4000669196
Short name T332
Test name
Test status
Simulation time 490446238 ps
CPU time 1.19 seconds
Started Aug 25 02:17:46 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 201772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000669196 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4000669196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.3475309264
Short name T330
Test name
Test status
Simulation time 464083559 ps
CPU time 1.13 seconds
Started Aug 25 02:17:46 AM UTC 24
Finished Aug 25 02:17:48 AM UTC 24
Peak memory 201840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475309264 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3475309264
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4027897695
Short name T353
Test name
Test status
Simulation time 2499507900 ps
CPU time 5.36 seconds
Started Aug 25 02:17:46 AM UTC 24
Finished Aug 25 02:17:52 AM UTC 24
Peak memory 205688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027897695 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.4027897695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.2008867863
Short name T340
Test name
Test status
Simulation time 975780999 ps
CPU time 2.83 seconds
Started Aug 25 02:17:45 AM UTC 24
Finished Aug 25 02:17:49 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008867863 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2008867863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4070866112
Short name T366
Test name
Test status
Simulation time 8066100986 ps
CPU time 8.21 seconds
Started Aug 25 02:17:45 AM UTC 24
Finished Aug 25 02:17:55 AM UTC 24
Peak memory 207140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070866112 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.4070866112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.2040661762
Short name T261
Test name
Test status
Simulation time 34218034555 ps
CPU time 109.93 seconds
Started Aug 25 02:14:57 AM UTC 24
Finished Aug 25 02:17:01 AM UTC 24
Peak memory 200900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040661762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2040661762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1418512612
Short name T9
Test name
Test status
Simulation time 550793078 ps
CPU time 1.03 seconds
Started Aug 25 02:14:55 AM UTC 24
Finished Aug 25 02:15:11 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418512612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1418512612
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/0.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.2740923350
Short name T209
Test name
Test status
Simulation time 20735704342 ps
CPU time 7.62 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:25 AM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740923350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2740923350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.2727218174
Short name T18
Test name
Test status
Simulation time 5080625465 ps
CPU time 4.93 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:22 AM UTC 24
Peak memory 231396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727218174 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2727218174
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.1826088541
Short name T29
Test name
Test status
Simulation time 528240619 ps
CPU time 1.28 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:18 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826088541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1826088541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/1.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.221418303
Short name T215
Test name
Test status
Simulation time 41010871543 ps
CPU time 35.32 seconds
Started Aug 25 02:15:18 AM UTC 24
Finished Aug 25 02:15:55 AM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221418303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.221418303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.3006463818
Short name T16
Test name
Test status
Simulation time 409693320 ps
CPU time 1.2 seconds
Started Aug 25 02:15:18 AM UTC 24
Finished Aug 25 02:15:21 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006463818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3006463818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/10.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.2552945837
Short name T284
Test name
Test status
Simulation time 52970334395 ps
CPU time 157.86 seconds
Started Aug 25 02:15:21 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552945837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2552945837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.1935191611
Short name T217
Test name
Test status
Simulation time 444701006 ps
CPU time 1.3 seconds
Started Aug 25 02:15:20 AM UTC 24
Finished Aug 25 02:15:22 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935191611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1935191611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/11.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.863703296
Short name T256
Test name
Test status
Simulation time 31574006556 ps
CPU time 86.82 seconds
Started Aug 25 02:15:23 AM UTC 24
Finished Aug 25 02:16:53 AM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863703296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.863703296
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.1450391641
Short name T218
Test name
Test status
Simulation time 415591616 ps
CPU time 1.08 seconds
Started Aug 25 02:15:23 AM UTC 24
Finished Aug 25 02:15:25 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450391641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1450391641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.1713396216
Short name T213
Test name
Test status
Simulation time 31754884207 ps
CPU time 10.92 seconds
Started Aug 25 02:15:26 AM UTC 24
Finished Aug 25 02:15:41 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713396216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1713396216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.35470405
Short name T222
Test name
Test status
Simulation time 547524704 ps
CPU time 2.76 seconds
Started Aug 25 02:15:26 AM UTC 24
Finished Aug 25 02:15:30 AM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35470405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.35470405
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/13.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.3951594620
Short name T208
Test name
Test status
Simulation time 7501773349 ps
CPU time 13.94 seconds
Started Aug 25 02:15:26 AM UTC 24
Finished Aug 25 02:15:45 AM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951594620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3951594620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.1651825331
Short name T219
Test name
Test status
Simulation time 653670083 ps
CPU time 1.04 seconds
Started Aug 25 02:15:26 AM UTC 24
Finished Aug 25 02:15:32 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651825331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1651825331
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/14.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.2008638314
Short name T226
Test name
Test status
Simulation time 31665147738 ps
CPU time 25.11 seconds
Started Aug 25 02:15:31 AM UTC 24
Finished Aug 25 02:15:58 AM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008638314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2008638314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.2077523284
Short name T223
Test name
Test status
Simulation time 570797551 ps
CPU time 1.71 seconds
Started Aug 25 02:15:29 AM UTC 24
Finished Aug 25 02:15:31 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077523284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2077523284
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.1018721256
Short name T46
Test name
Test status
Simulation time 1584632308 ps
CPU time 19.59 seconds
Started Aug 25 02:15:33 AM UTC 24
Finished Aug 25 02:15:54 AM UTC 24
Peak memory 217100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1018721256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 15.aon_timer_stress_all_with_rand_reset.1018721256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.675374223
Short name T286
Test name
Test status
Simulation time 61547533531 ps
CPU time 168.93 seconds
Started Aug 25 02:15:34 AM UTC 24
Finished Aug 25 02:18:26 AM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675374223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.675374223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.2286594855
Short name T220
Test name
Test status
Simulation time 530395322 ps
CPU time 1.26 seconds
Started Aug 25 02:15:33 AM UTC 24
Finished Aug 25 02:15:35 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286594855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2286594855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/16.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.4276673300
Short name T214
Test name
Test status
Simulation time 57714951824 ps
CPU time 47.72 seconds
Started Aug 25 02:15:37 AM UTC 24
Finished Aug 25 02:16:26 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276673300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.4276673300
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.2268049390
Short name T221
Test name
Test status
Simulation time 437591158 ps
CPU time 1.2 seconds
Started Aug 25 02:15:37 AM UTC 24
Finished Aug 25 02:15:39 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268049390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2268049390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/17.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.16575435
Short name T247
Test name
Test status
Simulation time 31479270225 ps
CPU time 53.3 seconds
Started Aug 25 02:15:42 AM UTC 24
Finished Aug 25 02:16:37 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16575435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.16575435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.3657305971
Short name T161
Test name
Test status
Simulation time 519764644 ps
CPU time 1.76 seconds
Started Aug 25 02:15:42 AM UTC 24
Finished Aug 25 02:15:45 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657305971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3657305971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/18.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.3652129379
Short name T83
Test name
Test status
Simulation time 577184362 ps
CPU time 1.38 seconds
Started Aug 25 02:15:46 AM UTC 24
Finished Aug 25 02:15:48 AM UTC 24
Peak memory 199248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652129379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3652129379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.3965200086
Short name T227
Test name
Test status
Simulation time 6109165852 ps
CPU time 11.59 seconds
Started Aug 25 02:15:46 AM UTC 24
Finished Aug 25 02:15:59 AM UTC 24
Peak memory 200560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965200086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3965200086
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.2216274341
Short name T82
Test name
Test status
Simulation time 397817389 ps
CPU time 2.32 seconds
Started Aug 25 02:15:45 AM UTC 24
Finished Aug 25 02:15:48 AM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216274341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2216274341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/19.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.741762110
Short name T211
Test name
Test status
Simulation time 36565132946 ps
CPU time 28.69 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:28 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741762110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.741762110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.3887342699
Short name T17
Test name
Test status
Simulation time 4569698527 ps
CPU time 4.89 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:15 AM UTC 24
Peak memory 231248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887342699 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3887342699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.998994330
Short name T1
Test name
Test status
Simulation time 432897543 ps
CPU time 1.15 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:00 AM UTC 24
Peak memory 199992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998994330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.998994330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/2.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.3679511830
Short name T240
Test name
Test status
Simulation time 31441804822 ps
CPU time 27.29 seconds
Started Aug 25 02:15:48 AM UTC 24
Finished Aug 25 02:16:17 AM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679511830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3679511830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/20.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.2799786355
Short name T84
Test name
Test status
Simulation time 558698592 ps
CPU time 1.17 seconds
Started Aug 25 02:15:47 AM UTC 24
Finished Aug 25 02:15:49 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799786355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2799786355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/20.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.1006218301
Short name T254
Test name
Test status
Simulation time 18011264413 ps
CPU time 58.03 seconds
Started Aug 25 02:15:51 AM UTC 24
Finished Aug 25 02:16:51 AM UTC 24
Peak memory 200900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006218301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1006218301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/21.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.2176260678
Short name T224
Test name
Test status
Simulation time 380445454 ps
CPU time 2.07 seconds
Started Aug 25 02:15:51 AM UTC 24
Finished Aug 25 02:15:54 AM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176260678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2176260678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/21.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.2588682320
Short name T231
Test name
Test status
Simulation time 4369588885 ps
CPU time 7.75 seconds
Started Aug 25 02:15:54 AM UTC 24
Finished Aug 25 02:16:04 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588682320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2588682320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/22.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.4288121565
Short name T225
Test name
Test status
Simulation time 390117875 ps
CPU time 1.49 seconds
Started Aug 25 02:15:53 AM UTC 24
Finished Aug 25 02:15:56 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288121565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4288121565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/22.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.680145564
Short name T236
Test name
Test status
Simulation time 30524229412 ps
CPU time 13.87 seconds
Started Aug 25 02:15:57 AM UTC 24
Finished Aug 25 02:16:12 AM UTC 24
Peak memory 200616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680145564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.680145564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/23.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.3543057499
Short name T228
Test name
Test status
Simulation time 488911682 ps
CPU time 1.11 seconds
Started Aug 25 02:15:57 AM UTC 24
Finished Aug 25 02:15:59 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543057499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3543057499
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/23.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.893317380
Short name T206
Test name
Test status
Simulation time 1314281506 ps
CPU time 3.13 seconds
Started Aug 25 02:16:00 AM UTC 24
Finished Aug 25 02:16:04 AM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893317380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.893317380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/24.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.1735340146
Short name T230
Test name
Test status
Simulation time 440812354 ps
CPU time 2.17 seconds
Started Aug 25 02:16:00 AM UTC 24
Finished Aug 25 02:16:03 AM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735340146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1735340146
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/24.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.4143373308
Short name T239
Test name
Test status
Simulation time 20076422939 ps
CPU time 14.09 seconds
Started Aug 25 02:16:00 AM UTC 24
Finished Aug 25 02:16:15 AM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143373308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4143373308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/25.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.733685365
Short name T80
Test name
Test status
Simulation time 483487236 ps
CPU time 2.18 seconds
Started Aug 25 02:16:00 AM UTC 24
Finished Aug 25 02:16:03 AM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733685365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.733685365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/25.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.1387598617
Short name T233
Test name
Test status
Simulation time 373956879 ps
CPU time 2.11 seconds
Started Aug 25 02:16:02 AM UTC 24
Finished Aug 25 02:16:06 AM UTC 24
Peak memory 200644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387598617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1387598617
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/26.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.2082088459
Short name T232
Test name
Test status
Simulation time 379599135 ps
CPU time 1.43 seconds
Started Aug 25 02:16:02 AM UTC 24
Finished Aug 25 02:16:05 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082088459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2082088459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/26.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.1095479516
Short name T281
Test name
Test status
Simulation time 33010827588 ps
CPU time 95.33 seconds
Started Aug 25 02:16:04 AM UTC 24
Finished Aug 25 02:17:42 AM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095479516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1095479516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/27.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.162760271
Short name T234
Test name
Test status
Simulation time 367083224 ps
CPU time 1.93 seconds
Started Aug 25 02:16:04 AM UTC 24
Finished Aug 25 02:16:07 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162760271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.162760271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/27.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.2418020849
Short name T242
Test name
Test status
Simulation time 3859051497 ps
CPU time 13.71 seconds
Started Aug 25 02:16:05 AM UTC 24
Finished Aug 25 02:16:20 AM UTC 24
Peak memory 200900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418020849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2418020849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/28.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.866520892
Short name T235
Test name
Test status
Simulation time 446157600 ps
CPU time 1.11 seconds
Started Aug 25 02:16:05 AM UTC 24
Finished Aug 25 02:16:07 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866520892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.866520892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/28.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.3177189015
Short name T282
Test name
Test status
Simulation time 37963666495 ps
CPU time 105.15 seconds
Started Aug 25 02:16:09 AM UTC 24
Finished Aug 25 02:17:56 AM UTC 24
Peak memory 200336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177189015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3177189015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/29.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.333375897
Short name T237
Test name
Test status
Simulation time 442919354 ps
CPU time 2.2 seconds
Started Aug 25 02:16:09 AM UTC 24
Finished Aug 25 02:16:12 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333375897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.333375897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/29.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.1743521036
Short name T210
Test name
Test status
Simulation time 30871930359 ps
CPU time 15.58 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:26 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743521036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1743521036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.649685126
Short name T19
Test name
Test status
Simulation time 4594796987 ps
CPU time 8.03 seconds
Started Aug 25 02:15:01 AM UTC 24
Finished Aug 25 02:15:23 AM UTC 24
Peak memory 231316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649685126 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.649685126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.1303914941
Short name T8
Test name
Test status
Simulation time 643396928 ps
CPU time 1.16 seconds
Started Aug 25 02:14:58 AM UTC 24
Finished Aug 25 02:15:11 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303914941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1303914941
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/3.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.3950516136
Short name T285
Test name
Test status
Simulation time 37068323807 ps
CPU time 110 seconds
Started Aug 25 02:16:12 AM UTC 24
Finished Aug 25 02:18:05 AM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950516136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3950516136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/30.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.3306494779
Short name T238
Test name
Test status
Simulation time 378319483 ps
CPU time 1.21 seconds
Started Aug 25 02:16:12 AM UTC 24
Finished Aug 25 02:16:14 AM UTC 24
Peak memory 198928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306494779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3306494779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/30.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.67563060
Short name T287
Test name
Test status
Simulation time 51602896646 ps
CPU time 135.55 seconds
Started Aug 25 02:16:15 AM UTC 24
Finished Aug 25 02:18:34 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67563060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.67563060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/31.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.696609525
Short name T241
Test name
Test status
Simulation time 559444881 ps
CPU time 1.83 seconds
Started Aug 25 02:16:15 AM UTC 24
Finished Aug 25 02:16:18 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696609525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.696609525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/31.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.2249518907
Short name T250
Test name
Test status
Simulation time 5956518414 ps
CPU time 19.68 seconds
Started Aug 25 02:16:20 AM UTC 24
Finished Aug 25 02:16:41 AM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249518907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2249518907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/32.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.4046100242
Short name T243
Test name
Test status
Simulation time 388334180 ps
CPU time 2 seconds
Started Aug 25 02:16:19 AM UTC 24
Finished Aug 25 02:16:22 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046100242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.4046100242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/32.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.2698801760
Short name T289
Test name
Test status
Simulation time 122566874435 ps
CPU time 263.24 seconds
Started Aug 25 02:16:24 AM UTC 24
Finished Aug 25 02:20:51 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698801760 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.2698801760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/32.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.1457426164
Short name T283
Test name
Test status
Simulation time 28530348020 ps
CPU time 93.43 seconds
Started Aug 25 02:16:25 AM UTC 24
Finished Aug 25 02:18:01 AM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457426164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1457426164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/33.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.2786508840
Short name T244
Test name
Test status
Simulation time 546754823 ps
CPU time 1.79 seconds
Started Aug 25 02:16:24 AM UTC 24
Finished Aug 25 02:16:27 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786508840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2786508840
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/33.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.3720425188
Short name T265
Test name
Test status
Simulation time 12562653790 ps
CPU time 40.17 seconds
Started Aug 25 02:16:28 AM UTC 24
Finished Aug 25 02:17:10 AM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720425188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3720425188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/34.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.2977378062
Short name T245
Test name
Test status
Simulation time 467984958 ps
CPU time 2.56 seconds
Started Aug 25 02:16:27 AM UTC 24
Finished Aug 25 02:16:31 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977378062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2977378062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/34.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.4164840586
Short name T248
Test name
Test status
Simulation time 15718932593 ps
CPU time 3.48 seconds
Started Aug 25 02:16:35 AM UTC 24
Finished Aug 25 02:16:39 AM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164840586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4164840586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/35.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.3924821075
Short name T246
Test name
Test status
Simulation time 462210426 ps
CPU time 2.2 seconds
Started Aug 25 02:16:34 AM UTC 24
Finished Aug 25 02:16:37 AM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924821075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3924821075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/35.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.1153523070
Short name T257
Test name
Test status
Simulation time 9388530151 ps
CPU time 14.05 seconds
Started Aug 25 02:16:38 AM UTC 24
Finished Aug 25 02:16:54 AM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153523070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1153523070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/36.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.1164965383
Short name T249
Test name
Test status
Simulation time 512432654 ps
CPU time 0.96 seconds
Started Aug 25 02:16:38 AM UTC 24
Finished Aug 25 02:16:40 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164965383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1164965383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/36.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.3889330019
Short name T288
Test name
Test status
Simulation time 44308897499 ps
CPU time 126.18 seconds
Started Aug 25 02:16:41 AM UTC 24
Finished Aug 25 02:18:50 AM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889330019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3889330019
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/37.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.2185037500
Short name T251
Test name
Test status
Simulation time 544945442 ps
CPU time 1.63 seconds
Started Aug 25 02:16:41 AM UTC 24
Finished Aug 25 02:16:44 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185037500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2185037500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/37.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.2995718565
Short name T181
Test name
Test status
Simulation time 360052793 ps
CPU time 1.97 seconds
Started Aug 25 02:16:45 AM UTC 24
Finished Aug 25 02:16:47 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995718565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2995718565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/38.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.3237569972
Short name T260
Test name
Test status
Simulation time 19468237622 ps
CPU time 14.59 seconds
Started Aug 25 02:16:44 AM UTC 24
Finished Aug 25 02:16:59 AM UTC 24
Peak memory 200900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237569972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3237569972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/38.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.2964156053
Short name T252
Test name
Test status
Simulation time 604685969 ps
CPU time 1.37 seconds
Started Aug 25 02:16:43 AM UTC 24
Finished Aug 25 02:16:46 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964156053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2964156053
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/38.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.3866226551
Short name T274
Test name
Test status
Simulation time 20955954292 ps
CPU time 39.52 seconds
Started Aug 25 02:16:48 AM UTC 24
Finished Aug 25 02:17:29 AM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866226551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3866226551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/39.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.1804997562
Short name T253
Test name
Test status
Simulation time 526999241 ps
CPU time 1.18 seconds
Started Aug 25 02:16:47 AM UTC 24
Finished Aug 25 02:16:49 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804997562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1804997562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/39.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.194400
Short name T212
Test name
Test status
Simulation time 25467786318 ps
CPU time 43.22 seconds
Started Aug 25 02:15:01 AM UTC 24
Finished Aug 25 02:15:59 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_
SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.194400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.3057374139
Short name T25
Test name
Test status
Simulation time 4476998393 ps
CPU time 17.66 seconds
Started Aug 25 02:15:01 AM UTC 24
Finished Aug 25 02:15:33 AM UTC 24
Peak memory 231256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057374139 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3057374139
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.2464784335
Short name T23
Test name
Test status
Simulation time 549079041 ps
CPU time 2.41 seconds
Started Aug 25 02:15:01 AM UTC 24
Finished Aug 25 02:15:18 AM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464784335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2464784335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/4.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.145349129
Short name T140
Test name
Test status
Simulation time 501357898 ps
CPU time 1.19 seconds
Started Aug 25 02:16:50 AM UTC 24
Finished Aug 25 02:16:53 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145349129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.145349129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/40.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.1559604343
Short name T278
Test name
Test status
Simulation time 17292076678 ps
CPU time 45.77 seconds
Started Aug 25 02:16:50 AM UTC 24
Finished Aug 25 02:17:38 AM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559604343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1559604343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/40.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.2470938893
Short name T255
Test name
Test status
Simulation time 485660417 ps
CPU time 1.55 seconds
Started Aug 25 02:16:49 AM UTC 24
Finished Aug 25 02:16:52 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470938893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2470938893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/40.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.3339326132
Short name T196
Test name
Test status
Simulation time 567083842 ps
CPU time 2.74 seconds
Started Aug 25 02:16:54 AM UTC 24
Finished Aug 25 02:16:59 AM UTC 24
Peak memory 200652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339326132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3339326132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/41.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.3767670049
Short name T279
Test name
Test status
Simulation time 29614078010 ps
CPU time 43.49 seconds
Started Aug 25 02:16:54 AM UTC 24
Finished Aug 25 02:17:39 AM UTC 24
Peak memory 200900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767670049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3767670049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/41.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.2921484217
Short name T258
Test name
Test status
Simulation time 381831912 ps
CPU time 2.09 seconds
Started Aug 25 02:16:53 AM UTC 24
Finished Aug 25 02:16:56 AM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921484217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2921484217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/41.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.1842421337
Short name T268
Test name
Test status
Simulation time 31003414510 ps
CPU time 15.85 seconds
Started Aug 25 02:16:55 AM UTC 24
Finished Aug 25 02:17:13 AM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842421337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1842421337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/42.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.128864578
Short name T259
Test name
Test status
Simulation time 521493031 ps
CPU time 2.21 seconds
Started Aug 25 02:16:54 AM UTC 24
Finished Aug 25 02:16:58 AM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128864578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.128864578
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/42.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.525572079
Short name T263
Test name
Test status
Simulation time 4906728692 ps
CPU time 4.3 seconds
Started Aug 25 02:17:00 AM UTC 24
Finished Aug 25 02:17:05 AM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525572079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.525572079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/43.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.3020332609
Short name T162
Test name
Test status
Simulation time 405549056 ps
CPU time 2.14 seconds
Started Aug 25 02:16:59 AM UTC 24
Finished Aug 25 02:17:02 AM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020332609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3020332609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/43.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.1171776038
Short name T266
Test name
Test status
Simulation time 3540002425 ps
CPU time 9.61 seconds
Started Aug 25 02:17:01 AM UTC 24
Finished Aug 25 02:17:12 AM UTC 24
Peak memory 216280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1171776038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 43.aon_timer_stress_all_with_rand_reset.1171776038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.1324162442
Short name T189
Test name
Test status
Simulation time 556170863 ps
CPU time 1.24 seconds
Started Aug 25 02:17:04 AM UTC 24
Finished Aug 25 02:17:06 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324162442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1324162442
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/44.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.3637000360
Short name T271
Test name
Test status
Simulation time 52062231567 ps
CPU time 14.52 seconds
Started Aug 25 02:17:03 AM UTC 24
Finished Aug 25 02:17:19 AM UTC 24
Peak memory 200900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637000360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3637000360
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/44.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.2414700095
Short name T262
Test name
Test status
Simulation time 588322178 ps
CPU time 1.88 seconds
Started Aug 25 02:17:02 AM UTC 24
Finished Aug 25 02:17:05 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414700095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2414700095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/44.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.3031385216
Short name T273
Test name
Test status
Simulation time 18757823481 ps
CPU time 14.1 seconds
Started Aug 25 02:17:07 AM UTC 24
Finished Aug 25 02:17:22 AM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031385216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3031385216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/45.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.1075999102
Short name T264
Test name
Test status
Simulation time 403377081 ps
CPU time 1.08 seconds
Started Aug 25 02:17:07 AM UTC 24
Finished Aug 25 02:17:09 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075999102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1075999102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/45.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.3203546630
Short name T277
Test name
Test status
Simulation time 30303877911 ps
CPU time 22.23 seconds
Started Aug 25 02:17:11 AM UTC 24
Finished Aug 25 02:17:35 AM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203546630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3203546630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/46.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.1812943265
Short name T267
Test name
Test status
Simulation time 477370590 ps
CPU time 1.37 seconds
Started Aug 25 02:17:09 AM UTC 24
Finished Aug 25 02:17:12 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812943265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1812943265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/46.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.3327482303
Short name T276
Test name
Test status
Simulation time 40564354216 ps
CPU time 15.53 seconds
Started Aug 25 02:17:12 AM UTC 24
Finished Aug 25 02:17:29 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327482303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3327482303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/47.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.571604887
Short name T269
Test name
Test status
Simulation time 453145284 ps
CPU time 1.17 seconds
Started Aug 25 02:17:12 AM UTC 24
Finished Aug 25 02:17:15 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571604887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.571604887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/47.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.4042828904
Short name T275
Test name
Test status
Simulation time 14993817699 ps
CPU time 13.19 seconds
Started Aug 25 02:17:15 AM UTC 24
Finished Aug 25 02:17:29 AM UTC 24
Peak memory 200296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042828904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4042828904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/48.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.3521639279
Short name T270
Test name
Test status
Simulation time 553886872 ps
CPU time 1.07 seconds
Started Aug 25 02:17:15 AM UTC 24
Finished Aug 25 02:17:17 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521639279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3521639279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/48.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.1258450385
Short name T280
Test name
Test status
Simulation time 30649366127 ps
CPU time 22.97 seconds
Started Aug 25 02:17:17 AM UTC 24
Finished Aug 25 02:17:41 AM UTC 24
Peak memory 200424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258450385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1258450385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/49.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.144121787
Short name T272
Test name
Test status
Simulation time 499729321 ps
CPU time 1.18 seconds
Started Aug 25 02:17:17 AM UTC 24
Finished Aug 25 02:17:19 AM UTC 24
Peak memory 199008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144121787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.144121787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/49.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.3040788381
Short name T229
Test name
Test status
Simulation time 42923861329 ps
CPU time 54.1 seconds
Started Aug 25 02:15:03 AM UTC 24
Finished Aug 25 02:15:59 AM UTC 24
Peak memory 200644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040788381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3040788381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.1370125570
Short name T5
Test name
Test status
Simulation time 362337968 ps
CPU time 2.09 seconds
Started Aug 25 02:15:03 AM UTC 24
Finished Aug 25 02:15:07 AM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370125570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1370125570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/5.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.3039140015
Short name T6
Test name
Test status
Simulation time 2425024864 ps
CPU time 3.45 seconds
Started Aug 25 02:15:03 AM UTC 24
Finished Aug 25 02:15:08 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039140015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3039140015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/6.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.248983104
Short name T85
Test name
Test status
Simulation time 11676427107 ps
CPU time 36.35 seconds
Started Aug 25 02:15:10 AM UTC 24
Finished Aug 25 02:15:51 AM UTC 24
Peak memory 200840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248983104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.248983104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.686610874
Short name T30
Test name
Test status
Simulation time 418091527 ps
CPU time 1.17 seconds
Started Aug 25 02:15:09 AM UTC 24
Finished Aug 25 02:15:18 AM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686610874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.686610874
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/7.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.1606788958
Short name T207
Test name
Test status
Simulation time 4073702844 ps
CPU time 12.75 seconds
Started Aug 25 02:15:13 AM UTC 24
Finished Aug 25 02:15:28 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606788958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1606788958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.4237820955
Short name T13
Test name
Test status
Simulation time 550182438 ps
CPU time 1.28 seconds
Started Aug 25 02:15:12 AM UTC 24
Finished Aug 25 02:15:17 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237820955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4237820955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/8.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.390684187
Short name T49
Test name
Test status
Simulation time 50266414236 ps
CPU time 8.44 seconds
Started Aug 25 02:15:15 AM UTC 24
Finished Aug 25 02:15:25 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390684187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.390684187
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.3942336099
Short name T12
Test name
Test status
Simulation time 378580453 ps
CPU time 1.46 seconds
Started Aug 25 02:15:13 AM UTC 24
Finished Aug 25 02:15:17 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942336099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3942336099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/9.aon_timer_smoke/latest
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