Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 19563 1 T1 10 T4 12 T5 11
bark[1] 196 1 T196 14 T47 5 T48 21
bark[2] 415 1 T95 129 T102 21 T191 26
bark[3] 599 1 T3 14 T37 21 T113 105
bark[4] 169 1 T195 14 T136 7 T170 14
bark[5] 261 1 T35 14 T149 21 T105 21
bark[6] 502 1 T7 49 T14 14 T33 14
bark[7] 307 1 T24 7 T26 51 T37 5
bark[8] 294 1 T37 56 T27 38 T189 14
bark[9] 565 1 T48 128 T95 21 T129 21
bark[10] 155 1 T188 14 T80 21 T160 30
bark[11] 471 1 T177 14 T24 21 T47 64
bark[12] 244 1 T178 14 T91 26 T126 21
bark[13] 349 1 T175 14 T105 52 T127 21
bark[14] 203 1 T50 5 T88 7 T137 23
bark[15] 379 1 T197 14 T129 98 T134 14
bark[16] 437 1 T79 138 T138 14 T142 14
bark[17] 295 1 T187 14 T26 99 T173 14
bark[18] 216 1 T46 5 T171 14 T149 21
bark[19] 391 1 T37 21 T113 176 T172 52
bark[20] 413 1 T50 21 T79 14 T136 5
bark[21] 569 1 T36 209 T95 5 T192 14
bark[22] 474 1 T30 14 T129 7 T105 21
bark[23] 493 1 T48 139 T106 21 T80 176
bark[24] 383 1 T47 21 T106 55 T113 21
bark[25] 686 1 T95 21 T79 21 T88 30
bark[26] 280 1 T2 14 T17 14 T26 40
bark[27] 292 1 T23 14 T34 14 T185 14
bark[28] 519 1 T47 21 T48 21 T149 21
bark[29] 461 1 T8 14 T24 21 T154 14
bark[30] 92 1 T27 26 T127 14 T111 26
bark[31] 302 1 T7 92 T26 21 T172 31
bark_0 5006 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 19161 1 T1 9 T3 13 T4 11
bite[1] 312 1 T34 13 T95 21 T136 21
bite[2] 321 1 T2 13 T79 137 T149 6
bite[3] 451 1 T17 13 T24 6 T37 83
bite[4] 686 1 T48 127 T127 25 T80 199
bite[5] 233 1 T177 13 T169 13 T188 13
bite[6] 263 1 T26 21 T37 21 T106 21
bite[7] 354 1 T14 13 T105 51 T113 104
bite[8] 600 1 T113 170 T88 6 T127 21
bite[9] 533 1 T37 4 T95 128 T79 130
bite[10] 159 1 T175 13 T195 13 T173 13
bite[11] 390 1 T36 208 T95 59 T155 13
bite[12] 512 1 T30 13 T48 21 T27 35
bite[13] 386 1 T23 13 T154 13 T129 21
bite[14] 249 1 T105 6 T102 21 T160 21
bite[15] 351 1 T33 13 T48 25 T80 42
bite[16] 677 1 T26 72 T105 72 T111 354
bite[17] 242 1 T26 78 T49 39 T178 13
bite[18] 84 1 T37 21 T97 21 T109 21
bite[19] 193 1 T8 13 T192 13 T162 26
bite[20] 267 1 T47 4 T37 55 T134 13
bite[21] 405 1 T185 13 T37 21 T149 42
bite[22] 368 1 T47 21 T138 13 T103 21
bite[23] 475 1 T7 92 T24 21 T26 40
bite[24] 364 1 T35 13 T197 13 T50 4
bite[25] 360 1 T7 49 T50 21 T27 38
bite[26] 430 1 T48 21 T102 21 T127 30
bite[27] 402 1 T88 234 T87 38 T152 13
bite[28] 310 1 T47 6 T95 21 T189 13
bite[29] 463 1 T187 13 T196 13 T171 13
bite[30] 242 1 T47 13 T85 70 T160 30
bite[31] 145 1 T24 21 T46 4 T106 55
bite_0 5593 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32735 1 T1 17 T2 21 T3 21
auto[1] 3246 1 T6 7 T7 34 T13 7


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 370 1 T4 9 T206 9 T149 2
prescale[1] 493 1 T36 2 T47 46 T37 42
prescale[2] 367 1 T7 71 T36 9 T105 2
prescale[3] 102 1 T24 2 T37 2 T91 54
prescale[4] 631 1 T24 66 T46 2 T48 2
prescale[5] 560 1 T21 9 T36 80 T95 135
prescale[6] 599 1 T50 2 T207 9 T149 92
prescale[7] 351 1 T49 113 T95 36 T146 36
prescale[8] 312 1 T36 54 T47 19 T129 2
prescale[9] 540 1 T37 67 T49 2 T27 18
prescale[10] 261 1 T36 30 T208 9 T48 2
prescale[11] 522 1 T22 2 T47 9 T149 21
prescale[12] 584 1 T15 2 T20 9 T36 19
prescale[13] 165 1 T24 9 T49 19 T191 14
prescale[14] 380 1 T24 9 T95 2 T80 232
prescale[15] 509 1 T36 54 T49 2 T162 44
prescale[16] 290 1 T47 92 T79 2 T136 23
prescale[17] 345 1 T37 60 T48 45 T79 40
prescale[18] 231 1 T24 4 T48 43 T106 23
prescale[19] 757 1 T24 217 T37 78 T129 19
prescale[20] 523 1 T37 2 T79 55 T209 9
prescale[21] 398 1 T15 2 T24 36 T210 9
prescale[22] 494 1 T26 19 T47 19 T95 52
prescale[23] 522 1 T19 9 T22 2 T36 51
prescale[24] 389 1 T211 9 T22 2 T26 40
prescale[25] 261 1 T24 39 T46 2 T27 28
prescale[26] 362 1 T84 9 T24 2 T48 40
prescale[27] 618 1 T49 87 T149 65 T212 9
prescale[28] 479 1 T15 2 T48 2 T106 9
prescale[29] 343 1 T24 57 T46 2 T213 9
prescale[30] 635 1 T7 23 T37 81 T48 2
prescale[31] 451 1 T214 9 T26 23 T215 9
prescale_0 22137 1 T1 17 T2 21 T3 21


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23900 1 T1 17 T2 21 T3 21
auto[1] 12081 1 T5 9 T6 9 T7 36


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 35981 1 T1 17 T2 21 T3 21


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 20413 1 T1 12 T2 1 T3 1
wkup[1] 247 1 T24 21 T79 31 T191 6
wkup[2] 99 1 T188 15 T102 21 T137 21
wkup[3] 205 1 T48 21 T88 8 T146 8
wkup[4] 340 1 T26 21 T79 21 T178 15
wkup[5] 92 1 T47 35 T37 21 T50 15
wkup[6] 136 1 T17 15 T175 15 T105 21
wkup[7] 220 1 T79 21 T149 8 T113 30
wkup[8] 155 1 T7 21 T8 15 T171 15
wkup[9] 178 1 T27 35 T79 21 T80 21
wkup[10] 176 1 T37 15 T79 6 T129 8
wkup[11] 254 1 T7 26 T36 21 T50 21
wkup[12] 163 1 T49 21 T95 6 T113 21
wkup[13] 84 1 T192 15 T80 21 T81 6
wkup[14] 219 1 T24 45 T49 6 T195 15
wkup[15] 65 1 T93 39 T165 26 - -
wkup[16] 280 1 T23 15 T149 39 T191 21
wkup[17] 221 1 T36 15 T162 26 T173 15
wkup[18] 120 1 T187 15 T37 21 T50 6
wkup[19] 147 1 T149 42 T80 21 T166 21
wkup[20] 56 1 T159 21 T107 35 - -
wkup[21] 326 1 T24 8 T36 15 T37 21
wkup[22] 182 1 T3 15 T50 15 T136 21
wkup[23] 157 1 T37 21 T129 21 T111 26
wkup[24] 215 1 T50 21 T95 21 T88 48
wkup[25] 131 1 T37 21 T27 21 T88 21
wkup[26] 165 1 T47 21 T88 21 T111 60
wkup[27] 230 1 T26 21 T50 21 T149 21
wkup[28] 128 1 T30 15 T162 29 T191 21
wkup[29] 298 1 T33 15 T24 26 T26 21
wkup[30] 149 1 T24 21 T37 21 T149 21
wkup[31] 168 1 T14 15 T49 24 T95 21
wkup[32] 190 1 T7 21 T47 8 T49 35
wkup[33] 197 1 T27 21 T105 30 T113 21
wkup[34] 269 1 T35 15 T37 21 T27 26
wkup[35] 119 1 T24 21 T95 30 T104 21
wkup[36] 265 1 T37 42 T48 21 T154 15
wkup[37] 165 1 T7 21 T24 21 T155 15
wkup[38] 137 1 T47 6 T48 42 T111 26
wkup[39] 113 1 T24 21 T136 26 T117 21
wkup[40] 257 1 T37 24 T48 26 T95 21
wkup[41] 192 1 T177 15 T26 21 T37 21
wkup[42] 173 1 T37 42 T48 21 T111 21
wkup[43] 283 1 T36 21 T105 8 T127 21
wkup[44] 78 1 T24 21 T157 15 T109 21
wkup[45] 114 1 T37 6 T105 21 T199 15
wkup[46] 259 1 T46 6 T47 15 T49 21
wkup[47] 212 1 T2 15 T26 21 T36 21
wkup[48] 204 1 T80 42 T170 15 T118 8
wkup[49] 203 1 T48 21 T113 21 T85 21
wkup[50] 122 1 T129 21 T117 21 T126 21
wkup[51] 154 1 T34 15 T143 8 T181 21
wkup[52] 224 1 T7 30 T24 21 T80 21
wkup[53] 156 1 T105 21 T80 21 T135 15
wkup[54] 186 1 T136 21 T138 15 T113 21
wkup[55] 125 1 T158 15 T88 21 T80 21
wkup[56] 157 1 T196 15 T185 15 T79 8
wkup[57] 163 1 T127 30 T172 6 T123 15
wkup[58] 260 1 T26 30 T103 21 T117 21
wkup[59] 213 1 T197 15 T37 21 T48 6
wkup[60] 269 1 T26 21 T143 21 T117 21
wkup[61] 192 1 T24 35 T85 30 T81 21
wkup[62] 189 1 T48 8 T142 15 T102 21
wkup[63] 171 1 T48 21 T147 15 T97 21
wkup_0 3951 1 T1 5 T2 5 T3 5

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