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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.75 99.33 95.61 100.00 98.40 99.51 45.64


Total test records in report: 426
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T184 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.4071849589 Aug 27 07:58:00 PM UTC 24 Aug 27 08:18:03 PM UTC 24 675023233928 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.4052808690 Aug 27 07:59:26 PM UTC 24 Aug 27 07:59:28 PM UTC 24 356146926 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.1489826567 Aug 27 07:59:26 PM UTC 24 Aug 27 07:59:28 PM UTC 24 292291777 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.2801525902 Aug 27 07:59:24 PM UTC 24 Aug 27 07:59:29 PM UTC 24 520116231 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3274647989 Aug 27 07:59:27 PM UTC 24 Aug 27 07:59:29 PM UTC 24 517657619 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.2909898269 Aug 27 07:59:28 PM UTC 24 Aug 27 07:59:31 PM UTC 24 354095069 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1671286205 Aug 27 07:59:29 PM UTC 24 Aug 27 07:59:31 PM UTC 24 550304962 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2866183088 Aug 27 07:59:28 PM UTC 24 Aug 27 07:59:32 PM UTC 24 1275625740 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2430256253 Aug 27 07:59:30 PM UTC 24 Aug 27 07:59:33 PM UTC 24 468987050 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.3490600118 Aug 27 07:59:32 PM UTC 24 Aug 27 07:59:35 PM UTC 24 442766844 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.960360409 Aug 27 07:59:34 PM UTC 24 Aug 27 07:59:36 PM UTC 24 742308355 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.780007092 Aug 27 07:59:34 PM UTC 24 Aug 27 07:59:36 PM UTC 24 499637648 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3835982584 Aug 27 07:59:33 PM UTC 24 Aug 27 07:59:36 PM UTC 24 497715469 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2040585602 Aug 27 07:59:31 PM UTC 24 Aug 27 07:59:36 PM UTC 24 316247205 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1104322457 Aug 27 07:59:34 PM UTC 24 Aug 27 07:59:36 PM UTC 24 361708336 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1116831153 Aug 27 07:59:30 PM UTC 24 Aug 27 07:59:37 PM UTC 24 1926294704 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.404879935 Aug 27 07:59:32 PM UTC 24 Aug 27 07:59:38 PM UTC 24 4361510218 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1555018985 Aug 27 07:59:29 PM UTC 24 Aug 27 07:59:38 PM UTC 24 14528654990 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2328525972 Aug 27 07:59:36 PM UTC 24 Aug 27 07:59:39 PM UTC 24 443432325 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3353690195 Aug 27 07:59:37 PM UTC 24 Aug 27 07:59:39 PM UTC 24 456620636 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.1794294854 Aug 27 07:59:37 PM UTC 24 Aug 27 07:59:39 PM UTC 24 412290522 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.876311790 Aug 27 07:59:37 PM UTC 24 Aug 27 07:59:40 PM UTC 24 1030323681 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1180790413 Aug 27 07:59:26 PM UTC 24 Aug 27 07:59:40 PM UTC 24 8288666158 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.3229991596 Aug 27 07:59:38 PM UTC 24 Aug 27 07:59:40 PM UTC 24 343994573 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3870142686 Aug 27 07:59:37 PM UTC 24 Aug 27 07:59:41 PM UTC 24 1678983787 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1183084097 Aug 27 07:59:39 PM UTC 24 Aug 27 07:59:41 PM UTC 24 571248065 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1744267985 Aug 27 07:59:39 PM UTC 24 Aug 27 07:59:41 PM UTC 24 375393433 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2853490697 Aug 27 07:59:39 PM UTC 24 Aug 27 07:59:42 PM UTC 24 662241882 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.2022588444 Aug 27 07:59:41 PM UTC 24 Aug 27 07:59:42 PM UTC 24 279474281 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.90131758 Aug 27 07:59:40 PM UTC 24 Aug 27 07:59:43 PM UTC 24 541999997 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.592183101 Aug 27 07:59:39 PM UTC 24 Aug 27 07:59:43 PM UTC 24 489456616 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2125680178 Aug 27 07:59:42 PM UTC 24 Aug 27 07:59:44 PM UTC 24 441431807 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.4039016493 Aug 27 07:59:42 PM UTC 24 Aug 27 07:59:44 PM UTC 24 481768059 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2331950777 Aug 27 07:59:40 PM UTC 24 Aug 27 07:59:44 PM UTC 24 479965904 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4119005454 Aug 27 07:59:34 PM UTC 24 Aug 27 07:59:44 PM UTC 24 7123479706 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3194254978 Aug 27 07:59:43 PM UTC 24 Aug 27 07:59:45 PM UTC 24 595637846 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.524828074 Aug 27 07:59:43 PM UTC 24 Aug 27 07:59:45 PM UTC 24 416469946 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2720775908 Aug 27 07:59:42 PM UTC 24 Aug 27 07:59:46 PM UTC 24 1164358737 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.776924810 Aug 27 07:59:44 PM UTC 24 Aug 27 07:59:46 PM UTC 24 378013022 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2241164989 Aug 27 07:59:44 PM UTC 24 Aug 27 07:59:47 PM UTC 24 2262916560 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3284504246 Aug 27 07:59:40 PM UTC 24 Aug 27 07:59:47 PM UTC 24 2312874718 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2200076727 Aug 27 07:59:45 PM UTC 24 Aug 27 07:59:47 PM UTC 24 353905540 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.1051175180 Aug 27 07:59:45 PM UTC 24 Aug 27 07:59:47 PM UTC 24 344765466 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3649846038 Aug 27 07:59:46 PM UTC 24 Aug 27 07:59:48 PM UTC 24 415105370 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2223404671 Aug 27 07:59:45 PM UTC 24 Aug 27 07:59:48 PM UTC 24 488968868 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2086782833 Aug 27 07:59:46 PM UTC 24 Aug 27 07:59:48 PM UTC 24 770583353 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.613321123 Aug 27 07:59:43 PM UTC 24 Aug 27 07:59:49 PM UTC 24 6962745916 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.3798283832 Aug 27 07:59:45 PM UTC 24 Aug 27 07:59:49 PM UTC 24 533243255 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2641230745 Aug 27 07:59:47 PM UTC 24 Aug 27 07:59:49 PM UTC 24 966903534 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.22577901 Aug 27 07:59:47 PM UTC 24 Aug 27 07:59:49 PM UTC 24 701567850 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1907579652 Aug 27 07:59:47 PM UTC 24 Aug 27 07:59:49 PM UTC 24 488108548 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.134208506 Aug 27 07:59:48 PM UTC 24 Aug 27 07:59:50 PM UTC 24 470820061 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.739615470 Aug 27 07:59:48 PM UTC 24 Aug 27 07:59:50 PM UTC 24 480292602 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3389507427 Aug 27 07:59:49 PM UTC 24 Aug 27 07:59:51 PM UTC 24 438285048 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2499020245 Aug 27 07:59:41 PM UTC 24 Aug 27 07:59:52 PM UTC 24 8584046455 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.2663387013 Aug 27 07:59:48 PM UTC 24 Aug 27 07:59:52 PM UTC 24 538229750 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.4285978917 Aug 27 07:59:50 PM UTC 24 Aug 27 07:59:52 PM UTC 24 477875728 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.30866086 Aug 27 07:59:49 PM UTC 24 Aug 27 07:59:52 PM UTC 24 2579295325 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.391226449 Aug 27 07:59:50 PM UTC 24 Aug 27 07:59:53 PM UTC 24 431819332 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1116164048 Aug 27 07:59:50 PM UTC 24 Aug 27 07:59:53 PM UTC 24 1419111367 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.3317773892 Aug 27 07:59:52 PM UTC 24 Aug 27 07:59:54 PM UTC 24 273943492 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.998438133 Aug 27 07:59:50 PM UTC 24 Aug 27 07:59:54 PM UTC 24 448191076 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.3408661835 Aug 27 07:59:51 PM UTC 24 Aug 27 07:59:55 PM UTC 24 730892221 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.1904970090 Aug 27 07:59:49 PM UTC 24 Aug 27 07:59:55 PM UTC 24 422485359 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.4220606047 Aug 27 07:59:53 PM UTC 24 Aug 27 07:59:55 PM UTC 24 536352596 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.524126292 Aug 27 07:59:45 PM UTC 24 Aug 27 07:59:56 PM UTC 24 4624836274 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.1287829183 Aug 27 07:59:53 PM UTC 24 Aug 27 07:59:56 PM UTC 24 527246670 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2758912587 Aug 27 07:59:53 PM UTC 24 Aug 27 07:59:56 PM UTC 24 459346028 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3406936637 Aug 27 07:59:53 PM UTC 24 Aug 27 07:59:57 PM UTC 24 2076266798 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3994335852 Aug 27 07:59:37 PM UTC 24 Aug 27 07:59:57 PM UTC 24 7639513193 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.1599103828 Aug 27 07:59:53 PM UTC 24 Aug 27 07:59:57 PM UTC 24 431725754 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1850692873 Aug 27 07:59:54 PM UTC 24 Aug 27 07:59:57 PM UTC 24 534179246 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2854458740 Aug 27 07:59:48 PM UTC 24 Aug 27 07:59:57 PM UTC 24 4535758098 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.4072491080 Aug 27 07:59:53 PM UTC 24 Aug 27 07:59:57 PM UTC 24 431859217 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1817204768 Aug 27 07:59:50 PM UTC 24 Aug 27 07:59:57 PM UTC 24 4451546417 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1366006369 Aug 27 07:59:57 PM UTC 24 Aug 27 08:00:00 PM UTC 24 440177807 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1921450872 Aug 27 07:59:55 PM UTC 24 Aug 27 07:59:58 PM UTC 24 432989209 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.2144516223 Aug 27 07:59:56 PM UTC 24 Aug 27 07:59:59 PM UTC 24 473257256 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1303643850 Aug 27 07:59:53 PM UTC 24 Aug 27 07:59:59 PM UTC 24 2200509388 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.551284835 Aug 27 07:59:57 PM UTC 24 Aug 27 07:59:59 PM UTC 24 416505505 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.619157036 Aug 27 07:59:53 PM UTC 24 Aug 27 08:00:00 PM UTC 24 7812196824 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.2441031512 Aug 27 07:59:56 PM UTC 24 Aug 27 08:00:00 PM UTC 24 423785415 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.605786022 Aug 27 07:59:58 PM UTC 24 Aug 27 08:00:00 PM UTC 24 504645709 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1054457502 Aug 27 07:59:57 PM UTC 24 Aug 27 08:00:00 PM UTC 24 2933077627 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.756143717 Aug 27 07:59:58 PM UTC 24 Aug 27 08:00:01 PM UTC 24 557492132 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.743461118 Aug 27 07:59:58 PM UTC 24 Aug 27 08:00:01 PM UTC 24 363789766 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1483615079 Aug 27 07:59:52 PM UTC 24 Aug 27 08:00:01 PM UTC 24 8299164018 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2531435428 Aug 27 07:59:58 PM UTC 24 Aug 27 08:00:01 PM UTC 24 1301361605 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3102482415 Aug 27 07:59:59 PM UTC 24 Aug 27 08:00:02 PM UTC 24 385487407 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.552338263 Aug 27 07:59:55 PM UTC 24 Aug 27 08:00:02 PM UTC 24 8150478166 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1843155794 Aug 27 07:59:58 PM UTC 24 Aug 27 08:00:02 PM UTC 24 523558480 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.3214308026 Aug 27 07:59:59 PM UTC 24 Aug 27 08:00:02 PM UTC 24 361622364 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2258724914 Aug 27 07:59:58 PM UTC 24 Aug 27 08:00:03 PM UTC 24 525203830 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1552904358 Aug 27 07:59:47 PM UTC 24 Aug 27 08:00:03 PM UTC 24 6837408134 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2685720827 Aug 27 07:59:59 PM UTC 24 Aug 27 08:00:03 PM UTC 24 1243844668 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3259789517 Aug 27 07:59:57 PM UTC 24 Aug 27 08:00:04 PM UTC 24 7785379683 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2754346091 Aug 27 08:00:01 PM UTC 24 Aug 27 08:00:06 PM UTC 24 604072486 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2086943198 Aug 27 08:00:01 PM UTC 24 Aug 27 08:00:06 PM UTC 24 1636858193 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.595270256 Aug 27 08:00:00 PM UTC 24 Aug 27 08:00:07 PM UTC 24 304191136 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.424808515 Aug 27 07:59:58 PM UTC 24 Aug 27 08:00:07 PM UTC 24 4416618893 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1004046304 Aug 27 08:00:02 PM UTC 24 Aug 27 08:00:07 PM UTC 24 347510051 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2093783150 Aug 27 08:00:02 PM UTC 24 Aug 27 08:00:07 PM UTC 24 373121335 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.918870060 Aug 27 08:00:01 PM UTC 24 Aug 27 08:00:08 PM UTC 24 526353294 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.641531784 Aug 27 08:00:02 PM UTC 24 Aug 27 08:00:08 PM UTC 24 388827325 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3635181443 Aug 27 08:00:00 PM UTC 24 Aug 27 08:00:08 PM UTC 24 677481678 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.36841431 Aug 27 08:00:02 PM UTC 24 Aug 27 08:00:08 PM UTC 24 3004993254 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1192351427 Aug 27 08:00:00 PM UTC 24 Aug 27 08:00:08 PM UTC 24 4329218807 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3907960250 Aug 27 08:00:02 PM UTC 24 Aug 27 08:00:08 PM UTC 24 4532932572 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3138224352 Aug 27 08:00:01 PM UTC 24 Aug 27 08:00:08 PM UTC 24 564276277 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.3622431790 Aug 27 08:00:06 PM UTC 24 Aug 27 08:00:08 PM UTC 24 453831077 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.1181298847 Aug 27 08:00:06 PM UTC 24 Aug 27 08:00:09 PM UTC 24 529507498 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.127850921 Aug 27 08:00:07 PM UTC 24 Aug 27 08:00:09 PM UTC 24 389042279 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.2707821566 Aug 27 08:00:06 PM UTC 24 Aug 27 08:00:09 PM UTC 24 521892275 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.415114980 Aug 27 08:00:06 PM UTC 24 Aug 27 08:00:09 PM UTC 24 1398249607 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1129642064 Aug 27 08:00:06 PM UTC 24 Aug 27 08:00:09 PM UTC 24 946984383 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.1990565408 Aug 27 08:00:06 PM UTC 24 Aug 27 08:00:10 PM UTC 24 470897904 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.347382726 Aug 27 08:00:08 PM UTC 24 Aug 27 08:00:10 PM UTC 24 452848589 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.2583159480 Aug 27 08:00:08 PM UTC 24 Aug 27 08:00:10 PM UTC 24 288478358 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.894281182 Aug 27 08:00:06 PM UTC 24 Aug 27 08:00:10 PM UTC 24 4552605881 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.3203984978 Aug 27 08:00:06 PM UTC 24 Aug 27 08:00:10 PM UTC 24 901662236 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.171844893 Aug 27 08:00:08 PM UTC 24 Aug 27 08:00:10 PM UTC 24 454147418 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3448007873 Aug 27 08:00:08 PM UTC 24 Aug 27 08:00:10 PM UTC 24 2016929798 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3343277722 Aug 27 08:00:09 PM UTC 24 Aug 27 08:00:11 PM UTC 24 1511091441 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.679135028 Aug 27 08:00:13 PM UTC 24 Aug 27 08:00:16 PM UTC 24 371832828 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.3812998936 Aug 27 08:00:08 PM UTC 24 Aug 27 08:00:11 PM UTC 24 357377782 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2253564009 Aug 27 08:00:09 PM UTC 24 Aug 27 08:00:11 PM UTC 24 445175634 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3361863250 Aug 27 07:59:39 PM UTC 24 Aug 27 08:00:11 PM UTC 24 11672718230 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2094040616 Aug 27 08:00:09 PM UTC 24 Aug 27 08:00:11 PM UTC 24 397352590 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.3813163518 Aug 27 08:00:09 PM UTC 24 Aug 27 08:00:11 PM UTC 24 306135109 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.1196148064 Aug 27 08:00:09 PM UTC 24 Aug 27 08:00:11 PM UTC 24 552654017 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.2348210837 Aug 27 08:00:09 PM UTC 24 Aug 27 08:00:11 PM UTC 24 328677033 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2794101551 Aug 27 08:00:09 PM UTC 24 Aug 27 08:00:12 PM UTC 24 1879324994 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1499212436 Aug 27 08:00:09 PM UTC 24 Aug 27 08:00:13 PM UTC 24 510397866 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.828650293 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:13 PM UTC 24 513881482 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.3555382566 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:13 PM UTC 24 470760722 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.2520590696 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:13 PM UTC 24 502149728 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.27303477 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:13 PM UTC 24 491681408 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.2996403375 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:13 PM UTC 24 506018282 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.4156178444 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:13 PM UTC 24 346367826 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.2756275932 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:13 PM UTC 24 476066498 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1441209581 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:14 PM UTC 24 490622780 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2457751737 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:14 PM UTC 24 540340301 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.179506290 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:14 PM UTC 24 1113035146 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.3125154023 Aug 27 08:00:12 PM UTC 24 Aug 27 08:00:14 PM UTC 24 403493333 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2651968563 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:14 PM UTC 24 2928897526 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.3756806941 Aug 27 08:00:12 PM UTC 24 Aug 27 08:00:14 PM UTC 24 519286819 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.980754441 Aug 27 08:00:12 PM UTC 24 Aug 27 08:00:14 PM UTC 24 345404698 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.1403102306 Aug 27 08:00:12 PM UTC 24 Aug 27 08:00:14 PM UTC 24 526663172 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.1038874138 Aug 27 08:00:12 PM UTC 24 Aug 27 08:00:14 PM UTC 24 374067756 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2000584377 Aug 27 08:00:12 PM UTC 24 Aug 27 08:00:14 PM UTC 24 291162404 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.1248045 Aug 27 08:00:12 PM UTC 24 Aug 27 08:00:14 PM UTC 24 488531126 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.4043375941 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:14 PM UTC 24 555447578 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.2410034220 Aug 27 08:00:12 PM UTC 24 Aug 27 08:00:15 PM UTC 24 443512405 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.40635902 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:15 PM UTC 24 4355834004 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.1638642540 Aug 27 08:00:13 PM UTC 24 Aug 27 08:00:16 PM UTC 24 351904840 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.1245467319 Aug 27 08:00:14 PM UTC 24 Aug 27 08:00:16 PM UTC 24 403855522 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.3931122843 Aug 27 08:00:14 PM UTC 24 Aug 27 08:00:16 PM UTC 24 360027723 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.906128694 Aug 27 08:00:14 PM UTC 24 Aug 27 08:00:16 PM UTC 24 348701185 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.1271485087 Aug 27 08:00:14 PM UTC 24 Aug 27 08:00:16 PM UTC 24 281373299 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.1645271051 Aug 27 08:00:14 PM UTC 24 Aug 27 08:00:16 PM UTC 24 430347798 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1440657769 Aug 27 08:00:08 PM UTC 24 Aug 27 08:00:17 PM UTC 24 4228464319 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.199320712 Aug 27 08:00:11 PM UTC 24 Aug 27 08:00:17 PM UTC 24 4317381839 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.2921160612 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:17 PM UTC 24 313127933 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.4121543783 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:17 PM UTC 24 412724761 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.245745611 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:17 PM UTC 24 431951365 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.4076065108 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:17 PM UTC 24 511708910 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.3757329090 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:17 PM UTC 24 316879472 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.480200375 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:17 PM UTC 24 400467920 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.787695433 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:17 PM UTC 24 539213825 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.2558800503 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:18 PM UTC 24 316844110 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.2375557774 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:18 PM UTC 24 459960222 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.3737766383 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:18 PM UTC 24 396005948 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.527454698 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:18 PM UTC 24 374350411 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.9246412 Aug 27 08:00:15 PM UTC 24 Aug 27 08:00:18 PM UTC 24 392661401 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3669462386 Aug 27 08:00:09 PM UTC 24 Aug 27 08:00:19 PM UTC 24 4466774826 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1538419150 Aug 27 08:00:06 PM UTC 24 Aug 27 08:00:21 PM UTC 24 8196266395 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.1515156078
Short name T7
Test name
Test status
Simulation time 11975353913 ps
CPU time 4.99 seconds
Started Aug 27 07:56:46 PM UTC 24
Finished Aug 27 07:56:52 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515156078 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.1515156078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.2576494292
Short name T24
Test name
Test status
Simulation time 9099302356 ps
CPU time 21.25 seconds
Started Aug 27 07:56:50 PM UTC 24
Finished Aug 27 07:57:13 PM UTC 24
Peak memory 215560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2576494292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 2.aon_timer_stress_all_with_rand_reset.2576494292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.1588372531
Short name T11
Test name
Test status
Simulation time 4025774627 ps
CPU time 2.26 seconds
Started Aug 27 07:56:45 PM UTC 24
Finished Aug 27 07:56:49 PM UTC 24
Peak memory 230880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588372531 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1588372531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2328525972
Short name T53
Test name
Test status
Simulation time 443432325 ps
CPU time 2.03 seconds
Started Aug 27 07:59:36 PM UTC 24
Finished Aug 27 07:59:39 PM UTC 24
Peak memory 203264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328525972 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.2328525972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.2956976851
Short name T88
Test name
Test status
Simulation time 13552606361 ps
CPU time 30.46 seconds
Started Aug 27 07:57:33 PM UTC 24
Finished Aug 27 07:58:05 PM UTC 24
Peak memory 219200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2956976851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 19.aon_timer_stress_all_with_rand_reset.2956976851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.293131723
Short name T8
Test name
Test status
Simulation time 467644582 ps
CPU time 1.16 seconds
Started Aug 27 07:56:50 PM UTC 24
Finished Aug 27 07:56:52 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293131723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.293131723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.2098548464
Short name T127
Test name
Test status
Simulation time 6025840572 ps
CPU time 46.08 seconds
Started Aug 27 07:57:23 PM UTC 24
Finished Aug 27 07:58:11 PM UTC 24
Peak memory 219612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2098548464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 16.aon_timer_stress_all_with_rand_reset.2098548464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.245498502
Short name T100
Test name
Test status
Simulation time 132659035803 ps
CPU time 204.27 seconds
Started Aug 27 07:57:39 PM UTC 24
Finished Aug 27 08:01:06 PM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245498502 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.245498502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/22.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.1153486563
Short name T117
Test name
Test status
Simulation time 9807941462 ps
CPU time 49.69 seconds
Started Aug 27 07:57:41 PM UTC 24
Finished Aug 27 07:58:32 PM UTC 24
Peak memory 215316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1153486563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 23.aon_timer_stress_all_with_rand_reset.1153486563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.3458019000
Short name T114
Test name
Test status
Simulation time 32926905489 ps
CPU time 42.17 seconds
Started Aug 27 07:59:00 PM UTC 24
Finished Aug 27 07:59:44 PM UTC 24
Peak memory 220076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3458019000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 42.aon_timer_stress_all_with_rand_reset.3458019000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.1070741864
Short name T104
Test name
Test status
Simulation time 3462422582 ps
CPU time 19.74 seconds
Started Aug 27 07:58:52 PM UTC 24
Finished Aug 27 07:59:13 PM UTC 24
Peak memory 215436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1070741864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 40.aon_timer_stress_all_with_rand_reset.1070741864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.292436571
Short name T85
Test name
Test status
Simulation time 95883527901 ps
CPU time 78.29 seconds
Started Aug 27 07:57:16 PM UTC 24
Finished Aug 27 07:58:36 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292436571 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.292436571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.3508500645
Short name T80
Test name
Test status
Simulation time 13624549502 ps
CPU time 28.21 seconds
Started Aug 27 07:57:44 PM UTC 24
Finished Aug 27 07:58:13 PM UTC 24
Peak memory 214068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3508500645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 24.aon_timer_stress_all_with_rand_reset.3508500645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.102744916
Short name T48
Test name
Test status
Simulation time 7024541696 ps
CPU time 29.58 seconds
Started Aug 27 07:56:57 PM UTC 24
Finished Aug 27 07:57:28 PM UTC 24
Peak memory 217484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=102744916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.aon_timer_stress_all_with_rand_reset.102744916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.943981081
Short name T111
Test name
Test status
Simulation time 10887062677 ps
CPU time 49.89 seconds
Started Aug 27 07:57:28 PM UTC 24
Finished Aug 27 07:58:19 PM UTC 24
Peak memory 211864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=943981081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 17.aon_timer_stress_all_with_rand_reset.943981081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.2749645759
Short name T97
Test name
Test status
Simulation time 5383857169 ps
CPU time 21.06 seconds
Started Aug 27 07:58:16 PM UTC 24
Finished Aug 27 07:58:39 PM UTC 24
Peak memory 215352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2749645759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 33.aon_timer_stress_all_with_rand_reset.2749645759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.2954771022
Short name T86
Test name
Test status
Simulation time 8145283850 ps
CPU time 19.76 seconds
Started Aug 27 07:58:36 PM UTC 24
Finished Aug 27 07:58:57 PM UTC 24
Peak memory 214216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2954771022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 36.aon_timer_stress_all_with_rand_reset.2954771022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.3490962809
Short name T103
Test name
Test status
Simulation time 94053973356 ps
CPU time 79.04 seconds
Started Aug 27 07:56:52 PM UTC 24
Finished Aug 27 07:58:13 PM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490962809 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.3490962809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.3407262238
Short name T26
Test name
Test status
Simulation time 135446461205 ps
CPU time 11.18 seconds
Started Aug 27 07:57:05 PM UTC 24
Finished Aug 27 07:57:17 PM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407262238 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.3407262238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.808941789
Short name T149
Test name
Test status
Simulation time 7006502152 ps
CPU time 49.09 seconds
Started Aug 27 07:56:52 PM UTC 24
Finished Aug 27 07:57:43 PM UTC 24
Peak memory 218512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=808941789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 5.aon_timer_stress_all_with_rand_reset.808941789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.3312802046
Short name T125
Test name
Test status
Simulation time 180688076659 ps
CPU time 74.49 seconds
Started Aug 27 07:58:11 PM UTC 24
Finished Aug 27 07:59:27 PM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312802046 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.3312802046
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/31.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.1992271235
Short name T37
Test name
Test status
Simulation time 10335599048 ps
CPU time 39.74 seconds
Started Aug 27 07:56:46 PM UTC 24
Finished Aug 27 07:57:27 PM UTC 24
Peak memory 206560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1992271235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 1.aon_timer_stress_all_with_rand_reset.1992271235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.2490743692
Short name T120
Test name
Test status
Simulation time 11151226262 ps
CPU time 5.96 seconds
Started Aug 27 07:59:10 PM UTC 24
Finished Aug 27 07:59:17 PM UTC 24
Peak memory 200896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490743692 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.2490743692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/44.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.4013804454
Short name T122
Test name
Test status
Simulation time 60288277378 ps
CPU time 48.01 seconds
Started Aug 27 07:58:43 PM UTC 24
Finished Aug 27 07:59:32 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013804454 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.4013804454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/38.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1180790413
Short name T42
Test name
Test status
Simulation time 8288666158 ps
CPU time 13.02 seconds
Started Aug 27 07:59:26 PM UTC 24
Finished Aug 27 07:59:40 PM UTC 24
Peak memory 206864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180790413 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.1180790413
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.4071659251
Short name T102
Test name
Test status
Simulation time 53999230906 ps
CPU time 29.72 seconds
Started Aug 27 07:57:38 PM UTC 24
Finished Aug 27 07:58:09 PM UTC 24
Peak memory 201052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071659251 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.4071659251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/21.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.3050821897
Short name T93
Test name
Test status
Simulation time 306976777517 ps
CPU time 89.14 seconds
Started Aug 27 07:59:20 PM UTC 24
Finished Aug 27 08:00:51 PM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050821897 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.3050821897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/48.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.2162557010
Short name T94
Test name
Test status
Simulation time 82673008414 ps
CPU time 36.03 seconds
Started Aug 27 07:58:36 PM UTC 24
Finished Aug 27 07:59:14 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162557010 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.2162557010
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/36.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.4278332638
Short name T137
Test name
Test status
Simulation time 106313627657 ps
CPU time 68.08 seconds
Started Aug 27 07:57:44 PM UTC 24
Finished Aug 27 07:58:53 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278332638 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.4278332638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/24.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.3181832749
Short name T126
Test name
Test status
Simulation time 116412256835 ps
CPU time 107.26 seconds
Started Aug 27 07:57:23 PM UTC 24
Finished Aug 27 07:59:13 PM UTC 24
Peak memory 200896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181832749 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.3181832749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.2134883390
Short name T128
Test name
Test status
Simulation time 76708330246 ps
CPU time 135.24 seconds
Started Aug 27 07:59:06 PM UTC 24
Finished Aug 27 08:01:23 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134883390 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.2134883390
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/43.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.1681826818
Short name T121
Test name
Test status
Simulation time 141380881073 ps
CPU time 123.6 seconds
Started Aug 27 07:58:14 PM UTC 24
Finished Aug 27 08:00:20 PM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681826818 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.1681826818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/32.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.1826555457
Short name T79
Test name
Test status
Simulation time 3861831582 ps
CPU time 30.12 seconds
Started Aug 27 07:57:05 PM UTC 24
Finished Aug 27 07:57:36 PM UTC 24
Peak memory 206748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1826555457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.aon_timer_stress_all_with_rand_reset.1826555457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.3287959366
Short name T113
Test name
Test status
Simulation time 4294971187 ps
CPU time 27.41 seconds
Started Aug 27 07:57:34 PM UTC 24
Finished Aug 27 07:58:03 PM UTC 24
Peak memory 206068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3287959366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 20.aon_timer_stress_all_with_rand_reset.3287959366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.3444415623
Short name T172
Test name
Test status
Simulation time 4731145600 ps
CPU time 45.35 seconds
Started Aug 27 07:58:09 PM UTC 24
Finished Aug 27 07:58:56 PM UTC 24
Peak memory 218824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3444415623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.aon_timer_stress_all_with_rand_reset.3444415623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.2477973739
Short name T96
Test name
Test status
Simulation time 128975874903 ps
CPU time 182.19 seconds
Started Aug 27 07:57:11 PM UTC 24
Finished Aug 27 08:00:16 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477973739 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.2477973739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.2770377966
Short name T140
Test name
Test status
Simulation time 339487501833 ps
CPU time 154.32 seconds
Started Aug 27 07:58:23 PM UTC 24
Finished Aug 27 08:00:59 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770377966 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.2770377966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/34.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.1623640824
Short name T144
Test name
Test status
Simulation time 191555947361 ps
CPU time 72.65 seconds
Started Aug 27 07:59:13 PM UTC 24
Finished Aug 27 08:00:28 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623640824 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.1623640824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/45.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.1734661801
Short name T87
Test name
Test status
Simulation time 188386690651 ps
CPU time 271.17 seconds
Started Aug 27 07:59:18 PM UTC 24
Finished Aug 27 08:03:53 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734661801 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.1734661801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/47.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.3917144968
Short name T141
Test name
Test status
Simulation time 452017428746 ps
CPU time 589.42 seconds
Started Aug 27 07:57:18 PM UTC 24
Finished Aug 27 08:07:14 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917144968 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.3917144968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.328449830
Short name T91
Test name
Test status
Simulation time 78307863216 ps
CPU time 61.39 seconds
Started Aug 27 07:58:05 PM UTC 24
Finished Aug 27 07:59:08 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328449830 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.328449830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/29.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.1552913194
Short name T118
Test name
Test status
Simulation time 2522039099 ps
CPU time 18.76 seconds
Started Aug 27 07:58:31 PM UTC 24
Finished Aug 27 07:58:51 PM UTC 24
Peak memory 206736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1552913194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 35.aon_timer_stress_all_with_rand_reset.1552913194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.2625090462
Short name T17
Test name
Test status
Simulation time 525040489 ps
CPU time 1.1 seconds
Started Aug 27 07:56:54 PM UTC 24
Finished Aug 27 07:56:56 PM UTC 24
Peak memory 199432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625090462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2625090462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.317672958
Short name T139
Test name
Test status
Simulation time 529981760041 ps
CPU time 86.36 seconds
Started Aug 27 07:57:42 PM UTC 24
Finished Aug 27 07:59:10 PM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317672958 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.317672958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/23.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.3680032732
Short name T131
Test name
Test status
Simulation time 159215971434 ps
CPU time 309.16 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 08:02:04 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680032732 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.3680032732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.2179194899
Short name T190
Test name
Test status
Simulation time 7429379890 ps
CPU time 56.75 seconds
Started Aug 27 07:58:10 PM UTC 24
Finished Aug 27 07:59:09 PM UTC 24
Peak memory 215564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2179194899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 31.aon_timer_stress_all_with_rand_reset.2179194899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.1344643791
Short name T161
Test name
Test status
Simulation time 6028221644 ps
CPU time 59.21 seconds
Started Aug 27 07:59:12 PM UTC 24
Finished Aug 27 08:00:13 PM UTC 24
Peak memory 205964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1344643791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 45.aon_timer_stress_all_with_rand_reset.1344643791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.3642691565
Short name T106
Test name
Test status
Simulation time 27843027183 ps
CPU time 26.01 seconds
Started Aug 27 07:57:09 PM UTC 24
Finished Aug 27 07:57:36 PM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642691565 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.3642691565
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.2438158383
Short name T116
Test name
Test status
Simulation time 150328666915 ps
CPU time 110.48 seconds
Started Aug 27 07:58:16 PM UTC 24
Finished Aug 27 08:00:09 PM UTC 24
Peak memory 200720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438158383 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.2438158383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/33.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.3449999355
Short name T101
Test name
Test status
Simulation time 3454269564 ps
CPU time 14.7 seconds
Started Aug 27 07:58:45 PM UTC 24
Finished Aug 27 07:59:02 PM UTC 24
Peak memory 216708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3449999355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 39.aon_timer_stress_all_with_rand_reset.3449999355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.1264344404
Short name T90
Test name
Test status
Simulation time 323434702492 ps
CPU time 464.42 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 08:04:40 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264344404 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.1264344404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.1987224263
Short name T166
Test name
Test status
Simulation time 2651460417 ps
CPU time 7.54 seconds
Started Aug 27 07:59:10 PM UTC 24
Finished Aug 27 07:59:19 PM UTC 24
Peak memory 206380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1987224263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 44.aon_timer_stress_all_with_rand_reset.1987224263
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.3220474956
Short name T151
Test name
Test status
Simulation time 329456900881 ps
CPU time 109.49 seconds
Started Aug 27 07:57:28 PM UTC 24
Finished Aug 27 07:59:20 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220474956 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.3220474956
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.1472938773
Short name T160
Test name
Test status
Simulation time 95476214319 ps
CPU time 40.18 seconds
Started Aug 27 07:57:57 PM UTC 24
Finished Aug 27 07:58:39 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472938773 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.1472938773
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/27.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.163640170
Short name T130
Test name
Test status
Simulation time 197624902255 ps
CPU time 339.31 seconds
Started Aug 27 07:58:46 PM UTC 24
Finished Aug 27 08:04:30 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163640170 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.163640170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/39.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.2331134498
Short name T156
Test name
Test status
Simulation time 145525463791 ps
CPU time 32.99 seconds
Started Aug 27 07:59:24 PM UTC 24
Finished Aug 27 07:59:58 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331134498 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.2331134498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/49.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.2227380812
Short name T119
Test name
Test status
Simulation time 227571423231 ps
CPU time 193.41 seconds
Started Aug 27 07:56:56 PM UTC 24
Finished Aug 27 08:00:12 PM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227380812 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.2227380812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.1351522167
Short name T148
Test name
Test status
Simulation time 416368236958 ps
CPU time 93.42 seconds
Started Aug 27 07:58:09 PM UTC 24
Finished Aug 27 07:59:44 PM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351522167 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.1351522167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/30.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.811318241
Short name T81
Test name
Test status
Simulation time 4554078436 ps
CPU time 27.4 seconds
Started Aug 27 07:58:14 PM UTC 24
Finished Aug 27 07:58:42 PM UTC 24
Peak memory 218048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=811318241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 32.aon_timer_stress_all_with_rand_reset.811318241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.2594785855
Short name T92
Test name
Test status
Simulation time 320553307186 ps
CPU time 271.86 seconds
Started Aug 27 07:56:58 PM UTC 24
Finished Aug 27 08:01:33 PM UTC 24
Peak memory 200692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594785855 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.2594785855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1116831153
Short name T68
Test name
Test status
Simulation time 1926294704 ps
CPU time 5.48 seconds
Started Aug 27 07:59:30 PM UTC 24
Finished Aug 27 07:59:37 PM UTC 24
Peak memory 203312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116831153 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.1116831153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.2208246841
Short name T109
Test name
Test status
Simulation time 256837400232 ps
CPU time 102.61 seconds
Started Aug 27 07:57:33 PM UTC 24
Finished Aug 27 07:59:18 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208246841 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.2208246841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.221323091
Short name T107
Test name
Test status
Simulation time 161812869438 ps
CPU time 266.29 seconds
Started Aug 27 07:56:54 PM UTC 24
Finished Aug 27 08:01:24 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221323091 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.221323091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.118356659
Short name T27
Test name
Test status
Simulation time 274089990552 ps
CPU time 31 seconds
Started Aug 27 07:57:01 PM UTC 24
Finished Aug 27 07:57:34 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118356659 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.118356659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.517464015
Short name T50
Test name
Test status
Simulation time 3650393678 ps
CPU time 23.42 seconds
Started Aug 27 07:57:07 PM UTC 24
Finished Aug 27 07:57:32 PM UTC 24
Peak memory 215380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=517464015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 11.aon_timer_stress_all_with_rand_reset.517464015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.3032250134
Short name T105
Test name
Test status
Simulation time 10473718852 ps
CPU time 30.29 seconds
Started Aug 27 07:57:11 PM UTC 24
Finished Aug 27 07:57:43 PM UTC 24
Peak memory 219412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3032250134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 13.aon_timer_stress_all_with_rand_reset.3032250134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.2352958519
Short name T112
Test name
Test status
Simulation time 323206907949 ps
CPU time 401.87 seconds
Started Aug 27 07:58:52 PM UTC 24
Finished Aug 27 08:05:39 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352958519 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.2352958519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/40.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.93088304
Short name T115
Test name
Test status
Simulation time 33794823687 ps
CPU time 25.44 seconds
Started Aug 27 07:59:16 PM UTC 24
Finished Aug 27 07:59:42 PM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93088304 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.93088304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/46.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.2489157215
Short name T95
Test name
Test status
Simulation time 4341758167 ps
CPU time 35.03 seconds
Started Aug 27 07:56:56 PM UTC 24
Finished Aug 27 07:57:33 PM UTC 24
Peak memory 206556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2489157215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 7.aon_timer_stress_all_with_rand_reset.2489157215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.4071849589
Short name T184
Test name
Test status
Simulation time 675023233928 ps
CPU time 1190.24 seconds
Started Aug 27 07:58:00 PM UTC 24
Finished Aug 27 08:18:03 PM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071849589 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.4071849589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/28.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.3280330171
Short name T108
Test name
Test status
Simulation time 583553213 ps
CPU time 1.54 seconds
Started Aug 27 07:58:44 PM UTC 24
Finished Aug 27 07:58:47 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280330171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3280330171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/39.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.3262260530
Short name T47
Test name
Test status
Simulation time 2236455410 ps
CPU time 12.95 seconds
Started Aug 27 07:57:08 PM UTC 24
Finished Aug 27 07:57:22 PM UTC 24
Peak memory 215504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3262260530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 12.aon_timer_stress_all_with_rand_reset.3262260530
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.3737288463
Short name T146
Test name
Test status
Simulation time 2722741139 ps
CPU time 16.14 seconds
Started Aug 27 07:57:50 PM UTC 24
Finished Aug 27 07:58:08 PM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3737288463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 26.aon_timer_stress_all_with_rand_reset.3737288463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.3474364118
Short name T82
Test name
Test status
Simulation time 6735077019 ps
CPU time 46.09 seconds
Started Aug 27 07:58:00 PM UTC 24
Finished Aug 27 07:58:48 PM UTC 24
Peak memory 219216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3474364118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 28.aon_timer_stress_all_with_rand_reset.3474364118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.1208704149
Short name T153
Test name
Test status
Simulation time 615796915 ps
CPU time 1.29 seconds
Started Aug 27 07:59:17 PM UTC 24
Finished Aug 27 07:59:19 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208704149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1208704149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/47.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.505342329
Short name T136
Test name
Test status
Simulation time 4661623251 ps
CPU time 28.64 seconds
Started Aug 27 07:57:14 PM UTC 24
Finished Aug 27 07:57:44 PM UTC 24
Peak memory 215496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=505342329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 14.aon_timer_stress_all_with_rand_reset.505342329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.3721500601
Short name T124
Test name
Test status
Simulation time 339960069553 ps
CPU time 462.19 seconds
Started Aug 27 07:57:35 PM UTC 24
Finished Aug 27 08:05:22 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721500601 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.3721500601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/20.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.880574013
Short name T23
Test name
Test status
Simulation time 478500719 ps
CPU time 2.59 seconds
Started Aug 27 07:56:50 PM UTC 24
Finished Aug 27 07:56:54 PM UTC 24
Peak memory 200644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880574013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.880574013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.1537291894
Short name T99
Test name
Test status
Simulation time 613806306 ps
CPU time 1.09 seconds
Started Aug 27 07:59:12 PM UTC 24
Finished Aug 27 07:59:14 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537291894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1537291894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/45.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.3463285402
Short name T129
Test name
Test status
Simulation time 2276327083 ps
CPU time 19.21 seconds
Started Aug 27 07:57:18 PM UTC 24
Finished Aug 27 07:57:38 PM UTC 24
Peak memory 217484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3463285402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 15.aon_timer_stress_all_with_rand_reset.3463285402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.236257247
Short name T143
Test name
Test status
Simulation time 3884922987 ps
CPU time 16.25 seconds
Started Aug 27 07:57:39 PM UTC 24
Finished Aug 27 07:57:56 PM UTC 24
Peak memory 215596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=236257247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.aon_timer_stress_all_with_rand_reset.236257247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.4287020084
Short name T138
Test name
Test status
Simulation time 544168484 ps
CPU time 1.7 seconds
Started Aug 27 07:57:44 PM UTC 24
Finished Aug 27 07:57:46 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287020084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.4287020084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/24.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.1766145793
Short name T165
Test name
Test status
Simulation time 511569275635 ps
CPU time 873.02 seconds
Started Aug 27 07:57:46 PM UTC 24
Finished Aug 27 08:12:28 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766145793 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.1766145793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/25.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.3929142944
Short name T135
Test name
Test status
Simulation time 390905747 ps
CPU time 1.17 seconds
Started Aug 27 07:58:30 PM UTC 24
Finished Aug 27 07:58:32 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929142944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3929142944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/35.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.903834895
Short name T145
Test name
Test status
Simulation time 606904173 ps
CPU time 1.4 seconds
Started Aug 27 07:58:41 PM UTC 24
Finished Aug 27 07:58:43 PM UTC 24
Peak memory 199372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903834895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.903834895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/38.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.1670314670
Short name T182
Test name
Test status
Simulation time 2944174721 ps
CPU time 28.37 seconds
Started Aug 27 07:58:55 PM UTC 24
Finished Aug 27 07:59:25 PM UTC 24
Peak memory 215444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1670314670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 41.aon_timer_stress_all_with_rand_reset.1670314670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.34776039
Short name T123
Test name
Test status
Simulation time 453805734 ps
CPU time 2.1 seconds
Started Aug 27 07:58:58 PM UTC 24
Finished Aug 27 07:59:01 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34776039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.34776039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/42.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.2283087354
Short name T49
Test name
Test status
Simulation time 3777232977 ps
CPU time 33.74 seconds
Started Aug 27 07:56:54 PM UTC 24
Finished Aug 27 07:57:29 PM UTC 24
Peak memory 200972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2283087354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 6.aon_timer_stress_all_with_rand_reset.2283087354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.2450389792
Short name T33
Test name
Test status
Simulation time 606139866 ps
CPU time 1.36 seconds
Started Aug 27 07:57:01 PM UTC 24
Finished Aug 27 07:57:04 PM UTC 24
Peak memory 199432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450389792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2450389792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.297791374
Short name T181
Test name
Test status
Simulation time 5343704418 ps
CPU time 38.75 seconds
Started Aug 27 07:57:29 PM UTC 24
Finished Aug 27 07:58:09 PM UTC 24
Peak memory 218340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=297791374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 18.aon_timer_stress_all_with_rand_reset.297791374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.2967412776
Short name T132
Test name
Test status
Simulation time 405308282657 ps
CPU time 150.32 seconds
Started Aug 27 07:56:50 PM UTC 24
Finished Aug 27 07:59:23 PM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967412776 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.2967412776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.3510318046
Short name T150
Test name
Test status
Simulation time 65685768881 ps
CPU time 93.42 seconds
Started Aug 27 07:57:50 PM UTC 24
Finished Aug 27 07:59:26 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510318046 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.3510318046
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/26.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.3736130038
Short name T142
Test name
Test status
Simulation time 467965661 ps
CPU time 1.37 seconds
Started Aug 27 07:58:03 PM UTC 24
Finished Aug 27 07:58:06 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736130038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3736130038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/29.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.1605816373
Short name T157
Test name
Test status
Simulation time 395723916 ps
CPU time 1.92 seconds
Started Aug 27 07:59:04 PM UTC 24
Finished Aug 27 07:59:07 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605816373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1605816373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/43.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.2142378440
Short name T158
Test name
Test status
Simulation time 357251266 ps
CPU time 1.89 seconds
Started Aug 27 07:57:56 PM UTC 24
Finished Aug 27 07:57:59 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142378440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2142378440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/27.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.2901545544
Short name T155
Test name
Test status
Simulation time 475423363 ps
CPU time 0.91 seconds
Started Aug 27 07:58:09 PM UTC 24
Finished Aug 27 07:58:11 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901545544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2901545544
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/31.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.2066265036
Short name T110
Test name
Test status
Simulation time 217193074500 ps
CPU time 51.62 seconds
Started Aug 27 07:58:40 PM UTC 24
Finished Aug 27 07:59:33 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066265036 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.2066265036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/37.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.1999384710
Short name T152
Test name
Test status
Simulation time 420957438 ps
CPU time 1.62 seconds
Started Aug 27 07:59:22 PM UTC 24
Finished Aug 27 07:59:25 PM UTC 24
Peak memory 198960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999384710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1999384710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/49.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.2445154083
Short name T98
Test name
Test status
Simulation time 5560030210 ps
CPU time 38.18 seconds
Started Aug 27 07:59:24 PM UTC 24
Finished Aug 27 08:00:03 PM UTC 24
Peak memory 219292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2445154083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 49.aon_timer_stress_all_with_rand_reset.2445154083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.1409336800
Short name T36
Test name
Test status
Simulation time 2159443428 ps
CPU time 15.71 seconds
Started Aug 27 07:57:01 PM UTC 24
Finished Aug 27 07:57:19 PM UTC 24
Peak memory 214444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1409336800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 9.aon_timer_stress_all_with_rand_reset.1409336800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.433387818
Short name T2
Test name
Test status
Simulation time 456118089 ps
CPU time 1.39 seconds
Started Aug 27 07:56:45 PM UTC 24
Finished Aug 27 07:56:48 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433387818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.433387818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.4163839955
Short name T174
Test name
Test status
Simulation time 646584773941 ps
CPU time 259.09 seconds
Started Aug 27 07:56:45 PM UTC 24
Finished Aug 27 08:01:08 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163839955 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.4163839955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.3654568107
Short name T3
Test name
Test status
Simulation time 589669994 ps
CPU time 1.29 seconds
Started Aug 27 07:56:46 PM UTC 24
Finished Aug 27 07:56:48 PM UTC 24
Peak memory 199432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654568107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3654568107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.2238332550
Short name T162
Test name
Test status
Simulation time 3946829956 ps
CPU time 4.61 seconds
Started Aug 27 07:57:31 PM UTC 24
Finished Aug 27 07:57:36 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238332550 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.2238332550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.2666411734
Short name T173
Test name
Test status
Simulation time 605327010 ps
CPU time 2.75 seconds
Started Aug 27 07:57:37 PM UTC 24
Finished Aug 27 07:57:41 PM UTC 24
Peak memory 200648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666411734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2666411734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/21.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.438485499
Short name T178
Test name
Test status
Simulation time 650585632 ps
CPU time 1.12 seconds
Started Aug 27 07:57:39 PM UTC 24
Finished Aug 27 07:57:41 PM UTC 24
Peak memory 199372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438485499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.438485499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/22.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.3720860592
Short name T169
Test name
Test status
Simulation time 513180981 ps
CPU time 1.27 seconds
Started Aug 27 07:57:45 PM UTC 24
Finished Aug 27 07:57:47 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720860592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3720860592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/25.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.1207688609
Short name T191
Test name
Test status
Simulation time 4595606751 ps
CPU time 22.42 seconds
Started Aug 27 07:57:45 PM UTC 24
Finished Aug 27 07:58:09 PM UTC 24
Peak memory 206648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1207688609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 25.aon_timer_stress_all_with_rand_reset.1207688609
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.4156039982
Short name T89
Test name
Test status
Simulation time 606202696 ps
CPU time 2.31 seconds
Started Aug 27 07:58:49 PM UTC 24
Finished Aug 27 07:58:52 PM UTC 24
Peak memory 200572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156039982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4156039982
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/40.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.2016793799
Short name T180
Test name
Test status
Simulation time 3004356084 ps
CPU time 22.05 seconds
Started Aug 27 07:59:06 PM UTC 24
Finished Aug 27 07:59:29 PM UTC 24
Peak memory 215044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2016793799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 43.aon_timer_stress_all_with_rand_reset.2016793799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.868629696
Short name T133
Test name
Test status
Simulation time 404547333 ps
CPU time 1.92 seconds
Started Aug 27 07:59:09 PM UTC 24
Finished Aug 27 07:59:12 PM UTC 24
Peak memory 199372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868629696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.868629696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/44.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.4089333488
Short name T179
Test name
Test status
Simulation time 6049372552 ps
CPU time 15.72 seconds
Started Aug 27 07:59:16 PM UTC 24
Finished Aug 27 07:59:33 PM UTC 24
Peak memory 216960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4089333488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 46.aon_timer_stress_all_with_rand_reset.4089333488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.696512331
Short name T176
Test name
Test status
Simulation time 4634448102 ps
CPU time 11.81 seconds
Started Aug 27 07:59:20 PM UTC 24
Finished Aug 27 07:59:33 PM UTC 24
Peak memory 217352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=696512331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 48.aon_timer_stress_all_with_rand_reset.696512331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1192351427
Short name T202
Test name
Test status
Simulation time 4329218807 ps
CPU time 2.6 seconds
Started Aug 27 08:00:00 PM UTC 24
Finished Aug 27 08:00:08 PM UTC 24
Peak memory 206452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192351427 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.1192351427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.2920818626
Short name T177
Test name
Test status
Simulation time 663538483 ps
CPU time 1.04 seconds
Started Aug 27 07:57:03 PM UTC 24
Finished Aug 27 07:57:05 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920818626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2920818626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.1305961221
Short name T196
Test name
Test status
Simulation time 382822723 ps
CPU time 2.23 seconds
Started Aug 27 07:57:10 PM UTC 24
Finished Aug 27 07:57:13 PM UTC 24
Peak memory 200648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305961221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1305961221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.2547184740
Short name T171
Test name
Test status
Simulation time 380699945 ps
CPU time 1.18 seconds
Started Aug 27 07:57:14 PM UTC 24
Finished Aug 27 07:57:17 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547184740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2547184740
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.2864260568
Short name T185
Test name
Test status
Simulation time 525691634 ps
CPU time 1.27 seconds
Started Aug 27 07:57:22 PM UTC 24
Finished Aug 27 07:57:25 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864260568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2864260568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.2244735750
Short name T195
Test name
Test status
Simulation time 454245096 ps
CPU time 1.27 seconds
Started Aug 27 07:57:27 PM UTC 24
Finished Aug 27 07:57:29 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244735750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2244735750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.3031491465
Short name T192
Test name
Test status
Simulation time 580944911 ps
CPU time 2.65 seconds
Started Aug 27 07:57:29 PM UTC 24
Finished Aug 27 07:57:33 PM UTC 24
Peak memory 200644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031491465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3031491465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.438875576
Short name T154
Test name
Test status
Simulation time 610412105 ps
CPU time 1.4 seconds
Started Aug 27 07:57:32 PM UTC 24
Finished Aug 27 07:57:35 PM UTC 24
Peak memory 199372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438875576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.438875576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.4140990722
Short name T189
Test name
Test status
Simulation time 477122356 ps
CPU time 1.93 seconds
Started Aug 27 07:57:34 PM UTC 24
Finished Aug 27 07:57:37 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140990722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4140990722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/20.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.3715633191
Short name T188
Test name
Test status
Simulation time 559753696 ps
CPU time 2.9 seconds
Started Aug 27 07:57:49 PM UTC 24
Finished Aug 27 07:57:53 PM UTC 24
Peak memory 200648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715633191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3715633191
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/26.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.1124485116
Short name T200
Test name
Test status
Simulation time 3934298339 ps
CPU time 29.95 seconds
Started Aug 27 07:58:05 PM UTC 24
Finished Aug 27 07:58:36 PM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1124485116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.aon_timer_stress_all_with_rand_reset.1124485116
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.334179056
Short name T199
Test name
Test status
Simulation time 420035612 ps
CPU time 1.4 seconds
Started Aug 27 07:58:09 PM UTC 24
Finished Aug 27 07:58:11 PM UTC 24
Peak memory 199372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334179056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.334179056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/30.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.3389467469
Short name T193
Test name
Test status
Simulation time 550710470 ps
CPU time 1.32 seconds
Started Aug 27 07:58:13 PM UTC 24
Finished Aug 27 07:58:15 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389467469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3389467469
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/32.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.4011505342
Short name T183
Test name
Test status
Simulation time 607623507 ps
CPU time 1.26 seconds
Started Aug 27 07:58:15 PM UTC 24
Finished Aug 27 07:58:17 PM UTC 24
Peak memory 199432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011505342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4011505342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/33.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.2011389178
Short name T186
Test name
Test status
Simulation time 515570753 ps
CPU time 1.06 seconds
Started Aug 27 07:58:36 PM UTC 24
Finished Aug 27 07:58:38 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011389178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2011389178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/36.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.2600219724
Short name T164
Test name
Test status
Simulation time 534540565 ps
CPU time 2.37 seconds
Started Aug 27 07:58:38 PM UTC 24
Finished Aug 27 07:58:42 PM UTC 24
Peak memory 200572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600219724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2600219724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/37.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.4119725620
Short name T14
Test name
Test status
Simulation time 514263784 ps
CPU time 2.34 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 07:56:54 PM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119725620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.4119725620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.2181223694
Short name T147
Test name
Test status
Simulation time 378085108 ps
CPU time 1.08 seconds
Started Aug 27 07:58:54 PM UTC 24
Finished Aug 27 07:58:56 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181223694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2181223694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/41.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.2220678518
Short name T159
Test name
Test status
Simulation time 64032896372 ps
CPU time 48.74 seconds
Started Aug 27 07:59:01 PM UTC 24
Finished Aug 27 07:59:52 PM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220678518 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.2220678518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/42.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.2570587208
Short name T198
Test name
Test status
Simulation time 558979821 ps
CPU time 2.42 seconds
Started Aug 27 07:59:19 PM UTC 24
Finished Aug 27 07:59:23 PM UTC 24
Peak memory 200776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570587208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2570587208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/48.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.2312329463
Short name T30
Test name
Test status
Simulation time 398209395 ps
CPU time 1.02 seconds
Started Aug 27 07:56:52 PM UTC 24
Finished Aug 27 07:56:54 PM UTC 24
Peak memory 199432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312329463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2312329463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.1943422951
Short name T34
Test name
Test status
Simulation time 532606915 ps
CPU time 1.66 seconds
Started Aug 27 07:56:55 PM UTC 24
Finished Aug 27 07:56:58 PM UTC 24
Peak memory 199432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943422951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1943422951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.4221594139
Short name T197
Test name
Test status
Simulation time 518298603 ps
CPU time 1.03 seconds
Started Aug 27 07:57:06 PM UTC 24
Finished Aug 27 07:57:09 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221594139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4221594139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.4140964423
Short name T187
Test name
Test status
Simulation time 424940452 ps
CPU time 1.6 seconds
Started Aug 27 07:57:08 PM UTC 24
Finished Aug 27 07:57:11 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140964423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.4140964423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.4178349999
Short name T175
Test name
Test status
Simulation time 579665929 ps
CPU time 2.4 seconds
Started Aug 27 07:57:18 PM UTC 24
Finished Aug 27 07:57:21 PM UTC 24
Peak memory 200840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178349999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4178349999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.1027945102
Short name T134
Test name
Test status
Simulation time 473376107 ps
CPU time 1.37 seconds
Started Aug 27 07:57:41 PM UTC 24
Finished Aug 27 07:57:44 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027945102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1027945102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/23.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.732585258
Short name T194
Test name
Test status
Simulation time 418731791 ps
CPU time 1 seconds
Started Aug 27 07:58:00 PM UTC 24
Finished Aug 27 07:58:02 PM UTC 24
Peak memory 199372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732585258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.732585258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/28.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.2491417013
Short name T170
Test name
Test status
Simulation time 401527185 ps
CPU time 1.09 seconds
Started Aug 27 07:58:19 PM UTC 24
Finished Aug 27 07:58:22 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491417013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2491417013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/34.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.1198421368
Short name T167
Test name
Test status
Simulation time 1627652635 ps
CPU time 14.12 seconds
Started Aug 27 07:58:21 PM UTC 24
Finished Aug 27 07:58:36 PM UTC 24
Peak memory 206584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1198421368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 34.aon_timer_stress_all_with_rand_reset.1198421368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.3625880915
Short name T168
Test name
Test status
Simulation time 582818890 ps
CPU time 1.17 seconds
Started Aug 27 07:59:15 PM UTC 24
Finished Aug 27 07:59:17 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625880915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3625880915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/46.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.4248993331
Short name T35
Test name
Test status
Simulation time 586403174 ps
CPU time 3.05 seconds
Started Aug 27 07:56:56 PM UTC 24
Finished Aug 27 07:57:01 PM UTC 24
Peak memory 200644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248993331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4248993331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1671286205
Short name T45
Test name
Test status
Simulation time 550304962 ps
CPU time 1.24 seconds
Started Aug 27 07:59:29 PM UTC 24
Finished Aug 27 07:59:31 PM UTC 24
Peak memory 201784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671286205 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.1671286205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1555018985
Short name T77
Test name
Test status
Simulation time 14528654990 ps
CPU time 7.96 seconds
Started Aug 27 07:59:29 PM UTC 24
Finished Aug 27 07:59:38 PM UTC 24
Peak memory 205656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555018985 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.1555018985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2866183088
Short name T38
Test name
Test status
Simulation time 1275625740 ps
CPU time 2.96 seconds
Started Aug 27 07:59:28 PM UTC 24
Finished Aug 27 07:59:32 PM UTC 24
Peak memory 203256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866183088 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.2866183088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2430256253
Short name T39
Test name
Test status
Simulation time 468987050 ps
CPU time 1.48 seconds
Started Aug 27 07:59:30 PM UTC 24
Finished Aug 27 07:59:33 PM UTC 24
Peak memory 207008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2430256253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_csr_mem_rw_with_rand_reset.2430256253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.2909898269
Short name T44
Test name
Test status
Simulation time 354095069 ps
CPU time 1.95 seconds
Started Aug 27 07:59:28 PM UTC 24
Finished Aug 27 07:59:31 PM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909898269 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2909898269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.4052808690
Short name T292
Test name
Test status
Simulation time 356146926 ps
CPU time 0.95 seconds
Started Aug 27 07:59:26 PM UTC 24
Finished Aug 27 07:59:28 PM UTC 24
Peak memory 199916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052808690 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4052808690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3274647989
Short name T295
Test name
Test status
Simulation time 517657619 ps
CPU time 1.06 seconds
Started Aug 27 07:59:27 PM UTC 24
Finished Aug 27 07:59:29 PM UTC 24
Peak memory 199856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274647989 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.3274647989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.1489826567
Short name T293
Test name
Test status
Simulation time 292291777 ps
CPU time 1.21 seconds
Started Aug 27 07:59:26 PM UTC 24
Finished Aug 27 07:59:28 PM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489826567 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.1489826567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.2801525902
Short name T294
Test name
Test status
Simulation time 520116231 ps
CPU time 4.03 seconds
Started Aug 27 07:59:24 PM UTC 24
Finished Aug 27 07:59:29 PM UTC 24
Peak memory 207040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801525902 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2801525902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4119005454
Short name T311
Test name
Test status
Simulation time 7123479706 ps
CPU time 9.71 seconds
Started Aug 27 07:59:34 PM UTC 24
Finished Aug 27 07:59:44 PM UTC 24
Peak memory 205648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119005454 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.4119005454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.960360409
Short name T40
Test name
Test status
Simulation time 742308355 ps
CPU time 1.21 seconds
Started Aug 27 07:59:34 PM UTC 24
Finished Aug 27 07:59:36 PM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960360409 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.960360409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3353690195
Short name T300
Test name
Test status
Simulation time 456620636 ps
CPU time 1.24 seconds
Started Aug 27 07:59:37 PM UTC 24
Finished Aug 27 07:59:39 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3353690195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_csr_mem_rw_with_rand_reset.3353690195
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.780007092
Short name T52
Test name
Test status
Simulation time 499637648 ps
CPU time 1.21 seconds
Started Aug 27 07:59:34 PM UTC 24
Finished Aug 27 07:59:36 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780007092 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.780007092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.3490600118
Short name T296
Test name
Test status
Simulation time 442766844 ps
CPU time 1.11 seconds
Started Aug 27 07:59:32 PM UTC 24
Finished Aug 27 07:59:35 PM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490600118 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3490600118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1104322457
Short name T299
Test name
Test status
Simulation time 361708336 ps
CPU time 1.91 seconds
Started Aug 27 07:59:34 PM UTC 24
Finished Aug 27 07:59:36 PM UTC 24
Peak memory 199856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104322457 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.1104322457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3835982584
Short name T297
Test name
Test status
Simulation time 497715469 ps
CPU time 1.49 seconds
Started Aug 27 07:59:33 PM UTC 24
Finished Aug 27 07:59:36 PM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835982584 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.3835982584
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.876311790
Short name T69
Test name
Test status
Simulation time 1030323681 ps
CPU time 1.72 seconds
Started Aug 27 07:59:37 PM UTC 24
Finished Aug 27 07:59:40 PM UTC 24
Peak memory 201964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876311790 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.876311790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2040585602
Short name T298
Test name
Test status
Simulation time 316247205 ps
CPU time 4 seconds
Started Aug 27 07:59:31 PM UTC 24
Finished Aug 27 07:59:36 PM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040585602 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2040585602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.404879935
Short name T41
Test name
Test status
Simulation time 4361510218 ps
CPU time 4.46 seconds
Started Aug 27 07:59:32 PM UTC 24
Finished Aug 27 07:59:38 PM UTC 24
Peak memory 206412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404879935 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.404879935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1843155794
Short name T348
Test name
Test status
Simulation time 523558480 ps
CPU time 2.77 seconds
Started Aug 27 07:59:58 PM UTC 24
Finished Aug 27 08:00:02 PM UTC 24
Peak memory 205496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1843155794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_ti
mer_csr_mem_rw_with_rand_reset.1843155794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.756143717
Short name T62
Test name
Test status
Simulation time 557492132 ps
CPU time 1.55 seconds
Started Aug 27 07:59:58 PM UTC 24
Finished Aug 27 08:00:01 PM UTC 24
Peak memory 201800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756143717 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.756143717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.605786022
Short name T342
Test name
Test status
Simulation time 504645709 ps
CPU time 1.12 seconds
Started Aug 27 07:59:58 PM UTC 24
Finished Aug 27 08:00:00 PM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605786022 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.605786022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2531435428
Short name T345
Test name
Test status
Simulation time 1301361605 ps
CPU time 1.84 seconds
Started Aug 27 07:59:58 PM UTC 24
Finished Aug 27 08:00:01 PM UTC 24
Peak memory 201956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531435428 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.2531435428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1366006369
Short name T336
Test name
Test status
Simulation time 440177807 ps
CPU time 1.82 seconds
Started Aug 27 07:59:57 PM UTC 24
Finished Aug 27 08:00:00 PM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366006369 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1366006369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3259789517
Short name T352
Test name
Test status
Simulation time 7785379683 ps
CPU time 5.69 seconds
Started Aug 27 07:59:57 PM UTC 24
Finished Aug 27 08:00:04 PM UTC 24
Peak memory 207056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259789517 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.3259789517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3102482415
Short name T346
Test name
Test status
Simulation time 385487407 ps
CPU time 1.28 seconds
Started Aug 27 07:59:59 PM UTC 24
Finished Aug 27 08:00:02 PM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3102482415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_ti
mer_csr_mem_rw_with_rand_reset.3102482415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.3214308026
Short name T65
Test name
Test status
Simulation time 361622364 ps
CPU time 1.82 seconds
Started Aug 27 07:59:59 PM UTC 24
Finished Aug 27 08:00:02 PM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214308026 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3214308026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.743461118
Short name T344
Test name
Test status
Simulation time 363789766 ps
CPU time 1.43 seconds
Started Aug 27 07:59:58 PM UTC 24
Finished Aug 27 08:00:01 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743461118 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.743461118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2685720827
Short name T351
Test name
Test status
Simulation time 1243844668 ps
CPU time 2.9 seconds
Started Aug 27 07:59:59 PM UTC 24
Finished Aug 27 08:00:03 PM UTC 24
Peak memory 203248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685720827 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.2685720827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2258724914
Short name T349
Test name
Test status
Simulation time 525203830 ps
CPU time 3.91 seconds
Started Aug 27 07:59:58 PM UTC 24
Finished Aug 27 08:00:03 PM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258724914 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2258724914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.424808515
Short name T355
Test name
Test status
Simulation time 4416618893 ps
CPU time 7.92 seconds
Started Aug 27 07:59:58 PM UTC 24
Finished Aug 27 08:00:07 PM UTC 24
Peak memory 206888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424808515 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.424808515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.918870060
Short name T358
Test name
Test status
Simulation time 526353294 ps
CPU time 1.91 seconds
Started Aug 27 08:00:01 PM UTC 24
Finished Aug 27 08:00:08 PM UTC 24
Peak memory 203556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=918870060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_tim
er_csr_mem_rw_with_rand_reset.918870060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2754346091
Short name T66
Test name
Test status
Simulation time 604072486 ps
CPU time 0.7 seconds
Started Aug 27 08:00:01 PM UTC 24
Finished Aug 27 08:00:06 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754346091 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2754346091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.595270256
Short name T354
Test name
Test status
Simulation time 304191136 ps
CPU time 1.27 seconds
Started Aug 27 08:00:00 PM UTC 24
Finished Aug 27 08:00:07 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595270256 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.595270256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2086943198
Short name T353
Test name
Test status
Simulation time 1636858193 ps
CPU time 0.92 seconds
Started Aug 27 08:00:01 PM UTC 24
Finished Aug 27 08:00:06 PM UTC 24
Peak memory 201964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086943198 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.2086943198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3635181443
Short name T360
Test name
Test status
Simulation time 677481678 ps
CPU time 2.39 seconds
Started Aug 27 08:00:00 PM UTC 24
Finished Aug 27 08:00:08 PM UTC 24
Peak memory 207036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635181443 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3635181443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.641531784
Short name T359
Test name
Test status
Simulation time 388827325 ps
CPU time 1.78 seconds
Started Aug 27 08:00:02 PM UTC 24
Finished Aug 27 08:00:08 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=641531784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_tim
er_csr_mem_rw_with_rand_reset.641531784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2093783150
Short name T357
Test name
Test status
Simulation time 373121335 ps
CPU time 1.63 seconds
Started Aug 27 08:00:02 PM UTC 24
Finished Aug 27 08:00:07 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093783150 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2093783150
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1004046304
Short name T356
Test name
Test status
Simulation time 347510051 ps
CPU time 1.44 seconds
Started Aug 27 08:00:02 PM UTC 24
Finished Aug 27 08:00:07 PM UTC 24
Peak memory 201764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004046304 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1004046304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.36841431
Short name T361
Test name
Test status
Simulation time 3004993254 ps
CPU time 1.89 seconds
Started Aug 27 08:00:02 PM UTC 24
Finished Aug 27 08:00:08 PM UTC 24
Peak memory 203820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36841431 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.36841431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3138224352
Short name T363
Test name
Test status
Simulation time 564276277 ps
CPU time 2.74 seconds
Started Aug 27 08:00:01 PM UTC 24
Finished Aug 27 08:00:08 PM UTC 24
Peak memory 206704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138224352 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3138224352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3907960250
Short name T362
Test name
Test status
Simulation time 4532932572 ps
CPU time 2.58 seconds
Started Aug 27 08:00:02 PM UTC 24
Finished Aug 27 08:00:08 PM UTC 24
Peak memory 206236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907960250 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.3907960250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1129642064
Short name T369
Test name
Test status
Simulation time 946984383 ps
CPU time 1.61 seconds
Started Aug 27 08:00:06 PM UTC 24
Finished Aug 27 08:00:09 PM UTC 24
Peak memory 207064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1129642064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_ti
mer_csr_mem_rw_with_rand_reset.1129642064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.1181298847
Short name T365
Test name
Test status
Simulation time 529507498 ps
CPU time 1.27 seconds
Started Aug 27 08:00:06 PM UTC 24
Finished Aug 27 08:00:09 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181298847 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1181298847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.3622431790
Short name T364
Test name
Test status
Simulation time 453831077 ps
CPU time 0.82 seconds
Started Aug 27 08:00:06 PM UTC 24
Finished Aug 27 08:00:08 PM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622431790 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3622431790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.415114980
Short name T368
Test name
Test status
Simulation time 1398249607 ps
CPU time 1.57 seconds
Started Aug 27 08:00:06 PM UTC 24
Finished Aug 27 08:00:09 PM UTC 24
Peak memory 201968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415114980 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.415114980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.1990565408
Short name T370
Test name
Test status
Simulation time 470897904 ps
CPU time 2.43 seconds
Started Aug 27 08:00:06 PM UTC 24
Finished Aug 27 08:00:10 PM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990565408 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1990565408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.894281182
Short name T372
Test name
Test status
Simulation time 4552605881 ps
CPU time 2.47 seconds
Started Aug 27 08:00:06 PM UTC 24
Finished Aug 27 08:00:10 PM UTC 24
Peak memory 206804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894281182 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.894281182
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.171844893
Short name T374
Test name
Test status
Simulation time 454147418 ps
CPU time 1.42 seconds
Started Aug 27 08:00:08 PM UTC 24
Finished Aug 27 08:00:10 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=171844893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_tim
er_csr_mem_rw_with_rand_reset.171844893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.127850921
Short name T366
Test name
Test status
Simulation time 389042279 ps
CPU time 1.04 seconds
Started Aug 27 08:00:07 PM UTC 24
Finished Aug 27 08:00:09 PM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127850921 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.127850921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.2707821566
Short name T367
Test name
Test status
Simulation time 521892275 ps
CPU time 1.07 seconds
Started Aug 27 08:00:06 PM UTC 24
Finished Aug 27 08:00:09 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707821566 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2707821566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3448007873
Short name T375
Test name
Test status
Simulation time 2016929798 ps
CPU time 1.35 seconds
Started Aug 27 08:00:08 PM UTC 24
Finished Aug 27 08:00:10 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448007873 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.3448007873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.3203984978
Short name T373
Test name
Test status
Simulation time 901662236 ps
CPU time 2.5 seconds
Started Aug 27 08:00:06 PM UTC 24
Finished Aug 27 08:00:10 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203984978 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3203984978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1538419150
Short name T203
Test name
Test status
Simulation time 8196266395 ps
CPU time 12.83 seconds
Started Aug 27 08:00:06 PM UTC 24
Finished Aug 27 08:00:21 PM UTC 24
Peak memory 207000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538419150 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.1538419150
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2253564009
Short name T379
Test name
Test status
Simulation time 445175634 ps
CPU time 1.01 seconds
Started Aug 27 08:00:09 PM UTC 24
Finished Aug 27 08:00:11 PM UTC 24
Peak memory 205328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2253564009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti
mer_csr_mem_rw_with_rand_reset.2253564009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.347382726
Short name T67
Test name
Test status
Simulation time 452848589 ps
CPU time 0.89 seconds
Started Aug 27 08:00:08 PM UTC 24
Finished Aug 27 08:00:10 PM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347382726 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.347382726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.2583159480
Short name T371
Test name
Test status
Simulation time 288478358 ps
CPU time 1.04 seconds
Started Aug 27 08:00:08 PM UTC 24
Finished Aug 27 08:00:10 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583159480 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2583159480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3343277722
Short name T376
Test name
Test status
Simulation time 1511091441 ps
CPU time 0.86 seconds
Started Aug 27 08:00:09 PM UTC 24
Finished Aug 27 08:00:11 PM UTC 24
Peak memory 201964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343277722 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.3343277722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.3812998936
Short name T378
Test name
Test status
Simulation time 357377782 ps
CPU time 2.09 seconds
Started Aug 27 08:00:08 PM UTC 24
Finished Aug 27 08:00:11 PM UTC 24
Peak memory 207096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812998936 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3812998936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1440657769
Short name T412
Test name
Test status
Simulation time 4228464319 ps
CPU time 7.71 seconds
Started Aug 27 08:00:08 PM UTC 24
Finished Aug 27 08:00:17 PM UTC 24
Peak memory 207024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440657769 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.1440657769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2094040616
Short name T380
Test name
Test status
Simulation time 397352590 ps
CPU time 0.82 seconds
Started Aug 27 08:00:09 PM UTC 24
Finished Aug 27 08:00:11 PM UTC 24
Peak memory 205064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2094040616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti
mer_csr_mem_rw_with_rand_reset.2094040616
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.1196148064
Short name T64
Test name
Test status
Simulation time 552654017 ps
CPU time 1.14 seconds
Started Aug 27 08:00:09 PM UTC 24
Finished Aug 27 08:00:11 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196148064 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1196148064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.3813163518
Short name T381
Test name
Test status
Simulation time 306135109 ps
CPU time 0.91 seconds
Started Aug 27 08:00:09 PM UTC 24
Finished Aug 27 08:00:11 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813163518 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3813163518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2794101551
Short name T383
Test name
Test status
Simulation time 1879324994 ps
CPU time 1.71 seconds
Started Aug 27 08:00:09 PM UTC 24
Finished Aug 27 08:00:12 PM UTC 24
Peak memory 204012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794101551 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.2794101551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.2348210837
Short name T382
Test name
Test status
Simulation time 328677033 ps
CPU time 1.44 seconds
Started Aug 27 08:00:09 PM UTC 24
Finished Aug 27 08:00:11 PM UTC 24
Peak memory 207076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348210837 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2348210837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3669462386
Short name T426
Test name
Test status
Simulation time 4466774826 ps
CPU time 8.46 seconds
Started Aug 27 08:00:09 PM UTC 24
Finished Aug 27 08:00:19 PM UTC 24
Peak memory 206776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669462386 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.3669462386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1441209581
Short name T392
Test name
Test status
Simulation time 490622780 ps
CPU time 1.32 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 205296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1441209581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_ti
mer_csr_mem_rw_with_rand_reset.1441209581
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.828650293
Short name T385
Test name
Test status
Simulation time 513881482 ps
CPU time 0.88 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:13 PM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828650293 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.828650293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.3555382566
Short name T386
Test name
Test status
Simulation time 470760722 ps
CPU time 1.09 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:13 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555382566 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3555382566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2651968563
Short name T396
Test name
Test status
Simulation time 2928897526 ps
CPU time 2.11 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 205560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651968563 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.2651968563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1499212436
Short name T384
Test name
Test status
Simulation time 510397866 ps
CPU time 2.52 seconds
Started Aug 27 08:00:09 PM UTC 24
Finished Aug 27 08:00:13 PM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499212436 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1499212436
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.40635902
Short name T405
Test name
Test status
Simulation time 4355834004 ps
CPU time 3.27 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:15 PM UTC 24
Peak memory 205436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40635902 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.40635902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2457751737
Short name T393
Test name
Test status
Simulation time 540340301 ps
CPU time 1.43 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 203288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2457751737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti
mer_csr_mem_rw_with_rand_reset.2457751737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.2520590696
Short name T387
Test name
Test status
Simulation time 502149728 ps
CPU time 0.83 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:13 PM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520590696 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2520590696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.4156178444
Short name T390
Test name
Test status
Simulation time 346367826 ps
CPU time 1.05 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:13 PM UTC 24
Peak memory 199076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156178444 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.4156178444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.179506290
Short name T394
Test name
Test status
Simulation time 1113035146 ps
CPU time 1.81 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 201968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179506290 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.179506290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.4043375941
Short name T403
Test name
Test status
Simulation time 555447578 ps
CPU time 2.22 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043375941 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.4043375941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.199320712
Short name T413
Test name
Test status
Simulation time 4317381839 ps
CPU time 4.55 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:17 PM UTC 24
Peak memory 205836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199320712 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.199320712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.592183101
Short name T307
Test name
Test status
Simulation time 489456616 ps
CPU time 2.75 seconds
Started Aug 27 07:59:39 PM UTC 24
Finished Aug 27 07:59:43 PM UTC 24
Peak memory 203516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592183101 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.592183101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3361863250
Short name T63
Test name
Test status
Simulation time 11672718230 ps
CPU time 30.34 seconds
Started Aug 27 07:59:39 PM UTC 24
Finished Aug 27 08:00:11 PM UTC 24
Peak memory 205496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361863250 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.3361863250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2853490697
Short name T54
Test name
Test status
Simulation time 662241882 ps
CPU time 1.4 seconds
Started Aug 27 07:59:39 PM UTC 24
Finished Aug 27 07:59:42 PM UTC 24
Peak memory 199736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853490697 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.2853490697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.90131758
Short name T306
Test name
Test status
Simulation time 541999997 ps
CPU time 1.59 seconds
Started Aug 27 07:59:40 PM UTC 24
Finished Aug 27 07:59:43 PM UTC 24
Peak memory 204012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=90131758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer
_csr_mem_rw_with_rand_reset.90131758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1183084097
Short name T78
Test name
Test status
Simulation time 571248065 ps
CPU time 0.94 seconds
Started Aug 27 07:59:39 PM UTC 24
Finished Aug 27 07:59:41 PM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183084097 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1183084097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.1794294854
Short name T301
Test name
Test status
Simulation time 412290522 ps
CPU time 1.35 seconds
Started Aug 27 07:59:37 PM UTC 24
Finished Aug 27 07:59:39 PM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794294854 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1794294854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1744267985
Short name T304
Test name
Test status
Simulation time 375393433 ps
CPU time 1.05 seconds
Started Aug 27 07:59:39 PM UTC 24
Finished Aug 27 07:59:41 PM UTC 24
Peak memory 199856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744267985 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.1744267985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.3229991596
Short name T302
Test name
Test status
Simulation time 343994573 ps
CPU time 0.87 seconds
Started Aug 27 07:59:38 PM UTC 24
Finished Aug 27 07:59:40 PM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229991596 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.3229991596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3284504246
Short name T71
Test name
Test status
Simulation time 2312874718 ps
CPU time 5.72 seconds
Started Aug 27 07:59:40 PM UTC 24
Finished Aug 27 07:59:47 PM UTC 24
Peak memory 205424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284504246 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.3284504246
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3870142686
Short name T303
Test name
Test status
Simulation time 1678983787 ps
CPU time 3.09 seconds
Started Aug 27 07:59:37 PM UTC 24
Finished Aug 27 07:59:41 PM UTC 24
Peak memory 207040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870142686 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3870142686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3994335852
Short name T204
Test name
Test status
Simulation time 7639513193 ps
CPU time 18.53 seconds
Started Aug 27 07:59:37 PM UTC 24
Finished Aug 27 07:59:57 PM UTC 24
Peak memory 206904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994335852 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.3994335852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.27303477
Short name T388
Test name
Test status
Simulation time 491681408 ps
CPU time 0.72 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:13 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27303477 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.27303477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/20.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.2756275932
Short name T391
Test name
Test status
Simulation time 476066498 ps
CPU time 0.87 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:13 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756275932 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2756275932
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/21.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.2996403375
Short name T389
Test name
Test status
Simulation time 506018282 ps
CPU time 0.73 seconds
Started Aug 27 08:00:11 PM UTC 24
Finished Aug 27 08:00:13 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996403375 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2996403375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/22.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2000584377
Short name T401
Test name
Test status
Simulation time 291162404 ps
CPU time 1.07 seconds
Started Aug 27 08:00:12 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000584377 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2000584377
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/23.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.2410034220
Short name T404
Test name
Test status
Simulation time 443512405 ps
CPU time 1.18 seconds
Started Aug 27 08:00:12 PM UTC 24
Finished Aug 27 08:00:15 PM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410034220 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2410034220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/24.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.1248045
Short name T402
Test name
Test status
Simulation time 488531126 ps
CPU time 1 seconds
Started Aug 27 08:00:12 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248045 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1248045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/25.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.1403102306
Short name T399
Test name
Test status
Simulation time 526663172 ps
CPU time 1 seconds
Started Aug 27 08:00:12 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403102306 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1403102306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/26.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.3125154023
Short name T395
Test name
Test status
Simulation time 403493333 ps
CPU time 0.73 seconds
Started Aug 27 08:00:12 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125154023 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3125154023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/27.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.980754441
Short name T398
Test name
Test status
Simulation time 345404698 ps
CPU time 0.82 seconds
Started Aug 27 08:00:12 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980754441 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.980754441
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/28.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.1038874138
Short name T400
Test name
Test status
Simulation time 374067756 ps
CPU time 0.84 seconds
Started Aug 27 08:00:12 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 199420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038874138 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1038874138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/29.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3194254978
Short name T312
Test name
Test status
Simulation time 595637846 ps
CPU time 1.41 seconds
Started Aug 27 07:59:43 PM UTC 24
Finished Aug 27 07:59:45 PM UTC 24
Peak memory 201784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194254978 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.3194254978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.613321123
Short name T59
Test name
Test status
Simulation time 6962745916 ps
CPU time 5.08 seconds
Started Aug 27 07:59:43 PM UTC 24
Finished Aug 27 07:59:49 PM UTC 24
Peak memory 205644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613321123 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.613321123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2720775908
Short name T56
Test name
Test status
Simulation time 1164358737 ps
CPU time 2.86 seconds
Started Aug 27 07:59:42 PM UTC 24
Finished Aug 27 07:59:46 PM UTC 24
Peak memory 203196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720775908 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.2720775908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.776924810
Short name T313
Test name
Test status
Simulation time 378013022 ps
CPU time 1.36 seconds
Started Aug 27 07:59:44 PM UTC 24
Finished Aug 27 07:59:46 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=776924810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_time
r_csr_mem_rw_with_rand_reset.776924810
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.524828074
Short name T55
Test name
Test status
Simulation time 416469946 ps
CPU time 1.59 seconds
Started Aug 27 07:59:43 PM UTC 24
Finished Aug 27 07:59:45 PM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524828074 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.524828074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.2022588444
Short name T305
Test name
Test status
Simulation time 279474281 ps
CPU time 0.88 seconds
Started Aug 27 07:59:41 PM UTC 24
Finished Aug 27 07:59:42 PM UTC 24
Peak memory 201840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022588444 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2022588444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2125680178
Short name T308
Test name
Test status
Simulation time 441431807 ps
CPU time 1.15 seconds
Started Aug 27 07:59:42 PM UTC 24
Finished Aug 27 07:59:44 PM UTC 24
Peak memory 199856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125680178 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.2125680178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.4039016493
Short name T309
Test name
Test status
Simulation time 481768059 ps
CPU time 1.51 seconds
Started Aug 27 07:59:42 PM UTC 24
Finished Aug 27 07:59:44 PM UTC 24
Peak memory 199476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039016493 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.4039016493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2241164989
Short name T70
Test name
Test status
Simulation time 2262916560 ps
CPU time 1.84 seconds
Started Aug 27 07:59:44 PM UTC 24
Finished Aug 27 07:59:47 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241164989 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.2241164989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2331950777
Short name T310
Test name
Test status
Simulation time 479965904 ps
CPU time 2.76 seconds
Started Aug 27 07:59:40 PM UTC 24
Finished Aug 27 07:59:44 PM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331950777 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2331950777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2499020245
Short name T43
Test name
Test status
Simulation time 8584046455 ps
CPU time 10.22 seconds
Started Aug 27 07:59:41 PM UTC 24
Finished Aug 27 07:59:52 PM UTC 24
Peak memory 206904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499020245 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.2499020245
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.3756806941
Short name T397
Test name
Test status
Simulation time 519286819 ps
CPU time 0.75 seconds
Started Aug 27 08:00:12 PM UTC 24
Finished Aug 27 08:00:14 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756806941 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3756806941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/30.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.1638642540
Short name T406
Test name
Test status
Simulation time 351904840 ps
CPU time 0.87 seconds
Started Aug 27 08:00:13 PM UTC 24
Finished Aug 27 08:00:16 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638642540 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1638642540
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/31.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.679135028
Short name T377
Test name
Test status
Simulation time 371832828 ps
CPU time 0.97 seconds
Started Aug 27 08:00:13 PM UTC 24
Finished Aug 27 08:00:16 PM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679135028 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.679135028
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/32.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.1645271051
Short name T411
Test name
Test status
Simulation time 430347798 ps
CPU time 1.2 seconds
Started Aug 27 08:00:14 PM UTC 24
Finished Aug 27 08:00:16 PM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645271051 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1645271051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/33.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.906128694
Short name T409
Test name
Test status
Simulation time 348701185 ps
CPU time 0.9 seconds
Started Aug 27 08:00:14 PM UTC 24
Finished Aug 27 08:00:16 PM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906128694 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.906128694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/34.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.3931122843
Short name T408
Test name
Test status
Simulation time 360027723 ps
CPU time 0.84 seconds
Started Aug 27 08:00:14 PM UTC 24
Finished Aug 27 08:00:16 PM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931122843 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3931122843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/35.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.1271485087
Short name T410
Test name
Test status
Simulation time 281373299 ps
CPU time 0.95 seconds
Started Aug 27 08:00:14 PM UTC 24
Finished Aug 27 08:00:16 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271485087 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1271485087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/36.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.1245467319
Short name T407
Test name
Test status
Simulation time 403855522 ps
CPU time 0.64 seconds
Started Aug 27 08:00:14 PM UTC 24
Finished Aug 27 08:00:16 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245467319 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1245467319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/37.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.4076065108
Short name T417
Test name
Test status
Simulation time 511708910 ps
CPU time 0.97 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:17 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076065108 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4076065108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/38.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.2921160612
Short name T414
Test name
Test status
Simulation time 313127933 ps
CPU time 0.79 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:17 PM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921160612 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2921160612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/39.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1907579652
Short name T60
Test name
Test status
Simulation time 488108548 ps
CPU time 1.73 seconds
Started Aug 27 07:59:47 PM UTC 24
Finished Aug 27 07:59:49 PM UTC 24
Peak memory 201784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907579652 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.1907579652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1552904358
Short name T350
Test name
Test status
Simulation time 6837408134 ps
CPU time 15.28 seconds
Started Aug 27 07:59:47 PM UTC 24
Finished Aug 27 08:00:03 PM UTC 24
Peak memory 205724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552904358 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.1552904358
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2086782833
Short name T58
Test name
Test status
Simulation time 770583353 ps
CPU time 1.38 seconds
Started Aug 27 07:59:46 PM UTC 24
Finished Aug 27 07:59:48 PM UTC 24
Peak memory 199552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086782833 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.2086782833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.22577901
Short name T318
Test name
Test status
Simulation time 701567850 ps
CPU time 1.45 seconds
Started Aug 27 07:59:47 PM UTC 24
Finished Aug 27 07:59:49 PM UTC 24
Peak memory 206948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=22577901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer
_csr_mem_rw_with_rand_reset.22577901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3649846038
Short name T57
Test name
Test status
Simulation time 415105370 ps
CPU time 1.09 seconds
Started Aug 27 07:59:46 PM UTC 24
Finished Aug 27 07:59:48 PM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649846038 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3649846038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.1051175180
Short name T315
Test name
Test status
Simulation time 344765466 ps
CPU time 1 seconds
Started Aug 27 07:59:45 PM UTC 24
Finished Aug 27 07:59:47 PM UTC 24
Peak memory 201824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051175180 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1051175180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2200076727
Short name T314
Test name
Test status
Simulation time 353905540 ps
CPU time 0.83 seconds
Started Aug 27 07:59:45 PM UTC 24
Finished Aug 27 07:59:47 PM UTC 24
Peak memory 199856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200076727 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.2200076727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2223404671
Short name T316
Test name
Test status
Simulation time 488968868 ps
CPU time 1.35 seconds
Started Aug 27 07:59:45 PM UTC 24
Finished Aug 27 07:59:48 PM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223404671 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.2223404671
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2641230745
Short name T72
Test name
Test status
Simulation time 966903534 ps
CPU time 1.47 seconds
Started Aug 27 07:59:47 PM UTC 24
Finished Aug 27 07:59:49 PM UTC 24
Peak memory 201904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641230745 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.2641230745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.3798283832
Short name T317
Test name
Test status
Simulation time 533243255 ps
CPU time 2.67 seconds
Started Aug 27 07:59:45 PM UTC 24
Finished Aug 27 07:59:49 PM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798283832 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3798283832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.524126292
Short name T330
Test name
Test status
Simulation time 4624836274 ps
CPU time 9.14 seconds
Started Aug 27 07:59:45 PM UTC 24
Finished Aug 27 07:59:56 PM UTC 24
Peak memory 206844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524126292 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.524126292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.245745611
Short name T416
Test name
Test status
Simulation time 431951365 ps
CPU time 0.86 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:17 PM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245745611 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.245745611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/40.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.4121543783
Short name T415
Test name
Test status
Simulation time 412724761 ps
CPU time 0.67 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:17 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121543783 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.4121543783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/41.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.3757329090
Short name T418
Test name
Test status
Simulation time 316879472 ps
CPU time 0.94 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:17 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757329090 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3757329090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/42.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.480200375
Short name T419
Test name
Test status
Simulation time 400467920 ps
CPU time 1.05 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:17 PM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480200375 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.480200375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/43.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.527454698
Short name T424
Test name
Test status
Simulation time 374350411 ps
CPU time 1.21 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:18 PM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527454698 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.527454698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/44.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.787695433
Short name T420
Test name
Test status
Simulation time 539213825 ps
CPU time 0.75 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:17 PM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787695433 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.787695433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/45.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.3737766383
Short name T423
Test name
Test status
Simulation time 396005948 ps
CPU time 1.1 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:18 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737766383 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3737766383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/46.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.2375557774
Short name T422
Test name
Test status
Simulation time 459960222 ps
CPU time 1.02 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:18 PM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375557774 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2375557774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/47.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.9246412
Short name T425
Test name
Test status
Simulation time 392661401 ps
CPU time 1.37 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:18 PM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9246412 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.9246412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/48.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.2558800503
Short name T421
Test name
Test status
Simulation time 316844110 ps
CPU time 0.83 seconds
Started Aug 27 08:00:15 PM UTC 24
Finished Aug 27 08:00:18 PM UTC 24
Peak memory 201768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558800503 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2558800503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/49.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3389507427
Short name T321
Test name
Test status
Simulation time 438285048 ps
CPU time 0.96 seconds
Started Aug 27 07:59:49 PM UTC 24
Finished Aug 27 07:59:51 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3389507427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_tim
er_csr_mem_rw_with_rand_reset.3389507427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.739615470
Short name T320
Test name
Test status
Simulation time 480292602 ps
CPU time 1.23 seconds
Started Aug 27 07:59:48 PM UTC 24
Finished Aug 27 07:59:50 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739615470 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.739615470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.134208506
Short name T319
Test name
Test status
Simulation time 470820061 ps
CPU time 1.14 seconds
Started Aug 27 07:59:48 PM UTC 24
Finished Aug 27 07:59:50 PM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134208506 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.134208506
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.30866086
Short name T73
Test name
Test status
Simulation time 2579295325 ps
CPU time 1.94 seconds
Started Aug 27 07:59:49 PM UTC 24
Finished Aug 27 07:59:52 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30866086 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.30866086
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.2663387013
Short name T322
Test name
Test status
Simulation time 538229750 ps
CPU time 3.04 seconds
Started Aug 27 07:59:48 PM UTC 24
Finished Aug 27 07:59:52 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663387013 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2663387013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2854458740
Short name T205
Test name
Test status
Simulation time 4535758098 ps
CPU time 8 seconds
Started Aug 27 07:59:48 PM UTC 24
Finished Aug 27 07:59:57 PM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854458740 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.2854458740
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.998438133
Short name T326
Test name
Test status
Simulation time 448191076 ps
CPU time 2.39 seconds
Started Aug 27 07:59:50 PM UTC 24
Finished Aug 27 07:59:54 PM UTC 24
Peak memory 205760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=998438133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_time
r_csr_mem_rw_with_rand_reset.998438133
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.391226449
Short name T324
Test name
Test status
Simulation time 431819332 ps
CPU time 1.1 seconds
Started Aug 27 07:59:50 PM UTC 24
Finished Aug 27 07:59:53 PM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391226449 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.391226449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.4285978917
Short name T323
Test name
Test status
Simulation time 477875728 ps
CPU time 0.96 seconds
Started Aug 27 07:59:50 PM UTC 24
Finished Aug 27 07:59:52 PM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285978917 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.4285978917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1116164048
Short name T74
Test name
Test status
Simulation time 1419111367 ps
CPU time 1.82 seconds
Started Aug 27 07:59:50 PM UTC 24
Finished Aug 27 07:59:53 PM UTC 24
Peak memory 201904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116164048 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.1116164048
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.1904970090
Short name T328
Test name
Test status
Simulation time 422485359 ps
CPU time 4.37 seconds
Started Aug 27 07:59:49 PM UTC 24
Finished Aug 27 07:59:55 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904970090 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1904970090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1817204768
Short name T335
Test name
Test status
Simulation time 4451546417 ps
CPU time 5.75 seconds
Started Aug 27 07:59:50 PM UTC 24
Finished Aug 27 07:59:57 PM UTC 24
Peak memory 206976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817204768 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.1817204768
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2758912587
Short name T332
Test name
Test status
Simulation time 459346028 ps
CPU time 1.72 seconds
Started Aug 27 07:59:53 PM UTC 24
Finished Aug 27 07:59:56 PM UTC 24
Peak memory 204892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2758912587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim
er_csr_mem_rw_with_rand_reset.2758912587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.4220606047
Short name T329
Test name
Test status
Simulation time 536352596 ps
CPU time 1.17 seconds
Started Aug 27 07:59:53 PM UTC 24
Finished Aug 27 07:59:55 PM UTC 24
Peak memory 200864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220606047 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.4220606047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.3317773892
Short name T325
Test name
Test status
Simulation time 273943492 ps
CPU time 1.18 seconds
Started Aug 27 07:59:52 PM UTC 24
Finished Aug 27 07:59:54 PM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317773892 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3317773892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3406936637
Short name T75
Test name
Test status
Simulation time 2076266798 ps
CPU time 2.25 seconds
Started Aug 27 07:59:53 PM UTC 24
Finished Aug 27 07:59:57 PM UTC 24
Peak memory 205432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406936637 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.3406936637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.3408661835
Short name T327
Test name
Test status
Simulation time 730892221 ps
CPU time 3.19 seconds
Started Aug 27 07:59:51 PM UTC 24
Finished Aug 27 07:59:55 PM UTC 24
Peak memory 207012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408661835 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3408661835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1483615079
Short name T201
Test name
Test status
Simulation time 8299164018 ps
CPU time 8.02 seconds
Started Aug 27 07:59:52 PM UTC 24
Finished Aug 27 08:00:01 PM UTC 24
Peak memory 207116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483615079 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.1483615079
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1850692873
Short name T333
Test name
Test status
Simulation time 534179246 ps
CPU time 1.28 seconds
Started Aug 27 07:59:54 PM UTC 24
Finished Aug 27 07:59:57 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1850692873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim
er_csr_mem_rw_with_rand_reset.1850692873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.1599103828
Short name T76
Test name
Test status
Simulation time 431725754 ps
CPU time 2.16 seconds
Started Aug 27 07:59:53 PM UTC 24
Finished Aug 27 07:59:57 PM UTC 24
Peak memory 203196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599103828 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1599103828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.1287829183
Short name T331
Test name
Test status
Simulation time 527246670 ps
CPU time 1.47 seconds
Started Aug 27 07:59:53 PM UTC 24
Finished Aug 27 07:59:56 PM UTC 24
Peak memory 198924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287829183 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1287829183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1303643850
Short name T338
Test name
Test status
Simulation time 2200509388 ps
CPU time 4.53 seconds
Started Aug 27 07:59:53 PM UTC 24
Finished Aug 27 07:59:59 PM UTC 24
Peak memory 205496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303643850 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.1303643850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.4072491080
Short name T334
Test name
Test status
Simulation time 431859217 ps
CPU time 2.7 seconds
Started Aug 27 07:59:53 PM UTC 24
Finished Aug 27 07:59:57 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072491080 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4072491080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.619157036
Short name T340
Test name
Test status
Simulation time 7812196824 ps
CPU time 5.2 seconds
Started Aug 27 07:59:53 PM UTC 24
Finished Aug 27 08:00:00 PM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619157036 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.619157036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.551284835
Short name T339
Test name
Test status
Simulation time 416505505 ps
CPU time 1.13 seconds
Started Aug 27 07:59:57 PM UTC 24
Finished Aug 27 07:59:59 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=551284835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_time
r_csr_mem_rw_with_rand_reset.551284835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.2144516223
Short name T61
Test name
Test status
Simulation time 473257256 ps
CPU time 0.89 seconds
Started Aug 27 07:59:56 PM UTC 24
Finished Aug 27 07:59:59 PM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144516223 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2144516223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.2441031512
Short name T341
Test name
Test status
Simulation time 423785415 ps
CPU time 2.18 seconds
Started Aug 27 07:59:56 PM UTC 24
Finished Aug 27 08:00:00 PM UTC 24
Peak memory 201460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441031512 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2441031512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1054457502
Short name T343
Test name
Test status
Simulation time 2933077627 ps
CPU time 2.31 seconds
Started Aug 27 07:59:57 PM UTC 24
Finished Aug 27 08:00:00 PM UTC 24
Peak memory 205624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054457502 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.1054457502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1921450872
Short name T337
Test name
Test status
Simulation time 432989209 ps
CPU time 1.89 seconds
Started Aug 27 07:59:55 PM UTC 24
Finished Aug 27 07:59:58 PM UTC 24
Peak memory 207028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921450872 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1921450872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.552338263
Short name T347
Test name
Test status
Simulation time 8150478166 ps
CPU time 5.33 seconds
Started Aug 27 07:59:55 PM UTC 24
Finished Aug 27 08:00:02 PM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552338263 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.552338263
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.2057978515
Short name T4
Test name
Test status
Simulation time 1652593097 ps
CPU time 1.7 seconds
Started Aug 27 07:56:45 PM UTC 24
Finished Aug 27 07:56:48 PM UTC 24
Peak memory 199616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057978515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2057978515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1032879365
Short name T5
Test name
Test status
Simulation time 424067925 ps
CPU time 1.99 seconds
Started Aug 27 07:56:45 PM UTC 24
Finished Aug 27 07:56:48 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032879365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1032879365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.1957381946
Short name T15
Test name
Test status
Simulation time 3992156011 ps
CPU time 8.3 seconds
Started Aug 27 07:56:45 PM UTC 24
Finished Aug 27 07:56:55 PM UTC 24
Peak memory 201104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1957381946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.aon_timer_stress_all_with_rand_reset.1957381946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.3814079623
Short name T238
Test name
Test status
Simulation time 41334668412 ps
CPU time 72.6 seconds
Started Aug 27 07:56:45 PM UTC 24
Finished Aug 27 07:58:00 PM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814079623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3814079623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.4176685188
Short name T12
Test name
Test status
Simulation time 8556944624 ps
CPU time 3.24 seconds
Started Aug 27 07:56:47 PM UTC 24
Finished Aug 27 07:56:51 PM UTC 24
Peak memory 231380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176685188 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.4176685188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.54002518
Short name T1
Test name
Test status
Simulation time 492430924 ps
CPU time 0.84 seconds
Started Aug 27 07:56:45 PM UTC 24
Finished Aug 27 07:56:47 PM UTC 24
Peak memory 199980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54002518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.54002518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/1.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.2206820778
Short name T84
Test name
Test status
Simulation time 34383292999 ps
CPU time 5.17 seconds
Started Aug 27 07:57:03 PM UTC 24
Finished Aug 27 07:57:09 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206820778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2206820778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.971007741
Short name T31
Test name
Test status
Simulation time 454787588 ps
CPU time 2.25 seconds
Started Aug 27 07:57:01 PM UTC 24
Finished Aug 27 07:57:05 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971007741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.971007741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/10.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.1103111082
Short name T210
Test name
Test status
Simulation time 28506470819 ps
CPU time 9.46 seconds
Started Aug 27 07:57:06 PM UTC 24
Finished Aug 27 07:57:17 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103111082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1103111082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.4246472751
Short name T218
Test name
Test status
Simulation time 446573133 ps
CPU time 1.04 seconds
Started Aug 27 07:57:05 PM UTC 24
Finished Aug 27 07:57:07 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246472751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4246472751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.1297644554
Short name T209
Test name
Test status
Simulation time 39982462517 ps
CPU time 29.73 seconds
Started Aug 27 07:57:07 PM UTC 24
Finished Aug 27 07:57:38 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297644554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1297644554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.861175196
Short name T217
Test name
Test status
Simulation time 608254731 ps
CPU time 1.53 seconds
Started Aug 27 07:57:07 PM UTC 24
Finished Aug 27 07:57:10 PM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861175196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.861175196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/12.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.624624113
Short name T223
Test name
Test status
Simulation time 23534137681 ps
CPU time 15.99 seconds
Started Aug 27 07:57:10 PM UTC 24
Finished Aug 27 07:57:27 PM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624624113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.624624113
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.4046272846
Short name T219
Test name
Test status
Simulation time 556304899 ps
CPU time 2.04 seconds
Started Aug 27 07:57:10 PM UTC 24
Finished Aug 27 07:57:13 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046272846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.4046272846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/13.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.2746195612
Short name T243
Test name
Test status
Simulation time 31080598488 ps
CPU time 53.48 seconds
Started Aug 27 07:57:13 PM UTC 24
Finished Aug 27 07:58:08 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746195612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2746195612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.2869357051
Short name T32
Test name
Test status
Simulation time 455260756 ps
CPU time 1.18 seconds
Started Aug 27 07:57:12 PM UTC 24
Finished Aug 27 07:57:15 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869357051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2869357051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/14.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.3494934364
Short name T268
Test name
Test status
Simulation time 58906512594 ps
CPU time 106.54 seconds
Started Aug 27 07:57:17 PM UTC 24
Finished Aug 27 07:59:05 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494934364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3494934364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.3493144405
Short name T220
Test name
Test status
Simulation time 498494153 ps
CPU time 1.13 seconds
Started Aug 27 07:57:16 PM UTC 24
Finished Aug 27 07:57:18 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493144405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3493144405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/15.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.1617173024
Short name T275
Test name
Test status
Simulation time 46808731817 ps
CPU time 113.71 seconds
Started Aug 27 07:57:19 PM UTC 24
Finished Aug 27 07:59:15 PM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617173024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1617173024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.1562543913
Short name T221
Test name
Test status
Simulation time 515918820 ps
CPU time 2.23 seconds
Started Aug 27 07:57:19 PM UTC 24
Finished Aug 27 07:57:22 PM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562543913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1562543913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/16.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.1170515249
Short name T229
Test name
Test status
Simulation time 38174874880 ps
CPU time 15.94 seconds
Started Aug 27 07:57:25 PM UTC 24
Finished Aug 27 07:57:43 PM UTC 24
Peak memory 200644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170515249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1170515249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.2598337274
Short name T222
Test name
Test status
Simulation time 590005397 ps
CPU time 1.4 seconds
Started Aug 27 07:57:24 PM UTC 24
Finished Aug 27 07:57:27 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598337274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2598337274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/17.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.2465758630
Short name T206
Test name
Test status
Simulation time 851382604 ps
CPU time 1.51 seconds
Started Aug 27 07:57:28 PM UTC 24
Finished Aug 27 07:57:31 PM UTC 24
Peak memory 199620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465758630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2465758630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.3241862222
Short name T224
Test name
Test status
Simulation time 509563114 ps
CPU time 2.17 seconds
Started Aug 27 07:57:28 PM UTC 24
Finished Aug 27 07:57:31 PM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241862222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3241862222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/18.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.310354662
Short name T207
Test name
Test status
Simulation time 9426873697 ps
CPU time 5.28 seconds
Started Aug 27 07:57:32 PM UTC 24
Finished Aug 27 07:57:38 PM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310354662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.310354662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.918023203
Short name T225
Test name
Test status
Simulation time 400031027 ps
CPU time 2.06 seconds
Started Aug 27 07:57:31 PM UTC 24
Finished Aug 27 07:57:34 PM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918023203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.918023203
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/19.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.2964535694
Short name T208
Test name
Test status
Simulation time 20046099795 ps
CPU time 31.97 seconds
Started Aug 27 07:56:50 PM UTC 24
Finished Aug 27 07:57:24 PM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964535694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2964535694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.1125439889
Short name T25
Test name
Test status
Simulation time 4343099384 ps
CPU time 3.78 seconds
Started Aug 27 07:56:50 PM UTC 24
Finished Aug 27 07:56:55 PM UTC 24
Peak memory 231156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125439889 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1125439889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.4292974060
Short name T6
Test name
Test status
Simulation time 595455662 ps
CPU time 1.66 seconds
Started Aug 27 07:56:47 PM UTC 24
Finished Aug 27 07:56:50 PM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292974060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.4292974060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/2.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.826536716
Short name T264
Test name
Test status
Simulation time 49658518837 ps
CPU time 81.52 seconds
Started Aug 27 07:57:34 PM UTC 24
Finished Aug 27 07:58:57 PM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826536716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.826536716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/20.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.321726042
Short name T163
Test name
Test status
Simulation time 395246539 ps
CPU time 1.44 seconds
Started Aug 27 07:57:34 PM UTC 24
Finished Aug 27 07:57:36 PM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321726042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.321726042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/20.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.28870581
Short name T212
Test name
Test status
Simulation time 35614488806 ps
CPU time 10.46 seconds
Started Aug 27 07:57:36 PM UTC 24
Finished Aug 27 07:57:48 PM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28870581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.28870581
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/21.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.695837445
Short name T226
Test name
Test status
Simulation time 495352050 ps
CPU time 1.02 seconds
Started Aug 27 07:57:36 PM UTC 24
Finished Aug 27 07:57:38 PM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695837445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.695837445
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/21.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.362191195
Short name T233
Test name
Test status
Simulation time 25463377877 ps
CPU time 12 seconds
Started Aug 27 07:57:38 PM UTC 24
Finished Aug 27 07:57:51 PM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362191195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.362191195
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/22.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.2959500493
Short name T227
Test name
Test status
Simulation time 369656887 ps
CPU time 1.86 seconds
Started Aug 27 07:57:38 PM UTC 24
Finished Aug 27 07:57:40 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959500493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2959500493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/22.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.62892281
Short name T235
Test name
Test status
Simulation time 42022449276 ps
CPU time 14.97 seconds
Started Aug 27 07:57:39 PM UTC 24
Finished Aug 27 07:57:55 PM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62892281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.62892281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/23.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.1033663139
Short name T228
Test name
Test status
Simulation time 583667795 ps
CPU time 1.26 seconds
Started Aug 27 07:57:39 PM UTC 24
Finished Aug 27 07:57:41 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033663139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1033663139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/23.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.1133512472
Short name T241
Test name
Test status
Simulation time 44965429586 ps
CPU time 20.3 seconds
Started Aug 27 07:57:42 PM UTC 24
Finished Aug 27 07:58:04 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133512472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1133512472
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/24.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.2168096215
Short name T230
Test name
Test status
Simulation time 600640340 ps
CPU time 0.89 seconds
Started Aug 27 07:57:42 PM UTC 24
Finished Aug 27 07:57:44 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168096215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2168096215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/24.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.3519234724
Short name T251
Test name
Test status
Simulation time 43583639247 ps
CPU time 43.07 seconds
Started Aug 27 07:57:45 PM UTC 24
Finished Aug 27 07:58:29 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519234724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3519234724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/25.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.3556087308
Short name T231
Test name
Test status
Simulation time 583849057 ps
CPU time 0.86 seconds
Started Aug 27 07:57:44 PM UTC 24
Finished Aug 27 07:57:46 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556087308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3556087308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/25.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.3172775802
Short name T236
Test name
Test status
Simulation time 10594000735 ps
CPU time 9.65 seconds
Started Aug 27 07:57:48 PM UTC 24
Finished Aug 27 07:57:59 PM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172775802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3172775802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/26.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.3212582122
Short name T232
Test name
Test status
Simulation time 476774192 ps
CPU time 1.16 seconds
Started Aug 27 07:57:47 PM UTC 24
Finished Aug 27 07:57:49 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212582122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3212582122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/26.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.932496488
Short name T239
Test name
Test status
Simulation time 23301265045 ps
CPU time 5.87 seconds
Started Aug 27 07:57:54 PM UTC 24
Finished Aug 27 07:58:01 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932496488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.932496488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/27.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.409268554
Short name T234
Test name
Test status
Simulation time 478554460 ps
CPU time 1.97 seconds
Started Aug 27 07:57:52 PM UTC 24
Finished Aug 27 07:57:54 PM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409268554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.409268554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/27.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.3775516916
Short name T244
Test name
Test status
Simulation time 2220887184 ps
CPU time 15.03 seconds
Started Aug 27 07:57:56 PM UTC 24
Finished Aug 27 07:58:12 PM UTC 24
Peak memory 217376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3775516916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 27.aon_timer_stress_all_with_rand_reset.3775516916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.3298942202
Short name T252
Test name
Test status
Simulation time 17289004813 ps
CPU time 29.72 seconds
Started Aug 27 07:57:59 PM UTC 24
Finished Aug 27 07:58:30 PM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298942202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3298942202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/28.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.515467039
Short name T237
Test name
Test status
Simulation time 387770400 ps
CPU time 1.78 seconds
Started Aug 27 07:57:57 PM UTC 24
Finished Aug 27 07:58:00 PM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515467039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.515467039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/28.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.3192160992
Short name T255
Test name
Test status
Simulation time 13543485631 ps
CPU time 32.4 seconds
Started Aug 27 07:58:03 PM UTC 24
Finished Aug 27 07:58:37 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192160992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3192160992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/29.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.1701066514
Short name T240
Test name
Test status
Simulation time 412759048 ps
CPU time 1.09 seconds
Started Aug 27 07:58:01 PM UTC 24
Finished Aug 27 07:58:03 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701066514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1701066514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/29.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.593486315
Short name T211
Test name
Test status
Simulation time 32120553279 ps
CPU time 16.36 seconds
Started Aug 27 07:56:50 PM UTC 24
Finished Aug 27 07:57:08 PM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593486315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.593486315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.3798485788
Short name T29
Test name
Test status
Simulation time 7870860256 ps
CPU time 13.49 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 07:57:05 PM UTC 24
Peak memory 231248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798485788 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3798485788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.873347650
Short name T10
Test name
Test status
Simulation time 441603742 ps
CPU time 1.49 seconds
Started Aug 27 07:56:50 PM UTC 24
Finished Aug 27 07:56:53 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873347650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.873347650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.1467748968
Short name T22
Test name
Test status
Simulation time 7840150389 ps
CPU time 18.04 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 07:57:10 PM UTC 24
Peak memory 218040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1467748968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 3.aon_timer_stress_all_with_rand_reset.1467748968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.4007287434
Short name T249
Test name
Test status
Simulation time 15587683940 ps
CPU time 13.85 seconds
Started Aug 27 07:58:07 PM UTC 24
Finished Aug 27 07:58:22 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007287434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4007287434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/30.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.4146802883
Short name T242
Test name
Test status
Simulation time 455854418 ps
CPU time 1.06 seconds
Started Aug 27 07:58:06 PM UTC 24
Finished Aug 27 07:58:08 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146802883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.4146802883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/30.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.1902849845
Short name T262
Test name
Test status
Simulation time 23672197164 ps
CPU time 40.71 seconds
Started Aug 27 07:58:09 PM UTC 24
Finished Aug 27 07:58:51 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902849845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1902849845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/31.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.2265051600
Short name T245
Test name
Test status
Simulation time 609413438 ps
CPU time 2.2 seconds
Started Aug 27 07:58:09 PM UTC 24
Finished Aug 27 07:58:12 PM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265051600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2265051600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/31.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.4237434862
Short name T256
Test name
Test status
Simulation time 39778301813 ps
CPU time 24.33 seconds
Started Aug 27 07:58:12 PM UTC 24
Finished Aug 27 07:58:38 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237434862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.4237434862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/32.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.1016041864
Short name T246
Test name
Test status
Simulation time 583188324 ps
CPU time 0.98 seconds
Started Aug 27 07:58:12 PM UTC 24
Finished Aug 27 07:58:14 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016041864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1016041864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/32.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.2915577380
Short name T272
Test name
Test status
Simulation time 26344997761 ps
CPU time 55.92 seconds
Started Aug 27 07:58:14 PM UTC 24
Finished Aug 27 07:59:11 PM UTC 24
Peak memory 200636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915577380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2915577380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/33.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.1037208357
Short name T247
Test name
Test status
Simulation time 562763520 ps
CPU time 1.19 seconds
Started Aug 27 07:58:14 PM UTC 24
Finished Aug 27 07:58:16 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037208357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1037208357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/33.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.3354595362
Short name T253
Test name
Test status
Simulation time 15090319294 ps
CPU time 12.35 seconds
Started Aug 27 07:58:18 PM UTC 24
Finished Aug 27 07:58:32 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354595362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3354595362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/34.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.429877941
Short name T248
Test name
Test status
Simulation time 359911280 ps
CPU time 1.12 seconds
Started Aug 27 07:58:16 PM UTC 24
Finished Aug 27 07:58:18 PM UTC 24
Peak memory 199212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429877941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.429877941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/34.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.516049679
Short name T258
Test name
Test status
Simulation time 24734872257 ps
CPU time 13.98 seconds
Started Aug 27 07:58:26 PM UTC 24
Finished Aug 27 07:58:41 PM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516049679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.516049679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/35.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.1660177653
Short name T250
Test name
Test status
Simulation time 559329853 ps
CPU time 0.94 seconds
Started Aug 27 07:58:23 PM UTC 24
Finished Aug 27 07:58:25 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660177653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1660177653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/35.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.4090611331
Short name T283
Test name
Test status
Simulation time 49228695570 ps
CPU time 49.78 seconds
Started Aug 27 07:58:33 PM UTC 24
Finished Aug 27 07:59:25 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090611331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.4090611331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/36.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.224372238
Short name T254
Test name
Test status
Simulation time 493963660 ps
CPU time 2.23 seconds
Started Aug 27 07:58:33 PM UTC 24
Finished Aug 27 07:58:37 PM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224372238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.224372238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/36.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.2808910493
Short name T266
Test name
Test status
Simulation time 26149112513 ps
CPU time 24.05 seconds
Started Aug 27 07:58:37 PM UTC 24
Finished Aug 27 07:59:03 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808910493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2808910493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/37.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.1392618146
Short name T257
Test name
Test status
Simulation time 537546565 ps
CPU time 1.46 seconds
Started Aug 27 07:58:37 PM UTC 24
Finished Aug 27 07:58:40 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392618146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1392618146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/37.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.4133458601
Short name T276
Test name
Test status
Simulation time 4581941946 ps
CPU time 35.14 seconds
Started Aug 27 07:58:38 PM UTC 24
Finished Aug 27 07:59:15 PM UTC 24
Peak memory 219136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4133458601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 37.aon_timer_stress_all_with_rand_reset.4133458601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.2904492900
Short name T281
Test name
Test status
Simulation time 27892188408 ps
CPU time 40.73 seconds
Started Aug 27 07:58:40 PM UTC 24
Finished Aug 27 07:59:22 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904492900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2904492900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/38.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.390792743
Short name T259
Test name
Test status
Simulation time 591370860 ps
CPU time 1.13 seconds
Started Aug 27 07:58:40 PM UTC 24
Finished Aug 27 07:58:42 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390792743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.390792743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/38.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.181310677
Short name T83
Test name
Test status
Simulation time 5761257164 ps
CPU time 17.02 seconds
Started Aug 27 07:58:42 PM UTC 24
Finished Aug 27 07:59:00 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=181310677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 38.aon_timer_stress_all_with_rand_reset.181310677
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.3255594966
Short name T287
Test name
Test status
Simulation time 38364096640 ps
CPU time 81.49 seconds
Started Aug 27 07:58:43 PM UTC 24
Finished Aug 27 08:00:06 PM UTC 24
Peak memory 200772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255594966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3255594966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/39.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.327945698
Short name T260
Test name
Test status
Simulation time 428362071 ps
CPU time 1.1 seconds
Started Aug 27 07:58:43 PM UTC 24
Finished Aug 27 07:58:45 PM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327945698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.327945698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/39.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.25882486
Short name T19
Test name
Test status
Simulation time 29925700786 ps
CPU time 8.54 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 07:57:00 PM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25882486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.25882486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.3272717151
Short name T28
Test name
Test status
Simulation time 4818053419 ps
CPU time 4.7 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 07:56:57 PM UTC 24
Peak memory 231344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272717151 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3272717151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.3830619358
Short name T9
Test name
Test status
Simulation time 548170316 ps
CPU time 1.15 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 07:56:53 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830619358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3830619358
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.2265503516
Short name T46
Test name
Test status
Simulation time 3711262854 ps
CPU time 23.32 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 07:57:15 PM UTC 24
Peak memory 213812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2265503516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 4.aon_timer_stress_all_with_rand_reset.2265503516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.25807516
Short name T271
Test name
Test status
Simulation time 12661834059 ps
CPU time 21.06 seconds
Started Aug 27 07:58:48 PM UTC 24
Finished Aug 27 07:59:10 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25807516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.25807516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/40.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.1974454229
Short name T261
Test name
Test status
Simulation time 531194056 ps
CPU time 1.63 seconds
Started Aug 27 07:58:48 PM UTC 24
Finished Aug 27 07:58:51 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974454229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1974454229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/40.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.348196691
Short name T286
Test name
Test status
Simulation time 25843097509 ps
CPU time 55.06 seconds
Started Aug 27 07:58:53 PM UTC 24
Finished Aug 27 07:59:50 PM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348196691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.348196691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/41.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.3196031382
Short name T263
Test name
Test status
Simulation time 385140059 ps
CPU time 0.97 seconds
Started Aug 27 07:58:52 PM UTC 24
Finished Aug 27 07:58:54 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196031382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3196031382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/41.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.4244172086
Short name T269
Test name
Test status
Simulation time 37765970101 ps
CPU time 6.68 seconds
Started Aug 27 07:58:58 PM UTC 24
Finished Aug 27 07:59:06 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244172086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4244172086
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/42.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.3374095367
Short name T265
Test name
Test status
Simulation time 556079051 ps
CPU time 2.16 seconds
Started Aug 27 07:58:57 PM UTC 24
Finished Aug 27 07:59:00 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374095367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3374095367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/42.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.3244934663
Short name T288
Test name
Test status
Simulation time 36954785902 ps
CPU time 67.86 seconds
Started Aug 27 07:59:03 PM UTC 24
Finished Aug 27 08:00:12 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244934663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3244934663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/43.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.1104244015
Short name T267
Test name
Test status
Simulation time 486801391 ps
CPU time 1.18 seconds
Started Aug 27 07:59:03 PM UTC 24
Finished Aug 27 07:59:05 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104244015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1104244015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/43.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.2117528288
Short name T273
Test name
Test status
Simulation time 16793400459 ps
CPU time 4.88 seconds
Started Aug 27 07:59:08 PM UTC 24
Finished Aug 27 07:59:14 PM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117528288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2117528288
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/44.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.2649690549
Short name T270
Test name
Test status
Simulation time 559007701 ps
CPU time 1.23 seconds
Started Aug 27 07:59:07 PM UTC 24
Finished Aug 27 07:59:09 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649690549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2649690549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/44.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.2892794441
Short name T279
Test name
Test status
Simulation time 9908883634 ps
CPU time 6.9 seconds
Started Aug 27 07:59:11 PM UTC 24
Finished Aug 27 07:59:19 PM UTC 24
Peak memory 200836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892794441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2892794441
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/45.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.2476743053
Short name T274
Test name
Test status
Simulation time 533001823 ps
CPU time 2.3 seconds
Started Aug 27 07:59:11 PM UTC 24
Finished Aug 27 07:59:15 PM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476743053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2476743053
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/45.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.145080774
Short name T291
Test name
Test status
Simulation time 50039523480 ps
CPU time 98.74 seconds
Started Aug 27 07:59:15 PM UTC 24
Finished Aug 27 08:00:55 PM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145080774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.145080774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/46.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.2350520838
Short name T277
Test name
Test status
Simulation time 403734745 ps
CPU time 1.42 seconds
Started Aug 27 07:59:13 PM UTC 24
Finished Aug 27 07:59:16 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350520838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2350520838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/46.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.2628714161
Short name T285
Test name
Test status
Simulation time 13427425455 ps
CPU time 21.75 seconds
Started Aug 27 07:59:16 PM UTC 24
Finished Aug 27 07:59:39 PM UTC 24
Peak memory 200708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628714161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2628714161
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/47.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.2299901026
Short name T278
Test name
Test status
Simulation time 363249056 ps
CPU time 1.71 seconds
Started Aug 27 07:59:16 PM UTC 24
Finished Aug 27 07:59:18 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299901026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2299901026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/47.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.1806029493
Short name T284
Test name
Test status
Simulation time 8516423273 ps
CPU time 19.31 seconds
Started Aug 27 07:59:18 PM UTC 24
Finished Aug 27 07:59:38 PM UTC 24
Peak memory 201328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1806029493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 47.aon_timer_stress_all_with_rand_reset.1806029493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.1965221453
Short name T290
Test name
Test status
Simulation time 34465038257 ps
CPU time 67.6 seconds
Started Aug 27 07:59:19 PM UTC 24
Finished Aug 27 08:00:28 PM UTC 24
Peak memory 200900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965221453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1965221453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/48.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.1805352790
Short name T280
Test name
Test status
Simulation time 461225210 ps
CPU time 1.25 seconds
Started Aug 27 07:59:19 PM UTC 24
Finished Aug 27 07:59:21 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805352790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1805352790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/48.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.3276111689
Short name T289
Test name
Test status
Simulation time 46620200223 ps
CPU time 58.99 seconds
Started Aug 27 07:59:22 PM UTC 24
Finished Aug 27 08:00:23 PM UTC 24
Peak memory 200512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276111689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3276111689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/49.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.3573531966
Short name T282
Test name
Test status
Simulation time 518520238 ps
CPU time 1.47 seconds
Started Aug 27 07:59:20 PM UTC 24
Finished Aug 27 07:59:23 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573531966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3573531966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/49.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.3317678604
Short name T21
Test name
Test status
Simulation time 7866384493 ps
CPU time 12.47 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 07:57:05 PM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317678604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3317678604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.2675546178
Short name T13
Test name
Test status
Simulation time 436268436 ps
CPU time 1.09 seconds
Started Aug 27 07:56:51 PM UTC 24
Finished Aug 27 07:56:53 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675546178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2675546178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/5.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.3804451877
Short name T20
Test name
Test status
Simulation time 16402217208 ps
CPU time 9.73 seconds
Started Aug 27 07:56:54 PM UTC 24
Finished Aug 27 07:57:04 PM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804451877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3804451877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.362514580
Short name T16
Test name
Test status
Simulation time 479078438 ps
CPU time 1.02 seconds
Started Aug 27 07:56:54 PM UTC 24
Finished Aug 27 07:56:56 PM UTC 24
Peak memory 199312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362514580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.362514580
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/6.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.2874246695
Short name T215
Test name
Test status
Simulation time 40746580865 ps
CPU time 35.59 seconds
Started Aug 27 07:56:55 PM UTC 24
Finished Aug 27 07:57:32 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874246695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2874246695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.3456222925
Short name T18
Test name
Test status
Simulation time 590728340 ps
CPU time 1.1 seconds
Started Aug 27 07:56:55 PM UTC 24
Finished Aug 27 07:56:57 PM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456222925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3456222925
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/7.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.2125218914
Short name T214
Test name
Test status
Simulation time 60505918710 ps
CPU time 9.17 seconds
Started Aug 27 07:56:56 PM UTC 24
Finished Aug 27 07:57:07 PM UTC 24
Peak memory 200892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125218914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2125218914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.1770302847
Short name T51
Test name
Test status
Simulation time 563665908 ps
CPU time 2.39 seconds
Started Aug 27 07:56:56 PM UTC 24
Finished Aug 27 07:57:00 PM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770302847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1770302847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/8.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.3807589229
Short name T213
Test name
Test status
Simulation time 56563669344 ps
CPU time 32.63 seconds
Started Aug 27 07:56:59 PM UTC 24
Finished Aug 27 07:57:33 PM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807589229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3807589229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.3879429564
Short name T216
Test name
Test status
Simulation time 575682379 ps
CPU time 1.43 seconds
Started Aug 27 07:56:59 PM UTC 24
Finished Aug 27 07:57:01 PM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879429564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3879429564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/9.aon_timer_smoke/latest
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