Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	16615	1			T1	11		T3	10		T5	11
bark[1]	309	1			T189	14		T93	21		T128	55
bark[2]	521	1			T20	84		T107	56		T91	21
bark[3]	433	1			T46	68		T99	55		T169	5
bark[4]	281	1			T47	180		T105	21		T91	21
bark[5]	103	1			T12	14		T191	14		T47	5
bark[6]	31	1			T103	21		T137	5		T116	5
bark[7]	246	1			T28	30		T44	7		T152	14
bark[8]	131	1			T34	14		T136	21		T134	7
bark[9]	626	1			T28	21		T107	197		T103	106
bark[10]	414	1			T35	14		T27	35		T113	14
bark[11]	472	1			T21	31		T44	47		T115	14
bark[12]	178	1			T117	14		T99	30		T91	21
bark[13]	410	1			T2	14		T21	5		T49	14
bark[14]	189	1			T30	5		T165	21		T93	51
bark[15]	218	1			T80	21		T125	21		T91	21
bark[16]	385	1			T14	14		T27	21		T44	5
bark[17]	475	1			T33	14		T90	49		T182	14
bark[18]	348	1			T174	14		T86	14		T173	7
bark[19]	113	1			T28	14		T173	26		T137	31
bark[20]	324	1			T4	14		T30	35		T28	21
bark[21]	460	1			T7	14		T164	14		T141	21
bark[22]	198	1			T125	14		T91	21		T157	7
bark[23]	572	1			T27	42		T78	255		T145	14
bark[24]	204	1			T90	26		T109	21		T157	47
bark[25]	172	1			T27	21		T175	14		T147	74
bark[26]	240	1			T43	106		T29	73		T109	35
bark[27]	706	1			T21	21		T44	231		T107	21
bark[28]	312	1			T126	14		T170	14		T125	14
bark[29]	330	1			T23	14		T13	14		T188	14
bark[30]	557	1			T8	14		T22	7		T30	21
bark[31]	448	1			T51	14		T99	14		T131	14
bark_0	4367	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	16197	1			T1	10		T3	9		T5	10
bite[1]	505	1			T30	34		T115	13		T103	21
bite[2]	259	1			T4	13		T14	13		T176	13
bite[3]	509	1			T13	13		T43	105		T28	30
bite[4]	190	1			T103	106		T97	21		T142	21
bite[5]	123	1			T35	13		T21	30		T47	4
bite[6]	113	1			T21	21		T169	6		T102	13
bite[7]	693	1			T27	42		T107	30		T105	64
bite[8]	438	1			T29	32		T90	49		T107	21
bite[9]	85	1			T30	21		T109	35		T91	21
bite[10]	596	1			T2	13		T49	13		T28	21
bite[11]	210	1			T28	21		T173	6		T169	4
bite[12]	85	1			T118	13		T104	51		T89	21
bite[13]	375	1			T107	196		T184	13		T181	42
bite[14]	289	1			T7	13		T27	21		T107	55
bite[15]	153	1			T30	4		T126	13		T157	6
bite[16]	284	1			T47	179		T80	59		T125	4
bite[17]	347	1			T12	13		T53	13		T165	21
bite[18]	601	1			T156	13		T117	13		T97	68
bite[19]	129	1			T34	13		T144	13		T165	21
bite[20]	421	1			T33	13		T78	214		T139	13
bite[21]	225	1			T145	13		T182	13		T91	21
bite[22]	545	1			T20	83		T47	4		T169	154
bite[23]	325	1			T8	13		T188	13		T44	46
bite[24]	410	1			T86	13		T45	21		T183	13
bite[25]	275	1			T23	13		T22	6		T99	55
bite[26]	76	1			T27	21		T169	4		T93	30
bite[27]	172	1			T191	13		T28	13		T29	40
bite[28]	698	1			T21	4		T51	13		T107	44
bite[29]	675	1			T44	6		T46	67		T78	34
bite[30]	189	1			T27	35		T189	13		T91	21
bite[31]	393	1			T174	13		T44	230		T149	21
bite_0	4803	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27610

1

T1

11

T2

21

T3

17

auto[1]

3778

1

T1

7

T20

98

T77

7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	279	1			T107	19		T199	9		T99	33
prescale[1]	218	1			T28	23		T48	2		T90	23
prescale[2]	392	1			T45	38		T46	2		T48	9
prescale[3]	383	1			T28	24		T78	2		T149	76
prescale[4]	506	1			T99	23		T169	40		T103	28
prescale[5]	408	1			T85	9		T45	19		T29	9
prescale[6]	451	1			T30	19		T46	38		T47	24
prescale[7]	233	1			T200	9		T78	2		T99	19
prescale[8]	642	1			T20	2		T21	2		T201	9
prescale[9]	306	1			T28	19		T45	36		T107	2
prescale[10]	302	1			T30	2		T45	85		T48	2
prescale[11]	283	1			T30	111		T44	2		T45	2
prescale[12]	426	1			T46	49		T178	2		T80	2
prescale[13]	669	1			T27	30		T44	28		T45	38
prescale[14]	235	1			T20	2		T30	57		T88	9
prescale[15]	390	1			T99	28		T178	2		T109	23
prescale[16]	281	1			T50	9		T43	2		T78	23
prescale[17]	210	1			T45	2		T90	19		T165	50
prescale[18]	407	1			T30	2		T46	2		T47	2
prescale[19]	359	1			T202	9		T79	2		T157	41
prescale[20]	387	1			T30	4		T28	19		T44	75
prescale[21]	116	1			T103	24		T97	2		T106	19
prescale[22]	289	1			T19	9		T46	2		T107	40
prescale[23]	244	1			T43	2		T87	9		T28	19
prescale[24]	623	1			T22	2		T47	12		T107	9
prescale[25]	205	1			T29	19		T149	23		T203	9
prescale[26]	457	1			T22	2		T43	2		T29	38
prescale[27]	184	1			T78	2		T105	28		T93	19
prescale[28]	559	1			T43	2		T46	59		T78	2
prescale[29]	450	1			T22	12		T30	19		T45	19
prescale[30]	475	1			T30	2		T44	19		T46	78
prescale[31]	582	1			T30	40		T44	68		T46	9
prescale_0	19437	1			T1	18		T2	21		T3	17

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20977

1

T1

9

T2

9

T3

17

auto[1]

10411

1

T1

9

T2

12

T5

9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

31388

1

T1

18

T2

21

T3

17

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	17557	1			T1	13		T2	1		T3	12
wkup[1]	143	1			T14	15		T183	15		T169	35
wkup[2]	113	1			T44	8		T45	21		T78	21
wkup[3]	21	1			T27	21		-	-		-	-
wkup[4]	218	1			T47	21		T78	21		T90	21
wkup[5]	140	1			T30	6		T44	21		T45	21
wkup[6]	218	1			T125	15		T91	21		T82	8
wkup[7]	185	1			T44	21		T46	21		T78	15
wkup[8]	282	1			T20	70		T48	21		T78	21
wkup[9]	106	1			T123	15		T104	6		T151	21
wkup[10]	242	1			T188	15		T169	6		T80	21
wkup[11]	185	1			T48	21		T78	21		T176	15
wkup[12]	184	1			T27	35		T44	21		T45	21
wkup[13]	168	1			T30	15		T47	21		T149	21
wkup[14]	99	1			T105	21		T169	15		T96	21
wkup[15]	135	1			T21	21		T80	21		T106	20
wkup[16]	233	1			T53	15		T28	15		T91	21
wkup[17]	313	1			T27	42		T47	6		T107	21
wkup[18]	101	1			T78	8		T144	15		T157	21
wkup[19]	129	1			T109	21		T96	30		T142	21
wkup[20]	202	1			T45	21		T47	21		T78	26
wkup[21]	156	1			T78	21		T182	15		T142	21
wkup[22]	212	1			T43	21		T44	21		T107	21
wkup[23]	119	1			T51	15		T107	30		T131	15
wkup[24]	72	1			T23	15		T27	15		T154	21
wkup[25]	141	1			T43	21		T30	42		T99	21
wkup[26]	166	1			T47	21		T78	40		T169	21
wkup[27]	218	1			T78	36		T163	21		T97	21
wkup[28]	145	1			T78	21		T107	21		T157	21
wkup[29]	257	1			T174	15		T46	42		T165	21
wkup[30]	135	1			T30	30		T46	30		T172	54
wkup[31]	220	1			T30	15		T103	21		T109	35
wkup[32]	186	1			T33	15		T90	26		T126	15
wkup[33]	99	1			T184	15		T163	21		T96	21
wkup[34]	120	1			T164	15		T141	21		T83	6
wkup[35]	213	1			T20	15		T47	20		T90	30
wkup[36]	104	1			T169	8		T83	6		T142	6
wkup[37]	159	1			T157	26		T141	21		T134	21
wkup[38]	228	1			T44	6		T78	21		T178	21
wkup[39]	188	1			T2	15		T45	15		T46	21
wkup[40]	138	1			T44	21		T169	21		T170	15
wkup[41]	140	1			T30	21		T115	15		T189	15
wkup[42]	218	1			T7	15		T191	15		T45	21
wkup[43]	316	1			T30	27		T47	21		T93	61
wkup[44]	178	1			T12	15		T43	21		T163	26
wkup[45]	120	1			T30	21		T179	15		T163	21
wkup[46]	156	1			T46	21		T96	21		T128	21
wkup[47]	115	1			T13	15		T22	8		T28	21
wkup[48]	224	1			T28	30		T157	8		T192	15
wkup[49]	144	1			T34	15		T29	42		T78	42
wkup[50]	185	1			T80	21		T157	21		T140	15
wkup[51]	99	1			T21	21		T156	15		T78	21
wkup[52]	69	1			T21	6		T165	21		T154	21
wkup[53]	114	1			T43	21		T30	21		T78	21
wkup[54]	217	1			T48	21		T80	21		T97	26
wkup[55]	83	1			T27	21		T80	15		T163	26
wkup[56]	238	1			T4	15		T107	30		T105	21
wkup[57]	78	1			T28	21		T97	21		T96	21
wkup[58]	155	1			T47	6		T139	15		T157	21
wkup[59]	191	1			T35	15		T28	21		T44	15
wkup[60]	181	1			T30	21		T190	15		T104	21
wkup[61]	187	1			T8	15		T78	26		T107	21
wkup[62]	132	1			T30	21		T173	21		T81	39
wkup[63]	191	1			T49	15		T86	15		T149	21
wkup_0	3407	1			T1	5		T2	5		T3	5