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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.02 99.33 95.61 100.00 98.40 99.51 41.28


Total test records in report: 422
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T286 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.1137784656 Aug 29 11:02:03 AM UTC 24 Aug 29 11:02:06 AM UTC 24 522994425 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.734741250 Aug 29 11:02:04 AM UTC 24 Aug 29 11:02:08 AM UTC 24 477547668 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.375027335 Aug 29 11:02:05 AM UTC 24 Aug 29 11:02:08 AM UTC 24 998376090 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.3592061367 Aug 29 11:02:05 AM UTC 24 Aug 29 11:02:08 AM UTC 24 359318590 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1578928822 Aug 29 11:02:06 AM UTC 24 Aug 29 11:02:09 AM UTC 24 477905781 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3487909076 Aug 29 11:02:09 AM UTC 24 Aug 29 11:02:11 AM UTC 24 495728468 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2092332947 Aug 29 11:02:08 AM UTC 24 Aug 29 11:02:11 AM UTC 24 440303267 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.4274003221 Aug 29 11:02:09 AM UTC 24 Aug 29 11:02:12 AM UTC 24 551005302 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.475054102 Aug 29 11:02:08 AM UTC 24 Aug 29 11:02:12 AM UTC 24 9208995493 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2886146817 Aug 29 11:02:09 AM UTC 24 Aug 29 11:02:12 AM UTC 24 655740218 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2570719395 Aug 29 11:02:08 AM UTC 24 Aug 29 11:02:12 AM UTC 24 2057139064 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.373571206 Aug 29 11:02:09 AM UTC 24 Aug 29 11:02:12 AM UTC 24 456332528 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.84022853 Aug 29 11:02:09 AM UTC 24 Aug 29 11:02:12 AM UTC 24 403150009 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.725446724 Aug 29 11:02:08 AM UTC 24 Aug 29 11:02:12 AM UTC 24 397245474 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.929431820 Aug 29 11:02:06 AM UTC 24 Aug 29 11:02:13 AM UTC 24 7241852516 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3480021112 Aug 29 11:02:10 AM UTC 24 Aug 29 11:02:13 AM UTC 24 474678032 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4227201053 Aug 29 11:02:11 AM UTC 24 Aug 29 11:02:14 AM UTC 24 2116912109 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.2208198259 Aug 29 11:02:12 AM UTC 24 Aug 29 11:02:14 AM UTC 24 374082218 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.1170172024 Aug 29 11:02:12 AM UTC 24 Aug 29 11:02:14 AM UTC 24 399407557 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1738203820 Aug 29 11:02:12 AM UTC 24 Aug 29 11:02:15 AM UTC 24 541497436 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2173660709 Aug 29 11:02:12 AM UTC 24 Aug 29 11:02:15 AM UTC 24 1175121295 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.863773813 Aug 29 11:02:12 AM UTC 24 Aug 29 11:02:15 AM UTC 24 422572215 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2590285779 Aug 29 11:02:12 AM UTC 24 Aug 29 11:02:15 AM UTC 24 602752908 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3880720726 Aug 29 11:02:14 AM UTC 24 Aug 29 11:02:16 AM UTC 24 531355432 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1346476790 Aug 29 11:02:13 AM UTC 24 Aug 29 11:02:16 AM UTC 24 320831360 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.908866403 Aug 29 11:02:15 AM UTC 24 Aug 29 11:02:18 AM UTC 24 510939762 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.1605872094 Aug 29 11:02:16 AM UTC 24 Aug 29 11:02:18 AM UTC 24 471088014 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.3851307319 Aug 29 11:02:15 AM UTC 24 Aug 29 11:02:18 AM UTC 24 422243419 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2391254940 Aug 29 11:02:15 AM UTC 24 Aug 29 11:02:18 AM UTC 24 2265832085 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1247777368 Aug 29 11:02:16 AM UTC 24 Aug 29 11:02:18 AM UTC 24 1062403218 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2619688388 Aug 29 11:02:10 AM UTC 24 Aug 29 11:02:19 AM UTC 24 1430646559 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.1537843612 Aug 29 11:02:16 AM UTC 24 Aug 29 11:02:19 AM UTC 24 483416007 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2898088493 Aug 29 11:02:16 AM UTC 24 Aug 29 11:02:19 AM UTC 24 493656169 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.4185758426 Aug 29 11:02:16 AM UTC 24 Aug 29 11:02:19 AM UTC 24 408488823 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3698955996 Aug 29 11:02:16 AM UTC 24 Aug 29 11:02:20 AM UTC 24 4583936745 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3101396313 Aug 29 11:02:18 AM UTC 24 Aug 29 11:02:20 AM UTC 24 305009620 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1174298228 Aug 29 11:02:17 AM UTC 24 Aug 29 11:02:21 AM UTC 24 643045736 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.1304710545 Aug 29 11:02:19 AM UTC 24 Aug 29 11:02:21 AM UTC 24 407648167 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3920353242 Aug 29 11:02:20 AM UTC 24 Aug 29 11:02:21 AM UTC 24 338768316 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3161300404 Aug 29 11:02:20 AM UTC 24 Aug 29 11:02:22 AM UTC 24 1007849988 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.501283983 Aug 29 11:02:18 AM UTC 24 Aug 29 11:02:22 AM UTC 24 333613804 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2436288578 Aug 29 11:02:19 AM UTC 24 Aug 29 11:02:22 AM UTC 24 349015798 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.782091912 Aug 29 11:02:19 AM UTC 24 Aug 29 11:02:22 AM UTC 24 470464710 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.970495239 Aug 29 11:02:20 AM UTC 24 Aug 29 11:02:22 AM UTC 24 649395183 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1989223451 Aug 29 11:02:21 AM UTC 24 Aug 29 11:02:23 AM UTC 24 447150789 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3409079078 Aug 29 11:02:14 AM UTC 24 Aug 29 11:02:23 AM UTC 24 7241270372 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2119871115 Aug 29 11:02:21 AM UTC 24 Aug 29 11:02:24 AM UTC 24 1103785002 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.2594641135 Aug 29 11:02:21 AM UTC 24 Aug 29 11:02:24 AM UTC 24 372426289 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.210960240 Aug 29 11:02:21 AM UTC 24 Aug 29 11:02:24 AM UTC 24 496298975 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.2051975168 Aug 29 11:02:22 AM UTC 24 Aug 29 11:02:24 AM UTC 24 386473807 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2506233558 Aug 29 11:02:22 AM UTC 24 Aug 29 11:02:24 AM UTC 24 358979743 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.2438189665 Aug 29 11:02:21 AM UTC 24 Aug 29 11:02:25 AM UTC 24 546190833 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4065535258 Aug 29 11:02:22 AM UTC 24 Aug 29 11:02:25 AM UTC 24 406529462 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3249765223 Aug 29 11:02:20 AM UTC 24 Aug 29 11:02:25 AM UTC 24 7163169158 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1964831958 Aug 29 11:02:23 AM UTC 24 Aug 29 11:02:26 AM UTC 24 463592267 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1456204621 Aug 29 11:02:17 AM UTC 24 Aug 29 11:02:26 AM UTC 24 4337943995 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2044731116 Aug 29 11:02:23 AM UTC 24 Aug 29 11:02:26 AM UTC 24 1194653302 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.1854254138 Aug 29 11:02:22 AM UTC 24 Aug 29 11:02:26 AM UTC 24 623497318 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2670048505 Aug 29 11:02:21 AM UTC 24 Aug 29 11:02:26 AM UTC 24 4270578778 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.2572805019 Aug 29 11:02:25 AM UTC 24 Aug 29 11:02:27 AM UTC 24 558794181 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.1878799240 Aug 29 11:02:24 AM UTC 24 Aug 29 11:02:27 AM UTC 24 916412332 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.1078188735 Aug 29 11:02:25 AM UTC 24 Aug 29 11:02:27 AM UTC 24 486356340 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4257140281 Aug 29 11:02:25 AM UTC 24 Aug 29 11:02:27 AM UTC 24 1718586016 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1177323501 Aug 29 11:02:18 AM UTC 24 Aug 29 11:02:28 AM UTC 24 2084096937 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2602660150 Aug 29 11:02:26 AM UTC 24 Aug 29 11:02:28 AM UTC 24 623197272 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.1478261078 Aug 29 11:02:26 AM UTC 24 Aug 29 11:02:29 AM UTC 24 455230769 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.872268202 Aug 29 11:02:22 AM UTC 24 Aug 29 11:02:29 AM UTC 24 2661954113 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.881030545 Aug 29 11:02:26 AM UTC 24 Aug 29 11:02:29 AM UTC 24 728025051 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2467906433 Aug 29 11:02:26 AM UTC 24 Aug 29 11:02:29 AM UTC 24 1703825920 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.26697392 Aug 29 11:02:27 AM UTC 24 Aug 29 11:02:29 AM UTC 24 648030808 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.414395799 Aug 29 11:02:26 AM UTC 24 Aug 29 11:02:29 AM UTC 24 419303914 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.4093420013 Aug 29 11:02:27 AM UTC 24 Aug 29 11:02:29 AM UTC 24 435938323 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1052190224 Aug 29 11:02:27 AM UTC 24 Aug 29 11:02:30 AM UTC 24 705162428 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.3831501336 Aug 29 11:02:27 AM UTC 24 Aug 29 11:02:30 AM UTC 24 285170715 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.2845510256 Aug 29 11:02:27 AM UTC 24 Aug 29 11:02:30 AM UTC 24 462173929 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.2529971398 Aug 29 11:02:28 AM UTC 24 Aug 29 11:02:30 AM UTC 24 431331784 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.1057017124 Aug 29 11:02:29 AM UTC 24 Aug 29 11:02:31 AM UTC 24 435792476 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.226326116 Aug 29 11:02:12 AM UTC 24 Aug 29 11:02:31 AM UTC 24 8375031501 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.938118763 Aug 29 11:02:26 AM UTC 24 Aug 29 11:02:31 AM UTC 24 8244435081 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3342103553 Aug 29 11:02:22 AM UTC 24 Aug 29 11:02:31 AM UTC 24 8040120484 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.4180992436 Aug 29 11:02:30 AM UTC 24 Aug 29 11:02:32 AM UTC 24 529439323 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1234570993 Aug 29 11:02:30 AM UTC 24 Aug 29 11:02:32 AM UTC 24 2629291396 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.1538551041 Aug 29 11:02:30 AM UTC 24 Aug 29 11:02:32 AM UTC 24 406916066 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1560335452 Aug 29 11:02:28 AM UTC 24 Aug 29 11:02:32 AM UTC 24 473082494 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2652145911 Aug 29 11:02:30 AM UTC 24 Aug 29 11:02:33 AM UTC 24 363176961 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2561064015 Aug 29 11:02:30 AM UTC 24 Aug 29 11:02:33 AM UTC 24 500738337 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.239663423 Aug 29 11:02:35 AM UTC 24 Aug 29 11:02:44 AM UTC 24 4301323812 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2976637106 Aug 29 11:02:27 AM UTC 24 Aug 29 11:02:33 AM UTC 24 2629276946 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3416952868 Aug 29 11:02:31 AM UTC 24 Aug 29 11:02:33 AM UTC 24 429661467 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3919547020 Aug 29 11:02:30 AM UTC 24 Aug 29 11:02:33 AM UTC 24 512304211 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.2421309234 Aug 29 11:02:31 AM UTC 24 Aug 29 11:02:33 AM UTC 24 318921747 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2814656063 Aug 29 11:02:31 AM UTC 24 Aug 29 11:02:33 AM UTC 24 530536558 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3977945664 Aug 29 11:02:31 AM UTC 24 Aug 29 11:02:34 AM UTC 24 396852610 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.77554658 Aug 29 11:02:30 AM UTC 24 Aug 29 11:02:34 AM UTC 24 463167991 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3372787046 Aug 29 11:02:30 AM UTC 24 Aug 29 11:02:34 AM UTC 24 1539652486 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3134192140 Aug 29 11:02:27 AM UTC 24 Aug 29 11:02:34 AM UTC 24 8652353957 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2248398544 Aug 29 11:02:32 AM UTC 24 Aug 29 11:02:35 AM UTC 24 494103344 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.376935789 Aug 29 11:02:32 AM UTC 24 Aug 29 11:02:35 AM UTC 24 473553114 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1678540963 Aug 29 11:02:32 AM UTC 24 Aug 29 11:02:35 AM UTC 24 508465561 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.271881237 Aug 29 11:02:30 AM UTC 24 Aug 29 11:02:36 AM UTC 24 4237063103 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.1647240368 Aug 29 11:02:33 AM UTC 24 Aug 29 11:02:36 AM UTC 24 538630220 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1382034515 Aug 29 11:02:32 AM UTC 24 Aug 29 11:02:36 AM UTC 24 4084393907 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1394306846 Aug 29 11:02:31 AM UTC 24 Aug 29 11:02:37 AM UTC 24 2463746549 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.3191164613 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:37 AM UTC 24 507851118 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2888575596 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:37 AM UTC 24 409488564 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.1695863973 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:37 AM UTC 24 349623425 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.2603297205 Aug 29 11:02:41 AM UTC 24 Aug 29 11:02:44 AM UTC 24 431930224 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3470968224 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:37 AM UTC 24 723937193 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.1391355337 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:37 AM UTC 24 511557489 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.379106149 Aug 29 11:02:32 AM UTC 24 Aug 29 11:02:37 AM UTC 24 2399470916 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3321852541 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:37 AM UTC 24 322706145 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4292124034 Aug 29 11:02:35 AM UTC 24 Aug 29 11:02:38 AM UTC 24 544846516 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.1518821312 Aug 29 11:02:35 AM UTC 24 Aug 29 11:02:38 AM UTC 24 449731553 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.3304595870 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:38 AM UTC 24 740864329 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.947411898 Aug 29 11:02:35 AM UTC 24 Aug 29 11:02:38 AM UTC 24 460817532 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.619600087 Aug 29 11:02:36 AM UTC 24 Aug 29 11:02:38 AM UTC 24 447958273 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.4055522240 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:39 AM UTC 24 729253951 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1674151082 Aug 29 11:02:37 AM UTC 24 Aug 29 11:02:39 AM UTC 24 465171907 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.711597224 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:39 AM UTC 24 2729053095 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.717230630 Aug 29 11:02:36 AM UTC 24 Aug 29 11:02:39 AM UTC 24 389886927 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3402652408 Aug 29 11:02:35 AM UTC 24 Aug 29 11:02:39 AM UTC 24 3508559397 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.3185651089 Aug 29 11:02:36 AM UTC 24 Aug 29 11:02:40 AM UTC 24 507930807 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2297019872 Aug 29 11:02:24 AM UTC 24 Aug 29 11:02:40 AM UTC 24 8249167559 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.1344284640 Aug 29 11:02:38 AM UTC 24 Aug 29 11:02:40 AM UTC 24 373761723 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3986784027 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:40 AM UTC 24 2461117432 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2512344604 Aug 29 11:02:36 AM UTC 24 Aug 29 11:02:40 AM UTC 24 4423543140 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4192055654 Aug 29 11:02:38 AM UTC 24 Aug 29 11:02:40 AM UTC 24 512592699 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.3693692064 Aug 29 11:02:38 AM UTC 24 Aug 29 11:02:41 AM UTC 24 475903710 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.650110217 Aug 29 11:02:38 AM UTC 24 Aug 29 11:02:41 AM UTC 24 463868547 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.3454652611 Aug 29 11:02:38 AM UTC 24 Aug 29 11:02:41 AM UTC 24 379787673 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1180055412 Aug 29 11:02:37 AM UTC 24 Aug 29 11:02:41 AM UTC 24 1718050752 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.531350564 Aug 29 11:02:38 AM UTC 24 Aug 29 11:02:41 AM UTC 24 391973996 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.3214867547 Aug 29 11:02:39 AM UTC 24 Aug 29 11:02:42 AM UTC 24 336688598 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.260832607 Aug 29 11:02:38 AM UTC 24 Aug 29 11:02:42 AM UTC 24 455331392 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4280382542 Aug 29 11:02:39 AM UTC 24 Aug 29 11:02:42 AM UTC 24 442730149 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.4067053154 Aug 29 11:02:39 AM UTC 24 Aug 29 11:02:42 AM UTC 24 522611777 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.4200061370 Aug 29 11:02:39 AM UTC 24 Aug 29 11:02:43 AM UTC 24 478729840 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.11225754 Aug 29 11:02:39 AM UTC 24 Aug 29 11:02:43 AM UTC 24 494022623 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1969224862 Aug 29 11:02:19 AM UTC 24 Aug 29 11:02:43 AM UTC 24 8365201461 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.851116774 Aug 29 11:02:39 AM UTC 24 Aug 29 11:02:43 AM UTC 24 326613828 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2148609395 Aug 29 11:02:41 AM UTC 24 Aug 29 11:02:43 AM UTC 24 357831163 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.478884290 Aug 29 11:02:39 AM UTC 24 Aug 29 11:02:43 AM UTC 24 2507216273 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3008934007 Aug 29 11:02:41 AM UTC 24 Aug 29 11:02:43 AM UTC 24 318668066 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.674014596 Aug 29 11:02:38 AM UTC 24 Aug 29 11:02:43 AM UTC 24 2403270372 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.3594345295 Aug 29 11:02:41 AM UTC 24 Aug 29 11:02:43 AM UTC 24 480533886 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2991290477 Aug 29 11:02:41 AM UTC 24 Aug 29 11:02:43 AM UTC 24 416730787 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.2389588208 Aug 29 11:02:40 AM UTC 24 Aug 29 11:02:43 AM UTC 24 453697725 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2669384836 Aug 29 11:02:39 AM UTC 24 Aug 29 11:02:43 AM UTC 24 480388767 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.3697818149 Aug 29 11:02:41 AM UTC 24 Aug 29 11:02:43 AM UTC 24 265135632 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.469486637 Aug 29 11:02:41 AM UTC 24 Aug 29 11:02:43 AM UTC 24 318145164 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.776426735 Aug 29 11:02:39 AM UTC 24 Aug 29 11:02:44 AM UTC 24 478721910 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3798971228 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:44 AM UTC 24 4608294843 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.1094387841 Aug 29 11:02:41 AM UTC 24 Aug 29 11:02:44 AM UTC 24 428360688 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2938533560 Aug 29 11:02:34 AM UTC 24 Aug 29 11:02:44 AM UTC 24 8273995077 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.2025175897 Aug 29 11:02:42 AM UTC 24 Aug 29 11:02:44 AM UTC 24 519525963 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.4141891716 Aug 29 11:02:42 AM UTC 24 Aug 29 11:02:44 AM UTC 24 511453222 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.289958392 Aug 29 11:02:42 AM UTC 24 Aug 29 11:02:44 AM UTC 24 529816146 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.3209995398 Aug 29 11:02:42 AM UTC 24 Aug 29 11:02:44 AM UTC 24 482865562 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.1807950320 Aug 29 11:02:42 AM UTC 24 Aug 29 11:02:44 AM UTC 24 425329597 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.4248242924 Aug 29 11:02:28 AM UTC 24 Aug 29 11:02:44 AM UTC 24 7753020821 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.4155095242 Aug 29 11:02:42 AM UTC 24 Aug 29 11:02:44 AM UTC 24 488188299 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.638978844 Aug 29 11:02:30 AM UTC 24 Aug 29 11:02:44 AM UTC 24 8449853969 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.3629016727 Aug 29 11:02:42 AM UTC 24 Aug 29 11:02:45 AM UTC 24 426543219 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2497739036 Aug 29 11:02:43 AM UTC 24 Aug 29 11:02:45 AM UTC 24 511104996 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.4065045679 Aug 29 11:02:43 AM UTC 24 Aug 29 11:02:45 AM UTC 24 302542974 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.2910234372 Aug 29 11:02:43 AM UTC 24 Aug 29 11:02:45 AM UTC 24 274455989 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.2863862949 Aug 29 11:02:43 AM UTC 24 Aug 29 11:02:46 AM UTC 24 422225917 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.2509158939 Aug 29 11:02:43 AM UTC 24 Aug 29 11:02:46 AM UTC 24 526597538 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.1059448392 Aug 29 11:02:43 AM UTC 24 Aug 29 11:02:46 AM UTC 24 443076859 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.2500446466 Aug 29 11:02:43 AM UTC 24 Aug 29 11:02:46 AM UTC 24 487879495 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1050588338 Aug 29 11:02:38 AM UTC 24 Aug 29 11:02:47 AM UTC 24 8178485174 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1137223349 Aug 29 11:02:38 AM UTC 24 Aug 29 11:02:48 AM UTC 24 4285779919 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.956882475
Short name T3
Test name
Test status
Simulation time 452796571 ps
CPU time 0.68 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 199084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956882475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.956882475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.2020574240
Short name T30
Test name
Test status
Simulation time 4190753897 ps
CPU time 9.86 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:40 AM UTC 24
Peak memory 218832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2020574240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 12.aon_timer_stress_all_with_rand_reset.2020574240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.833381128
Short name T7
Test name
Test status
Simulation time 549056405 ps
CPU time 1.31 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:23 AM UTC 24
Peak memory 199064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833381128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.833381128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.1076640385
Short name T25
Test name
Test status
Simulation time 8026407649 ps
CPU time 5.3 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 231180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076640385 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1076640385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.2000174298
Short name T20
Test name
Test status
Simulation time 2821907921 ps
CPU time 6.82 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:28 AM UTC 24
Peak memory 217464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2000174298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 1.aon_timer_stress_all_with_rand_reset.2000174298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.4274003221
Short name T54
Test name
Test status
Simulation time 551005302 ps
CPU time 1.54 seconds
Started Aug 29 11:02:09 AM UTC 24
Finished Aug 29 11:02:12 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274003221 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.4274003221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.873589086
Short name T27
Test name
Test status
Simulation time 31429382882 ps
CPU time 5.72 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:36 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873589086 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.873589086
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.4053703973
Short name T78
Test name
Test status
Simulation time 9250774622 ps
CPU time 27.45 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:53 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4053703973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 5.aon_timer_stress_all_with_rand_reset.4053703973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.1262537396
Short name T110
Test name
Test status
Simulation time 349851802232 ps
CPU time 577.77 seconds
Started Aug 29 11:00:37 AM UTC 24
Finished Aug 29 11:10:42 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262537396 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.1262537396
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.450204617
Short name T106
Test name
Test status
Simulation time 100171046253 ps
CPU time 39.65 seconds
Started Aug 29 11:00:30 AM UTC 24
Finished Aug 29 11:01:39 AM UTC 24
Peak memory 200892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450204617 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.450204617
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.1613334420
Short name T101
Test name
Test status
Simulation time 217892487268 ps
CPU time 120.67 seconds
Started Aug 29 11:01:19 AM UTC 24
Finished Aug 29 11:03:30 AM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613334420 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.1613334420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/34.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.1615409669
Short name T116
Test name
Test status
Simulation time 3763095772 ps
CPU time 30.81 seconds
Started Aug 29 11:01:37 AM UTC 24
Finished Aug 29 11:02:10 AM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1615409669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 40.aon_timer_stress_all_with_rand_reset.1615409669
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.1748578807
Short name T4
Test name
Test status
Simulation time 397290539 ps
CPU time 0.65 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748578807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1748578807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.3336783675
Short name T127
Test name
Test status
Simulation time 80534231034 ps
CPU time 123.73 seconds
Started Aug 29 11:01:16 AM UTC 24
Finished Aug 29 11:03:31 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336783675 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.3336783675
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/33.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.2726945467
Short name T104
Test name
Test status
Simulation time 14831939616 ps
CPU time 31.04 seconds
Started Aug 29 11:01:27 AM UTC 24
Finished Aug 29 11:02:00 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2726945467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 36.aon_timer_stress_all_with_rand_reset.2726945467
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.221337388
Short name T143
Test name
Test status
Simulation time 91008383694 ps
CPU time 168.66 seconds
Started Aug 29 11:01:43 AM UTC 24
Finished Aug 29 11:04:35 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221337388 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.221337388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/42.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.729396962
Short name T93
Test name
Test status
Simulation time 14563979930 ps
CPU time 37.19 seconds
Started Aug 29 11:00:54 AM UTC 24
Finished Aug 29 11:01:34 AM UTC 24
Peak memory 219336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=729396962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.aon_timer_stress_all_with_rand_reset.729396962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.334996883
Short name T96
Test name
Test status
Simulation time 14767908273 ps
CPU time 40.78 seconds
Started Aug 29 11:01:00 AM UTC 24
Finished Aug 29 11:01:42 AM UTC 24
Peak memory 206748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=334996883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.aon_timer_stress_all_with_rand_reset.334996883
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.517270214
Short name T114
Test name
Test status
Simulation time 233857525841 ps
CPU time 204.31 seconds
Started Aug 29 11:00:57 AM UTC 24
Finished Aug 29 11:04:25 AM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517270214 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.517270214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/24.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.1492254751
Short name T129
Test name
Test status
Simulation time 86329157530 ps
CPU time 77.37 seconds
Started Aug 29 11:01:27 AM UTC 24
Finished Aug 29 11:02:47 AM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492254751 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.1492254751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/36.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.475054102
Short name T39
Test name
Test status
Simulation time 9208995493 ps
CPU time 3.03 seconds
Started Aug 29 11:02:08 AM UTC 24
Finished Aug 29 11:02:12 AM UTC 24
Peak memory 206856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475054102 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.475054102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.1197463690
Short name T28
Test name
Test status
Simulation time 33513674776 ps
CPU time 13.82 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:40 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197463690 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.1197463690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.514699297
Short name T128
Test name
Test status
Simulation time 4362737779 ps
CPU time 4.55 seconds
Started Aug 29 11:02:01 AM UTC 24
Finished Aug 29 11:02:07 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514699297 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.514699297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/49.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.1418512044
Short name T91
Test name
Test status
Simulation time 88032744838 ps
CPU time 57.34 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:01:28 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418512044 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.1418512044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.1560504694
Short name T80
Test name
Test status
Simulation time 8922405809 ps
CPU time 18.95 seconds
Started Aug 29 11:00:57 AM UTC 24
Finished Aug 29 11:01:17 AM UTC 24
Peak memory 206616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1560504694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 24.aon_timer_stress_all_with_rand_reset.1560504694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.2959502637
Short name T109
Test name
Test status
Simulation time 147822274383 ps
CPU time 54.2 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:01:21 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959502637 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.2959502637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.2138802522
Short name T92
Test name
Test status
Simulation time 122434627841 ps
CPU time 193.84 seconds
Started Aug 29 11:01:09 AM UTC 24
Finished Aug 29 11:04:26 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138802522 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.2138802522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/31.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.1627581005
Short name T89
Test name
Test status
Simulation time 141937759536 ps
CPU time 48.65 seconds
Started Aug 29 11:01:41 AM UTC 24
Finished Aug 29 11:02:31 AM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627581005 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.1627581005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/41.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.752149786
Short name T45
Test name
Test status
Simulation time 9227693564 ps
CPU time 22.26 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:44 AM UTC 24
Peak memory 218176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=752149786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.aon_timer_stress_all_with_rand_reset.752149786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.2568437031
Short name T94
Test name
Test status
Simulation time 11389868604 ps
CPU time 24.8 seconds
Started Aug 29 11:01:52 AM UTC 24
Finished Aug 29 11:02:18 AM UTC 24
Peak memory 218912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2568437031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 46.aon_timer_stress_all_with_rand_reset.2568437031
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.711249132
Short name T142
Test name
Test status
Simulation time 13108352801 ps
CPU time 30.62 seconds
Started Aug 29 11:01:45 AM UTC 24
Finished Aug 29 11:02:17 AM UTC 24
Peak memory 218752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=711249132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 43.aon_timer_stress_all_with_rand_reset.711249132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.123388775
Short name T98
Test name
Test status
Simulation time 511727076047 ps
CPU time 175.21 seconds
Started Aug 29 11:01:08 AM UTC 24
Finished Aug 29 11:04:06 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123388775 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.123388775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/30.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.759409509
Short name T95
Test name
Test status
Simulation time 400011903891 ps
CPU time 94.61 seconds
Started Aug 29 11:00:58 AM UTC 24
Finished Aug 29 11:02:36 AM UTC 24
Peak memory 200712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759409509 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.759409509
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/25.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.4101098565
Short name T105
Test name
Test status
Simulation time 96951941278 ps
CPU time 37.19 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:59 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101098565 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.4101098565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.2524489426
Short name T100
Test name
Test status
Simulation time 106186910665 ps
CPU time 165.68 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:03:09 AM UTC 24
Peak memory 200760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524489426 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.2524489426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.2163986563
Short name T141
Test name
Test status
Simulation time 49647239436 ps
CPU time 64.28 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:01:35 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163986563 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.2163986563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.1729396174
Short name T157
Test name
Test status
Simulation time 24783836852 ps
CPU time 32.82 seconds
Started Aug 29 11:00:34 AM UTC 24
Finished Aug 29 11:01:30 AM UTC 24
Peak memory 206776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1729396174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 19.aon_timer_stress_all_with_rand_reset.1729396174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.1175384742
Short name T133
Test name
Test status
Simulation time 243449202834 ps
CPU time 45.89 seconds
Started Aug 29 11:01:02 AM UTC 24
Finished Aug 29 11:01:49 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175384742 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.1175384742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/28.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.3541007047
Short name T124
Test name
Test status
Simulation time 131138660927 ps
CPU time 252.55 seconds
Started Aug 29 11:00:32 AM UTC 24
Finished Aug 29 11:05:12 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541007047 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.3541007047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/17.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.1205308597
Short name T112
Test name
Test status
Simulation time 627050899207 ps
CPU time 210.94 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:03:58 AM UTC 24
Peak memory 200680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205308597 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.1205308597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.1413927733
Short name T130
Test name
Test status
Simulation time 184031441924 ps
CPU time 180.05 seconds
Started Aug 29 11:01:31 AM UTC 24
Finished Aug 29 11:04:34 AM UTC 24
Peak memory 200768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413927733 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.1413927733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/37.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.9793003
Short name T146
Test name
Test status
Simulation time 169315760561 ps
CPU time 304.18 seconds
Started Aug 29 11:01:33 AM UTC 24
Finished Aug 29 11:06:42 AM UTC 24
Peak memory 200888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9793003 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.9793003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/38.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.3119320911
Short name T47
Test name
Test status
Simulation time 6419951216 ps
CPU time 15.06 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:45 AM UTC 24
Peak memory 215436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3119320911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.aon_timer_stress_all_with_rand_reset.3119320911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.786021421
Short name T151
Test name
Test status
Simulation time 9255833977 ps
CPU time 63.59 seconds
Started Aug 29 11:00:30 AM UTC 24
Finished Aug 29 11:02:03 AM UTC 24
Peak memory 205160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=786021421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 15.aon_timer_stress_all_with_rand_reset.786021421
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.3565400339
Short name T103
Test name
Test status
Simulation time 184761146170 ps
CPU time 19.42 seconds
Started Aug 29 11:01:00 AM UTC 24
Finished Aug 29 11:01:20 AM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565400339 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.3565400339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/26.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.774197338
Short name T90
Test name
Test status
Simulation time 325327794026 ps
CPU time 27.11 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:53 AM UTC 24
Peak memory 200796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774197338 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.774197338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.3698264975
Short name T107
Test name
Test status
Simulation time 6848965703 ps
CPU time 28.61 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:55 AM UTC 24
Peak memory 215068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3698264975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 7.aon_timer_stress_all_with_rand_reset.3698264975
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.3307703509
Short name T149
Test name
Test status
Simulation time 161839925126 ps
CPU time 27.97 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:58 AM UTC 24
Peak memory 200408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307703509 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.3307703509
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.4232761719
Short name T111
Test name
Test status
Simulation time 307314212270 ps
CPU time 613.38 seconds
Started Aug 29 11:00:40 AM UTC 24
Finished Aug 29 11:11:18 AM UTC 24
Peak memory 200436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232761719 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.4232761719
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/20.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.1409202428
Short name T113
Test name
Test status
Simulation time 99207722588 ps
CPU time 56.4 seconds
Started Aug 29 11:00:49 AM UTC 24
Finished Aug 29 11:01:48 AM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409202428 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.1409202428
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/22.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.3425087719
Short name T155
Test name
Test status
Simulation time 346126275574 ps
CPU time 623.22 seconds
Started Aug 29 11:00:45 AM UTC 24
Finished Aug 29 11:11:25 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425087719 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.3425087719
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/21.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.1386623160
Short name T167
Test name
Test status
Simulation time 41466746406 ps
CPU time 66.45 seconds
Started Aug 29 11:01:46 AM UTC 24
Finished Aug 29 11:02:55 AM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386623160 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.1386623160
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/43.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.2241560936
Short name T132
Test name
Test status
Simulation time 95372898911 ps
CPU time 41.59 seconds
Started Aug 29 11:01:52 AM UTC 24
Finished Aug 29 11:02:35 AM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241560936 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.2241560936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/46.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.2564607464
Short name T119
Test name
Test status
Simulation time 167843333816 ps
CPU time 129.42 seconds
Started Aug 29 11:00:33 AM UTC 24
Finished Aug 29 11:03:06 AM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564607464 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.2564607464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.1308214993
Short name T97
Test name
Test status
Simulation time 7278472596 ps
CPU time 31.73 seconds
Started Aug 29 11:01:02 AM UTC 24
Finished Aug 29 11:01:35 AM UTC 24
Peak memory 219400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1308214993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 28.aon_timer_stress_all_with_rand_reset.1308214993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.395925160
Short name T147
Test name
Test status
Simulation time 174316022879 ps
CPU time 343.38 seconds
Started Aug 29 11:01:51 AM UTC 24
Finished Aug 29 11:07:39 AM UTC 24
Peak memory 201140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395925160 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.395925160
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/45.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.101332334
Short name T159
Test name
Test status
Simulation time 73392834264 ps
CPU time 31.86 seconds
Started Aug 29 11:01:55 AM UTC 24
Finished Aug 29 11:02:29 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101332334 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.101332334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/47.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.721105192
Short name T134
Test name
Test status
Simulation time 16400407582 ps
CPU time 40.94 seconds
Started Aug 29 11:01:15 AM UTC 24
Finished Aug 29 11:02:08 AM UTC 24
Peak memory 214476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=721105192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.aon_timer_stress_all_with_rand_reset.721105192
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.2387043226
Short name T140
Test name
Test status
Simulation time 3132326648 ps
CPU time 9.62 seconds
Started Aug 29 11:01:31 AM UTC 24
Finished Aug 29 11:01:42 AM UTC 24
Peak memory 215564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2387043226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 38.aon_timer_stress_all_with_rand_reset.2387043226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.3027362302
Short name T102
Test name
Test status
Simulation time 566342333 ps
CPU time 1 seconds
Started Aug 29 11:01:36 AM UTC 24
Finished Aug 29 11:01:39 AM UTC 24
Peak memory 199368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027362302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3027362302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/40.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.3681902562
Short name T120
Test name
Test status
Simulation time 499614049 ps
CPU time 1.01 seconds
Started Aug 29 11:01:47 AM UTC 24
Finished Aug 29 11:01:50 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681902562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3681902562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/44.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.2362211887
Short name T21
Test name
Test status
Simulation time 1417042162 ps
CPU time 8.43 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:30 AM UTC 24
Peak memory 206424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2362211887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.aon_timer_stress_all_with_rand_reset.2362211887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.704307311
Short name T108
Test name
Test status
Simulation time 150707405207 ps
CPU time 104.69 seconds
Started Aug 29 11:01:04 AM UTC 24
Finished Aug 29 11:02:51 AM UTC 24
Peak memory 200888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704307311 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.704307311
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/29.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.2445246599
Short name T46
Test name
Test status
Simulation time 4189170782 ps
CPU time 19.6 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:45 AM UTC 24
Peak memory 215244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2445246599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 3.aon_timer_stress_all_with_rand_reset.2445246599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.3253447266
Short name T137
Test name
Test status
Simulation time 2032889112 ps
CPU time 13.21 seconds
Started Aug 29 11:01:40 AM UTC 24
Finished Aug 29 11:01:54 AM UTC 24
Peak memory 206584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3253447266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 41.aon_timer_stress_all_with_rand_reset.3253447266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.1585778700
Short name T115
Test name
Test status
Simulation time 383201928 ps
CPU time 1.05 seconds
Started Aug 29 11:00:47 AM UTC 24
Finished Aug 29 11:00:52 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585778700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1585778700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/22.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.4032420037
Short name T163
Test name
Test status
Simulation time 9142653511 ps
CPU time 27.93 seconds
Started Aug 29 11:01:01 AM UTC 24
Finished Aug 29 11:01:30 AM UTC 24
Peak memory 206808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4032420037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 27.aon_timer_stress_all_with_rand_reset.4032420037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.2135885457
Short name T126
Test name
Test status
Simulation time 565312149 ps
CPU time 2.38 seconds
Started Aug 29 11:01:03 AM UTC 24
Finished Aug 29 11:01:07 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135885457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2135885457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/29.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.1420410941
Short name T131
Test name
Test status
Simulation time 611926819 ps
CPU time 1.25 seconds
Started Aug 29 11:01:07 AM UTC 24
Finished Aug 29 11:01:09 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420410941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1420410941
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/30.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.3495069920
Short name T154
Test name
Test status
Simulation time 5902202834 ps
CPU time 22.63 seconds
Started Aug 29 11:01:19 AM UTC 24
Finished Aug 29 11:01:51 AM UTC 24
Peak memory 218272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3495069920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 34.aon_timer_stress_all_with_rand_reset.3495069920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.1237684969
Short name T123
Test name
Test status
Simulation time 382415710 ps
CPU time 1.1 seconds
Started Aug 29 11:01:34 AM UTC 24
Finished Aug 29 11:01:37 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237684969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1237684969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/39.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.3817628769
Short name T135
Test name
Test status
Simulation time 235563760171 ps
CPU time 105.16 seconds
Started Aug 29 11:01:35 AM UTC 24
Finished Aug 29 11:03:23 AM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817628769 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.3817628769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/39.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.3455776735
Short name T23
Test name
Test status
Simulation time 579389250 ps
CPU time 1.39 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455776735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3455776735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.1843278605
Short name T51
Test name
Test status
Simulation time 438749852 ps
CPU time 0.67 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:30 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843278605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1843278605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.3450233489
Short name T117
Test name
Test status
Simulation time 483111854 ps
CPU time 1.18 seconds
Started Aug 29 11:00:45 AM UTC 24
Finished Aug 29 11:00:57 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450233489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3450233489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/21.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.2226444682
Short name T144
Test name
Test status
Simulation time 475270078 ps
CPU time 2.17 seconds
Started Aug 29 11:01:00 AM UTC 24
Finished Aug 29 11:01:03 AM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226444682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2226444682
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/26.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.2785025929
Short name T161
Test name
Test status
Simulation time 247973943504 ps
CPU time 354.37 seconds
Started Aug 29 11:01:01 AM UTC 24
Finished Aug 29 11:07:00 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785025929 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.2785025929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/27.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.2519612466
Short name T125
Test name
Test status
Simulation time 2405620385 ps
CPU time 13.48 seconds
Started Aug 29 11:01:08 AM UTC 24
Finished Aug 29 11:01:23 AM UTC 24
Peak memory 217056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2519612466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.aon_timer_stress_all_with_rand_reset.2519612466
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.1626906541
Short name T139
Test name
Test status
Simulation time 586473897 ps
CPU time 1.34 seconds
Started Aug 29 11:01:18 AM UTC 24
Finished Aug 29 11:01:27 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626906541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1626906541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/34.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.1688745549
Short name T122
Test name
Test status
Simulation time 490009351 ps
CPU time 2.28 seconds
Started Aug 29 11:01:29 AM UTC 24
Finished Aug 29 11:01:32 AM UTC 24
Peak memory 200028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688745549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1688745549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/37.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.3512510970
Short name T153
Test name
Test status
Simulation time 125507904593 ps
CPU time 178.88 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:03:26 AM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512510970 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.3512510970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.1740937357
Short name T118
Test name
Test status
Simulation time 430391363 ps
CPU time 1.53 seconds
Started Aug 29 11:01:42 AM UTC 24
Finished Aug 29 11:01:45 AM UTC 24
Peak memory 199272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740937357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1740937357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/42.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.2676563848
Short name T138
Test name
Test status
Simulation time 2041975060 ps
CPU time 17.37 seconds
Started Aug 29 11:01:50 AM UTC 24
Finished Aug 29 11:02:08 AM UTC 24
Peak memory 215564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2676563848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 45.aon_timer_stress_all_with_rand_reset.2676563848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.275018064
Short name T121
Test name
Test status
Simulation time 498788896 ps
CPU time 1.2 seconds
Started Aug 29 11:01:58 AM UTC 24
Finished Aug 29 11:02:00 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275018064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.275018064
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/48.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.1232799297
Short name T99
Test name
Test status
Simulation time 115202106072 ps
CPU time 38.26 seconds
Started Aug 29 11:00:28 AM UTC 24
Finished Aug 29 11:01:08 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232799297 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.1232799297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.2054347013
Short name T178
Test name
Test status
Simulation time 12429022832 ps
CPU time 43.37 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:01:14 AM UTC 24
Peak memory 218256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2054347013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 14.aon_timer_stress_all_with_rand_reset.2054347013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.3099589713
Short name T145
Test name
Test status
Simulation time 531374558 ps
CPU time 2.03 seconds
Started Aug 29 11:00:32 AM UTC 24
Finished Aug 29 11:00:58 AM UTC 24
Peak memory 200572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099589713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3099589713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/17.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.1920021354
Short name T79
Test name
Test status
Simulation time 2242042076 ps
CPU time 12.63 seconds
Started Aug 29 11:00:45 AM UTC 24
Finished Aug 29 11:01:08 AM UTC 24
Peak memory 215312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1920021354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 21.aon_timer_stress_all_with_rand_reset.1920021354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.739285763
Short name T181
Test name
Test status
Simulation time 4207227680 ps
CPU time 41.39 seconds
Started Aug 29 11:01:04 AM UTC 24
Finished Aug 29 11:01:47 AM UTC 24
Peak memory 215620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=739285763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 29.aon_timer_stress_all_with_rand_reset.739285763
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.1560643246
Short name T49
Test name
Test status
Simulation time 335793307 ps
CPU time 1.15 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:30 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560643246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1560643246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.3093061565
Short name T160
Test name
Test status
Simulation time 231286630409 ps
CPU time 84.91 seconds
Started Aug 29 11:01:12 AM UTC 24
Finished Aug 29 11:02:40 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093061565 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.3093061565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/32.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.1261444792
Short name T83
Test name
Test status
Simulation time 5596324465 ps
CPU time 15.71 seconds
Started Aug 29 11:01:29 AM UTC 24
Finished Aug 29 11:01:46 AM UTC 24
Peak memory 219568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1261444792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 37.aon_timer_stress_all_with_rand_reset.1261444792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.1179927181
Short name T148
Test name
Test status
Simulation time 172123441571 ps
CPU time 74.75 seconds
Started Aug 29 11:00:31 AM UTC 24
Finished Aug 29 11:02:14 AM UTC 24
Peak memory 202812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179927181 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.1179927181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.774236538
Short name T136
Test name
Test status
Simulation time 76874664181 ps
CPU time 51.73 seconds
Started Aug 29 11:00:54 AM UTC 24
Finished Aug 29 11:01:48 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774236538 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.774236538
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/23.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.3562485301
Short name T82
Test name
Test status
Simulation time 10332942717 ps
CPU time 27.2 seconds
Started Aug 29 11:01:09 AM UTC 24
Finished Aug 29 11:01:38 AM UTC 24
Peak memory 215092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3562485301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 31.aon_timer_stress_all_with_rand_reset.3562485301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.53178304
Short name T171
Test name
Test status
Simulation time 208028794116 ps
CPU time 348.46 seconds
Started Aug 29 11:01:37 AM UTC 24
Finished Aug 29 11:07:31 AM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53178304 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.53178304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/40.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.989101940
Short name T33
Test name
Test status
Simulation time 511430600 ps
CPU time 1.17 seconds
Started Aug 29 11:00:22 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989101940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.989101940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.1557765429
Short name T165
Test name
Test status
Simulation time 99877617977 ps
CPU time 37.67 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:01:03 AM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557765429 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.1557765429
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.3290915198
Short name T35
Test name
Test status
Simulation time 411958177 ps
CPU time 1.57 seconds
Started Aug 29 11:00:26 AM UTC 24
Finished Aug 29 11:00:29 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290915198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3290915198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.1593641091
Short name T44
Test name
Test status
Simulation time 4121056362 ps
CPU time 15.89 seconds
Started Aug 29 11:00:26 AM UTC 24
Finished Aug 29 11:00:43 AM UTC 24
Peak memory 206732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1593641091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 9.aon_timer_stress_all_with_rand_reset.1593641091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.1278124749
Short name T182
Test name
Test status
Simulation time 467014230 ps
CPU time 1.02 seconds
Started Aug 29 11:00:30 AM UTC 24
Finished Aug 29 11:00:59 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278124749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1278124749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.524520371
Short name T29
Test name
Test status
Simulation time 213614968686 ps
CPU time 26.43 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:48 AM UTC 24
Peak memory 200460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524520371 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.524520371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.391172910
Short name T12
Test name
Test status
Simulation time 556320623 ps
CPU time 0.65 seconds
Started Aug 29 11:00:53 AM UTC 24
Finished Aug 29 11:00:58 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391172910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.391172910
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/23.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.1754513287
Short name T164
Test name
Test status
Simulation time 507278898 ps
CPU time 1.35 seconds
Started Aug 29 11:00:57 AM UTC 24
Finished Aug 29 11:01:00 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754513287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1754513287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/24.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.1866032054
Short name T189
Test name
Test status
Simulation time 583150434 ps
CPU time 1.71 seconds
Started Aug 29 11:00:58 AM UTC 24
Finished Aug 29 11:01:02 AM UTC 24
Peak memory 199028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866032054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1866032054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/25.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.2985367902
Short name T179
Test name
Test status
Simulation time 593065650 ps
CPU time 3.13 seconds
Started Aug 29 11:01:09 AM UTC 24
Finished Aug 29 11:01:13 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985367902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2985367902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/31.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.3995908361
Short name T183
Test name
Test status
Simulation time 488905440 ps
CPU time 1.33 seconds
Started Aug 29 11:01:11 AM UTC 24
Finished Aug 29 11:01:14 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995908361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3995908361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/32.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.608528785
Short name T184
Test name
Test status
Simulation time 612781421 ps
CPU time 1.18 seconds
Started Aug 29 11:01:24 AM UTC 24
Finished Aug 29 11:01:27 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608528785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.608528785
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/36.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.2947456334
Short name T48
Test name
Test status
Simulation time 3390053782 ps
CPU time 20.54 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:46 AM UTC 24
Peak memory 214648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2947456334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 4.aon_timer_stress_all_with_rand_reset.2947456334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.556785599
Short name T158
Test name
Test status
Simulation time 104388330306 ps
CPU time 42.22 seconds
Started Aug 29 11:01:49 AM UTC 24
Finished Aug 29 11:02:32 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556785599 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.556785599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/44.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.258247606
Short name T172
Test name
Test status
Simulation time 2943627110 ps
CPU time 16.35 seconds
Started Aug 29 11:02:01 AM UTC 24
Finished Aug 29 11:02:18 AM UTC 24
Peak memory 203024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=258247606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 49.aon_timer_stress_all_with_rand_reset.258247606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.2900680016
Short name T8
Test name
Test status
Simulation time 443208045 ps
CPU time 0.6 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900680016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2900680016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.647142470
Short name T43
Test name
Test status
Simulation time 3734954750 ps
CPU time 11.13 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:37 AM UTC 24
Peak memory 211980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=647142470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 6.aon_timer_stress_all_with_rand_reset.647142470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.3028394955
Short name T2
Test name
Test status
Simulation time 387208685 ps
CPU time 0.64 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 198524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028394955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3028394955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.253339348
Short name T191
Test name
Test status
Simulation time 376618105 ps
CPU time 0.98 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:31 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253339348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.253339348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.771047115
Short name T188
Test name
Test status
Simulation time 351602733 ps
CPU time 1.05 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:31 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771047115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.771047115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.3801953495
Short name T190
Test name
Test status
Simulation time 344647317 ps
CPU time 1.1 seconds
Started Aug 29 11:00:30 AM UTC 24
Finished Aug 29 11:01:00 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801953495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3801953495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.2064431382
Short name T14
Test name
Test status
Simulation time 436823976 ps
CPU time 1.76 seconds
Started Aug 29 11:00:32 AM UTC 24
Finished Aug 29 11:00:58 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064431382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2064431382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.2973025710
Short name T156
Test name
Test status
Simulation time 354741157 ps
CPU time 0.95 seconds
Started Aug 29 11:00:38 AM UTC 24
Finished Aug 29 11:00:51 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973025710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2973025710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/20.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.974145787
Short name T176
Test name
Test status
Simulation time 443192652 ps
CPU time 1.17 seconds
Started Aug 29 11:01:01 AM UTC 24
Finished Aug 29 11:01:03 AM UTC 24
Peak memory 199096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974145787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.974145787
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/27.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.2800573863
Short name T180
Test name
Test status
Simulation time 440989468 ps
CPU time 1.23 seconds
Started Aug 29 11:01:02 AM UTC 24
Finished Aug 29 11:01:04 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800573863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2800573863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/28.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.2989325041
Short name T170
Test name
Test status
Simulation time 480648148 ps
CPU time 1.15 seconds
Started Aug 29 11:01:14 AM UTC 24
Finished Aug 29 11:01:17 AM UTC 24
Peak memory 199052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989325041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2989325041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/33.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.69490226
Short name T166
Test name
Test status
Simulation time 605510911 ps
CPU time 1.25 seconds
Started Aug 29 11:01:20 AM UTC 24
Finished Aug 29 11:01:30 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69490226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.69490226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/35.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.2733390240
Short name T162
Test name
Test status
Simulation time 164035128250 ps
CPU time 64.71 seconds
Started Aug 29 11:01:22 AM UTC 24
Finished Aug 29 11:02:32 AM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733390240 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.2733390240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/35.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.2394574717
Short name T175
Test name
Test status
Simulation time 574321409 ps
CPU time 2.78 seconds
Started Aug 29 11:01:54 AM UTC 24
Finished Aug 29 11:01:58 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394574717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2394574717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/47.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.519633165
Short name T168
Test name
Test status
Simulation time 48655492252 ps
CPU time 27.39 seconds
Started Aug 29 11:01:59 AM UTC 24
Finished Aug 29 11:02:27 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519633165 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.519633165
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/48.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.239663423
Short name T194
Test name
Test status
Simulation time 4301323812 ps
CPU time 7.32 seconds
Started Aug 29 11:02:35 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 206896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239663423 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.239663423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.2571608584
Short name T34
Test name
Test status
Simulation time 459071423 ps
CPU time 1.17 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:31 AM UTC 24
Peak memory 199368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571608584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2571608584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.2771181098
Short name T53
Test name
Test status
Simulation time 638426203 ps
CPU time 0.92 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:31 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771181098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2771181098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.3767578119
Short name T86
Test name
Test status
Simulation time 579757583 ps
CPU time 0.91 seconds
Started Aug 29 11:00:34 AM UTC 24
Finished Aug 29 11:00:36 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767578119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3767578119
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.884280885
Short name T169
Test name
Test status
Simulation time 2035914506 ps
CPU time 20.76 seconds
Started Aug 29 11:00:48 AM UTC 24
Finished Aug 29 11:01:17 AM UTC 24
Peak memory 214112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=884280885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.aon_timer_stress_all_with_rand_reset.884280885
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.291926009
Short name T152
Test name
Test status
Simulation time 486508464 ps
CPU time 1.18 seconds
Started Aug 29 11:01:45 AM UTC 24
Finished Aug 29 11:01:48 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291926009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.291926009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/43.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.22549882
Short name T186
Test name
Test status
Simulation time 579894852 ps
CPU time 0.97 seconds
Started Aug 29 11:01:51 AM UTC 24
Finished Aug 29 11:01:53 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22549882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.22549882
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/46.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.740668112
Short name T13
Test name
Test status
Simulation time 512423936 ps
CPU time 1.39 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740668112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.740668112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1578928822
Short name T37
Test name
Test status
Simulation time 477905781 ps
CPU time 1.53 seconds
Started Aug 29 11:02:06 AM UTC 24
Finished Aug 29 11:02:09 AM UTC 24
Peak memory 201780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578928822 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.1578928822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.929431820
Short name T75
Test name
Test status
Simulation time 7241852516 ps
CPU time 5.56 seconds
Started Aug 29 11:02:06 AM UTC 24
Finished Aug 29 11:02:13 AM UTC 24
Peak memory 205640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929431820 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.929431820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.375027335
Short name T41
Test name
Test status
Simulation time 998376090 ps
CPU time 1.82 seconds
Started Aug 29 11:02:05 AM UTC 24
Finished Aug 29 11:02:08 AM UTC 24
Peak memory 201960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375027335 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.375027335
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2092332947
Short name T38
Test name
Test status
Simulation time 440303267 ps
CPU time 2.46 seconds
Started Aug 29 11:02:08 AM UTC 24
Finished Aug 29 11:02:11 AM UTC 24
Peak memory 205500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2092332947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_csr_mem_rw_with_rand_reset.2092332947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.3592061367
Short name T42
Test name
Test status
Simulation time 359318590 ps
CPU time 1.9 seconds
Started Aug 29 11:02:05 AM UTC 24
Finished Aug 29 11:02:08 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592061367 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3592061367
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.189131570
Short name T285
Test name
Test status
Simulation time 395198638 ps
CPU time 2.03 seconds
Started Aug 29 11:02:03 AM UTC 24
Finished Aug 29 11:02:06 AM UTC 24
Peak memory 203444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189131570 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.189131570
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.734741250
Short name T287
Test name
Test status
Simulation time 477547668 ps
CPU time 2.33 seconds
Started Aug 29 11:02:04 AM UTC 24
Finished Aug 29 11:02:08 AM UTC 24
Peak memory 201136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734741250 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.734741250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.2667185141
Short name T284
Test name
Test status
Simulation time 397911320 ps
CPU time 1.03 seconds
Started Aug 29 11:02:03 AM UTC 24
Finished Aug 29 11:02:05 AM UTC 24
Peak memory 200544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667185141 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.2667185141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2570719395
Short name T66
Test name
Test status
Simulation time 2057139064 ps
CPU time 3.17 seconds
Started Aug 29 11:02:08 AM UTC 24
Finished Aug 29 11:02:12 AM UTC 24
Peak memory 205432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570719395 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.2570719395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.1137784656
Short name T286
Test name
Test status
Simulation time 522994425 ps
CPU time 2.33 seconds
Started Aug 29 11:02:03 AM UTC 24
Finished Aug 29 11:02:06 AM UTC 24
Peak memory 207104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137784656 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1137784656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1695854789
Short name T36
Test name
Test status
Simulation time 4388846703 ps
CPU time 1.98 seconds
Started Aug 29 11:02:03 AM UTC 24
Finished Aug 29 11:02:06 AM UTC 24
Peak memory 203884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695854789 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.1695854789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3480021112
Short name T56
Test name
Test status
Simulation time 474678032 ps
CPU time 2.29 seconds
Started Aug 29 11:02:10 AM UTC 24
Finished Aug 29 11:02:13 AM UTC 24
Peak memory 204832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480021112 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.3480021112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2619688388
Short name T59
Test name
Test status
Simulation time 1430646559 ps
CPU time 7.49 seconds
Started Aug 29 11:02:10 AM UTC 24
Finished Aug 29 11:02:19 AM UTC 24
Peak memory 205280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619688388 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.2619688388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2886146817
Short name T55
Test name
Test status
Simulation time 655740218 ps
CPU time 1.75 seconds
Started Aug 29 11:02:09 AM UTC 24
Finished Aug 29 11:02:12 AM UTC 24
Peak memory 199732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886146817 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.2886146817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1738203820
Short name T294
Test name
Test status
Simulation time 541497436 ps
CPU time 1.37 seconds
Started Aug 29 11:02:12 AM UTC 24
Finished Aug 29 11:02:15 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1738203820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_csr_mem_rw_with_rand_reset.1738203820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.84022853
Short name T290
Test name
Test status
Simulation time 403150009 ps
CPU time 2.1 seconds
Started Aug 29 11:02:09 AM UTC 24
Finished Aug 29 11:02:12 AM UTC 24
Peak memory 201396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84022853 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.84022853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.373571206
Short name T289
Test name
Test status
Simulation time 456332528 ps
CPU time 1.89 seconds
Started Aug 29 11:02:09 AM UTC 24
Finished Aug 29 11:02:12 AM UTC 24
Peak memory 199976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373571206 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.373571206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3487909076
Short name T288
Test name
Test status
Simulation time 495728468 ps
CPU time 1.11 seconds
Started Aug 29 11:02:09 AM UTC 24
Finished Aug 29 11:02:11 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487909076 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.3487909076
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4227201053
Short name T67
Test name
Test status
Simulation time 2116912109 ps
CPU time 1.96 seconds
Started Aug 29 11:02:11 AM UTC 24
Finished Aug 29 11:02:14 AM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227201053 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.4227201053
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.725446724
Short name T291
Test name
Test status
Simulation time 397245474 ps
CPU time 3.46 seconds
Started Aug 29 11:02:08 AM UTC 24
Finished Aug 29 11:02:12 AM UTC 24
Peak memory 207028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725446724 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.725446724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2652145911
Short name T341
Test name
Test status
Simulation time 363176961 ps
CPU time 1.9 seconds
Started Aug 29 11:02:30 AM UTC 24
Finished Aug 29 11:02:33 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2652145911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_ti
mer_csr_mem_rw_with_rand_reset.2652145911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.1057017124
Short name T335
Test name
Test status
Simulation time 435792476 ps
CPU time 1.13 seconds
Started Aug 29 11:02:29 AM UTC 24
Finished Aug 29 11:02:31 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057017124 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1057017124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.2529971398
Short name T334
Test name
Test status
Simulation time 431331784 ps
CPU time 1.03 seconds
Started Aug 29 11:02:28 AM UTC 24
Finished Aug 29 11:02:30 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529971398 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2529971398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1234570993
Short name T338
Test name
Test status
Simulation time 2629291396 ps
CPU time 1.62 seconds
Started Aug 29 11:02:30 AM UTC 24
Finished Aug 29 11:02:32 AM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234570993 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.1234570993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1560335452
Short name T340
Test name
Test status
Simulation time 473082494 ps
CPU time 3.04 seconds
Started Aug 29 11:02:28 AM UTC 24
Finished Aug 29 11:02:32 AM UTC 24
Peak memory 206480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560335452 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1560335452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.4248242924
Short name T411
Test name
Test status
Simulation time 7753020821 ps
CPU time 14.7 seconds
Started Aug 29 11:02:28 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 207032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248242924 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.4248242924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3919547020
Short name T345
Test name
Test status
Simulation time 512304211 ps
CPU time 2.02 seconds
Started Aug 29 11:02:30 AM UTC 24
Finished Aug 29 11:02:33 AM UTC 24
Peak memory 205652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3919547020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_ti
mer_csr_mem_rw_with_rand_reset.3919547020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.4180992436
Short name T337
Test name
Test status
Simulation time 529439323 ps
CPU time 1.02 seconds
Started Aug 29 11:02:30 AM UTC 24
Finished Aug 29 11:02:32 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180992436 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4180992436
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.1538551041
Short name T339
Test name
Test status
Simulation time 406916066 ps
CPU time 1.57 seconds
Started Aug 29 11:02:30 AM UTC 24
Finished Aug 29 11:02:32 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538551041 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1538551041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3372787046
Short name T350
Test name
Test status
Simulation time 1539652486 ps
CPU time 3.18 seconds
Started Aug 29 11:02:30 AM UTC 24
Finished Aug 29 11:02:34 AM UTC 24
Peak memory 203576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372787046 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.3372787046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2561064015
Short name T342
Test name
Test status
Simulation time 500738337 ps
CPU time 1.86 seconds
Started Aug 29 11:02:30 AM UTC 24
Finished Aug 29 11:02:33 AM UTC 24
Peak memory 206972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561064015 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2561064015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.638978844
Short name T198
Test name
Test status
Simulation time 8449853969 ps
CPU time 13.52 seconds
Started Aug 29 11:02:30 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 206800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638978844 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.638978844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3416952868
Short name T344
Test name
Test status
Simulation time 429661467 ps
CPU time 0.86 seconds
Started Aug 29 11:02:31 AM UTC 24
Finished Aug 29 11:02:33 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3416952868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_ti
mer_csr_mem_rw_with_rand_reset.3416952868
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2814656063
Short name T347
Test name
Test status
Simulation time 530536558 ps
CPU time 1.06 seconds
Started Aug 29 11:02:31 AM UTC 24
Finished Aug 29 11:02:33 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814656063 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2814656063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.2421309234
Short name T346
Test name
Test status
Simulation time 318921747 ps
CPU time 1 seconds
Started Aug 29 11:02:31 AM UTC 24
Finished Aug 29 11:02:33 AM UTC 24
Peak memory 201840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421309234 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2421309234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1394306846
Short name T357
Test name
Test status
Simulation time 2463746549 ps
CPU time 4.42 seconds
Started Aug 29 11:02:31 AM UTC 24
Finished Aug 29 11:02:37 AM UTC 24
Peak memory 205752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394306846 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.1394306846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.77554658
Short name T349
Test name
Test status
Simulation time 463167991 ps
CPU time 2.82 seconds
Started Aug 29 11:02:30 AM UTC 24
Finished Aug 29 11:02:34 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77554658 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.77554658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.271881237
Short name T354
Test name
Test status
Simulation time 4237063103 ps
CPU time 4.58 seconds
Started Aug 29 11:02:30 AM UTC 24
Finished Aug 29 11:02:36 AM UTC 24
Peak memory 206784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271881237 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.271881237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1678540963
Short name T353
Test name
Test status
Simulation time 508465561 ps
CPU time 1.32 seconds
Started Aug 29 11:02:32 AM UTC 24
Finished Aug 29 11:02:35 AM UTC 24
Peak memory 203940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1678540963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti
mer_csr_mem_rw_with_rand_reset.1678540963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2248398544
Short name T63
Test name
Test status
Simulation time 494103344 ps
CPU time 0.96 seconds
Started Aug 29 11:02:32 AM UTC 24
Finished Aug 29 11:02:35 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248398544 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2248398544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.376935789
Short name T352
Test name
Test status
Simulation time 473553114 ps
CPU time 1.26 seconds
Started Aug 29 11:02:32 AM UTC 24
Finished Aug 29 11:02:35 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376935789 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.376935789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.379106149
Short name T363
Test name
Test status
Simulation time 2399470916 ps
CPU time 3.34 seconds
Started Aug 29 11:02:32 AM UTC 24
Finished Aug 29 11:02:37 AM UTC 24
Peak memory 205424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379106149 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.379106149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3977945664
Short name T348
Test name
Test status
Simulation time 396852610 ps
CPU time 1.55 seconds
Started Aug 29 11:02:31 AM UTC 24
Finished Aug 29 11:02:34 AM UTC 24
Peak memory 206972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977945664 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3977945664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1382034515
Short name T356
Test name
Test status
Simulation time 4084393907 ps
CPU time 2.75 seconds
Started Aug 29 11:02:32 AM UTC 24
Finished Aug 29 11:02:36 AM UTC 24
Peak memory 206692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382034515 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.1382034515
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3321852541
Short name T364
Test name
Test status
Simulation time 322706145 ps
CPU time 1.9 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:37 AM UTC 24
Peak memory 205064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3321852541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_ti
mer_csr_mem_rw_with_rand_reset.3321852541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2888575596
Short name T64
Test name
Test status
Simulation time 409488564 ps
CPU time 1.12 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:37 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888575596 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2888575596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.3191164613
Short name T358
Test name
Test status
Simulation time 507851118 ps
CPU time 1.11 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:37 AM UTC 24
Peak memory 199780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191164613 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3191164613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.711597224
Short name T372
Test name
Test status
Simulation time 2729053095 ps
CPU time 3.08 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:39 AM UTC 24
Peak memory 205496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711597224 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.711597224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.1647240368
Short name T355
Test name
Test status
Simulation time 538630220 ps
CPU time 2.38 seconds
Started Aug 29 11:02:33 AM UTC 24
Finished Aug 29 11:02:36 AM UTC 24
Peak memory 206992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647240368 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1647240368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2938533560
Short name T405
Test name
Test status
Simulation time 8273995077 ps
CPU time 8.39 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 206792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938533560 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.2938533560
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3470968224
Short name T361
Test name
Test status
Simulation time 723937193 ps
CPU time 0.95 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:37 AM UTC 24
Peak memory 206184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3470968224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti
mer_csr_mem_rw_with_rand_reset.3470968224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.1391355337
Short name T362
Test name
Test status
Simulation time 511557489 ps
CPU time 1.2 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:37 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391355337 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1391355337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.1695863973
Short name T359
Test name
Test status
Simulation time 349623425 ps
CPU time 1.09 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:37 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695863973 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1695863973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3986784027
Short name T377
Test name
Test status
Simulation time 2461117432 ps
CPU time 4.15 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:40 AM UTC 24
Peak memory 205492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986784027 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.3986784027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.4055522240
Short name T370
Test name
Test status
Simulation time 729253951 ps
CPU time 2.88 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:39 AM UTC 24
Peak memory 207104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055522240 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4055522240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3798971228
Short name T403
Test name
Test status
Simulation time 4608294843 ps
CPU time 7.9 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 206704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798971228 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.3798971228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4292124034
Short name T365
Test name
Test status
Simulation time 544846516 ps
CPU time 1.29 seconds
Started Aug 29 11:02:35 AM UTC 24
Finished Aug 29 11:02:38 AM UTC 24
Peak memory 205892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4292124034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti
mer_csr_mem_rw_with_rand_reset.4292124034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.947411898
Short name T368
Test name
Test status
Simulation time 460817532 ps
CPU time 1.61 seconds
Started Aug 29 11:02:35 AM UTC 24
Finished Aug 29 11:02:38 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947411898 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.947411898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.1518821312
Short name T366
Test name
Test status
Simulation time 449731553 ps
CPU time 1.45 seconds
Started Aug 29 11:02:35 AM UTC 24
Finished Aug 29 11:02:38 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518821312 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1518821312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3402652408
Short name T374
Test name
Test status
Simulation time 3508559397 ps
CPU time 3.11 seconds
Started Aug 29 11:02:35 AM UTC 24
Finished Aug 29 11:02:39 AM UTC 24
Peak memory 205424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402652408 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.3402652408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.3304595870
Short name T367
Test name
Test status
Simulation time 740864329 ps
CPU time 2.07 seconds
Started Aug 29 11:02:34 AM UTC 24
Finished Aug 29 11:02:38 AM UTC 24
Peak memory 207028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304595870 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3304595870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1674151082
Short name T371
Test name
Test status
Simulation time 465171907 ps
CPU time 0.96 seconds
Started Aug 29 11:02:37 AM UTC 24
Finished Aug 29 11:02:39 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1674151082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti
mer_csr_mem_rw_with_rand_reset.1674151082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.717230630
Short name T373
Test name
Test status
Simulation time 389886927 ps
CPU time 1.57 seconds
Started Aug 29 11:02:36 AM UTC 24
Finished Aug 29 11:02:39 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717230630 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.717230630
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.619600087
Short name T369
Test name
Test status
Simulation time 447958273 ps
CPU time 1.03 seconds
Started Aug 29 11:02:36 AM UTC 24
Finished Aug 29 11:02:38 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619600087 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.619600087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/17.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1180055412
Short name T382
Test name
Test status
Simulation time 1718050752 ps
CPU time 3.5 seconds
Started Aug 29 11:02:37 AM UTC 24
Finished Aug 29 11:02:41 AM UTC 24
Peak memory 203576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180055412 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.1180055412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.3185651089
Short name T375
Test name
Test status
Simulation time 507930807 ps
CPU time 2.23 seconds
Started Aug 29 11:02:36 AM UTC 24
Finished Aug 29 11:02:40 AM UTC 24
Peak memory 207028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185651089 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3185651089
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2512344604
Short name T378
Test name
Test status
Simulation time 4423543140 ps
CPU time 2.61 seconds
Started Aug 29 11:02:36 AM UTC 24
Finished Aug 29 11:02:40 AM UTC 24
Peak memory 205808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512344604 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.2512344604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4192055654
Short name T379
Test name
Test status
Simulation time 512592699 ps
CPU time 0.95 seconds
Started Aug 29 11:02:38 AM UTC 24
Finished Aug 29 11:02:40 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4192055654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_ti
mer_csr_mem_rw_with_rand_reset.4192055654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.3693692064
Short name T65
Test name
Test status
Simulation time 475903710 ps
CPU time 1.42 seconds
Started Aug 29 11:02:38 AM UTC 24
Finished Aug 29 11:02:41 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693692064 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3693692064
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.1344284640
Short name T376
Test name
Test status
Simulation time 373761723 ps
CPU time 0.71 seconds
Started Aug 29 11:02:38 AM UTC 24
Finished Aug 29 11:02:40 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344284640 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1344284640
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.674014596
Short name T395
Test name
Test status
Simulation time 2403270372 ps
CPU time 3.77 seconds
Started Aug 29 11:02:38 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 205488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674014596 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.674014596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.3454652611
Short name T381
Test name
Test status
Simulation time 379787673 ps
CPU time 1.91 seconds
Started Aug 29 11:02:38 AM UTC 24
Finished Aug 29 11:02:41 AM UTC 24
Peak memory 207028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454652611 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3454652611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1050588338
Short name T421
Test name
Test status
Simulation time 8178485174 ps
CPU time 7.4 seconds
Started Aug 29 11:02:38 AM UTC 24
Finished Aug 29 11:02:47 AM UTC 24
Peak memory 207076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050588338 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.1050588338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4280382542
Short name T386
Test name
Test status
Simulation time 442730149 ps
CPU time 0.85 seconds
Started Aug 29 11:02:39 AM UTC 24
Finished Aug 29 11:02:42 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4280382542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti
mer_csr_mem_rw_with_rand_reset.4280382542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.260832607
Short name T385
Test name
Test status
Simulation time 455331392 ps
CPU time 1.78 seconds
Started Aug 29 11:02:38 AM UTC 24
Finished Aug 29 11:02:42 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260832607 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.260832607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.650110217
Short name T380
Test name
Test status
Simulation time 463868547 ps
CPU time 1.07 seconds
Started Aug 29 11:02:38 AM UTC 24
Finished Aug 29 11:02:41 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650110217 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.650110217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.478884290
Short name T393
Test name
Test status
Simulation time 2507216273 ps
CPU time 2.09 seconds
Started Aug 29 11:02:39 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 205688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478884290 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.478884290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.531350564
Short name T383
Test name
Test status
Simulation time 391973996 ps
CPU time 1.72 seconds
Started Aug 29 11:02:38 AM UTC 24
Finished Aug 29 11:02:41 AM UTC 24
Peak memory 207000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531350564 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.531350564
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1137223349
Short name T422
Test name
Test status
Simulation time 4285779919 ps
CPU time 7.62 seconds
Started Aug 29 11:02:38 AM UTC 24
Finished Aug 29 11:02:48 AM UTC 24
Peak memory 206848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137223349 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.1137223349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3880720726
Short name T57
Test name
Test status
Simulation time 531355432 ps
CPU time 1.46 seconds
Started Aug 29 11:02:14 AM UTC 24
Finished Aug 29 11:02:16 AM UTC 24
Peak memory 203828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880720726 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.3880720726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3409079078
Short name T311
Test name
Test status
Simulation time 7241270372 ps
CPU time 8.79 seconds
Started Aug 29 11:02:14 AM UTC 24
Finished Aug 29 11:02:23 AM UTC 24
Peak memory 205660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409079078 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.3409079078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2173660709
Short name T76
Test name
Test status
Simulation time 1175121295 ps
CPU time 1.26 seconds
Started Aug 29 11:02:12 AM UTC 24
Finished Aug 29 11:02:15 AM UTC 24
Peak memory 201780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173660709 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.2173660709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.908866403
Short name T297
Test name
Test status
Simulation time 510939762 ps
CPU time 2.2 seconds
Started Aug 29 11:02:15 AM UTC 24
Finished Aug 29 11:02:18 AM UTC 24
Peak memory 205428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=908866403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_time
r_csr_mem_rw_with_rand_reset.908866403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1346476790
Short name T58
Test name
Test status
Simulation time 320831360 ps
CPU time 1.87 seconds
Started Aug 29 11:02:13 AM UTC 24
Finished Aug 29 11:02:16 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346476790 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1346476790
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.2208198259
Short name T292
Test name
Test status
Simulation time 374082218 ps
CPU time 1.08 seconds
Started Aug 29 11:02:12 AM UTC 24
Finished Aug 29 11:02:14 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208198259 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2208198259
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.863773813
Short name T295
Test name
Test status
Simulation time 422572215 ps
CPU time 1.4 seconds
Started Aug 29 11:02:12 AM UTC 24
Finished Aug 29 11:02:15 AM UTC 24
Peak memory 199976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863773813 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.863773813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.1170172024
Short name T293
Test name
Test status
Simulation time 399407557 ps
CPU time 1.07 seconds
Started Aug 29 11:02:12 AM UTC 24
Finished Aug 29 11:02:14 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170172024 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.1170172024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2391254940
Short name T68
Test name
Test status
Simulation time 2265832085 ps
CPU time 2.55 seconds
Started Aug 29 11:02:15 AM UTC 24
Finished Aug 29 11:02:18 AM UTC 24
Peak memory 205688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391254940 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.2391254940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2590285779
Short name T296
Test name
Test status
Simulation time 602752908 ps
CPU time 1.99 seconds
Started Aug 29 11:02:12 AM UTC 24
Finished Aug 29 11:02:15 AM UTC 24
Peak memory 207000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590285779 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2590285779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.226326116
Short name T336
Test name
Test status
Simulation time 8375031501 ps
CPU time 17.36 seconds
Started Aug 29 11:02:12 AM UTC 24
Finished Aug 29 11:02:31 AM UTC 24
Peak memory 207216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226326116 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.226326116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.3214867547
Short name T384
Test name
Test status
Simulation time 336688598 ps
CPU time 0.65 seconds
Started Aug 29 11:02:39 AM UTC 24
Finished Aug 29 11:02:42 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214867547 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3214867547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/20.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.11225754
Short name T389
Test name
Test status
Simulation time 494022623 ps
CPU time 1.56 seconds
Started Aug 29 11:02:39 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11225754 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.11225754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/21.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.851116774
Short name T391
Test name
Test status
Simulation time 326613828 ps
CPU time 1.25 seconds
Started Aug 29 11:02:39 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851116774 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.851116774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/22.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2669384836
Short name T399
Test name
Test status
Simulation time 480388767 ps
CPU time 1.92 seconds
Started Aug 29 11:02:39 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669384836 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2669384836
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/23.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.776426735
Short name T402
Test name
Test status
Simulation time 478721910 ps
CPU time 2.05 seconds
Started Aug 29 11:02:39 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 201208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776426735 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.776426735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/24.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.4067053154
Short name T387
Test name
Test status
Simulation time 522611777 ps
CPU time 0.92 seconds
Started Aug 29 11:02:39 AM UTC 24
Finished Aug 29 11:02:42 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067053154 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.4067053154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/25.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.4200061370
Short name T388
Test name
Test status
Simulation time 478729840 ps
CPU time 0.95 seconds
Started Aug 29 11:02:39 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 199768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200061370 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4200061370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/26.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.2389588208
Short name T398
Test name
Test status
Simulation time 453697725 ps
CPU time 1.72 seconds
Started Aug 29 11:02:40 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 199760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389588208 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2389588208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/27.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.3697818149
Short name T400
Test name
Test status
Simulation time 265135632 ps
CPU time 1.34 seconds
Started Aug 29 11:02:41 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697818149 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3697818149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/28.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.1094387841
Short name T404
Test name
Test status
Simulation time 428360688 ps
CPU time 1.61 seconds
Started Aug 29 11:02:41 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094387841 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1094387841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/29.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1174298228
Short name T60
Test name
Test status
Simulation time 643045736 ps
CPU time 2.41 seconds
Started Aug 29 11:02:17 AM UTC 24
Finished Aug 29 11:02:21 AM UTC 24
Peak memory 203520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174298228 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.1174298228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1456204621
Short name T319
Test name
Test status
Simulation time 4337943995 ps
CPU time 7.6 seconds
Started Aug 29 11:02:17 AM UTC 24
Finished Aug 29 11:02:26 AM UTC 24
Peak memory 205976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456204621 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.1456204621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1247777368
Short name T300
Test name
Test status
Simulation time 1062403218 ps
CPU time 1.36 seconds
Started Aug 29 11:02:16 AM UTC 24
Finished Aug 29 11:02:18 AM UTC 24
Peak memory 201780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247777368 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.1247777368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3101396313
Short name T304
Test name
Test status
Simulation time 305009620 ps
CPU time 1.41 seconds
Started Aug 29 11:02:18 AM UTC 24
Finished Aug 29 11:02:20 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3101396313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_csr_mem_rw_with_rand_reset.3101396313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.4185758426
Short name T303
Test name
Test status
Simulation time 408488823 ps
CPU time 2.25 seconds
Started Aug 29 11:02:16 AM UTC 24
Finished Aug 29 11:02:19 AM UTC 24
Peak memory 201336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185758426 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4185758426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.1537843612
Short name T301
Test name
Test status
Simulation time 483416007 ps
CPU time 2.14 seconds
Started Aug 29 11:02:16 AM UTC 24
Finished Aug 29 11:02:19 AM UTC 24
Peak memory 201464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537843612 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1537843612
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2898088493
Short name T302
Test name
Test status
Simulation time 493656169 ps
CPU time 2.31 seconds
Started Aug 29 11:02:16 AM UTC 24
Finished Aug 29 11:02:19 AM UTC 24
Peak memory 201144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898088493 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.2898088493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.1605872094
Short name T298
Test name
Test status
Simulation time 471088014 ps
CPU time 1.13 seconds
Started Aug 29 11:02:16 AM UTC 24
Finished Aug 29 11:02:18 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605872094 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.1605872094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1177323501
Short name T74
Test name
Test status
Simulation time 2084096937 ps
CPU time 8.73 seconds
Started Aug 29 11:02:18 AM UTC 24
Finished Aug 29 11:02:28 AM UTC 24
Peak memory 205560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177323501 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.1177323501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.3851307319
Short name T299
Test name
Test status
Simulation time 422243419 ps
CPU time 2.47 seconds
Started Aug 29 11:02:15 AM UTC 24
Finished Aug 29 11:02:18 AM UTC 24
Peak memory 207028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851307319 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3851307319
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3698955996
Short name T40
Test name
Test status
Simulation time 4583936745 ps
CPU time 2.85 seconds
Started Aug 29 11:02:16 AM UTC 24
Finished Aug 29 11:02:20 AM UTC 24
Peak memory 206444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698955996 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.3698955996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.3594345295
Short name T396
Test name
Test status
Simulation time 480533886 ps
CPU time 1.03 seconds
Started Aug 29 11:02:41 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594345295 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3594345295
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/30.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.469486637
Short name T401
Test name
Test status
Simulation time 318145164 ps
CPU time 1.43 seconds
Started Aug 29 11:02:41 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469486637 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.469486637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/31.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3008934007
Short name T394
Test name
Test status
Simulation time 318668066 ps
CPU time 0.7 seconds
Started Aug 29 11:02:41 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008934007 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3008934007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/32.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2991290477
Short name T397
Test name
Test status
Simulation time 416730787 ps
CPU time 0.96 seconds
Started Aug 29 11:02:41 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 201840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991290477 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2991290477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/33.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2148609395
Short name T392
Test name
Test status
Simulation time 357831163 ps
CPU time 0.79 seconds
Started Aug 29 11:02:41 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148609395 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2148609395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/34.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.2603297205
Short name T360
Test name
Test status
Simulation time 431930224 ps
CPU time 1.27 seconds
Started Aug 29 11:02:41 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603297205 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2603297205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/35.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.4141891716
Short name T407
Test name
Test status
Simulation time 511453222 ps
CPU time 0.77 seconds
Started Aug 29 11:02:42 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 201840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141891716 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.4141891716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/36.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.2025175897
Short name T406
Test name
Test status
Simulation time 519525963 ps
CPU time 0.73 seconds
Started Aug 29 11:02:42 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025175897 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2025175897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/37.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.4155095242
Short name T412
Test name
Test status
Simulation time 488188299 ps
CPU time 1.06 seconds
Started Aug 29 11:02:42 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155095242 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4155095242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/38.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.3629016727
Short name T413
Test name
Test status
Simulation time 426543219 ps
CPU time 1.31 seconds
Started Aug 29 11:02:42 AM UTC 24
Finished Aug 29 11:02:45 AM UTC 24
Peak memory 199768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629016727 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3629016727
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/39.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.970495239
Short name T61
Test name
Test status
Simulation time 649395183 ps
CPU time 1.76 seconds
Started Aug 29 11:02:20 AM UTC 24
Finished Aug 29 11:02:22 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970495239 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.970495239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3249765223
Short name T317
Test name
Test status
Simulation time 7163169158 ps
CPU time 4.73 seconds
Started Aug 29 11:02:20 AM UTC 24
Finished Aug 29 11:02:25 AM UTC 24
Peak memory 205912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249765223 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.3249765223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3161300404
Short name T306
Test name
Test status
Simulation time 1007849988 ps
CPU time 1.16 seconds
Started Aug 29 11:02:20 AM UTC 24
Finished Aug 29 11:02:22 AM UTC 24
Peak memory 201780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161300404 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.3161300404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1989223451
Short name T310
Test name
Test status
Simulation time 447150789 ps
CPU time 1.24 seconds
Started Aug 29 11:02:21 AM UTC 24
Finished Aug 29 11:02:23 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1989223451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim
er_csr_mem_rw_with_rand_reset.1989223451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3920353242
Short name T69
Test name
Test status
Simulation time 338768316 ps
CPU time 0.89 seconds
Started Aug 29 11:02:20 AM UTC 24
Finished Aug 29 11:02:21 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920353242 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3920353242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.1304710545
Short name T305
Test name
Test status
Simulation time 407648167 ps
CPU time 1 seconds
Started Aug 29 11:02:19 AM UTC 24
Finished Aug 29 11:02:21 AM UTC 24
Peak memory 201500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304710545 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1304710545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.782091912
Short name T309
Test name
Test status
Simulation time 470464710 ps
CPU time 1.57 seconds
Started Aug 29 11:02:19 AM UTC 24
Finished Aug 29 11:02:22 AM UTC 24
Peak memory 199976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782091912 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.782091912
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2436288578
Short name T308
Test name
Test status
Simulation time 349015798 ps
CPU time 1.59 seconds
Started Aug 29 11:02:19 AM UTC 24
Finished Aug 29 11:02:22 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436288578 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.2436288578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2119871115
Short name T70
Test name
Test status
Simulation time 1103785002 ps
CPU time 1.85 seconds
Started Aug 29 11:02:21 AM UTC 24
Finished Aug 29 11:02:24 AM UTC 24
Peak memory 201904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119871115 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.2119871115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.501283983
Short name T307
Test name
Test status
Simulation time 333613804 ps
CPU time 2.44 seconds
Started Aug 29 11:02:18 AM UTC 24
Finished Aug 29 11:02:22 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501283983 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.501283983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1969224862
Short name T390
Test name
Test status
Simulation time 8365201461 ps
CPU time 21.99 seconds
Started Aug 29 11:02:19 AM UTC 24
Finished Aug 29 11:02:43 AM UTC 24
Peak memory 206568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969224862 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.1969224862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.289958392
Short name T408
Test name
Test status
Simulation time 529816146 ps
CPU time 0.83 seconds
Started Aug 29 11:02:42 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289958392 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.289958392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/40.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.1807950320
Short name T410
Test name
Test status
Simulation time 425329597 ps
CPU time 0.87 seconds
Started Aug 29 11:02:42 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807950320 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1807950320
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/41.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.3209995398
Short name T409
Test name
Test status
Simulation time 482865562 ps
CPU time 0.7 seconds
Started Aug 29 11:02:42 AM UTC 24
Finished Aug 29 11:02:44 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209995398 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3209995398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/42.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2497739036
Short name T414
Test name
Test status
Simulation time 511104996 ps
CPU time 0.84 seconds
Started Aug 29 11:02:43 AM UTC 24
Finished Aug 29 11:02:45 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497739036 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2497739036
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/43.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.2910234372
Short name T416
Test name
Test status
Simulation time 274455989 ps
CPU time 1.02 seconds
Started Aug 29 11:02:43 AM UTC 24
Finished Aug 29 11:02:45 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910234372 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2910234372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/44.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.2509158939
Short name T418
Test name
Test status
Simulation time 526597538 ps
CPU time 1.02 seconds
Started Aug 29 11:02:43 AM UTC 24
Finished Aug 29 11:02:46 AM UTC 24
Peak memory 199604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509158939 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2509158939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/45.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.1059448392
Short name T419
Test name
Test status
Simulation time 443076859 ps
CPU time 1.24 seconds
Started Aug 29 11:02:43 AM UTC 24
Finished Aug 29 11:02:46 AM UTC 24
Peak memory 201840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059448392 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1059448392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/46.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.2500446466
Short name T420
Test name
Test status
Simulation time 487879495 ps
CPU time 1.33 seconds
Started Aug 29 11:02:43 AM UTC 24
Finished Aug 29 11:02:46 AM UTC 24
Peak memory 201840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500446466 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2500446466
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/47.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.4065045679
Short name T415
Test name
Test status
Simulation time 302542974 ps
CPU time 0.84 seconds
Started Aug 29 11:02:43 AM UTC 24
Finished Aug 29 11:02:45 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065045679 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.4065045679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/48.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.2863862949
Short name T417
Test name
Test status
Simulation time 422225917 ps
CPU time 0.89 seconds
Started Aug 29 11:02:43 AM UTC 24
Finished Aug 29 11:02:46 AM UTC 24
Peak memory 201840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863862949 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2863862949
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/49.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4065535258
Short name T316
Test name
Test status
Simulation time 406529462 ps
CPU time 1.59 seconds
Started Aug 29 11:02:22 AM UTC 24
Finished Aug 29 11:02:25 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4065535258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_tim
er_csr_mem_rw_with_rand_reset.4065535258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.2438189665
Short name T315
Test name
Test status
Simulation time 546190833 ps
CPU time 2.57 seconds
Started Aug 29 11:02:21 AM UTC 24
Finished Aug 29 11:02:25 AM UTC 24
Peak memory 203184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438189665 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2438189665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.210960240
Short name T313
Test name
Test status
Simulation time 496298975 ps
CPU time 2.41 seconds
Started Aug 29 11:02:21 AM UTC 24
Finished Aug 29 11:02:24 AM UTC 24
Peak memory 203508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210960240 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.210960240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.872268202
Short name T325
Test name
Test status
Simulation time 2661954113 ps
CPU time 5.43 seconds
Started Aug 29 11:02:22 AM UTC 24
Finished Aug 29 11:02:29 AM UTC 24
Peak memory 205424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872268202 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.872268202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.2594641135
Short name T312
Test name
Test status
Simulation time 372426289 ps
CPU time 1.7 seconds
Started Aug 29 11:02:21 AM UTC 24
Finished Aug 29 11:02:24 AM UTC 24
Peak memory 206888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594641135 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2594641135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2670048505
Short name T196
Test name
Test status
Simulation time 4270578778 ps
CPU time 4.34 seconds
Started Aug 29 11:02:21 AM UTC 24
Finished Aug 29 11:02:26 AM UTC 24
Peak memory 206568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670048505 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.2670048505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1964831958
Short name T318
Test name
Test status
Simulation time 463592267 ps
CPU time 1.33 seconds
Started Aug 29 11:02:23 AM UTC 24
Finished Aug 29 11:02:26 AM UTC 24
Peak memory 203948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1964831958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_tim
er_csr_mem_rw_with_rand_reset.1964831958
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.2051975168
Short name T62
Test name
Test status
Simulation time 386473807 ps
CPU time 1.13 seconds
Started Aug 29 11:02:22 AM UTC 24
Finished Aug 29 11:02:24 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051975168 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2051975168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2506233558
Short name T314
Test name
Test status
Simulation time 358979743 ps
CPU time 1.24 seconds
Started Aug 29 11:02:22 AM UTC 24
Finished Aug 29 11:02:24 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506233558 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2506233558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2044731116
Short name T71
Test name
Test status
Simulation time 1194653302 ps
CPU time 1.48 seconds
Started Aug 29 11:02:23 AM UTC 24
Finished Aug 29 11:02:26 AM UTC 24
Peak memory 201904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044731116 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.2044731116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.1854254138
Short name T320
Test name
Test status
Simulation time 623497318 ps
CPU time 2.88 seconds
Started Aug 29 11:02:22 AM UTC 24
Finished Aug 29 11:02:26 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854254138 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1854254138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3342103553
Short name T197
Test name
Test status
Simulation time 8040120484 ps
CPU time 7.91 seconds
Started Aug 29 11:02:22 AM UTC 24
Finished Aug 29 11:02:31 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342103553 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.3342103553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2602660150
Short name T323
Test name
Test status
Simulation time 623197272 ps
CPU time 1.42 seconds
Started Aug 29 11:02:26 AM UTC 24
Finished Aug 29 11:02:28 AM UTC 24
Peak memory 206028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2602660150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim
er_csr_mem_rw_with_rand_reset.2602660150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.1078188735
Short name T72
Test name
Test status
Simulation time 486356340 ps
CPU time 1.13 seconds
Started Aug 29 11:02:25 AM UTC 24
Finished Aug 29 11:02:27 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078188735 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1078188735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.2572805019
Short name T321
Test name
Test status
Simulation time 558794181 ps
CPU time 0.92 seconds
Started Aug 29 11:02:25 AM UTC 24
Finished Aug 29 11:02:27 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572805019 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2572805019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4257140281
Short name T73
Test name
Test status
Simulation time 1718586016 ps
CPU time 1.3 seconds
Started Aug 29 11:02:25 AM UTC 24
Finished Aug 29 11:02:27 AM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257140281 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.4257140281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.1878799240
Short name T322
Test name
Test status
Simulation time 916412332 ps
CPU time 2.17 seconds
Started Aug 29 11:02:24 AM UTC 24
Finished Aug 29 11:02:27 AM UTC 24
Peak memory 207012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878799240 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1878799240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2297019872
Short name T195
Test name
Test status
Simulation time 8249167559 ps
CPU time 15.14 seconds
Started Aug 29 11:02:24 AM UTC 24
Finished Aug 29 11:02:40 AM UTC 24
Peak memory 207056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297019872 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.2297019872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.26697392
Short name T328
Test name
Test status
Simulation time 648030808 ps
CPU time 1.16 seconds
Started Aug 29 11:02:27 AM UTC 24
Finished Aug 29 11:02:29 AM UTC 24
Peak memory 205304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=26697392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer
_csr_mem_rw_with_rand_reset.26697392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.1478261078
Short name T324
Test name
Test status
Simulation time 455230769 ps
CPU time 1.56 seconds
Started Aug 29 11:02:26 AM UTC 24
Finished Aug 29 11:02:29 AM UTC 24
Peak memory 201836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478261078 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1478261078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.414395799
Short name T329
Test name
Test status
Simulation time 419303914 ps
CPU time 2.29 seconds
Started Aug 29 11:02:26 AM UTC 24
Finished Aug 29 11:02:29 AM UTC 24
Peak memory 201128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414395799 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.414395799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2467906433
Short name T327
Test name
Test status
Simulation time 1703825920 ps
CPU time 2.04 seconds
Started Aug 29 11:02:26 AM UTC 24
Finished Aug 29 11:02:29 AM UTC 24
Peak memory 205560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467906433 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.2467906433
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.881030545
Short name T326
Test name
Test status
Simulation time 728025051 ps
CPU time 1.94 seconds
Started Aug 29 11:02:26 AM UTC 24
Finished Aug 29 11:02:29 AM UTC 24
Peak memory 206168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881030545 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.881030545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.938118763
Short name T193
Test name
Test status
Simulation time 8244435081 ps
CPU time 4.15 seconds
Started Aug 29 11:02:26 AM UTC 24
Finished Aug 29 11:02:31 AM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938118763 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.938118763
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1052190224
Short name T331
Test name
Test status
Simulation time 705162428 ps
CPU time 1.45 seconds
Started Aug 29 11:02:27 AM UTC 24
Finished Aug 29 11:02:30 AM UTC 24
Peak memory 206948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1052190224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_tim
er_csr_mem_rw_with_rand_reset.1052190224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.3831501336
Short name T332
Test name
Test status
Simulation time 285170715 ps
CPU time 1.7 seconds
Started Aug 29 11:02:27 AM UTC 24
Finished Aug 29 11:02:30 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831501336 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3831501336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.4093420013
Short name T330
Test name
Test status
Simulation time 435938323 ps
CPU time 1.09 seconds
Started Aug 29 11:02:27 AM UTC 24
Finished Aug 29 11:02:29 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093420013 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.4093420013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2976637106
Short name T343
Test name
Test status
Simulation time 2629276946 ps
CPU time 4.32 seconds
Started Aug 29 11:02:27 AM UTC 24
Finished Aug 29 11:02:33 AM UTC 24
Peak memory 205688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976637106 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.2976637106
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.2845510256
Short name T333
Test name
Test status
Simulation time 462173929 ps
CPU time 2.17 seconds
Started Aug 29 11:02:27 AM UTC 24
Finished Aug 29 11:02:30 AM UTC 24
Peak memory 207104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845510256 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2845510256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3134192140
Short name T351
Test name
Test status
Simulation time 8652353957 ps
CPU time 5.9 seconds
Started Aug 29 11:02:27 AM UTC 24
Finished Aug 29 11:02:34 AM UTC 24
Peak memory 207068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134192140 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.3134192140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.3213619270
Short name T19
Test name
Test status
Simulation time 43432474290 ps
CPU time 7.26 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:28 AM UTC 24
Peak memory 200676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213619270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3213619270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1373027624
Short name T1
Test name
Test status
Simulation time 558880793 ps
CPU time 0.56 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373027624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1373027624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/0.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.3088204107
Short name T220
Test name
Test status
Simulation time 54779108520 ps
CPU time 44.34 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:01:06 AM UTC 24
Peak memory 200452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088204107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3088204107
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.392829356
Short name T26
Test name
Test status
Simulation time 3887303927 ps
CPU time 6.07 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:28 AM UTC 24
Peak memory 230828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392829356 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.392829356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.2397498835
Short name T85
Test name
Test status
Simulation time 10417708292 ps
CPU time 3.84 seconds
Started Aug 29 11:00:28 AM UTC 24
Finished Aug 29 11:00:33 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397498835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2397498835
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.669357043
Short name T205
Test name
Test status
Simulation time 422325812 ps
CPU time 1.4 seconds
Started Aug 29 11:00:28 AM UTC 24
Finished Aug 29 11:00:31 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669357043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.669357043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/10.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.1476072871
Short name T87
Test name
Test status
Simulation time 30704598667 ps
CPU time 9.59 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:39 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476072871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1476072871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.757021293
Short name T52
Test name
Test status
Simulation time 464438652 ps
CPU time 1.06 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:31 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757021293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.757021293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.2341176688
Short name T203
Test name
Test status
Simulation time 49968206458 ps
CPU time 31.55 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:01:02 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341176688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2341176688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.850081928
Short name T206
Test name
Test status
Simulation time 606279046 ps
CPU time 1.43 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:31 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850081928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.850081928
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/12.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.3971710429
Short name T88
Test name
Test status
Simulation time 19058323748 ps
CPU time 12.24 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:42 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971710429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3971710429
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.996744554
Short name T204
Test name
Test status
Simulation time 415978403 ps
CPU time 1.63 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:32 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996744554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.996744554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.703578029
Short name T283
Test name
Test status
Simulation time 157535699222 ps
CPU time 287.41 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:05:21 AM UTC 24
Peak memory 200892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703578029 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.703578029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.165316259
Short name T202
Test name
Test status
Simulation time 38340249150 ps
CPU time 13.93 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:44 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165316259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.165316259
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.3352078266
Short name T77
Test name
Test status
Simulation time 525940577 ps
CPU time 1.55 seconds
Started Aug 29 11:00:29 AM UTC 24
Finished Aug 29 11:00:32 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352078266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3352078266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/14.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.1406110183
Short name T252
Test name
Test status
Simulation time 24502452857 ps
CPU time 46.06 seconds
Started Aug 29 11:00:30 AM UTC 24
Finished Aug 29 11:01:45 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406110183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1406110183
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.3182807629
Short name T215
Test name
Test status
Simulation time 486113660 ps
CPU time 0.92 seconds
Started Aug 29 11:00:30 AM UTC 24
Finished Aug 29 11:00:59 AM UTC 24
Peak memory 199364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182807629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3182807629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/15.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.3725673358
Short name T218
Test name
Test status
Simulation time 4023602648 ps
CPU time 2.49 seconds
Started Aug 29 11:00:30 AM UTC 24
Finished Aug 29 11:01:02 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725673358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3725673358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.3349575422
Short name T217
Test name
Test status
Simulation time 446397517 ps
CPU time 1.39 seconds
Started Aug 29 11:00:30 AM UTC 24
Finished Aug 29 11:01:00 AM UTC 24
Peak memory 199364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349575422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3349575422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.1867923988
Short name T229
Test name
Test status
Simulation time 2358292724 ps
CPU time 14.48 seconds
Started Aug 29 11:00:31 AM UTC 24
Finished Aug 29 11:01:14 AM UTC 24
Peak memory 218856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1867923988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 16.aon_timer_stress_all_with_rand_reset.1867923988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.498002214
Short name T270
Test name
Test status
Simulation time 36397408716 ps
CPU time 70.18 seconds
Started Aug 29 11:00:32 AM UTC 24
Finished Aug 29 11:02:07 AM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498002214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.498002214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/17.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.3943910339
Short name T210
Test name
Test status
Simulation time 464668111 ps
CPU time 1.12 seconds
Started Aug 29 11:00:32 AM UTC 24
Finished Aug 29 11:00:57 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943910339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3943910339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/17.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.2962619742
Short name T224
Test name
Test status
Simulation time 31961360361 ps
CPU time 11.7 seconds
Started Aug 29 11:00:32 AM UTC 24
Finished Aug 29 11:01:08 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962619742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2962619742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.342752918
Short name T84
Test name
Test status
Simulation time 522544841 ps
CPU time 1.15 seconds
Started Aug 29 11:00:32 AM UTC 24
Finished Aug 29 11:00:57 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342752918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.342752918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.3863609782
Short name T173
Test name
Test status
Simulation time 7644281915 ps
CPU time 14.1 seconds
Started Aug 29 11:00:32 AM UTC 24
Finished Aug 29 11:01:10 AM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3863609782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 18.aon_timer_stress_all_with_rand_reset.3863609782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.4016152375
Short name T235
Test name
Test status
Simulation time 50085659864 ps
CPU time 30.39 seconds
Started Aug 29 11:00:34 AM UTC 24
Finished Aug 29 11:01:27 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016152375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.4016152375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.3762356641
Short name T213
Test name
Test status
Simulation time 452007562 ps
CPU time 0.73 seconds
Started Aug 29 11:00:33 AM UTC 24
Finished Aug 29 11:00:59 AM UTC 24
Peak memory 199240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762356641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3762356641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/19.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.3528529495
Short name T231
Test name
Test status
Simulation time 39924979594 ps
CPU time 56.35 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:01:18 AM UTC 24
Peak memory 200620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528529495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3528529495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.1909258144
Short name T11
Test name
Test status
Simulation time 4350596091 ps
CPU time 1.41 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:23 AM UTC 24
Peak memory 230716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909258144 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1909258144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.3769270687
Short name T6
Test name
Test status
Simulation time 390113493 ps
CPU time 0.95 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769270687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3769270687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/2.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.621244999
Short name T199
Test name
Test status
Simulation time 1501603092 ps
CPU time 1.19 seconds
Started Aug 29 11:00:37 AM UTC 24
Finished Aug 29 11:00:57 AM UTC 24
Peak memory 199360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621244999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.621244999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/20.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.3716872233
Short name T209
Test name
Test status
Simulation time 455339578 ps
CPU time 1.22 seconds
Started Aug 29 11:00:37 AM UTC 24
Finished Aug 29 11:00:57 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716872233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3716872233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/20.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.1788814962
Short name T233
Test name
Test status
Simulation time 12368100125 ps
CPU time 23.06 seconds
Started Aug 29 11:00:43 AM UTC 24
Finished Aug 29 11:01:19 AM UTC 24
Peak memory 200832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788814962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1788814962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/21.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.4072325749
Short name T208
Test name
Test status
Simulation time 519422614 ps
CPU time 0.69 seconds
Started Aug 29 11:00:41 AM UTC 24
Finished Aug 29 11:00:56 AM UTC 24
Peak memory 199240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072325749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4072325749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/21.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.3019874042
Short name T272
Test name
Test status
Simulation time 55939887543 ps
CPU time 79.83 seconds
Started Aug 29 11:00:46 AM UTC 24
Finished Aug 29 11:02:17 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019874042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3019874042
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/22.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.1433644343
Short name T15
Test name
Test status
Simulation time 556295258 ps
CPU time 0.88 seconds
Started Aug 29 11:00:46 AM UTC 24
Finished Aug 29 11:00:58 AM UTC 24
Peak memory 199240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433644343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1433644343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/22.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.2786498924
Short name T257
Test name
Test status
Simulation time 31763866803 ps
CPU time 53.71 seconds
Started Aug 29 11:00:52 AM UTC 24
Finished Aug 29 11:01:50 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786498924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2786498924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/23.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.4039620134
Short name T211
Test name
Test status
Simulation time 488880990 ps
CPU time 1.74 seconds
Started Aug 29 11:00:52 AM UTC 24
Finished Aug 29 11:00:58 AM UTC 24
Peak memory 199060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039620134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4039620134
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/23.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.1641558413
Short name T273
Test name
Test status
Simulation time 41146507613 ps
CPU time 80.86 seconds
Started Aug 29 11:00:57 AM UTC 24
Finished Aug 29 11:02:20 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641558413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1641558413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/24.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.2902989153
Short name T212
Test name
Test status
Simulation time 341244075 ps
CPU time 1.15 seconds
Started Aug 29 11:00:56 AM UTC 24
Finished Aug 29 11:00:58 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902989153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2902989153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/24.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.2052612018
Short name T225
Test name
Test status
Simulation time 17543144428 ps
CPU time 9.38 seconds
Started Aug 29 11:00:58 AM UTC 24
Finished Aug 29 11:01:10 AM UTC 24
Peak memory 200444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052612018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2052612018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/25.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.2788435699
Short name T216
Test name
Test status
Simulation time 547984698 ps
CPU time 1.59 seconds
Started Aug 29 11:00:57 AM UTC 24
Finished Aug 29 11:01:00 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788435699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2788435699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/25.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.1042337903
Short name T81
Test name
Test status
Simulation time 9549886573 ps
CPU time 21.44 seconds
Started Aug 29 11:00:58 AM UTC 24
Finished Aug 29 11:01:22 AM UTC 24
Peak memory 215284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1042337903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 25.aon_timer_stress_all_with_rand_reset.1042337903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.3729421691
Short name T223
Test name
Test status
Simulation time 34302169591 ps
CPU time 7.2 seconds
Started Aug 29 11:00:58 AM UTC 24
Finished Aug 29 11:01:08 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729421691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3729421691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/26.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.3846454849
Short name T214
Test name
Test status
Simulation time 593521519 ps
CPU time 0.98 seconds
Started Aug 29 11:00:58 AM UTC 24
Finished Aug 29 11:01:01 AM UTC 24
Peak memory 199160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846454849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3846454849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/26.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.2688510961
Short name T271
Test name
Test status
Simulation time 39097092736 ps
CPU time 66.62 seconds
Started Aug 29 11:01:01 AM UTC 24
Finished Aug 29 11:02:09 AM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688510961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2688510961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/27.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.1477907091
Short name T150
Test name
Test status
Simulation time 464201939 ps
CPU time 0.99 seconds
Started Aug 29 11:01:00 AM UTC 24
Finished Aug 29 11:01:02 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477907091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1477907091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/27.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.3955095723
Short name T264
Test name
Test status
Simulation time 58607393994 ps
CPU time 57.95 seconds
Started Aug 29 11:01:01 AM UTC 24
Finished Aug 29 11:02:01 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955095723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3955095723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/28.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.2045690880
Short name T219
Test name
Test status
Simulation time 362391717 ps
CPU time 1.45 seconds
Started Aug 29 11:01:01 AM UTC 24
Finished Aug 29 11:01:03 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045690880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2045690880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/28.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.3967287052
Short name T254
Test name
Test status
Simulation time 39765450263 ps
CPU time 41.53 seconds
Started Aug 29 11:01:03 AM UTC 24
Finished Aug 29 11:01:46 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967287052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3967287052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/29.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.2484433698
Short name T222
Test name
Test status
Simulation time 557166579 ps
CPU time 2.36 seconds
Started Aug 29 11:01:03 AM UTC 24
Finished Aug 29 11:01:07 AM UTC 24
Peak memory 200640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484433698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2484433698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/29.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.2481434988
Short name T50
Test name
Test status
Simulation time 32624663496 ps
CPU time 8.3 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:30 AM UTC 24
Peak memory 200428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481434988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2481434988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.880001752
Short name T31
Test name
Test status
Simulation time 8606173730 ps
CPU time 3.57 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:28 AM UTC 24
Peak memory 231376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880001752 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.880001752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.3864846962
Short name T5
Test name
Test status
Simulation time 490174235 ps
CPU time 0.68 seconds
Started Aug 29 11:00:10 AM UTC 24
Finished Aug 29 11:00:22 AM UTC 24
Peak memory 199212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864846962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3864846962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/3.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.1315282525
Short name T243
Test name
Test status
Simulation time 17983039157 ps
CPU time 28.27 seconds
Started Aug 29 11:01:06 AM UTC 24
Finished Aug 29 11:01:35 AM UTC 24
Peak memory 200632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315282525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1315282525
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/30.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.1770532809
Short name T221
Test name
Test status
Simulation time 459209011 ps
CPU time 1.16 seconds
Started Aug 29 11:01:04 AM UTC 24
Finished Aug 29 11:01:07 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770532809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1770532809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/30.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.1056032180
Short name T232
Test name
Test status
Simulation time 58218065877 ps
CPU time 8.17 seconds
Started Aug 29 11:01:09 AM UTC 24
Finished Aug 29 11:01:18 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056032180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1056032180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/31.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.621114444
Short name T227
Test name
Test status
Simulation time 419173951 ps
CPU time 1.96 seconds
Started Aug 29 11:01:08 AM UTC 24
Finished Aug 29 11:01:11 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621114444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.621114444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/31.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.100182651
Short name T259
Test name
Test status
Simulation time 39141501340 ps
CPU time 39.26 seconds
Started Aug 29 11:01:11 AM UTC 24
Finished Aug 29 11:01:52 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100182651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.100182651
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/32.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.4015486729
Short name T228
Test name
Test status
Simulation time 491550511 ps
CPU time 1.12 seconds
Started Aug 29 11:01:10 AM UTC 24
Finished Aug 29 11:01:12 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015486729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.4015486729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/32.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.2459111952
Short name T245
Test name
Test status
Simulation time 6595804429 ps
CPU time 23.49 seconds
Started Aug 29 11:01:12 AM UTC 24
Finished Aug 29 11:01:38 AM UTC 24
Peak memory 206204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2459111952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 32.aon_timer_stress_all_with_rand_reset.2459111952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.834793140
Short name T282
Test name
Test status
Simulation time 59840859418 ps
CPU time 123.53 seconds
Started Aug 29 11:01:14 AM UTC 24
Finished Aug 29 11:03:21 AM UTC 24
Peak memory 200424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834793140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.834793140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/33.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.3585943267
Short name T230
Test name
Test status
Simulation time 459865742 ps
CPU time 1.06 seconds
Started Aug 29 11:01:13 AM UTC 24
Finished Aug 29 11:01:16 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585943267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3585943267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/33.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.4194919936
Short name T240
Test name
Test status
Simulation time 3571233127 ps
CPU time 5.86 seconds
Started Aug 29 11:01:18 AM UTC 24
Finished Aug 29 11:01:32 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194919936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4194919936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/34.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.3710613955
Short name T238
Test name
Test status
Simulation time 438777835 ps
CPU time 1.43 seconds
Started Aug 29 11:01:17 AM UTC 24
Finished Aug 29 11:01:29 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710613955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3710613955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/34.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.3090731513
Short name T253
Test name
Test status
Simulation time 40811560669 ps
CPU time 17.05 seconds
Started Aug 29 11:01:20 AM UTC 24
Finished Aug 29 11:01:45 AM UTC 24
Peak memory 200620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090731513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3090731513
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/35.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.4112622006
Short name T239
Test name
Test status
Simulation time 609495048 ps
CPU time 1.29 seconds
Started Aug 29 11:01:19 AM UTC 24
Finished Aug 29 11:01:29 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112622006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.4112622006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/35.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.311115209
Short name T236
Test name
Test status
Simulation time 5357742005 ps
CPU time 2.38 seconds
Started Aug 29 11:01:23 AM UTC 24
Finished Aug 29 11:01:28 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311115209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.311115209
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/36.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.1869445235
Short name T237
Test name
Test status
Simulation time 598679128 ps
CPU time 2.56 seconds
Started Aug 29 11:01:23 AM UTC 24
Finished Aug 29 11:01:28 AM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869445235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1869445235
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/36.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.2447276368
Short name T268
Test name
Test status
Simulation time 38389531165 ps
CPU time 33.46 seconds
Started Aug 29 11:01:29 AM UTC 24
Finished Aug 29 11:02:04 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447276368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2447276368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/37.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.4097649221
Short name T241
Test name
Test status
Simulation time 534517229 ps
CPU time 2.04 seconds
Started Aug 29 11:01:28 AM UTC 24
Finished Aug 29 11:01:32 AM UTC 24
Peak memory 200028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097649221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.4097649221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/37.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.624125383
Short name T192
Test name
Test status
Simulation time 568233553 ps
CPU time 1.2 seconds
Started Aug 29 11:01:31 AM UTC 24
Finished Aug 29 11:01:34 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624125383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.624125383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/38.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.2923047483
Short name T277
Test name
Test status
Simulation time 41045315687 ps
CPU time 62.95 seconds
Started Aug 29 11:01:31 AM UTC 24
Finished Aug 29 11:02:36 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923047483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2923047483
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/38.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.3474723025
Short name T242
Test name
Test status
Simulation time 410174253 ps
CPU time 1.99 seconds
Started Aug 29 11:01:31 AM UTC 24
Finished Aug 29 11:01:34 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474723025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3474723025
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/38.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.3186803289
Short name T249
Test name
Test status
Simulation time 20440077824 ps
CPU time 6.67 seconds
Started Aug 29 11:01:33 AM UTC 24
Finished Aug 29 11:01:41 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186803289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3186803289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/39.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.642500501
Short name T244
Test name
Test status
Simulation time 565422074 ps
CPU time 1.25 seconds
Started Aug 29 11:01:33 AM UTC 24
Finished Aug 29 11:01:36 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642500501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.642500501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/39.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.2596922849
Short name T267
Test name
Test status
Simulation time 8156557165 ps
CPU time 25.36 seconds
Started Aug 29 11:01:35 AM UTC 24
Finished Aug 29 11:02:03 AM UTC 24
Peak memory 217296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2596922849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 39.aon_timer_stress_all_with_rand_reset.2596922849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.3840030199
Short name T226
Test name
Test status
Simulation time 32891442211 ps
CPU time 45.86 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:01:11 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840030199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3840030199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.677873356
Short name T32
Test name
Test status
Simulation time 7798009340 ps
CPU time 3.51 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:29 AM UTC 24
Peak memory 231228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677873356 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.677873356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.1424342713
Short name T9
Test name
Test status
Simulation time 413862327 ps
CPU time 1.02 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424342713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1424342713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/4.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.2706015700
Short name T279
Test name
Test status
Simulation time 32687693482 ps
CPU time 67.58 seconds
Started Aug 29 11:01:36 AM UTC 24
Finished Aug 29 11:02:47 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706015700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2706015700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/40.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.3155366742
Short name T247
Test name
Test status
Simulation time 447413348 ps
CPU time 2.17 seconds
Started Aug 29 11:01:35 AM UTC 24
Finished Aug 29 11:01:39 AM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155366742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3155366742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/40.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.274134757
Short name T177
Test name
Test status
Simulation time 410359698 ps
CPU time 2.05 seconds
Started Aug 29 11:01:40 AM UTC 24
Finished Aug 29 11:01:43 AM UTC 24
Peak memory 200568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274134757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.274134757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/41.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.3400987620
Short name T255
Test name
Test status
Simulation time 2691425453 ps
CPU time 9.05 seconds
Started Aug 29 11:01:39 AM UTC 24
Finished Aug 29 11:01:49 AM UTC 24
Peak memory 200764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400987620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3400987620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/41.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.3209586465
Short name T248
Test name
Test status
Simulation time 501195425 ps
CPU time 1.15 seconds
Started Aug 29 11:01:39 AM UTC 24
Finished Aug 29 11:01:41 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209586465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3209586465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/41.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.2422606965
Short name T262
Test name
Test status
Simulation time 24830663436 ps
CPU time 13.77 seconds
Started Aug 29 11:01:42 AM UTC 24
Finished Aug 29 11:01:57 AM UTC 24
Peak memory 200552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422606965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2422606965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/42.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.4238700880
Short name T250
Test name
Test status
Simulation time 554111650 ps
CPU time 1.16 seconds
Started Aug 29 11:01:41 AM UTC 24
Finished Aug 29 11:01:43 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238700880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.4238700880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/42.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.1907907463
Short name T274
Test name
Test status
Simulation time 23273901306 ps
CPU time 35.17 seconds
Started Aug 29 11:01:43 AM UTC 24
Finished Aug 29 11:02:20 AM UTC 24
Peak memory 219044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1907907463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 42.aon_timer_stress_all_with_rand_reset.1907907463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.377452731
Short name T269
Test name
Test status
Simulation time 26844141474 ps
CPU time 18.36 seconds
Started Aug 29 11:01:44 AM UTC 24
Finished Aug 29 11:02:04 AM UTC 24
Peak memory 200628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377452731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.377452731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/43.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.3965863577
Short name T251
Test name
Test status
Simulation time 551250144 ps
CPU time 1.99 seconds
Started Aug 29 11:01:44 AM UTC 24
Finished Aug 29 11:01:47 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965863577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3965863577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/43.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.1896569629
Short name T266
Test name
Test status
Simulation time 30843061641 ps
CPU time 14.36 seconds
Started Aug 29 11:01:46 AM UTC 24
Finished Aug 29 11:02:02 AM UTC 24
Peak memory 200828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896569629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1896569629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/44.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.1346320799
Short name T256
Test name
Test status
Simulation time 466771543 ps
CPU time 1.97 seconds
Started Aug 29 11:01:46 AM UTC 24
Finished Aug 29 11:01:50 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346320799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1346320799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/44.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.3291329443
Short name T185
Test name
Test status
Simulation time 587352129 ps
CPU time 1.35 seconds
Started Aug 29 11:01:50 AM UTC 24
Finished Aug 29 11:01:52 AM UTC 24
Peak memory 199368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291329443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3291329443
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/45.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.1596346789
Short name T280
Test name
Test status
Simulation time 23617668872 ps
CPU time 59.16 seconds
Started Aug 29 11:01:49 AM UTC 24
Finished Aug 29 11:02:50 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596346789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1596346789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/45.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.3400069057
Short name T258
Test name
Test status
Simulation time 548290487 ps
CPU time 1.17 seconds
Started Aug 29 11:01:49 AM UTC 24
Finished Aug 29 11:01:51 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400069057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3400069057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/45.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.2641483315
Short name T275
Test name
Test status
Simulation time 28007040187 ps
CPU time 40.7 seconds
Started Aug 29 11:01:51 AM UTC 24
Finished Aug 29 11:02:33 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641483315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2641483315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/46.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.3813451286
Short name T260
Test name
Test status
Simulation time 517767015 ps
CPU time 0.97 seconds
Started Aug 29 11:01:51 AM UTC 24
Finished Aug 29 11:01:53 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813451286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3813451286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/46.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.862892730
Short name T281
Test name
Test status
Simulation time 35196482064 ps
CPU time 62.63 seconds
Started Aug 29 11:01:53 AM UTC 24
Finished Aug 29 11:02:58 AM UTC 24
Peak memory 200704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862892730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.862892730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/47.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.3756088221
Short name T261
Test name
Test status
Simulation time 486958413 ps
CPU time 0.96 seconds
Started Aug 29 11:01:53 AM UTC 24
Finished Aug 29 11:01:55 AM UTC 24
Peak memory 199304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756088221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3756088221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/47.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.3491526553
Short name T276
Test name
Test status
Simulation time 16018170228 ps
CPU time 34.46 seconds
Started Aug 29 11:01:58 AM UTC 24
Finished Aug 29 11:02:33 AM UTC 24
Peak memory 200624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491526553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3491526553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/48.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.442163359
Short name T263
Test name
Test status
Simulation time 361165902 ps
CPU time 1.27 seconds
Started Aug 29 11:01:55 AM UTC 24
Finished Aug 29 11:01:58 AM UTC 24
Peak memory 199308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442163359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.442163359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/48.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.4030525
Short name T187
Test name
Test status
Simulation time 374280577 ps
CPU time 2.1 seconds
Started Aug 29 11:02:01 AM UTC 24
Finished Aug 29 11:02:04 AM UTC 24
Peak memory 200576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST
_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4030525
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/49.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.1410168690
Short name T278
Test name
Test status
Simulation time 29307994083 ps
CPU time 36.19 seconds
Started Aug 29 11:02:01 AM UTC 24
Finished Aug 29 11:02:38 AM UTC 24
Peak memory 200700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410168690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1410168690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/49.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.2047354876
Short name T265
Test name
Test status
Simulation time 531948871 ps
CPU time 2.28 seconds
Started Aug 29 11:01:59 AM UTC 24
Finished Aug 29 11:02:02 AM UTC 24
Peak memory 200564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047354876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2047354876
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/49.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.3383255262
Short name T234
Test name
Test status
Simulation time 43733929743 ps
CPU time 53.68 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:01:19 AM UTC 24
Peak memory 200760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383255262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3383255262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.1225820142
Short name T24
Test name
Test status
Simulation time 537964355 ps
CPU time 1.18 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225820142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1225820142
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/5.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.1983518639
Short name T246
Test name
Test status
Simulation time 52137118046 ps
CPU time 71.8 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:01:39 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983518639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1983518639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.1596917247
Short name T16
Test name
Test status
Simulation time 397422438 ps
CPU time 0.9 seconds
Started Aug 29 11:00:18 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596917247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1596917247
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/6.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.2419594446
Short name T174
Test name
Test status
Simulation time 421331309 ps
CPU time 1.68 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:28 AM UTC 24
Peak memory 199428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419594446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2419594446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.2843065938
Short name T207
Test name
Test status
Simulation time 33779795653 ps
CPU time 24.88 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:51 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843065938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2843065938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.4196428663
Short name T17
Test name
Test status
Simulation time 440839737 ps
CPU time 0.84 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196428663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.4196428663
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/7.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.2811143269
Short name T200
Test name
Test status
Simulation time 15229622749 ps
CPU time 20.61 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:47 AM UTC 24
Peak memory 200696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811143269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2811143269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.3248033658
Short name T18
Test name
Test status
Simulation time 375125109 ps
CPU time 0.67 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:27 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248033658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3248033658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.1798176838
Short name T22
Test name
Test status
Simulation time 1630326599 ps
CPU time 7.57 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:33 AM UTC 24
Peak memory 217416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1798176838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 8.aon_timer_stress_all_with_rand_reset.1798176838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.1132743163
Short name T201
Test name
Test status
Simulation time 11861770903 ps
CPU time 3.66 seconds
Started Aug 29 11:00:26 AM UTC 24
Finished Aug 29 11:00:31 AM UTC 24
Peak memory 200620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132743163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1132743163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.2349023385
Short name T10
Test name
Test status
Simulation time 446852069 ps
CPU time 0.76 seconds
Started Aug 29 11:00:24 AM UTC 24
Finished Aug 29 11:00:26 AM UTC 24
Peak memory 199244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349023385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2349023385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/9.aon_timer_smoke/latest
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