Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	19727	1			T1	10		T2	11		T5	10
bark[1]	315	1			T19	42		T85	35		T44	26
bark[2]	305	1			T169	14		T32	21		T33	21
bark[3]	287	1			T90	14		T192	40		T150	88
bark[4]	182	1			T180	14		T195	14		T162	14
bark[5]	359	1			T6	14		T18	98		T31	14
bark[6]	194	1			T102	14		T40	21		T97	14
bark[7]	337	1			T31	21		T120	227		T92	21
bark[8]	251	1			T107	14		T110	21		T109	21
bark[9]	131	1			T42	21		T96	14		T184	14
bark[10]	437	1			T165	14		T40	5		T156	26
bark[11]	332	1			T172	14		T110	68		T93	47
bark[12]	374	1			T21	14		T129	38		T78	12
bark[13]	166	1			T32	14		T80	21		T152	21
bark[14]	138	1			T19	30		T32	35		T125	26
bark[15]	201	1			T160	42		T125	26		T78	21
bark[16]	105	1			T30	14		T193	14		T138	21
bark[17]	301	1			T10	14		T25	14		T78	21
bark[18]	480	1			T18	14		T25	62		T26	21
bark[19]	113	1			T9	14		T158	14		T183	14
bark[20]	369	1			T42	26		T122	14		T77	7
bark[21]	196	1			T45	14		T25	21		T85	21
bark[22]	167	1			T178	14		T133	21		T125	21
bark[23]	560	1			T188	47		T76	77		T78	21
bark[24]	378	1			T18	21		T32	129		T129	26
bark[25]	352	1			T143	14		T186	14		T42	52
bark[26]	738	1			T3	14		T14	14		T131	14
bark[27]	240	1			T40	14		T43	5		T160	35
bark[28]	624	1			T157	14		T19	21		T42	52
bark[29]	108	1			T19	19		T164	14		T81	7
bark[30]	169	1			T26	40		T44	5		T145	14
bark[31]	298	1			T4	14		T48	14		T43	26
bark_0	4770	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	19488	1			T1	9		T2	10		T5	9
bite[1]	255	1			T4	13		T26	21		T43	4
bite[2]	240	1			T26	39		T107	13		T32	21
bite[3]	301	1			T42	51		T162	13		T138	53
bite[4]	402	1			T18	21		T32	13		T178	13
bite[5]	401	1			T19	30		T190	13		T109	21
bite[6]	194	1			T14	13		T48	13		T172	13
bite[7]	458	1			T133	21		T160	34		T188	46
bite[8]	133	1			T40	4		T44	25		T195	13
bite[9]	387	1			T138	35		T166	13		T80	132
bite[10]	464	1			T19	18		T85	21		T44	4
bite[11]	280	1			T148	55		T159	13		T76	21
bite[12]	296	1			T98	13		T129	30		T116	133
bite[13]	311	1			T158	13		T120	256		T146	42
bite[14]	283	1			T31	13		T40	13		T129	26
bite[15]	499	1			T18	97		T76	100		T192	40
bite[16]	322	1			T138	21		T140	13		T92	96
bite[17]	104	1			T18	13		T169	13		T125	26
bite[18]	197	1			T156	25		T77	6		T192	59
bite[19]	363	1			T3	13		T42	26		T32	128
bite[20]	360	1			T10	13		T25	62		T186	13
bite[21]	245	1			T6	13		T193	13		T43	25
bite[22]	509	1			T25	21		T131	13		T102	13
bite[23]	330	1			T19	21		T160	42		T78	21
bite[24]	414	1			T21	13		T30	13		T45	13
bite[25]	209	1			T31	21		T32	34		T120	21
bite[26]	145	1			T157	13		T85	35		T129	21
bite[27]	136	1			T129	38		T87	47		T118	21
bite[28]	134	1			T143	13		T33	21		T145	13
bite[29]	209	1			T25	13		T75	30		T110	67
bite[30]	188	1			T19	42		T85	21		T32	6
bite[31]	196	1			T9	13		T183	13		T165	13
bite_0	5251	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30252

1

T1

17

T2

18

T3

21

auto[1]

3452

1

T19

38

T74

7

T75

20

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	294	1			T202	9		T85	23		T110	2
prescale[1]	202	1			T25	40		T43	2		T44	19
prescale[2]	276	1			T31	61		T203	9		T78	51
prescale[3]	269	1			T24	2		T41	2		T129	36
prescale[4]	390	1			T12	9		T19	19		T82	9
prescale[5]	275	1			T47	9		T20	2		T26	19
prescale[6]	341	1			T85	45		T204	9		T113	2
prescale[7]	397	1			T19	35		T49	9		T129	23
prescale[8]	316	1			T25	23		T78	9		T171	2
prescale[9]	544	1			T18	2		T20	2		T31	97
prescale[10]	506	1			T75	43		T205	9		T41	2
prescale[11]	526	1			T31	19		T75	45		T43	2
prescale[12]	502	1			T24	2		T41	2		T42	41
prescale[13]	209	1			T44	2		T206	9		T32	2
prescale[14]	298	1			T31	19		T42	2		T32	2
prescale[15]	446	1			T25	24		T85	24		T33	2
prescale[16]	462	1			T24	2		T31	47		T42	57
prescale[17]	306	1			T84	9		T110	2		T188	35
prescale[18]	205	1			T32	2		T156	2		T113	2
prescale[19]	844	1			T25	23		T31	76		T42	136
prescale[20]	578	1			T18	2		T207	9		T129	28
prescale[21]	312	1			T31	76		T32	2		T125	19
prescale[22]	547	1			T20	2		T31	28		T33	2
prescale[23]	578	1			T31	36		T42	2		T133	19
prescale[24]	247	1			T42	2		T44	2		T156	6
prescale[25]	374	1			T31	2		T85	49		T44	2
prescale[26]	264	1			T110	2		T133	2		T116	40
prescale[27]	258	1			T42	4		T110	2		T78	40
prescale[28]	475	1			T83	9		T31	91		T42	47
prescale[29]	313	1			T40	2		T32	2		T110	2
prescale[30]	542	1			T188	23		T116	19		T149	2
prescale[31]	340	1			T43	2		T156	2		T188	24
prescale_0	21268	1			T1	17		T2	18		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23110

1

T1

17

T2

9

T3

21

auto[1]

10594

1

T2

9

T4

12

T8

9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

33704

1

T1

17

T2

18

T3

21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	19348	1			T1	12		T2	13		T3	1
wkup[1]	125	1			T158	15		T40	21		T42	21
wkup[2]	185	1			T186	15		T42	15		T44	21
wkup[3]	137	1			T26	21		T76	21		T149	6
wkup[4]	161	1			T25	41		T129	21		T148	21
wkup[5]	140	1			T31	21		T125	26		T117	21
wkup[6]	196	1			T18	21		T19	20		T75	30
wkup[7]	281	1			T45	15		T32	51		T110	21
wkup[8]	44	1			T195	15		T113	8		T179	21
wkup[9]	216	1			T183	15		T43	21		T132	15
wkup[10]	227	1			T19	21		T80	21		T81	6
wkup[11]	242	1			T4	15		T31	15		T133	21
wkup[12]	133	1			T24	21		T125	41		T92	8
wkup[13]	248	1			T143	15		T159	15		T76	21
wkup[14]	110	1			T107	15		T116	30		T171	8
wkup[15]	131	1			T6	15		T40	15		T148	30
wkup[16]	212	1			T42	21		T32	30		T129	21
wkup[17]	266	1			T172	15		T110	26		T188	8
wkup[18]	196	1			T192	21		T87	26		T208	8
wkup[19]	210	1			T31	21		T169	15		T180	15
wkup[20]	141	1			T32	21		T166	15		T161	21
wkup[21]	163	1			T131	15		T32	15		T148	21
wkup[22]	160	1			T42	21		T125	21		T192	21
wkup[23]	148	1			T48	15		T98	15		T42	21
wkup[24]	183	1			T9	15		T31	21		T42	21
wkup[25]	259	1			T25	57		T31	30		T133	21
wkup[26]	140	1			T31	21		T44	35		T110	21
wkup[27]	94	1			T85	21		T123	21		T155	21
wkup[28]	21	1			T134	21		-	-		-	-
wkup[29]	120	1			T18	15		T93	26		T96	15
wkup[30]	84	1			T149	21		T139	21		T103	21
wkup[31]	188	1			T31	21		T32	15		T138	21
wkup[32]	144	1			T156	21		T161	8		T120	42
wkup[33]	229	1			T24	15		T75	26		T85	21
wkup[34]	231	1			T85	21		T33	51		T76	21
wkup[35]	155	1			T26	26		T76	21		T78	21
wkup[36]	184	1			T75	35		T32	21		T160	21
wkup[37]	117	1			T117	15		T111	21		T119	21
wkup[38]	239	1			T19	21		T110	21		T93	35
wkup[39]	147	1			T19	21		T133	21		T150	21
wkup[40]	174	1			T40	6		T156	21		T93	21
wkup[41]	192	1			T157	15		T18	21		T78	21
wkup[42]	63	1			T148	21		T100	21		T89	21
wkup[43]	266	1			T10	15		T24	21		T33	21
wkup[44]	148	1			T31	21		T77	8		T120	35
wkup[45]	150	1			T32	26		T113	21		T116	30
wkup[46]	229	1			T21	15		T25	21		T42	21
wkup[47]	187	1			T76	21		T209	8		T80	21
wkup[48]	171	1			T110	31		T138	15		T76	21
wkup[49]	204	1			T165	15		T125	21		T116	42
wkup[50]	358	1			T85	35		T32	8		T188	21
wkup[51]	151	1			T26	15		T162	15		T129	26
wkup[52]	68	1			T18	21		T109	26		T103	21
wkup[53]	152	1			T193	15		T87	21		T176	6
wkup[54]	84	1			T116	21		T80	21		T118	21
wkup[55]	158	1			T3	15		T129	30		T76	30
wkup[56]	183	1			T85	21		T32	26		T133	24
wkup[57]	280	1			T19	30		T32	21		T110	21
wkup[58]	208	1			T75	26		T42	26		T80	21
wkup[59]	98	1			T30	15		T137	21		T155	21
wkup[60]	141	1			T31	21		T42	30		T138	21
wkup[61]	129	1			T76	21		T81	21		T194	15
wkup[62]	92	1			T160	21		T138	21		T161	21
wkup[63]	84	1			T113	21		T111	21		T108	21
wkup_0	3779	1			T1	5		T2	5		T3	5