| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.28 | 99.33 | 95.61 | 100.00 | 98.40 | 99.51 | 42.83 |
| T287 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.3889542482 | Sep 01 08:33:17 PM UTC 24 | Sep 01 08:33:20 PM UTC 24 | 304801215 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.885151158 | Sep 01 08:33:18 PM UTC 24 | Sep 01 08:33:20 PM UTC 24 | 403487930 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3488953563 | Sep 01 08:33:18 PM UTC 24 | Sep 01 08:33:20 PM UTC 24 | 353231247 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.3477023510 | Sep 01 08:33:18 PM UTC 24 | Sep 01 08:33:21 PM UTC 24 | 430839694 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.498064005 | Sep 01 08:33:19 PM UTC 24 | Sep 01 08:33:22 PM UTC 24 | 629246357 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2502271467 | Sep 01 08:33:17 PM UTC 24 | Sep 01 08:33:23 PM UTC 24 | 4670092507 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2251458567 | Sep 01 08:33:21 PM UTC 24 | Sep 01 08:33:23 PM UTC 24 | 387251935 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.1195604294 | Sep 01 08:33:20 PM UTC 24 | Sep 01 08:33:23 PM UTC 24 | 484782952 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3712592754 | Sep 01 08:33:21 PM UTC 24 | Sep 01 08:33:24 PM UTC 24 | 581564198 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.777083028 | Sep 01 08:33:22 PM UTC 24 | Sep 01 08:33:24 PM UTC 24 | 420719240 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.775834188 | Sep 01 08:33:22 PM UTC 24 | Sep 01 08:33:25 PM UTC 24 | 269100993 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3991492947 | Sep 01 08:33:20 PM UTC 24 | Sep 01 08:33:25 PM UTC 24 | 7245984183 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1682113547 | Sep 01 08:33:40 PM UTC 24 | Sep 01 08:33:43 PM UTC 24 | 378162025 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.1342745213 | Sep 01 08:33:22 PM UTC 24 | Sep 01 08:33:26 PM UTC 24 | 1902010060 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2770115419 | Sep 01 08:33:23 PM UTC 24 | Sep 01 08:33:26 PM UTC 24 | 512341868 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.4029888281 | Sep 01 08:33:24 PM UTC 24 | Sep 01 08:33:27 PM UTC 24 | 688643288 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.955278153 | Sep 01 08:33:24 PM UTC 24 | Sep 01 08:33:27 PM UTC 24 | 476455152 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1517938985 | Sep 01 08:33:24 PM UTC 24 | Sep 01 08:33:27 PM UTC 24 | 570605225 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3755276586 | Sep 01 08:33:25 PM UTC 24 | Sep 01 08:33:28 PM UTC 24 | 413431148 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3486981051 | Sep 01 08:33:37 PM UTC 24 | Sep 01 08:33:41 PM UTC 24 | 789047154 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2492635600 | Sep 01 08:33:22 PM UTC 24 | Sep 01 08:33:28 PM UTC 24 | 4343308782 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3725414333 | Sep 01 08:33:25 PM UTC 24 | Sep 01 08:33:29 PM UTC 24 | 335438907 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.101527301 | Sep 01 08:33:27 PM UTC 24 | Sep 01 08:33:29 PM UTC 24 | 332192864 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.515625720 | Sep 01 08:33:27 PM UTC 24 | Sep 01 08:33:29 PM UTC 24 | 305800176 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1381929462 | Sep 01 08:33:25 PM UTC 24 | Sep 01 08:33:29 PM UTC 24 | 1317468222 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2972416936 | Sep 01 08:33:27 PM UTC 24 | Sep 01 08:33:30 PM UTC 24 | 369967532 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.901196143 | Sep 01 08:33:28 PM UTC 24 | Sep 01 08:33:30 PM UTC 24 | 1311725587 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4051827738 | Sep 01 08:33:21 PM UTC 24 | Sep 01 08:33:31 PM UTC 24 | 2220679482 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2537714040 | Sep 01 08:33:26 PM UTC 24 | Sep 01 08:33:31 PM UTC 24 | 4254224340 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1897093327 | Sep 01 08:33:29 PM UTC 24 | Sep 01 08:33:31 PM UTC 24 | 402304004 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2451574525 | Sep 01 08:33:29 PM UTC 24 | Sep 01 08:33:32 PM UTC 24 | 669213798 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.982514696 | Sep 01 08:33:29 PM UTC 24 | Sep 01 08:33:32 PM UTC 24 | 499833953 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3806733953 | Sep 01 08:33:30 PM UTC 24 | Sep 01 08:33:32 PM UTC 24 | 322813407 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.296892482 | Sep 01 08:33:30 PM UTC 24 | Sep 01 08:33:33 PM UTC 24 | 471954446 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3847599486 | Sep 01 08:33:30 PM UTC 24 | Sep 01 08:33:33 PM UTC 24 | 420041275 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1087850084 | Sep 01 08:33:29 PM UTC 24 | Sep 01 08:33:33 PM UTC 24 | 515481526 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1785173144 | Sep 01 08:33:30 PM UTC 24 | Sep 01 08:33:33 PM UTC 24 | 828854584 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.3929779545 | Sep 01 08:33:30 PM UTC 24 | Sep 01 08:33:33 PM UTC 24 | 331493809 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3869755796 | Sep 01 08:33:29 PM UTC 24 | Sep 01 08:33:34 PM UTC 24 | 4465646590 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.971074176 | Sep 01 08:33:32 PM UTC 24 | Sep 01 08:33:35 PM UTC 24 | 514476675 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2842825008 | Sep 01 08:33:33 PM UTC 24 | Sep 01 08:33:35 PM UTC 24 | 358790744 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1678022134 | Sep 01 08:33:29 PM UTC 24 | Sep 01 08:33:35 PM UTC 24 | 1105387349 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1136648624 | Sep 01 08:33:32 PM UTC 24 | Sep 01 08:33:35 PM UTC 24 | 513402460 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.419108895 | Sep 01 08:33:32 PM UTC 24 | Sep 01 08:33:35 PM UTC 24 | 1696168030 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2734917292 | Sep 01 08:33:33 PM UTC 24 | Sep 01 08:33:35 PM UTC 24 | 524693535 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.1458937541 | Sep 01 08:33:33 PM UTC 24 | Sep 01 08:33:35 PM UTC 24 | 406488995 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.2140893555 | Sep 01 08:33:33 PM UTC 24 | Sep 01 08:33:35 PM UTC 24 | 535876984 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.894493055 | Sep 01 08:33:32 PM UTC 24 | Sep 01 08:33:35 PM UTC 24 | 538166935 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1300433504 | Sep 01 08:33:33 PM UTC 24 | Sep 01 08:33:36 PM UTC 24 | 663053397 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.366590871 | Sep 01 08:33:32 PM UTC 24 | Sep 01 08:33:36 PM UTC 24 | 4274811164 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.3216634978 | Sep 01 08:33:34 PM UTC 24 | Sep 01 08:33:37 PM UTC 24 | 311982878 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1435658961 | Sep 01 08:33:34 PM UTC 24 | Sep 01 08:33:37 PM UTC 24 | 665502031 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.940439248 | Sep 01 08:33:34 PM UTC 24 | Sep 01 08:33:37 PM UTC 24 | 391047158 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4188742243 | Sep 01 08:33:37 PM UTC 24 | Sep 01 08:33:43 PM UTC 24 | 8220006801 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2727021757 | Sep 01 08:33:24 PM UTC 24 | Sep 01 08:33:37 PM UTC 24 | 7052990266 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.4189752857 | Sep 01 08:33:34 PM UTC 24 | Sep 01 08:33:38 PM UTC 24 | 478539764 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1011827153 | Sep 01 08:33:34 PM UTC 24 | Sep 01 08:33:38 PM UTC 24 | 1957246356 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2037028406 | Sep 01 08:33:36 PM UTC 24 | Sep 01 08:33:38 PM UTC 24 | 606675365 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.2567928169 | Sep 01 08:33:36 PM UTC 24 | Sep 01 08:33:38 PM UTC 24 | 468827912 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.808988781 | Sep 01 08:33:36 PM UTC 24 | Sep 01 08:33:38 PM UTC 24 | 1144632621 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.679719278 | Sep 01 08:33:36 PM UTC 24 | Sep 01 08:33:39 PM UTC 24 | 437549028 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3144432991 | Sep 01 08:33:37 PM UTC 24 | Sep 01 08:33:39 PM UTC 24 | 478047336 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1395475380 | Sep 01 08:33:36 PM UTC 24 | Sep 01 08:33:40 PM UTC 24 | 510396747 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.4082497162 | Sep 01 08:33:36 PM UTC 24 | Sep 01 08:33:40 PM UTC 24 | 1266946200 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.903427484 | Sep 01 08:33:37 PM UTC 24 | Sep 01 08:33:40 PM UTC 24 | 404626894 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.3836586902 | Sep 01 08:33:38 PM UTC 24 | Sep 01 08:33:40 PM UTC 24 | 405820860 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.4029508122 | Sep 01 08:33:38 PM UTC 24 | Sep 01 08:33:40 PM UTC 24 | 419846780 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.1169409387 | Sep 01 08:33:37 PM UTC 24 | Sep 01 08:33:40 PM UTC 24 | 488042445 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1393080054 | Sep 01 08:33:39 PM UTC 24 | Sep 01 08:33:41 PM UTC 24 | 381823399 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.4010291944 | Sep 01 08:33:41 PM UTC 24 | Sep 01 08:33:43 PM UTC 24 | 495115895 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.24145736 | Sep 01 08:33:37 PM UTC 24 | Sep 01 08:33:42 PM UTC 24 | 628690247 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.1988315336 | Sep 01 08:33:40 PM UTC 24 | Sep 01 08:33:42 PM UTC 24 | 376022608 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.726784248 | Sep 01 08:33:38 PM UTC 24 | Sep 01 08:33:42 PM UTC 24 | 4229931570 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1111880233 | Sep 01 08:33:36 PM UTC 24 | Sep 01 08:33:42 PM UTC 24 | 2688957155 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3825948194 | Sep 01 08:33:38 PM UTC 24 | Sep 01 08:33:42 PM UTC 24 | 519972392 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.3054017734 | Sep 01 08:33:40 PM UTC 24 | Sep 01 08:33:42 PM UTC 24 | 449066076 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.3517934563 | Sep 01 08:33:38 PM UTC 24 | Sep 01 08:33:42 PM UTC 24 | 415595966 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1393702427 | Sep 01 08:33:40 PM UTC 24 | Sep 01 08:33:42 PM UTC 24 | 413741055 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.1334795279 | Sep 01 08:33:41 PM UTC 24 | Sep 01 08:33:44 PM UTC 24 | 274478807 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1391538353 | Sep 01 08:33:40 PM UTC 24 | Sep 01 08:33:44 PM UTC 24 | 291921351 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3768911131 | Sep 01 08:33:36 PM UTC 24 | Sep 01 08:33:44 PM UTC 24 | 4766215486 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.751723399 | Sep 01 08:33:41 PM UTC 24 | Sep 01 08:33:44 PM UTC 24 | 599582188 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1611792384 | Sep 01 08:33:40 PM UTC 24 | Sep 01 08:33:44 PM UTC 24 | 2189104757 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.2889146201 | Sep 01 08:33:43 PM UTC 24 | Sep 01 08:33:45 PM UTC 24 | 419821729 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.873440785 | Sep 01 08:33:43 PM UTC 24 | Sep 01 08:33:45 PM UTC 24 | 420674477 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.3732026969 | Sep 01 08:33:43 PM UTC 24 | Sep 01 08:33:45 PM UTC 24 | 460037127 ps | ||
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| T421 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.2974285062 | Sep 01 08:33:54 PM UTC 24 | Sep 01 08:33:57 PM UTC 24 | 361643925 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.3992501669 | Sep 01 08:33:54 PM UTC 24 | Sep 01 08:33:57 PM UTC 24 | 277256017 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.315612529 | Sep 01 08:33:54 PM UTC 24 | Sep 01 08:33:57 PM UTC 24 | 278431895 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.1191268559 | Sep 01 08:33:54 PM UTC 24 | Sep 01 08:33:57 PM UTC 24 | 498773261 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1145060770 | Sep 01 08:33:48 PM UTC 24 | Sep 01 08:33:58 PM UTC 24 | 4403444197 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.2724997416 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 481453649 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724997416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2724997416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.4154036507 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1920055335 ps |
| CPU time | 9.44 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:55 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4154036507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.aon_timer_stress_all_with_rand_reset.4154036507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.1677538223 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3367414742 ps |
| CPU time | 5.65 seconds |
| Started | Sep 01 08:31:57 PM UTC 24 |
| Finished | Sep 01 08:32:06 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677538223 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.1677538223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2502271467 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4670092507 ps |
| CPU time | 4.79 seconds |
| Started | Sep 01 08:33:17 PM UTC 24 |
| Finished | Sep 01 08:33:23 PM UTC 24 |
| Peak memory | 206688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502271467 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.2502271467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.4108463261 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3898814806 ps |
| CPU time | 34.51 seconds |
| Started | Sep 01 08:32:08 PM UTC 24 |
| Finished | Sep 01 08:32:44 PM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4108463261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 18.aon_timer_stress_all_with_rand_reset.4108463261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.2647950553 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 531528244 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:48 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647950553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2647950553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.727808969 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 10987004998 ps |
| CPU time | 32.22 seconds |
| Started | Sep 01 08:32:31 PM UTC 24 |
| Finished | Sep 01 08:33:05 PM UTC 24 |
| Peak memory | 219692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=727808969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.aon_timer_stress_all_with_rand_reset.727808969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.2739776826 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 8851218506 ps |
| CPU time | 43.66 seconds |
| Started | Sep 01 08:32:34 PM UTC 24 |
| Finished | Sep 01 08:33:20 PM UTC 24 |
| Peak memory | 206492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2739776826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 33.aon_timer_stress_all_with_rand_reset.2739776826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2609758275 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 396930593 ps |
| CPU time | 2.16 seconds |
| Started | Sep 01 08:33:44 PM UTC 24 |
| Finished | Sep 01 08:33:47 PM UTC 24 |
| Peak memory | 201460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609758275 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2609758275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.938575351 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 137556597355 ps |
| CPU time | 31.75 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:32:18 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938575351 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.938575351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.1487476756 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4217089625 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:47 PM UTC 24 |
| Peak memory | 230940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487476756 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1487476756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.861386144 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 91855704960 ps |
| CPU time | 90.84 seconds |
| Started | Sep 01 08:32:08 PM UTC 24 |
| Finished | Sep 01 08:33:41 PM UTC 24 |
| Peak memory | 200192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861386144 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.861386144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.2940465334 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 139885763183 ps |
| CPU time | 62.58 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:32:49 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940465334 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.2940465334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.969665447 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 23354551144 ps |
| CPU time | 51.32 seconds |
| Started | Sep 01 08:32:27 PM UTC 24 |
| Finished | Sep 01 08:33:20 PM UTC 24 |
| Peak memory | 206532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=969665447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.aon_timer_stress_all_with_rand_reset.969665447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.330888387 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 421926431959 ps |
| CPU time | 437.05 seconds |
| Started | Sep 01 08:33:17 PM UTC 24 |
| Finished | Sep 01 08:40:40 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330888387 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.330888387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/49.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.1555703478 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9073128770 ps |
| CPU time | 32.2 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:32:18 PM UTC 24 |
| Peak memory | 206680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1555703478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.aon_timer_stress_all_with_rand_reset.1555703478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.4070023437 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 184217549383 ps |
| CPU time | 43.26 seconds |
| Started | Sep 01 08:32:17 PM UTC 24 |
| Finished | Sep 01 08:33:02 PM UTC 24 |
| Peak memory | 200748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070023437 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.4070023437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/24.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.4162793683 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 69625907126 ps |
| CPU time | 52.23 seconds |
| Started | Sep 01 08:33:14 PM UTC 24 |
| Finished | Sep 01 08:34:08 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162793683 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.4162793683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/48.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.3066063797 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 187614712850 ps |
| CPU time | 88.47 seconds |
| Started | Sep 01 08:32:24 PM UTC 24 |
| Finished | Sep 01 08:33:54 PM UTC 24 |
| Peak memory | 200820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066063797 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.3066063797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/28.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.144658847 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 13720100927 ps |
| CPU time | 49.08 seconds |
| Started | Sep 01 08:32:59 PM UTC 24 |
| Finished | Sep 01 08:33:50 PM UTC 24 |
| Peak memory | 203320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=144658847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 44.aon_timer_stress_all_with_rand_reset.144658847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.1585385250 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 5514404481 ps |
| CPU time | 27.31 seconds |
| Started | Sep 01 08:32:08 PM UTC 24 |
| Finished | Sep 01 08:32:37 PM UTC 24 |
| Peak memory | 206500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1585385250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 19.aon_timer_stress_all_with_rand_reset.1585385250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.2849288074 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 47244136486 ps |
| CPU time | 17.82 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:32:04 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849288074 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.2849288074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.1890681493 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 129270714448 ps |
| CPU time | 17.47 seconds |
| Started | Sep 01 08:32:58 PM UTC 24 |
| Finished | Sep 01 08:33:17 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890681493 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.1890681493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/43.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.924389116 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 27271067572 ps |
| CPU time | 22.08 seconds |
| Started | Sep 01 08:32:15 PM UTC 24 |
| Finished | Sep 01 08:32:39 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924389116 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.924389116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/23.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.2276013440 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11491239107 ps |
| CPU time | 23.79 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:16 PM UTC 24 |
| Peak memory | 214272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2276013440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 7.aon_timer_stress_all_with_rand_reset.2276013440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.2013492620 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 92215035829 ps |
| CPU time | 48.21 seconds |
| Started | Sep 01 08:32:26 PM UTC 24 |
| Finished | Sep 01 08:33:16 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013492620 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.2013492620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/29.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.439442909 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 9958456483 ps |
| CPU time | 17.16 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:27 PM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=439442909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.aon_timer_stress_all_with_rand_reset.439442909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.1302163532 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 2872341316 ps |
| CPU time | 18.32 seconds |
| Started | Sep 01 08:32:16 PM UTC 24 |
| Finished | Sep 01 08:32:36 PM UTC 24 |
| Peak memory | 217412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1302163532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 24.aon_timer_stress_all_with_rand_reset.1302163532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1381929462 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1317468222 ps |
| CPU time | 2.51 seconds |
| Started | Sep 01 08:33:25 PM UTC 24 |
| Finished | Sep 01 08:33:29 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381929462 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.1381929462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.2663985982 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 137059396121 ps |
| CPU time | 74.5 seconds |
| Started | Sep 01 08:32:21 PM UTC 24 |
| Finished | Sep 01 08:33:37 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663985982 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.2663985982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/27.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.1125199737 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 21219132645 ps |
| CPU time | 44.82 seconds |
| Started | Sep 01 08:31:45 PM UTC 24 |
| Finished | Sep 01 08:32:31 PM UTC 24 |
| Peak memory | 219680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1125199737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 3.aon_timer_stress_all_with_rand_reset.1125199737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.1952474897 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 375949380528 ps |
| CPU time | 634.41 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:42:50 PM UTC 24 |
| Peak memory | 200584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952474897 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.1952474897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.2395162857 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 99714109295 ps |
| CPU time | 54.93 seconds |
| Started | Sep 01 08:32:42 PM UTC 24 |
| Finished | Sep 01 08:33:39 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395162857 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.2395162857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/36.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.1332762495 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 5797693060 ps |
| CPU time | 46.19 seconds |
| Started | Sep 01 08:32:17 PM UTC 24 |
| Finished | Sep 01 08:33:05 PM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1332762495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 25.aon_timer_stress_all_with_rand_reset.1332762495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.947122378 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 217245579560 ps |
| CPU time | 88.05 seconds |
| Started | Sep 01 08:32:12 PM UTC 24 |
| Finished | Sep 01 08:33:42 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947122378 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.947122378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/21.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.93981755 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2647885488 ps |
| CPU time | 18.91 seconds |
| Started | Sep 01 08:33:16 PM UTC 24 |
| Finished | Sep 01 08:33:36 PM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=93981755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 49.aon_timer_stress_all_with_rand_reset.93981755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.1905099185 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 22606392698 ps |
| CPU time | 30.24 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:40 PM UTC 24 |
| Peak memory | 218448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1905099185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 10.aon_timer_stress_all_with_rand_reset.1905099185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.2216714758 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 358692385057 ps |
| CPU time | 370.07 seconds |
| Started | Sep 01 08:31:53 PM UTC 24 |
| Finished | Sep 01 08:38:11 PM UTC 24 |
| Peak memory | 200572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216714758 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.2216714758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.3763037743 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3919992400 ps |
| CPU time | 26.52 seconds |
| Started | Sep 01 08:32:20 PM UTC 24 |
| Finished | Sep 01 08:32:48 PM UTC 24 |
| Peak memory | 217984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3763037743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 27.aon_timer_stress_all_with_rand_reset.3763037743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.2367968223 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 379155627969 ps |
| CPU time | 156.27 seconds |
| Started | Sep 01 08:32:32 PM UTC 24 |
| Finished | Sep 01 08:35:11 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367968223 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.2367968223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/32.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.497319576 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 100608284634 ps |
| CPU time | 61.02 seconds |
| Started | Sep 01 08:32:50 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497319576 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.497319576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/40.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.1759150383 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 115586576069 ps |
| CPU time | 44.6 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:36 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759150383 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.1759150383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.216498534 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2291920878 ps |
| CPU time | 13.92 seconds |
| Started | Sep 01 08:31:57 PM UTC 24 |
| Finished | Sep 01 08:32:15 PM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=216498534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.aon_timer_stress_all_with_rand_reset.216498534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.2294564006 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 442576196989 ps |
| CPU time | 343.92 seconds |
| Started | Sep 01 08:33:00 PM UTC 24 |
| Finished | Sep 01 08:38:48 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294564006 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.2294564006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/44.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.1457556135 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 14315266960 ps |
| CPU time | 32.65 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:42 PM UTC 24 |
| Peak memory | 219456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1457556135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.aon_timer_stress_all_with_rand_reset.1457556135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.1845430253 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 110895456429 ps |
| CPU time | 197.52 seconds |
| Started | Sep 01 08:32:10 PM UTC 24 |
| Finished | Sep 01 08:35:30 PM UTC 24 |
| Peak memory | 200440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845430253 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.1845430253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.3018078964 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 167869258763 ps |
| CPU time | 139.7 seconds |
| Started | Sep 01 08:32:35 PM UTC 24 |
| Finished | Sep 01 08:34:58 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018078964 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.3018078964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/33.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.2263295125 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 15797902097 ps |
| CPU time | 15.16 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:06 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2263295125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 5.aon_timer_stress_all_with_rand_reset.2263295125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.3357903287 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 105691268355 ps |
| CPU time | 218.39 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:35:50 PM UTC 24 |
| Peak memory | 200572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357903287 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.3357903287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.49860683 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 43897126751 ps |
| CPU time | 12.82 seconds |
| Started | Sep 01 08:32:11 PM UTC 24 |
| Finished | Sep 01 08:32:25 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49860683 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.49860683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/20.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.591976859 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 56173138156 ps |
| CPU time | 98.26 seconds |
| Started | Sep 01 08:32:12 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591976859 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.591976859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/22.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.3933352747 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 21662917463 ps |
| CPU time | 13.5 seconds |
| Started | Sep 01 08:31:45 PM UTC 24 |
| Finished | Sep 01 08:31:59 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933352747 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.3933352747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.200349732 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 179478717726 ps |
| CPU time | 39.69 seconds |
| Started | Sep 01 08:32:53 PM UTC 24 |
| Finished | Sep 01 08:33:34 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200349732 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.200349732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/41.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.1482894832 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 5754086822 ps |
| CPU time | 10.44 seconds |
| Started | Sep 01 08:32:17 PM UTC 24 |
| Finished | Sep 01 08:32:29 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482894832 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.1482894832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/25.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.3076880586 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6148325628 ps |
| CPU time | 24.5 seconds |
| Started | Sep 01 08:32:23 PM UTC 24 |
| Finished | Sep 01 08:32:49 PM UTC 24 |
| Peak memory | 215308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3076880586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 28.aon_timer_stress_all_with_rand_reset.3076880586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.2802996190 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 109741922153 ps |
| CPU time | 214.11 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:35:46 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802996190 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.2802996190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.573133096 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 27088318034 ps |
| CPU time | 14.24 seconds |
| Started | Sep 01 08:32:29 PM UTC 24 |
| Finished | Sep 01 08:32:44 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573133096 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.573133096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/30.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.3637317987 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 91913191066 ps |
| CPU time | 148.66 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:34:21 PM UTC 24 |
| Peak memory | 200756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637317987 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.3637317987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.3765644613 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 144705656847 ps |
| CPU time | 66.82 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:59 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765644613 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.3765644613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.3110551242 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2949782665 ps |
| CPU time | 28.55 seconds |
| Started | Sep 01 08:32:18 PM UTC 24 |
| Finished | Sep 01 08:32:48 PM UTC 24 |
| Peak memory | 206780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3110551242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 26.aon_timer_stress_all_with_rand_reset.3110551242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.4192167707 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 234717253053 ps |
| CPU time | 489.16 seconds |
| Started | Sep 01 08:33:04 PM UTC 24 |
| Finished | Sep 01 08:41:19 PM UTC 24 |
| Peak memory | 200896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192167707 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.4192167707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/45.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.1590699788 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 148171471948 ps |
| CPU time | 17.85 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:10 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590699788 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.1590699788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.3534521756 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 395986349169 ps |
| CPU time | 68.42 seconds |
| Started | Sep 01 08:32:01 PM UTC 24 |
| Finished | Sep 01 08:33:18 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534521756 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.3534521756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.504734356 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 517825245 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:31:45 PM UTC 24 |
| Finished | Sep 01 08:31:47 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504734356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.504734356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.930656839 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 388688886 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:32:49 PM UTC 24 |
| Finished | Sep 01 08:32:51 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930656839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.930656839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/39.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.2457174871 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 301829250551 ps |
| CPU time | 546.71 seconds |
| Started | Sep 01 08:32:55 PM UTC 24 |
| Finished | Sep 01 08:42:08 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457174871 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.2457174871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/42.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.1600717020 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 10100760122 ps |
| CPU time | 22.34 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:31 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600717020 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.1600717020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.2177046776 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 743541484034 ps |
| CPU time | 1292.32 seconds |
| Started | Sep 01 08:31:54 PM UTC 24 |
| Finished | Sep 01 08:53:42 PM UTC 24 |
| Peak memory | 200896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177046776 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.2177046776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.2151220621 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 475894042 ps |
| CPU time | 2.64 seconds |
| Started | Sep 01 08:32:19 PM UTC 24 |
| Finished | Sep 01 08:32:23 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151220621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2151220621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/27.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.4282728680 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 368447794 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 08:32:37 PM UTC 24 |
| Finished | Sep 01 08:32:39 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282728680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.4282728680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/34.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.3285859121 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 135059566121 ps |
| CPU time | 125.84 seconds |
| Started | Sep 01 08:32:38 PM UTC 24 |
| Finished | Sep 01 08:34:46 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285859121 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.3285859121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/34.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.1679974769 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 152899616833 ps |
| CPU time | 309.89 seconds |
| Started | Sep 01 08:32:47 PM UTC 24 |
| Finished | Sep 01 08:38:01 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679974769 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.1679974769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/38.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.2148081166 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 611966736 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:31:45 PM UTC 24 |
| Finished | Sep 01 08:31:48 PM UTC 24 |
| Peak memory | 199420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148081166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2148081166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.112023397 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 5238233577 ps |
| CPU time | 27.02 seconds |
| Started | Sep 01 08:32:55 PM UTC 24 |
| Finished | Sep 01 08:33:23 PM UTC 24 |
| Peak memory | 206624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=112023397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 42.aon_timer_stress_all_with_rand_reset.112023397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.3208745190 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 353089198 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 08:32:56 PM UTC 24 |
| Finished | Sep 01 08:32:58 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208745190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3208745190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/43.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.2895268601 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 485364619 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:31:52 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895268601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2895268601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.762066023 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 403506284 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:10 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762066023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.762066023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.2104161493 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 356427771 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:10 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104161493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2104161493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.2713184710 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 12954327536 ps |
| CPU time | 44.59 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:54 PM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2713184710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 13.aon_timer_stress_all_with_rand_reset.2713184710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.2846446220 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 478389983 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:32:27 PM UTC 24 |
| Finished | Sep 01 08:32:30 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846446220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2846446220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/30.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.1194442774 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 300024225752 ps |
| CPU time | 61.91 seconds |
| Started | Sep 01 08:32:45 PM UTC 24 |
| Finished | Sep 01 08:33:48 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194442774 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.1194442774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/37.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.2589221294 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 447047764635 ps |
| CPU time | 235.19 seconds |
| Started | Sep 01 08:33:11 PM UTC 24 |
| Finished | Sep 01 08:37:10 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589221294 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.2589221294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/47.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.2313402701 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2908783077 ps |
| CPU time | 9.14 seconds |
| Started | Sep 01 08:31:54 PM UTC 24 |
| Finished | Sep 01 08:32:06 PM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2313402701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 14.aon_timer_stress_all_with_rand_reset.2313402701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.1203259393 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 387844830 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 08:32:12 PM UTC 24 |
| Finished | Sep 01 08:32:14 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203259393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1203259393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/22.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.3002754035 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 452336312646 ps |
| CPU time | 510.78 seconds |
| Started | Sep 01 08:32:19 PM UTC 24 |
| Finished | Sep 01 08:40:56 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002754035 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.3002754035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/26.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.2519701267 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 346028782 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 08:32:32 PM UTC 24 |
| Finished | Sep 01 08:32:35 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519701267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2519701267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/32.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.2870746438 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 504690893 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:32:46 PM UTC 24 |
| Finished | Sep 01 08:32:48 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870746438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2870746438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/38.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.3117354517 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 386395268 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 08:33:02 PM UTC 24 |
| Finished | Sep 01 08:33:04 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117354517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3117354517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/45.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.1342795140 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 439700589 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 08:33:05 PM UTC 24 |
| Finished | Sep 01 08:33:08 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342795140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1342795140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/46.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.3077895798 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 385849199 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:32:12 PM UTC 24 |
| Finished | Sep 01 08:32:14 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077895798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3077895798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/21.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.2435490174 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 103575893399 ps |
| CPU time | 55.2 seconds |
| Started | Sep 01 08:32:31 PM UTC 24 |
| Finished | Sep 01 08:33:28 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435490174 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.2435490174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/31.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.3794035864 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 479873841 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:31:53 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794035864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3794035864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.1703213876 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 556427004 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:12 PM UTC 24 |
| Peak memory | 200528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703213876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1703213876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.1467291966 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 449953876 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 08:32:24 PM UTC 24 |
| Finished | Sep 01 08:32:26 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467291966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1467291966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/29.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.754694674 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 444843779535 ps |
| CPU time | 570.52 seconds |
| Started | Sep 01 08:32:49 PM UTC 24 |
| Finished | Sep 01 08:42:27 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754694674 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.754694674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/39.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.4107950650 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 15916303294 ps |
| CPU time | 40.64 seconds |
| Started | Sep 01 08:32:50 PM UTC 24 |
| Finished | Sep 01 08:33:32 PM UTC 24 |
| Peak memory | 217984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4107950650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 40.aon_timer_stress_all_with_rand_reset.4107950650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.1727281388 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 11911726707 ps |
| CPU time | 45.43 seconds |
| Started | Sep 01 08:33:03 PM UTC 24 |
| Finished | Sep 01 08:33:50 PM UTC 24 |
| Peak memory | 214940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1727281388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 45.aon_timer_stress_all_with_rand_reset.1727281388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.2233750564 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 237371723821 ps |
| CPU time | 208.41 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:35:39 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233750564 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.2233750564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.2903063344 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3706673467 ps |
| CPU time | 25 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:35 PM UTC 24 |
| Peak memory | 217500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2903063344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 12.aon_timer_stress_all_with_rand_reset.2903063344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.3263245601 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 523078965 ps |
| CPU time | 1.99 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:11 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263245601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3263245601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.798119017 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 561581331735 ps |
| CPU time | 255.49 seconds |
| Started | Sep 01 08:32:05 PM UTC 24 |
| Finished | Sep 01 08:36:24 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798119017 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.798119017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.867341584 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 341286913 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:32:08 PM UTC 24 |
| Finished | Sep 01 08:32:11 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867341584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.867341584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.2486135982 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 635969053 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:47 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486135982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2486135982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.2662147083 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 513297546 ps |
| CPU time | 2.33 seconds |
| Started | Sep 01 08:32:11 PM UTC 24 |
| Finished | Sep 01 08:32:14 PM UTC 24 |
| Peak memory | 200776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662147083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2662147083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/20.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.3106656168 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 475955847 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 08:32:13 PM UTC 24 |
| Finished | Sep 01 08:32:16 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106656168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3106656168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/23.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.1000024652 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 44052488317 ps |
| CPU time | 59.05 seconds |
| Started | Sep 01 08:32:15 PM UTC 24 |
| Finished | Sep 01 08:33:17 PM UTC 24 |
| Peak memory | 215448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1000024652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 23.aon_timer_stress_all_with_rand_reset.1000024652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.2886626792 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 568615949 ps |
| CPU time | 2.52 seconds |
| Started | Sep 01 08:32:16 PM UTC 24 |
| Finished | Sep 01 08:32:20 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886626792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2886626792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/24.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.2780217799 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 447794770 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:32:30 PM UTC 24 |
| Finished | Sep 01 08:32:32 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780217799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2780217799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/31.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.3699831586 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 448614845 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 08:32:40 PM UTC 24 |
| Finished | Sep 01 08:32:43 PM UTC 24 |
| Peak memory | 200712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699831586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3699831586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/35.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.744578425 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4469450969 ps |
| CPU time | 14.05 seconds |
| Started | Sep 01 08:32:40 PM UTC 24 |
| Finished | Sep 01 08:32:55 PM UTC 24 |
| Peak memory | 217504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=744578425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.aon_timer_stress_all_with_rand_reset.744578425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.1391753993 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2059041627 ps |
| CPU time | 12.74 seconds |
| Started | Sep 01 08:32:41 PM UTC 24 |
| Finished | Sep 01 08:32:55 PM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1391753993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 36.aon_timer_stress_all_with_rand_reset.1391753993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.3399040409 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3447098454 ps |
| CPU time | 22.6 seconds |
| Started | Sep 01 08:32:44 PM UTC 24 |
| Finished | Sep 01 08:33:08 PM UTC 24 |
| Peak memory | 214320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3399040409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 37.aon_timer_stress_all_with_rand_reset.3399040409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.66774083 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14164295639 ps |
| CPU time | 35.42 seconds |
| Started | Sep 01 08:31:45 PM UTC 24 |
| Finished | Sep 01 08:32:23 PM UTC 24 |
| Peak memory | 206680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=66774083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 4.aon_timer_stress_all_with_rand_reset.66774083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.4135989723 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 546058611 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 08:33:09 PM UTC 24 |
| Finished | Sep 01 08:33:12 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135989723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.4135989723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/47.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.3456427068 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1324789089 ps |
| CPU time | 7.98 seconds |
| Started | Sep 01 08:33:10 PM UTC 24 |
| Finished | Sep 01 08:33:19 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3456427068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 47.aon_timer_stress_all_with_rand_reset.3456427068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1145060770 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 4403444197 ps |
| CPU time | 8.44 seconds |
| Started | Sep 01 08:33:48 PM UTC 24 |
| Finished | Sep 01 08:33:58 PM UTC 24 |
| Peak memory | 206620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145060770 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.1145060770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.1983072309 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 455845425 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983072309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1983072309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.474792482 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 515338071 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:32:03 PM UTC 24 |
| Finished | Sep 01 08:32:08 PM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474792482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.474792482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.3233890670 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 7192196313 ps |
| CPU time | 22.17 seconds |
| Started | Sep 01 08:32:03 PM UTC 24 |
| Finished | Sep 01 08:32:30 PM UTC 24 |
| Peak memory | 216540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3233890670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 17.aon_timer_stress_all_with_rand_reset.3233890670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.56147674 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 463865149 ps |
| CPU time | 0.8 seconds |
| Started | Sep 01 08:32:06 PM UTC 24 |
| Finished | Sep 01 08:32:08 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56147674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.56147674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.3847049683 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 507419239 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 08:32:23 PM UTC 24 |
| Finished | Sep 01 08:32:25 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847049683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3847049683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/28.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.424648892 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 197062487004 ps |
| CPU time | 110.76 seconds |
| Started | Sep 01 08:32:41 PM UTC 24 |
| Finished | Sep 01 08:34:34 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424648892 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.424648892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/35.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.4105978716 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 11347131570 ps |
| CPU time | 34.62 seconds |
| Started | Sep 01 08:32:58 PM UTC 24 |
| Finished | Sep 01 08:33:34 PM UTC 24 |
| Peak memory | 201052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4105978716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 43.aon_timer_stress_all_with_rand_reset.4105978716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.1245848761 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 575896470 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 08:32:59 PM UTC 24 |
| Finished | Sep 01 08:33:03 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245848761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1245848761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/44.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.2867965001 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 299238602360 ps |
| CPU time | 609.19 seconds |
| Started | Sep 01 08:33:07 PM UTC 24 |
| Finished | Sep 01 08:43:24 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867965001 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.2867965001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/46.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.836115861 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 397306894 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 08:33:16 PM UTC 24 |
| Finished | Sep 01 08:33:19 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836115861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.836115861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/49.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.1152865938 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 399283790 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:31:53 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152865938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1152865938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.3787760099 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 10818679390 ps |
| CPU time | 31.21 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:33 PM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3787760099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 8.aon_timer_stress_all_with_rand_reset.3787760099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.2790320980 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 668215446 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:10 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790320980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2790320980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.1842805737 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 528414046 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:31:53 PM UTC 24 |
| Finished | Sep 01 08:32:01 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842805737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1842805737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.235800168 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 394446957 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 08:31:59 PM UTC 24 |
| Finished | Sep 01 08:32:08 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235800168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.235800168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.4002635266 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 530192210 ps |
| CPU time | 2.55 seconds |
| Started | Sep 01 08:32:18 PM UTC 24 |
| Finished | Sep 01 08:32:22 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002635266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4002635266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/26.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.155742369 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2872330036 ps |
| CPU time | 26.2 seconds |
| Started | Sep 01 08:32:25 PM UTC 24 |
| Finished | Sep 01 08:32:53 PM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=155742369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 29.aon_timer_stress_all_with_rand_reset.155742369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.2896010107 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 593594112 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 08:32:41 PM UTC 24 |
| Finished | Sep 01 08:32:44 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896010107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2896010107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/36.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.3473278124 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 393663052 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:32:44 PM UTC 24 |
| Finished | Sep 01 08:32:46 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473278124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3473278124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/37.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.3471660335 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 342051882 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 08:32:52 PM UTC 24 |
| Finished | Sep 01 08:32:54 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471660335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3471660335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/41.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.76847866 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 510690561 ps |
| CPU time | 2.42 seconds |
| Started | Sep 01 08:33:14 PM UTC 24 |
| Finished | Sep 01 08:33:17 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76847866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.76847866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/48.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.3459025306 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2073540814 ps |
| CPU time | 15.36 seconds |
| Started | Sep 01 08:33:14 PM UTC 24 |
| Finished | Sep 01 08:33:30 PM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3459025306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 48.aon_timer_stress_all_with_rand_reset.3459025306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.1094668025 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 421741580 ps |
| CPU time | 0.67 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:31:52 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094668025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1094668025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.3273208173 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3844883257 ps |
| CPU time | 30.56 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:22 PM UTC 24 |
| Peak memory | 216896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3273208173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 6.aon_timer_stress_all_with_rand_reset.3273208173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3712592754 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 581564198 ps |
| CPU time | 2.37 seconds |
| Started | Sep 01 08:33:21 PM UTC 24 |
| Finished | Sep 01 08:33:24 PM UTC 24 |
| Peak memory | 203196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712592754 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.3712592754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3991492947 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 7245984183 ps |
| CPU time | 4.97 seconds |
| Started | Sep 01 08:33:20 PM UTC 24 |
| Finished | Sep 01 08:33:25 PM UTC 24 |
| Peak memory | 205916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991492947 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.3991492947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.498064005 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 629246357 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:33:19 PM UTC 24 |
| Finished | Sep 01 08:33:22 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498064005 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.498064005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2251458567 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 387251935 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:33:21 PM UTC 24 |
| Finished | Sep 01 08:33:23 PM UTC 24 |
| Peak memory | 207008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2251458567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim er_csr_mem_rw_with_rand_reset.2251458567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.1195604294 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 484782952 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 08:33:20 PM UTC 24 |
| Finished | Sep 01 08:33:23 PM UTC 24 |
| Peak memory | 201392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195604294 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1195604294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.3477023510 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 430839694 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 08:33:18 PM UTC 24 |
| Finished | Sep 01 08:33:21 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477023510 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3477023510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3488953563 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 353231247 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:33:18 PM UTC 24 |
| Finished | Sep 01 08:33:20 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488953563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.3488953563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.885151158 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 403487930 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:33:18 PM UTC 24 |
| Finished | Sep 01 08:33:20 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885151158 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.885151158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4051827738 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2220679482 ps |
| CPU time | 8.89 seconds |
| Started | Sep 01 08:33:21 PM UTC 24 |
| Finished | Sep 01 08:33:31 PM UTC 24 |
| Peak memory | 205424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051827738 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.4051827738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.3889542482 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 304801215 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 08:33:17 PM UTC 24 |
| Finished | Sep 01 08:33:20 PM UTC 24 |
| Peak memory | 206172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889542482 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3889542482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1517938985 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 570605225 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 08:33:24 PM UTC 24 |
| Finished | Sep 01 08:33:27 PM UTC 24 |
| Peak memory | 205380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517938985 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.1517938985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2727021757 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 7052990266 ps |
| CPU time | 12.16 seconds |
| Started | Sep 01 08:33:24 PM UTC 24 |
| Finished | Sep 01 08:33:37 PM UTC 24 |
| Peak memory | 205788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727021757 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.2727021757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.4029888281 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 688643288 ps |
| CPU time | 2.27 seconds |
| Started | Sep 01 08:33:24 PM UTC 24 |
| Finished | Sep 01 08:33:27 PM UTC 24 |
| Peak memory | 203200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029888281 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.4029888281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3755276586 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 413431148 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 08:33:25 PM UTC 24 |
| Finished | Sep 01 08:33:28 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3755276586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim er_csr_mem_rw_with_rand_reset.3755276586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.955278153 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 476455152 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 08:33:24 PM UTC 24 |
| Finished | Sep 01 08:33:27 PM UTC 24 |
| Peak memory | 203388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955278153 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.955278153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.777083028 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 420719240 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:33:22 PM UTC 24 |
| Finished | Sep 01 08:33:24 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777083028 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.777083028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2770115419 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 512341868 ps |
| CPU time | 2.09 seconds |
| Started | Sep 01 08:33:23 PM UTC 24 |
| Finished | Sep 01 08:33:26 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770115419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.2770115419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.775834188 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 269100993 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 08:33:22 PM UTC 24 |
| Finished | Sep 01 08:33:25 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775834188 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.775834188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.1342745213 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1902010060 ps |
| CPU time | 2.97 seconds |
| Started | Sep 01 08:33:22 PM UTC 24 |
| Finished | Sep 01 08:33:26 PM UTC 24 |
| Peak memory | 207028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342745213 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1342745213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2492635600 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4343308782 ps |
| CPU time | 5.27 seconds |
| Started | Sep 01 08:33:22 PM UTC 24 |
| Finished | Sep 01 08:33:28 PM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492635600 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.2492635600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.751723399 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 599582188 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 08:33:41 PM UTC 24 |
| Finished | Sep 01 08:33:44 PM UTC 24 |
| Peak memory | 206052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=751723399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_tim er_csr_mem_rw_with_rand_reset.751723399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.4010291944 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 495115895 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:33:41 PM UTC 24 |
| Finished | Sep 01 08:33:43 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010291944 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4010291944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.1334795279 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 274478807 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 08:33:41 PM UTC 24 |
| Finished | Sep 01 08:33:44 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334795279 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1334795279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2688529087 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2801426471 ps |
| CPU time | 4.71 seconds |
| Started | Sep 01 08:33:41 PM UTC 24 |
| Finished | Sep 01 08:33:47 PM UTC 24 |
| Peak memory | 205236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688529087 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.2688529087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.1391538353 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 291921351 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 08:33:40 PM UTC 24 |
| Finished | Sep 01 08:33:44 PM UTC 24 |
| Peak memory | 206884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391538353 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1391538353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.291930580 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4880454605 ps |
| CPU time | 4.61 seconds |
| Started | Sep 01 08:33:41 PM UTC 24 |
| Finished | Sep 01 08:33:47 PM UTC 24 |
| Peak memory | 206356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291930580 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.291930580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.873440785 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 420674477 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 08:33:43 PM UTC 24 |
| Finished | Sep 01 08:33:45 PM UTC 24 |
| Peak memory | 206948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=873440785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_tim er_csr_mem_rw_with_rand_reset.873440785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.2889146201 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 419821729 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:33:43 PM UTC 24 |
| Finished | Sep 01 08:33:45 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889146201 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2889146201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.4188302420 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 380571021 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 08:33:42 PM UTC 24 |
| Finished | Sep 01 08:33:46 PM UTC 24 |
| Peak memory | 200712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188302420 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4188302420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3206497878 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2037474012 ps |
| CPU time | 2.68 seconds |
| Started | Sep 01 08:33:43 PM UTC 24 |
| Finished | Sep 01 08:33:46 PM UTC 24 |
| Peak memory | 205280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206497878 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.3206497878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.1902646563 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 459148711 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 08:33:41 PM UTC 24 |
| Finished | Sep 01 08:33:46 PM UTC 24 |
| Peak memory | 206748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902646563 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1902646563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4000368701 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4844812068 ps |
| CPU time | 4.61 seconds |
| Started | Sep 01 08:33:42 PM UTC 24 |
| Finished | Sep 01 08:33:48 PM UTC 24 |
| Peak memory | 205972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000368701 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.4000368701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2170086622 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 561368645 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 08:33:44 PM UTC 24 |
| Finished | Sep 01 08:33:47 PM UTC 24 |
| Peak memory | 205328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2170086622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_ti mer_csr_mem_rw_with_rand_reset.2170086622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.512709391 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 367823697 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 08:33:44 PM UTC 24 |
| Finished | Sep 01 08:33:47 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512709391 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.512709391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.3732026969 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 460037127 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:33:43 PM UTC 24 |
| Finished | Sep 01 08:33:45 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732026969 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3732026969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1666873369 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 988314656 ps |
| CPU time | 2.84 seconds |
| Started | Sep 01 08:33:44 PM UTC 24 |
| Finished | Sep 01 08:33:48 PM UTC 24 |
| Peak memory | 203448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666873369 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.1666873369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3552567246 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 977158596 ps |
| CPU time | 4.24 seconds |
| Started | Sep 01 08:33:43 PM UTC 24 |
| Finished | Sep 01 08:33:48 PM UTC 24 |
| Peak memory | 207072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552567246 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3552567246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.892738566 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 7803514405 ps |
| CPU time | 6.57 seconds |
| Started | Sep 01 08:33:43 PM UTC 24 |
| Finished | Sep 01 08:33:50 PM UTC 24 |
| Peak memory | 206876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892738566 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.892738566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3582965564 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 508010177 ps |
| CPU time | 2.7 seconds |
| Started | Sep 01 08:33:45 PM UTC 24 |
| Finished | Sep 01 08:33:49 PM UTC 24 |
| Peak memory | 205340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3582965564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti mer_csr_mem_rw_with_rand_reset.3582965564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1498233535 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 350357120 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 08:33:44 PM UTC 24 |
| Finished | Sep 01 08:33:47 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498233535 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1498233535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2787909478 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 880434072 ps |
| CPU time | 3.4 seconds |
| Started | Sep 01 08:33:44 PM UTC 24 |
| Finished | Sep 01 08:33:49 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787909478 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.2787909478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3709580201 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 402574200 ps |
| CPU time | 4.38 seconds |
| Started | Sep 01 08:33:44 PM UTC 24 |
| Finished | Sep 01 08:33:50 PM UTC 24 |
| Peak memory | 206964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709580201 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3709580201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3362894836 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 8220262179 ps |
| CPU time | 9.12 seconds |
| Started | Sep 01 08:33:44 PM UTC 24 |
| Finished | Sep 01 08:33:54 PM UTC 24 |
| Peak memory | 207076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362894836 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.3362894836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2168626842 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 533053244 ps |
| CPU time | 2.57 seconds |
| Started | Sep 01 08:33:46 PM UTC 24 |
| Finished | Sep 01 08:33:49 PM UTC 24 |
| Peak memory | 205624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2168626842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_ti mer_csr_mem_rw_with_rand_reset.2168626842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.484259726 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 440635973 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:33:46 PM UTC 24 |
| Finished | Sep 01 08:33:48 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484259726 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.484259726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.720280742 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 413307336 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:33:46 PM UTC 24 |
| Finished | Sep 01 08:33:48 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720280742 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.720280742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4255158238 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1250630148 ps |
| CPU time | 3.1 seconds |
| Started | Sep 01 08:33:46 PM UTC 24 |
| Finished | Sep 01 08:33:50 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255158238 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.4255158238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.2849204407 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 538299758 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 08:33:45 PM UTC 24 |
| Finished | Sep 01 08:33:49 PM UTC 24 |
| Peak memory | 206864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849204407 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2849204407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1355728649 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 4437374930 ps |
| CPU time | 6.37 seconds |
| Started | Sep 01 08:33:45 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 206576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355728649 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.1355728649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2099502014 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 328020315 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:33:48 PM UTC 24 |
| Finished | Sep 01 08:33:50 PM UTC 24 |
| Peak memory | 205328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2099502014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti mer_csr_mem_rw_with_rand_reset.2099502014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.2105519393 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 492033340 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:33:47 PM UTC 24 |
| Finished | Sep 01 08:33:49 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105519393 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2105519393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.3303011704 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 525453091 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 08:33:47 PM UTC 24 |
| Finished | Sep 01 08:33:49 PM UTC 24 |
| Peak memory | 201840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303011704 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3303011704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2225565843 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2129921423 ps |
| CPU time | 2.51 seconds |
| Started | Sep 01 08:33:47 PM UTC 24 |
| Finished | Sep 01 08:33:50 PM UTC 24 |
| Peak memory | 205356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225565843 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.2225565843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.4273044599 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1160112133 ps |
| CPU time | 3.91 seconds |
| Started | Sep 01 08:33:46 PM UTC 24 |
| Finished | Sep 01 08:33:51 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273044599 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4273044599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.267728532 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 4674367389 ps |
| CPU time | 3.79 seconds |
| Started | Sep 01 08:33:47 PM UTC 24 |
| Finished | Sep 01 08:33:52 PM UTC 24 |
| Peak memory | 205820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267728532 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.267728532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.917089399 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 463449697 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 08:33:48 PM UTC 24 |
| Finished | Sep 01 08:33:50 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=917089399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_tim er_csr_mem_rw_with_rand_reset.917089399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.429689150 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 342750225 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 08:33:48 PM UTC 24 |
| Finished | Sep 01 08:33:51 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429689150 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.429689150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.3067004361 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 518107859 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:33:48 PM UTC 24 |
| Finished | Sep 01 08:33:50 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067004361 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3067004361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1775334043 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2593843096 ps |
| CPU time | 6.15 seconds |
| Started | Sep 01 08:33:48 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775334043 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.1775334043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.1412652042 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 581550254 ps |
| CPU time | 2.78 seconds |
| Started | Sep 01 08:33:48 PM UTC 24 |
| Finished | Sep 01 08:33:52 PM UTC 24 |
| Peak memory | 207212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412652042 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1412652042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3341843646 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 410240280 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 08:33:49 PM UTC 24 |
| Finished | Sep 01 08:33:52 PM UTC 24 |
| Peak memory | 203944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3341843646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti mer_csr_mem_rw_with_rand_reset.3341843646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.3490782633 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 344179676 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:33:49 PM UTC 24 |
| Finished | Sep 01 08:33:51 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490782633 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3490782633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.1958441670 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 447384403 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 08:33:49 PM UTC 24 |
| Finished | Sep 01 08:33:52 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958441670 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1958441670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.792624333 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1448621861 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 08:33:49 PM UTC 24 |
| Finished | Sep 01 08:33:52 PM UTC 24 |
| Peak memory | 201964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792624333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.792624333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.2157215854 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 440819634 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 08:33:48 PM UTC 24 |
| Finished | Sep 01 08:33:51 PM UTC 24 |
| Peak memory | 206884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157215854 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2157215854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1860894304 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4128589215 ps |
| CPU time | 2.6 seconds |
| Started | Sep 01 08:33:49 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 206772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860894304 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.1860894304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.828223413 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 368593827 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:33:50 PM UTC 24 |
| Finished | Sep 01 08:33:52 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=828223413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_tim er_csr_mem_rw_with_rand_reset.828223413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.1035268523 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 530253811 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:33:50 PM UTC 24 |
| Finished | Sep 01 08:33:52 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035268523 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1035268523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.3819589337 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 325598096 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 08:33:50 PM UTC 24 |
| Finished | Sep 01 08:33:52 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819589337 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3819589337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4266287437 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2441234512 ps |
| CPU time | 3.29 seconds |
| Started | Sep 01 08:33:50 PM UTC 24 |
| Finished | Sep 01 08:33:54 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266287437 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.4266287437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.3392615169 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 514083137 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 08:33:50 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 205796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392615169 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3392615169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4109552154 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 7642869446 ps |
| CPU time | 4.84 seconds |
| Started | Sep 01 08:33:50 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 206980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109552154 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.4109552154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2624188638 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 352114132 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:54 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2624188638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti mer_csr_mem_rw_with_rand_reset.2624188638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.2196267826 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 517833491 ps |
| CPU time | 1.92 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:54 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196267826 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2196267826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.1264567747 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 380266414 ps |
| CPU time | 0.87 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 199696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264567747 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1264567747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3792984840 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1150119416 ps |
| CPU time | 3.2 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792984840 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.3792984840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.548892624 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 473561417 ps |
| CPU time | 2.8 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548892624 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.548892624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1188232544 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4186577975 ps |
| CPU time | 3.55 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 206228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188232544 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.1188232544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2451574525 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 669213798 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 08:33:29 PM UTC 24 |
| Finished | Sep 01 08:33:32 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451574525 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.2451574525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2913144824 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 11851863762 ps |
| CPU time | 21.05 seconds |
| Started | Sep 01 08:33:29 PM UTC 24 |
| Finished | Sep 01 08:33:51 PM UTC 24 |
| Peak memory | 205856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913144824 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.2913144824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.901196143 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1311725587 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 08:33:28 PM UTC 24 |
| Finished | Sep 01 08:33:30 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901196143 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.901196143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1087850084 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 515481526 ps |
| CPU time | 2.73 seconds |
| Started | Sep 01 08:33:29 PM UTC 24 |
| Finished | Sep 01 08:33:33 PM UTC 24 |
| Peak memory | 205364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1087850084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_tim er_csr_mem_rw_with_rand_reset.1087850084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1897093327 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 402304004 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:33:29 PM UTC 24 |
| Finished | Sep 01 08:33:31 PM UTC 24 |
| Peak memory | 201956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897093327 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1897093327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.515625720 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 305800176 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 08:33:27 PM UTC 24 |
| Finished | Sep 01 08:33:29 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515625720 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.515625720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2972416936 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 369967532 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 08:33:27 PM UTC 24 |
| Finished | Sep 01 08:33:30 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972416936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.2972416936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.101527301 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 332192864 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 08:33:27 PM UTC 24 |
| Finished | Sep 01 08:33:29 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101527301 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.101527301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1678022134 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1105387349 ps |
| CPU time | 4.77 seconds |
| Started | Sep 01 08:33:29 PM UTC 24 |
| Finished | Sep 01 08:33:35 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678022134 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.1678022134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3725414333 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 335438907 ps |
| CPU time | 2.13 seconds |
| Started | Sep 01 08:33:25 PM UTC 24 |
| Finished | Sep 01 08:33:29 PM UTC 24 |
| Peak memory | 207000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725414333 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3725414333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2537714040 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4254224340 ps |
| CPU time | 3.34 seconds |
| Started | Sep 01 08:33:26 PM UTC 24 |
| Finished | Sep 01 08:33:31 PM UTC 24 |
| Peak memory | 206816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537714040 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.2537714040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.1828064848 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 428403606 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828064848 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1828064848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/20.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.1108772563 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 453378274 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:54 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108772563 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1108772563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/21.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3042570178 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 272148951 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042570178 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3042570178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/22.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2820311194 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 408819268 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:54 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820311194 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2820311194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/23.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.3750811988 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 353086637 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:54 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750811988 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3750811988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/24.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.2265335463 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 322273609 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265335463 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2265335463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/25.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.2574266244 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 290353795 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:33:51 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574266244 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2574266244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/26.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.192924483 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 472014817 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 08:33:52 PM UTC 24 |
| Finished | Sep 01 08:33:56 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192924483 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.192924483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/27.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.1380324389 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 347525129 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380324389 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1380324389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/28.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.3286089129 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 504821500 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286089129 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3286089129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/29.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1136648624 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 513402460 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 08:33:32 PM UTC 24 |
| Finished | Sep 01 08:33:35 PM UTC 24 |
| Peak memory | 203496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136648624 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.1136648624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2921326606 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 7214213436 ps |
| CPU time | 16.76 seconds |
| Started | Sep 01 08:33:30 PM UTC 24 |
| Finished | Sep 01 08:33:49 PM UTC 24 |
| Peak memory | 205856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921326606 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.2921326606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1785173144 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 828854584 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 08:33:30 PM UTC 24 |
| Finished | Sep 01 08:33:33 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785173144 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.1785173144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.971074176 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 514476675 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 08:33:32 PM UTC 24 |
| Finished | Sep 01 08:33:35 PM UTC 24 |
| Peak memory | 206952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=971074176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_time r_csr_mem_rw_with_rand_reset.971074176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.296892482 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 471954446 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:33:30 PM UTC 24 |
| Finished | Sep 01 08:33:33 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296892482 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.296892482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3847599486 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 420041275 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 08:33:30 PM UTC 24 |
| Finished | Sep 01 08:33:33 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847599486 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3847599486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3806733953 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 322813407 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 08:33:30 PM UTC 24 |
| Finished | Sep 01 08:33:32 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806733953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.3806733953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.3929779545 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 331493809 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 08:33:30 PM UTC 24 |
| Finished | Sep 01 08:33:33 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929779545 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.3929779545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.419108895 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1696168030 ps |
| CPU time | 2.18 seconds |
| Started | Sep 01 08:33:32 PM UTC 24 |
| Finished | Sep 01 08:33:35 PM UTC 24 |
| Peak memory | 203616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419108895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.419108895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.982514696 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 499833953 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 08:33:29 PM UTC 24 |
| Finished | Sep 01 08:33:32 PM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982514696 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.982514696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3869755796 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4465646590 ps |
| CPU time | 3.47 seconds |
| Started | Sep 01 08:33:29 PM UTC 24 |
| Finished | Sep 01 08:33:34 PM UTC 24 |
| Peak memory | 206160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869755796 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.3869755796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.949577686 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 495426572 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949577686 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.949577686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/30.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.1749699180 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 276512651 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749699180 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1749699180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/31.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.2463527736 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 324256458 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463527736 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2463527736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/32.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.1516338457 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 472206991 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516338457 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1516338457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/33.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.1056307423 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 569625173 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056307423 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1056307423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/34.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.3821168250 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 478757144 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821168250 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3821168250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/35.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3452811472 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 457789442 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452811472 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3452811472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/36.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.2180698936 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 406686865 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180698936 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2180698936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/37.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.2859785438 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 457598988 ps |
| CPU time | 0.88 seconds |
| Started | Sep 01 08:33:53 PM UTC 24 |
| Finished | Sep 01 08:33:55 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859785438 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2859785438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/38.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.398028023 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 326207053 ps |
| CPU time | 0.76 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:56 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398028023 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.398028023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/39.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1435658961 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 665502031 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 08:33:34 PM UTC 24 |
| Finished | Sep 01 08:33:37 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435658961 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.1435658961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3903945846 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 7332627513 ps |
| CPU time | 19.01 seconds |
| Started | Sep 01 08:33:33 PM UTC 24 |
| Finished | Sep 01 08:33:53 PM UTC 24 |
| Peak memory | 205980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903945846 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.3903945846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1300433504 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 663053397 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 08:33:33 PM UTC 24 |
| Finished | Sep 01 08:33:36 PM UTC 24 |
| Peak memory | 199736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300433504 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.1300433504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.940439248 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 391047158 ps |
| CPU time | 2 seconds |
| Started | Sep 01 08:33:34 PM UTC 24 |
| Finished | Sep 01 08:33:37 PM UTC 24 |
| Peak memory | 206016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=940439248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_time r_csr_mem_rw_with_rand_reset.940439248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.2140893555 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 535876984 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 08:33:33 PM UTC 24 |
| Finished | Sep 01 08:33:35 PM UTC 24 |
| Peak memory | 201956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140893555 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2140893555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.1458937541 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 406488995 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:33:33 PM UTC 24 |
| Finished | Sep 01 08:33:35 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458937541 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1458937541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2842825008 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 358790744 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 08:33:33 PM UTC 24 |
| Finished | Sep 01 08:33:35 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842825008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.2842825008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2734917292 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 524693535 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 08:33:33 PM UTC 24 |
| Finished | Sep 01 08:33:35 PM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734917292 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.2734917292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1011827153 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1957246356 ps |
| CPU time | 2.49 seconds |
| Started | Sep 01 08:33:34 PM UTC 24 |
| Finished | Sep 01 08:33:38 PM UTC 24 |
| Peak memory | 205432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011827153 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.1011827153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.894493055 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 538166935 ps |
| CPU time | 2.57 seconds |
| Started | Sep 01 08:33:32 PM UTC 24 |
| Finished | Sep 01 08:33:35 PM UTC 24 |
| Peak memory | 207000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894493055 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.894493055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.366590871 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4274811164 ps |
| CPU time | 3.16 seconds |
| Started | Sep 01 08:33:32 PM UTC 24 |
| Finished | Sep 01 08:33:36 PM UTC 24 |
| Peak memory | 206812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366590871 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.366590871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.1847823151 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 334306183 ps |
| CPU time | 0.98 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:57 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847823151 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1847823151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/40.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.2641476202 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 518555679 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:57 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641476202 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2641476202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/41.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.4040657782 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 380856688 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:57 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040657782 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.4040657782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/42.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.1191268559 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 498773261 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:57 PM UTC 24 |
| Peak memory | 199764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191268559 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1191268559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/43.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1477059429 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 349842613 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:57 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477059429 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1477059429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/44.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.3854305006 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 308069900 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:57 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854305006 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3854305006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/45.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.1949138955 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 389596179 ps |
| CPU time | 0.72 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:57 PM UTC 24 |
| Peak memory | 201528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949138955 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1949138955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/46.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.315612529 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 278431895 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:57 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315612529 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.315612529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/47.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.2974285062 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 361643925 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:57 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974285062 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2974285062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/48.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.3992501669 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 277256017 ps |
| CPU time | 0.81 seconds |
| Started | Sep 01 08:33:54 PM UTC 24 |
| Finished | Sep 01 08:33:57 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992501669 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3992501669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/49.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1395475380 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 510396747 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 08:33:36 PM UTC 24 |
| Finished | Sep 01 08:33:40 PM UTC 24 |
| Peak memory | 205504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1395475380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_tim er_csr_mem_rw_with_rand_reset.1395475380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.2567928169 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 468827912 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 08:33:36 PM UTC 24 |
| Finished | Sep 01 08:33:38 PM UTC 24 |
| Peak memory | 201896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567928169 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2567928169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.3216634978 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 311982878 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:33:34 PM UTC 24 |
| Finished | Sep 01 08:33:37 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216634978 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3216634978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1111880233 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2688957155 ps |
| CPU time | 4.81 seconds |
| Started | Sep 01 08:33:36 PM UTC 24 |
| Finished | Sep 01 08:33:42 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111880233 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.1111880233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.4189752857 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 478539764 ps |
| CPU time | 2.13 seconds |
| Started | Sep 01 08:33:34 PM UTC 24 |
| Finished | Sep 01 08:33:38 PM UTC 24 |
| Peak memory | 206816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189752857 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.4189752857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2129762263 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 8054208741 ps |
| CPU time | 10.82 seconds |
| Started | Sep 01 08:33:34 PM UTC 24 |
| Finished | Sep 01 08:33:47 PM UTC 24 |
| Peak memory | 207148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129762263 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.2129762263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3144432991 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 478047336 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:33:37 PM UTC 24 |
| Finished | Sep 01 08:33:39 PM UTC 24 |
| Peak memory | 204724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3144432991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_tim er_csr_mem_rw_with_rand_reset.3144432991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.679719278 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 437549028 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 08:33:36 PM UTC 24 |
| Finished | Sep 01 08:33:39 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679719278 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.679719278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2037028406 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 606675365 ps |
| CPU time | 0.89 seconds |
| Started | Sep 01 08:33:36 PM UTC 24 |
| Finished | Sep 01 08:33:38 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037028406 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2037028406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.808988781 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1144632621 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 08:33:36 PM UTC 24 |
| Finished | Sep 01 08:33:38 PM UTC 24 |
| Peak memory | 201964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808988781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.808988781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.4082497162 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1266946200 ps |
| CPU time | 2.73 seconds |
| Started | Sep 01 08:33:36 PM UTC 24 |
| Finished | Sep 01 08:33:40 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082497162 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4082497162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3768911131 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4766215486 ps |
| CPU time | 6.72 seconds |
| Started | Sep 01 08:33:36 PM UTC 24 |
| Finished | Sep 01 08:33:44 PM UTC 24 |
| Peak memory | 206824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768911131 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.3768911131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3825948194 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 519972392 ps |
| CPU time | 2.73 seconds |
| Started | Sep 01 08:33:38 PM UTC 24 |
| Finished | Sep 01 08:33:42 PM UTC 24 |
| Peak memory | 205852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3825948194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim er_csr_mem_rw_with_rand_reset.3825948194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.903427484 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 404626894 ps |
| CPU time | 2.03 seconds |
| Started | Sep 01 08:33:37 PM UTC 24 |
| Finished | Sep 01 08:33:40 PM UTC 24 |
| Peak memory | 203324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903427484 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.903427484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.1169409387 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 488042445 ps |
| CPU time | 2.28 seconds |
| Started | Sep 01 08:33:37 PM UTC 24 |
| Finished | Sep 01 08:33:40 PM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169409387 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1169409387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3486981051 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 789047154 ps |
| CPU time | 2.71 seconds |
| Started | Sep 01 08:33:37 PM UTC 24 |
| Finished | Sep 01 08:33:41 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486981051 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.3486981051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.24145736 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 628690247 ps |
| CPU time | 3.68 seconds |
| Started | Sep 01 08:33:37 PM UTC 24 |
| Finished | Sep 01 08:33:42 PM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24145736 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.24145736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4188742243 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 8220006801 ps |
| CPU time | 4.49 seconds |
| Started | Sep 01 08:33:37 PM UTC 24 |
| Finished | Sep 01 08:33:43 PM UTC 24 |
| Peak memory | 207396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188742243 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.4188742243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1393080054 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 381823399 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 08:33:39 PM UTC 24 |
| Finished | Sep 01 08:33:41 PM UTC 24 |
| Peak memory | 205572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1393080054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim er_csr_mem_rw_with_rand_reset.1393080054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.3836586902 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 405820860 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:33:38 PM UTC 24 |
| Finished | Sep 01 08:33:40 PM UTC 24 |
| Peak memory | 201896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836586902 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3836586902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.4029508122 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 419846780 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 08:33:38 PM UTC 24 |
| Finished | Sep 01 08:33:40 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029508122 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.4029508122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.235059457 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2016912689 ps |
| CPU time | 6.1 seconds |
| Started | Sep 01 08:33:39 PM UTC 24 |
| Finished | Sep 01 08:33:46 PM UTC 24 |
| Peak memory | 205392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235059457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.235059457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.3517934563 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 415595966 ps |
| CPU time | 3.06 seconds |
| Started | Sep 01 08:33:38 PM UTC 24 |
| Finished | Sep 01 08:33:42 PM UTC 24 |
| Peak memory | 207164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517934563 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3517934563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.726784248 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4229931570 ps |
| CPU time | 2.44 seconds |
| Started | Sep 01 08:33:38 PM UTC 24 |
| Finished | Sep 01 08:33:42 PM UTC 24 |
| Peak memory | 206488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726784248 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.726784248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1393702427 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 413741055 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 08:33:40 PM UTC 24 |
| Finished | Sep 01 08:33:42 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1393702427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_tim er_csr_mem_rw_with_rand_reset.1393702427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.3054017734 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 449066076 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 08:33:40 PM UTC 24 |
| Finished | Sep 01 08:33:42 PM UTC 24 |
| Peak memory | 201840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054017734 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3054017734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.1988315336 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 376022608 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 08:33:40 PM UTC 24 |
| Finished | Sep 01 08:33:42 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988315336 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1988315336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1611792384 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2189104757 ps |
| CPU time | 3.47 seconds |
| Started | Sep 01 08:33:40 PM UTC 24 |
| Finished | Sep 01 08:33:44 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611792384 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.1611792384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1682113547 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 378162025 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 08:33:40 PM UTC 24 |
| Finished | Sep 01 08:33:43 PM UTC 24 |
| Peak memory | 206984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682113547 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1682113547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3931153541 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4412130134 ps |
| CPU time | 7.54 seconds |
| Started | Sep 01 08:33:40 PM UTC 24 |
| Finished | Sep 01 08:33:48 PM UTC 24 |
| Peak memory | 206768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931153541 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.3931153541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.86025426 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 36306310141 ps |
| CPU time | 55.97 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:32:42 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86025426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.86025426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1902972618 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 485675349 ps |
| CPU time | 0.68 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:46 PM UTC 24 |
| Peak memory | 199988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902972618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1902972618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/0.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.3456176141 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 40455808110 ps |
| CPU time | 29.17 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:32:16 PM UTC 24 |
| Peak memory | 200548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456176141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3456176141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.179825292 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7956814419 ps |
| CPU time | 5.48 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:52 PM UTC 24 |
| Peak memory | 231368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179825292 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.179825292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.1320122026 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 583007719 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:47 PM UTC 24 |
| Peak memory | 199196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320122026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1320122026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.3125376038 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2411627860 ps |
| CPU time | 14.55 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:32:01 PM UTC 24 |
| Peak memory | 216280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3125376038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.aon_timer_stress_all_with_rand_reset.3125376038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.624406782 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 19518699030 ps |
| CPU time | 30.82 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:40 PM UTC 24 |
| Peak memory | 200820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624406782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.624406782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.113488648 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 467934251 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:11 PM UTC 24 |
| Peak memory | 199068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113488648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.113488648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/10.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.1505589695 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 981666561 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:10 PM UTC 24 |
| Peak memory | 199300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505589695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1505589695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.3500928079 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 462568207 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:10 PM UTC 24 |
| Peak memory | 199364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500928079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3500928079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/11.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.1476550695 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 35010327663 ps |
| CPU time | 77.18 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:33:27 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476550695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1476550695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.3003340155 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 484966289 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:11 PM UTC 24 |
| Peak memory | 199424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003340155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3003340155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/12.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.2413102828 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 51027367371 ps |
| CPU time | 65.93 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:33:16 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413102828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2413102828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.2255505346 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 478591418 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 08:31:51 PM UTC 24 |
| Finished | Sep 01 08:32:10 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255505346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2255505346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/13.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.2339932215 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 45052208016 ps |
| CPU time | 90.84 seconds |
| Started | Sep 01 08:31:53 PM UTC 24 |
| Finished | Sep 01 08:33:32 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339932215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2339932215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.2393705041 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 606912702 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 08:31:53 PM UTC 24 |
| Finished | Sep 01 08:31:58 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393705041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2393705041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/14.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.3042262836 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 576991036 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 08:31:55 PM UTC 24 |
| Finished | Sep 01 08:31:58 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042262836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3042262836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.1264879393 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 22886794798 ps |
| CPU time | 10.38 seconds |
| Started | Sep 01 08:31:55 PM UTC 24 |
| Finished | Sep 01 08:32:07 PM UTC 24 |
| Peak memory | 200696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264879393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1264879393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.1430440537 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 428299089 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:31:54 PM UTC 24 |
| Finished | Sep 01 08:31:58 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430440537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1430440537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/15.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.3960565842 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 7990992402 ps |
| CPU time | 9.16 seconds |
| Started | Sep 01 08:31:59 PM UTC 24 |
| Finished | Sep 01 08:32:16 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960565842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3960565842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.2764510607 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 469478049 ps |
| CPU time | 0.75 seconds |
| Started | Sep 01 08:31:59 PM UTC 24 |
| Finished | Sep 01 08:32:08 PM UTC 24 |
| Peak memory | 199272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764510607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2764510607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.4038514884 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1749760654 ps |
| CPU time | 8.42 seconds |
| Started | Sep 01 08:31:59 PM UTC 24 |
| Finished | Sep 01 08:32:16 PM UTC 24 |
| Peak memory | 201204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4038514884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 16.aon_timer_stress_all_with_rand_reset.4038514884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.2231166147 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 13917434586 ps |
| CPU time | 8.1 seconds |
| Started | Sep 01 08:32:03 PM UTC 24 |
| Finished | Sep 01 08:32:15 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231166147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2231166147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.2481714851 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 416259090 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 08:32:01 PM UTC 24 |
| Finished | Sep 01 08:32:11 PM UTC 24 |
| Peak memory | 199284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481714851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2481714851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/17.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.2732365688 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 37501749609 ps |
| CPU time | 19.32 seconds |
| Started | Sep 01 08:32:06 PM UTC 24 |
| Finished | Sep 01 08:32:27 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732365688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2732365688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.2846676994 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 414315337 ps |
| CPU time | 0.79 seconds |
| Started | Sep 01 08:32:06 PM UTC 24 |
| Finished | Sep 01 08:32:08 PM UTC 24 |
| Peak memory | 199088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846676994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2846676994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/18.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.2971760793 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 26596565784 ps |
| CPU time | 37.45 seconds |
| Started | Sep 01 08:32:08 PM UTC 24 |
| Finished | Sep 01 08:32:47 PM UTC 24 |
| Peak memory | 199956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971760793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2971760793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.1445178875 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 461917850 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 08:32:08 PM UTC 24 |
| Finished | Sep 01 08:32:11 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445178875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1445178875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/19.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.3302742424 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 60211369101 ps |
| CPU time | 84.95 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:33:12 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302742424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3302742424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.1017146131 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8451968200 ps |
| CPU time | 3.46 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:49 PM UTC 24 |
| Peak memory | 231380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017146131 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1017146131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.2238627725 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 411655806 ps |
| CPU time | 0.82 seconds |
| Started | Sep 01 08:31:44 PM UTC 24 |
| Finished | Sep 01 08:31:47 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238627725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2238627725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/2.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.2737531226 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 39511962533 ps |
| CPU time | 16.63 seconds |
| Started | Sep 01 08:32:10 PM UTC 24 |
| Finished | Sep 01 08:32:28 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737531226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2737531226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/20.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.4276434565 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 446172808 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:32:10 PM UTC 24 |
| Finished | Sep 01 08:32:12 PM UTC 24 |
| Peak memory | 198796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276434565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.4276434565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/20.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.725002384 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 49700351992 ps |
| CPU time | 39.78 seconds |
| Started | Sep 01 08:32:12 PM UTC 24 |
| Finished | Sep 01 08:32:53 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725002384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.725002384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/21.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.3133179375 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 512515896 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 08:32:12 PM UTC 24 |
| Finished | Sep 01 08:32:15 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133179375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3133179375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/21.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.1644849814 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 13835147090 ps |
| CPU time | 13.71 seconds |
| Started | Sep 01 08:32:12 PM UTC 24 |
| Finished | Sep 01 08:32:27 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644849814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1644849814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/22.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.2789032177 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 553117971 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 08:32:12 PM UTC 24 |
| Finished | Sep 01 08:32:14 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789032177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2789032177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/22.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.887165926 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 37668624357 ps |
| CPU time | 62.12 seconds |
| Started | Sep 01 08:32:13 PM UTC 24 |
| Finished | Sep 01 08:33:17 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887165926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.887165926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/23.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.666889815 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 450782824 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 08:32:12 PM UTC 24 |
| Finished | Sep 01 08:32:16 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666889815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.666889815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/23.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.1672553213 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 14757323941 ps |
| CPU time | 26.9 seconds |
| Started | Sep 01 08:32:16 PM UTC 24 |
| Finished | Sep 01 08:32:44 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672553213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1672553213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/24.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.387620999 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 499087808 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 08:32:16 PM UTC 24 |
| Finished | Sep 01 08:32:18 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387620999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.387620999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/24.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.1008810359 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 481416732 ps |
| CPU time | 2.5 seconds |
| Started | Sep 01 08:32:17 PM UTC 24 |
| Finished | Sep 01 08:32:21 PM UTC 24 |
| Peak memory | 200600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008810359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1008810359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/25.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.1022430568 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 41166259711 ps |
| CPU time | 34.64 seconds |
| Started | Sep 01 08:32:17 PM UTC 24 |
| Finished | Sep 01 08:32:53 PM UTC 24 |
| Peak memory | 200652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022430568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1022430568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/25.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.3884167573 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 434191103 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 08:32:17 PM UTC 24 |
| Finished | Sep 01 08:32:19 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884167573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3884167573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/25.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.2391766280 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 30280487203 ps |
| CPU time | 12.4 seconds |
| Started | Sep 01 08:32:18 PM UTC 24 |
| Finished | Sep 01 08:32:32 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391766280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2391766280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/26.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.268640160 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 490242743 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:32:17 PM UTC 24 |
| Finished | Sep 01 08:32:20 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268640160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.268640160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/26.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.1655092836 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 28749625254 ps |
| CPU time | 24.82 seconds |
| Started | Sep 01 08:32:19 PM UTC 24 |
| Finished | Sep 01 08:32:46 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655092836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1655092836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/27.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.586016480 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 452909078 ps |
| CPU time | 2.45 seconds |
| Started | Sep 01 08:32:19 PM UTC 24 |
| Finished | Sep 01 08:32:23 PM UTC 24 |
| Peak memory | 200568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586016480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.586016480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/27.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.2785336069 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 10448673000 ps |
| CPU time | 7.59 seconds |
| Started | Sep 01 08:32:22 PM UTC 24 |
| Finished | Sep 01 08:32:30 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785336069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2785336069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/28.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.439345332 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 422869350 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:32:21 PM UTC 24 |
| Finished | Sep 01 08:32:23 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439345332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.439345332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/28.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.250645687 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 6145937774 ps |
| CPU time | 2.36 seconds |
| Started | Sep 01 08:32:24 PM UTC 24 |
| Finished | Sep 01 08:32:28 PM UTC 24 |
| Peak memory | 200548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250645687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.250645687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/29.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.1440322830 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 448790596 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 08:32:24 PM UTC 24 |
| Finished | Sep 01 08:32:26 PM UTC 24 |
| Peak memory | 198944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440322830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1440322830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/29.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.3810934050 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10571513221 ps |
| CPU time | 14.57 seconds |
| Started | Sep 01 08:31:45 PM UTC 24 |
| Finished | Sep 01 08:32:00 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810934050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3810934050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.3248031064 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 7964625076 ps |
| CPU time | 11.34 seconds |
| Started | Sep 01 08:31:45 PM UTC 24 |
| Finished | Sep 01 08:31:57 PM UTC 24 |
| Peak memory | 231436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248031064 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3248031064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.140045483 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 25075615697 ps |
| CPU time | 63.11 seconds |
| Started | Sep 01 08:32:27 PM UTC 24 |
| Finished | Sep 01 08:33:32 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140045483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.140045483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/30.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.651449685 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 347442047 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:32:27 PM UTC 24 |
| Finished | Sep 01 08:32:30 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651449685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.651449685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/30.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.2301413858 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 8169983144 ps |
| CPU time | 5.48 seconds |
| Started | Sep 01 08:32:29 PM UTC 24 |
| Finished | Sep 01 08:32:35 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301413858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2301413858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/31.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.3605852550 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 394914726 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 08:32:29 PM UTC 24 |
| Finished | Sep 01 08:32:31 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605852550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3605852550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/31.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.2814960802 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 53741700970 ps |
| CPU time | 108.08 seconds |
| Started | Sep 01 08:32:31 PM UTC 24 |
| Finished | Sep 01 08:34:22 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814960802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2814960802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/32.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.1675738063 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 457116532 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:32:31 PM UTC 24 |
| Finished | Sep 01 08:32:33 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675738063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1675738063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/32.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.1640262074 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1454993986 ps |
| CPU time | 10.36 seconds |
| Started | Sep 01 08:32:32 PM UTC 24 |
| Finished | Sep 01 08:32:44 PM UTC 24 |
| Peak memory | 216368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1640262074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 32.aon_timer_stress_all_with_rand_reset.1640262074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.2204768111 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 481448572 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 08:32:34 PM UTC 24 |
| Finished | Sep 01 08:32:37 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204768111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2204768111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/33.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.2231218248 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 28425129641 ps |
| CPU time | 53.28 seconds |
| Started | Sep 01 08:32:33 PM UTC 24 |
| Finished | Sep 01 08:33:28 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231218248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2231218248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/33.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.319477023 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 464328864 ps |
| CPU time | 2.21 seconds |
| Started | Sep 01 08:32:33 PM UTC 24 |
| Finished | Sep 01 08:32:37 PM UTC 24 |
| Peak memory | 200568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319477023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.319477023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/33.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.2583914077 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 9435082630 ps |
| CPU time | 2.54 seconds |
| Started | Sep 01 08:32:36 PM UTC 24 |
| Finished | Sep 01 08:32:40 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583914077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2583914077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/34.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.4104746645 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 446708600 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 08:32:36 PM UTC 24 |
| Finished | Sep 01 08:32:40 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104746645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4104746645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/34.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.1913584146 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 12450763890 ps |
| CPU time | 28.09 seconds |
| Started | Sep 01 08:32:39 PM UTC 24 |
| Finished | Sep 01 08:33:08 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913584146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1913584146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/35.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.3330314212 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 486194913 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 08:32:38 PM UTC 24 |
| Finished | Sep 01 08:32:40 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330314212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3330314212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/35.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.3497133950 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 16071297394 ps |
| CPU time | 18.52 seconds |
| Started | Sep 01 08:32:41 PM UTC 24 |
| Finished | Sep 01 08:33:01 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497133950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3497133950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/36.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.1775093876 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 417409825 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 08:32:41 PM UTC 24 |
| Finished | Sep 01 08:32:43 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775093876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1775093876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/36.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.1967485202 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 33141904509 ps |
| CPU time | 29.34 seconds |
| Started | Sep 01 08:32:44 PM UTC 24 |
| Finished | Sep 01 08:33:15 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967485202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1967485202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/37.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.4077587297 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 388722171 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 08:32:43 PM UTC 24 |
| Finished | Sep 01 08:32:45 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077587297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.4077587297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/37.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.240806144 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 27262033563 ps |
| CPU time | 38.1 seconds |
| Started | Sep 01 08:32:46 PM UTC 24 |
| Finished | Sep 01 08:33:25 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240806144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.240806144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/38.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.199005099 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 385398271 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 08:32:46 PM UTC 24 |
| Finished | Sep 01 08:32:48 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199005099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.199005099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/38.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.2159233214 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1073927249 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 08:32:47 PM UTC 24 |
| Finished | Sep 01 08:32:50 PM UTC 24 |
| Peak memory | 205440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2159233214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 38.aon_timer_stress_all_with_rand_reset.2159233214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.2129007018 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 54929215532 ps |
| CPU time | 104.49 seconds |
| Started | Sep 01 08:32:48 PM UTC 24 |
| Finished | Sep 01 08:34:35 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129007018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2129007018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/39.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.2458973516 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 499402228 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 08:32:48 PM UTC 24 |
| Finished | Sep 01 08:32:50 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458973516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2458973516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/39.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.134070314 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 7901517069 ps |
| CPU time | 22.54 seconds |
| Started | Sep 01 08:32:49 PM UTC 24 |
| Finished | Sep 01 08:33:13 PM UTC 24 |
| Peak memory | 206648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=134070314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.aon_timer_stress_all_with_rand_reset.134070314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.2681896684 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6357200421 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 08:31:45 PM UTC 24 |
| Finished | Sep 01 08:31:49 PM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681896684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2681896684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.2850286873 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7777622947 ps |
| CPU time | 3.44 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:31:54 PM UTC 24 |
| Peak memory | 231248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850286873 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2850286873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.3981637097 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 426735345 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 08:31:45 PM UTC 24 |
| Finished | Sep 01 08:31:47 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981637097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3981637097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/4.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.1808671216 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 589132501 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 08:32:49 PM UTC 24 |
| Finished | Sep 01 08:32:52 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808671216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1808671216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/40.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.632822318 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 5292650066 ps |
| CPU time | 7.41 seconds |
| Started | Sep 01 08:32:49 PM UTC 24 |
| Finished | Sep 01 08:32:58 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632822318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.632822318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/40.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.2616740157 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 481482799 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:32:49 PM UTC 24 |
| Finished | Sep 01 08:32:51 PM UTC 24 |
| Peak memory | 199268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616740157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2616740157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/40.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.162595247 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 47207027955 ps |
| CPU time | 45.3 seconds |
| Started | Sep 01 08:32:51 PM UTC 24 |
| Finished | Sep 01 08:33:38 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162595247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.162595247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/41.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.3073857553 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 464978778 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 08:32:51 PM UTC 24 |
| Finished | Sep 01 08:32:54 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073857553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3073857553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/41.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.3085496175 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2018196935 ps |
| CPU time | 21.38 seconds |
| Started | Sep 01 08:32:53 PM UTC 24 |
| Finished | Sep 01 08:33:15 PM UTC 24 |
| Peak memory | 215232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3085496175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 41.aon_timer_stress_all_with_rand_reset.3085496175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.1314935443 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 515332669 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 08:32:54 PM UTC 24 |
| Finished | Sep 01 08:32:57 PM UTC 24 |
| Peak memory | 200520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314935443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1314935443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/42.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.1383453064 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 44510930115 ps |
| CPU time | 5.31 seconds |
| Started | Sep 01 08:32:54 PM UTC 24 |
| Finished | Sep 01 08:33:00 PM UTC 24 |
| Peak memory | 200564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383453064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1383453064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/42.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.3045078801 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 534858968 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 08:32:54 PM UTC 24 |
| Finished | Sep 01 08:32:57 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045078801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3045078801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/42.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.1043568087 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 603564026 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 08:32:56 PM UTC 24 |
| Finished | Sep 01 08:32:59 PM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043568087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1043568087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/43.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.3416946619 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 560359124 ps |
| CPU time | 2.29 seconds |
| Started | Sep 01 08:32:55 PM UTC 24 |
| Finished | Sep 01 08:32:58 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416946619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3416946619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/43.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.1816323415 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 38211509148 ps |
| CPU time | 12.65 seconds |
| Started | Sep 01 08:32:59 PM UTC 24 |
| Finished | Sep 01 08:33:13 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816323415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1816323415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/44.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.2398772247 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 501625825 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 08:32:58 PM UTC 24 |
| Finished | Sep 01 08:33:01 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398772247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2398772247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/44.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.4218341417 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 35908030999 ps |
| CPU time | 39.17 seconds |
| Started | Sep 01 08:33:02 PM UTC 24 |
| Finished | Sep 01 08:33:42 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218341417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4218341417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/45.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.2373428671 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 509493576 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 08:33:01 PM UTC 24 |
| Finished | Sep 01 08:33:03 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373428671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2373428671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/45.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.4101245740 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 40599688878 ps |
| CPU time | 41.39 seconds |
| Started | Sep 01 08:33:05 PM UTC 24 |
| Finished | Sep 01 08:33:48 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101245740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4101245740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/46.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.3599968123 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 459680398 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 08:33:04 PM UTC 24 |
| Finished | Sep 01 08:33:06 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599968123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3599968123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/46.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.1175102357 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 14144911750 ps |
| CPU time | 5.26 seconds |
| Started | Sep 01 08:33:09 PM UTC 24 |
| Finished | Sep 01 08:33:16 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175102357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1175102357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/47.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.1654870537 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 351875010 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 08:33:08 PM UTC 24 |
| Finished | Sep 01 08:33:11 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654870537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1654870537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/47.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.529817043 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 49080327828 ps |
| CPU time | 15.12 seconds |
| Started | Sep 01 08:33:13 PM UTC 24 |
| Finished | Sep 01 08:33:29 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529817043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.529817043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/48.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.3530688155 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 540436653 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 08:33:13 PM UTC 24 |
| Finished | Sep 01 08:33:15 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530688155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3530688155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/48.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.2787393203 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 56555406829 ps |
| CPU time | 125.06 seconds |
| Started | Sep 01 08:33:16 PM UTC 24 |
| Finished | Sep 01 08:35:23 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787393203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2787393203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/49.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.4195665404 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 391799196 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 08:33:16 PM UTC 24 |
| Finished | Sep 01 08:33:19 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195665404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4195665404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/49.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.1293523794 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 36561607667 ps |
| CPU time | 13.39 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:04 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293523794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1293523794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.2239690836 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 436126048 ps |
| CPU time | 0.97 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:31:52 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239690836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2239690836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/5.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.195982210 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15471993517 ps |
| CPU time | 11.06 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:03 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195982210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.195982210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.1890306942 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 413992223 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:31:52 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890306942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1890306942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/6.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.798051461 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 8019615587 ps |
| CPU time | 11.2 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:03 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798051461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.798051461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.3161502728 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 522739051 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:31:53 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161502728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3161502728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/7.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.376204384 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 31854821412 ps |
| CPU time | 58.42 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:51 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376204384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.376204384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.639284668 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 463406690 ps |
| CPU time | 0.7 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:31:52 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639284668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.639284668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/8.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.2845529068 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 18101396372 ps |
| CPU time | 9.31 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:18 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845529068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2845529068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.761723396 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 479920902 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 08:31:50 PM UTC 24 |
| Finished | Sep 01 08:32:10 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761723396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.761723396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/9.aon_timer_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |