Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	17877	1			T2	10		T3	10		T6	11
bark[1]	285	1			T10	7		T86	145		T70	21
bark[2]	176	1			T14	14		T154	59		T135	26
bark[3]	406	1			T16	5		T35	148		T163	14
bark[4]	590	1			T27	178		T21	71		T170	14
bark[5]	362	1			T10	7		T139	140		T86	21
bark[6]	508	1			T15	122		T102	35		T174	14
bark[7]	153	1			T35	5		T103	14		T105	35
bark[8]	187	1			T26	14		T34	21		T37	21
bark[9]	264	1			T34	26		T38	39		T110	21
bark[10]	105	1			T40	14		T35	21		T23	21
bark[11]	120	1			T19	14		T27	5		T35	5
bark[12]	259	1			T8	14		T22	21		T78	14
bark[13]	522	1			T5	14		T23	33		T184	14
bark[14]	247	1			T139	64		T119	21		T86	5
bark[15]	383	1			T4	14		T16	26		T189	14
bark[16]	173	1			T10	5		T37	5		T190	35
bark[17]	262	1			T99	14		T146	7		T107	21
bark[18]	350	1			T1	14		T16	7		T34	21
bark[19]	412	1			T42	14		T128	21		T182	14
bark[20]	341	1			T34	21		T22	26		T102	24
bark[21]	136	1			T132	14		T155	26		T98	21
bark[22]	101	1			T139	5		T125	5		T173	14
bark[23]	999	1			T34	447		T146	290		T195	7
bark[24]	569	1			T10	168		T119	14		T89	7
bark[25]	136	1			T15	14		T89	26		T136	21
bark[26]	370	1			T16	87		T97	14		T35	5
bark[27]	175	1			T23	49		T70	21		T167	7
bark[28]	324	1			T10	7		T38	123		T143	14
bark[29]	224	1			T16	14		T146	21		T107	14
bark[30]	117	1			T34	14		T121	21		T113	26
bark[31]	204	1			T34	21		T180	14		T117	21
bark_0	4260	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	17510	1			T2	9		T3	9		T6	10
bite[1]	160	1			T4	13		T16	4		T186	13
bite[2]	684	1			T34	488		T22	30		T146	21
bite[3]	181	1			T10	27		T154	76		T72	25
bite[4]	215	1			T21	71		T102	13		T86	30
bite[5]	539	1			T5	13		T16	13		T97	13
bite[6]	440	1			T33	25		T34	21		T35	21
bite[7]	316	1			T27	177		T42	13		T187	13
bite[8]	136	1			T15	13		T107	39		T108	21
bite[9]	365	1			T27	4		T146	293		T121	21
bite[10]	185	1			T119	21		T86	21		T94	96
bite[11]	320	1			T139	139		T119	21		T113	21
bite[12]	359	1			T1	13		T34	26		T117	21
bite[13]	281	1			T35	21		T137	21		T102	51
bite[14]	188	1			T35	4		T180	13		T94	30
bite[15]	266	1			T38	39		T182	13		T119	21
bite[16]	300	1			T10	167		T22	26		T154	59
bite[17]	333	1			T10	6		T23	49		T102	121
bite[18]	161	1			T8	13		T26	13		T128	21
bite[19]	172	1			T163	13		T139	35		T121	26
bite[20]	272	1			T15	72		T34	21		T35	4
bite[21]	261	1			T16	86		T34	13		T143	13
bite[22]	350	1			T19	13		T132	13		T121	21
bite[23]	230	1			T10	6		T38	122		T125	4
bite[24]	326	1			T105	13		T102	21		T86	4
bite[25]	180	1			T157	78		T190	4		T135	26
bite[26]	470	1			T15	48		T102	126		T146	6
bite[27]	296	1			T14	13		T16	6		T102	23
bite[28]	302	1			T189	13		T103	13		T37	4
bite[29]	563	1			T10	4		T40	13		T36	155
bite[30]	357	1			T16	21		T35	4		T37	21
bite[31]	128	1			T16	4		T72	19		T136	21
bite_0	4751	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27989

1

T1

21

T2

17

T3

17

auto[1]

3608

1

T6

7

T10

267

T34

548

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	333	1			T34	2		T37	2		T128	60
prescale[1]	569	1			T10	9		T33	2		T34	19
prescale[2]	471	1			T27	51		T34	55		T89	139
prescale[3]	325	1			T16	2		T196	9		T197	11
prescale[4]	370	1			T198	9		T119	19		T86	41
prescale[5]	536	1			T10	19		T34	164		T128	2
prescale[6]	315	1			T21	28		T22	49		T89	2
prescale[7]	619	1			T23	47		T199	9		T146	19
prescale[8]	438	1			T16	2		T27	19		T34	58
prescale[9]	601	1			T10	4		T15	2		T17	9
prescale[10]	355	1			T10	2		T16	2		T200	9
prescale[11]	405	1			T10	76		T34	26		T201	9
prescale[12]	597	1			T10	45		T33	2		T34	2
prescale[13]	528	1			T35	69		T36	68		T21	60
prescale[14]	340	1			T202	9		T137	57		T146	2
prescale[15]	449	1			T10	24		T27	2		T195	9
prescale[16]	361	1			T139	106		T117	35		T190	2
prescale[17]	339	1			T10	19		T16	2		T37	2
prescale[18]	353	1			T36	2		T38	9		T203	9
prescale[19]	393	1			T102	2		T157	9		T86	19
prescale[20]	397	1			T146	2		T125	36		T94	61
prescale[21]	294	1			T41	9		T128	2		T146	2
prescale[22]	308	1			T27	40		T34	94		T36	2
prescale[23]	761	1			T33	19		T34	340		T197	59
prescale[24]	308	1			T16	100		T35	33		T21	24
prescale[25]	407	1			T16	63		T105	38		T137	50
prescale[26]	487	1			T15	2		T204	9		T35	2
prescale[27]	400	1			T27	2		T33	2		T128	2
prescale[28]	371	1			T21	28		T205	9		T206	9
prescale[29]	304	1			T10	36		T34	2		T43	9
prescale[30]	201	1			T146	45		T195	2		T113	19
prescale[31]	108	1			T15	2		T35	2		T207	9
prescale_0	18554	1			T1	21		T2	17		T3	17

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22034

1

T1

21

T2

17

T3

17

auto[1]

9563

1

T5

12

T6

9

T7

9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

31597

1

T1

21

T2

17

T3

17

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	17807	1			T1	1		T2	12		T3	12
wkup[1]	319	1			T10	21		T34	68		T97	15
wkup[2]	185	1			T35	6		T143	15		T86	26
wkup[3]	127	1			T139	21		T173	15		T113	21
wkup[4]	137	1			T139	6		T86	21		T113	21
wkup[5]	105	1			T103	15		T128	49		T186	15
wkup[6]	230	1			T16	21		T34	39		T139	21
wkup[7]	138	1			T14	15		T27	6		T42	15
wkup[8]	149	1			T121	21		T86	6		T70	21
wkup[9]	156	1			T139	21		T102	21		T146	15
wkup[10]	120	1			T154	21		T106	15		T89	21
wkup[11]	204	1			T35	6		T36	21		T102	8
wkup[12]	169	1			T184	15		T102	21		T157	35
wkup[13]	256	1			T34	21		T70	42		T94	26
wkup[14]	155	1			T34	21		T119	36		T89	26
wkup[15]	106	1			T10	8		T16	6		T22	30
wkup[16]	139	1			T16	6		T128	21		T174	15
wkup[17]	159	1			T128	24		T102	15		T146	12
wkup[18]	99	1			T123	15		T70	21		T94	21
wkup[19]	145	1			T35	21		T102	21		T154	21
wkup[20]	208	1			T10	6		T34	42		T37	21
wkup[21]	158	1			T10	21		T23	21		T86	30
wkup[22]	201	1			T36	26		T139	6		T102	8
wkup[23]	283	1			T1	15		T22	47		T102	21
wkup[24]	198	1			T15	15		T36	15		T139	21
wkup[25]	215	1			T15	35		T121	26		T154	21
wkup[26]	89	1			T34	6		T36	21		T163	15
wkup[27]	92	1			T34	21		T110	21		T96	8
wkup[28]	262	1			T105	21		T157	26		T86	21
wkup[29]	83	1			T5	15		T157	21		T113	26
wkup[30]	125	1			T34	21		T21	21		T167	21
wkup[31]	273	1			T4	15		T35	21		T139	51
wkup[32]	161	1			T10	21		T34	26		T35	21
wkup[33]	135	1			T16	35		T27	31		T37	6
wkup[34]	128	1			T27	21		T34	36		T70	21
wkup[35]	273	1			T10	70		T128	21		T139	21
wkup[36]	71	1			T119	21		T168	21		T153	21
wkup[37]	241	1			T16	15		T36	21		T139	8
wkup[38]	97	1			T10	8		T35	21		T86	21
wkup[39]	201	1			T16	39		T35	21		T23	30
wkup[40]	135	1			T94	30		T113	21		T153	21
wkup[41]	184	1			T137	21		T117	21		T195	8
wkup[42]	153	1			T27	21		T182	15		T102	21
wkup[43]	145	1			T117	36		T86	21		T89	8
wkup[44]	173	1			T15	21		T33	21		T102	21
wkup[45]	97	1			T34	21		T121	21		T70	26
wkup[46]	226	1			T27	15		T189	15		T102	21
wkup[47]	177	1			T10	21		T15	21		T70	30
wkup[48]	99	1			T197	21		T70	21		T78	15
wkup[49]	201	1			T105	35		T102	21		T70	35
wkup[50]	188	1			T105	15		T139	21		T117	26
wkup[51]	110	1			T146	21		T153	21		T158	21
wkup[52]	108	1			T19	15		T132	15		T95	15
wkup[53]	167	1			T16	30		T33	21		T35	21
wkup[54]	176	1			T10	8		T154	21		T125	6
wkup[55]	210	1			T36	21		T139	30		T146	29
wkup[56]	134	1			T16	15		T23	21		T137	21
wkup[57]	93	1			T36	30		T128	21		T177	21
wkup[58]	222	1			T26	15		T33	21		T35	6
wkup[59]	144	1			T8	15		T10	21		T15	15
wkup[60]	172	1			T34	26		T38	39		T89	21
wkup[61]	154	1			T16	21		T34	21		T128	21
wkup[62]	261	1			T34	21		T99	15		T146	8
wkup[63]	108	1			T33	30		T146	21		T140	15
wkup_0	3361	1			T1	5		T2	5		T3	5