| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.08 | 99.33 | 95.61 | 100.00 | 98.40 | 99.51 | 41.61 |
| T30 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.223791298 | Sep 04 01:30:46 PM UTC 24 | Sep 04 01:30:50 PM UTC 24 | 962735232 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3342098063 | Sep 04 01:30:51 PM UTC 24 | Sep 04 01:30:53 PM UTC 24 | 359640093 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2792456306 | Sep 04 01:30:54 PM UTC 24 | Sep 04 01:30:57 PM UTC 24 | 510034277 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3451750226 | Sep 04 01:30:51 PM UTC 24 | Sep 04 01:31:00 PM UTC 24 | 2490024849 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.717367279 | Sep 04 01:30:57 PM UTC 24 | Sep 04 01:31:02 PM UTC 24 | 576905108 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.2910597196 | Sep 04 01:31:03 PM UTC 24 | Sep 04 01:31:06 PM UTC 24 | 387304081 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3251772917 | Sep 04 01:31:06 PM UTC 24 | Sep 04 01:31:08 PM UTC 24 | 428834500 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3172729115 | Sep 04 01:30:50 PM UTC 24 | Sep 04 01:31:10 PM UTC 24 | 7186664806 ps | ||
| T31 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3228355478 | Sep 04 01:31:01 PM UTC 24 | Sep 04 01:31:11 PM UTC 24 | 4005944797 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.344515171 | Sep 04 01:31:09 PM UTC 24 | Sep 04 01:31:12 PM UTC 24 | 435617466 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3302398262 | Sep 04 01:31:10 PM UTC 24 | Sep 04 01:31:13 PM UTC 24 | 779752356 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.1303012918 | Sep 04 01:31:12 PM UTC 24 | Sep 04 01:31:14 PM UTC 24 | 433499500 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2342337142 | Sep 04 01:31:14 PM UTC 24 | Sep 04 01:31:16 PM UTC 24 | 678994160 ps | ||
| T46 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2590529000 | Sep 04 01:31:13 PM UTC 24 | Sep 04 01:31:17 PM UTC 24 | 464444139 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2545540190 | Sep 04 01:31:16 PM UTC 24 | Sep 04 01:31:18 PM UTC 24 | 403270063 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2723702607 | Sep 04 01:31:15 PM UTC 24 | Sep 04 01:31:19 PM UTC 24 | 1902994300 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2446749052 | Sep 04 01:31:16 PM UTC 24 | Sep 04 01:31:19 PM UTC 24 | 964143649 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.3013598329 | Sep 04 01:31:18 PM UTC 24 | Sep 04 01:31:20 PM UTC 24 | 497736563 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3620766930 | Sep 04 01:31:19 PM UTC 24 | Sep 04 01:31:21 PM UTC 24 | 467855233 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.2393486832 | Sep 04 01:31:19 PM UTC 24 | Sep 04 01:31:21 PM UTC 24 | 345010713 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1211263578 | Sep 04 01:31:20 PM UTC 24 | Sep 04 01:31:23 PM UTC 24 | 938630408 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1097629760 | Sep 04 01:31:20 PM UTC 24 | Sep 04 01:31:23 PM UTC 24 | 392424108 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.197836981 | Sep 04 01:31:21 PM UTC 24 | Sep 04 01:31:24 PM UTC 24 | 558698880 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2478680813 | Sep 04 01:31:23 PM UTC 24 | Sep 04 01:31:25 PM UTC 24 | 485466943 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4244903397 | Sep 04 01:31:21 PM UTC 24 | Sep 04 01:31:25 PM UTC 24 | 1279007938 ps | ||
| T48 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4274077064 | Sep 04 01:31:20 PM UTC 24 | Sep 04 01:31:25 PM UTC 24 | 6496723965 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3547345650 | Sep 04 01:31:25 PM UTC 24 | Sep 04 01:31:27 PM UTC 24 | 423401126 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.458958028 | Sep 04 01:31:25 PM UTC 24 | Sep 04 01:31:27 PM UTC 24 | 435378399 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2824805190 | Sep 04 01:31:24 PM UTC 24 | Sep 04 01:31:27 PM UTC 24 | 556632996 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1420889985 | Sep 04 01:31:26 PM UTC 24 | Sep 04 01:31:28 PM UTC 24 | 338136171 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.4048528045 | Sep 04 01:31:26 PM UTC 24 | Sep 04 01:31:28 PM UTC 24 | 333831031 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3443766890 | Sep 04 01:31:26 PM UTC 24 | Sep 04 01:31:29 PM UTC 24 | 805298862 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2780907788 | Sep 04 01:31:28 PM UTC 24 | Sep 04 01:31:32 PM UTC 24 | 440608475 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2364288270 | Sep 04 01:31:29 PM UTC 24 | Sep 04 01:31:32 PM UTC 24 | 409791021 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1454695935 | Sep 04 01:31:28 PM UTC 24 | Sep 04 01:31:32 PM UTC 24 | 1414920222 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.2383550466 | Sep 04 01:31:29 PM UTC 24 | Sep 04 01:31:33 PM UTC 24 | 406782140 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.458496085 | Sep 04 01:31:32 PM UTC 24 | Sep 04 01:31:34 PM UTC 24 | 430278313 ps | ||
| T32 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2253855927 | Sep 04 01:31:25 PM UTC 24 | Sep 04 01:31:34 PM UTC 24 | 8489718126 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.178798566 | Sep 04 01:31:32 PM UTC 24 | Sep 04 01:31:35 PM UTC 24 | 315320684 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2411504396 | Sep 04 01:31:33 PM UTC 24 | Sep 04 01:31:36 PM UTC 24 | 393534240 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4264616621 | Sep 04 01:31:34 PM UTC 24 | Sep 04 01:31:38 PM UTC 24 | 1275744751 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3316493173 | Sep 04 01:31:17 PM UTC 24 | Sep 04 01:31:38 PM UTC 24 | 8417066621 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.1690275062 | Sep 04 01:31:36 PM UTC 24 | Sep 04 01:31:38 PM UTC 24 | 294780836 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2252749138 | Sep 04 01:31:36 PM UTC 24 | Sep 04 01:31:39 PM UTC 24 | 661846443 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2987739851 | Sep 04 01:31:28 PM UTC 24 | Sep 04 01:31:39 PM UTC 24 | 7014594182 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1501534071 | Sep 04 01:31:37 PM UTC 24 | Sep 04 01:31:40 PM UTC 24 | 1231117874 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.1722937548 | Sep 04 01:31:40 PM UTC 24 | Sep 04 01:31:42 PM UTC 24 | 324626066 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4220045476 | Sep 04 01:31:36 PM UTC 24 | Sep 04 01:31:43 PM UTC 24 | 5873269297 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2830675384 | Sep 04 01:31:39 PM UTC 24 | Sep 04 01:31:43 PM UTC 24 | 417547742 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.1791914979 | Sep 04 01:31:40 PM UTC 24 | Sep 04 01:31:43 PM UTC 24 | 451540114 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.1172709012 | Sep 04 01:31:39 PM UTC 24 | Sep 04 01:31:43 PM UTC 24 | 904506284 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.601727608 | Sep 04 01:31:41 PM UTC 24 | Sep 04 01:31:44 PM UTC 24 | 468637699 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2034933482 | Sep 04 01:31:39 PM UTC 24 | Sep 04 01:31:44 PM UTC 24 | 4480643372 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2271573501 | Sep 04 01:31:43 PM UTC 24 | Sep 04 01:31:45 PM UTC 24 | 527236667 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.596657299 | Sep 04 01:31:41 PM UTC 24 | Sep 04 01:31:45 PM UTC 24 | 1284693554 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3224652764 | Sep 04 01:31:30 PM UTC 24 | Sep 04 01:31:47 PM UTC 24 | 4480835394 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2177012086 | Sep 04 01:31:44 PM UTC 24 | Sep 04 01:31:47 PM UTC 24 | 405173289 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.839071738 | Sep 04 01:31:44 PM UTC 24 | Sep 04 01:31:47 PM UTC 24 | 461664048 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3852773922 | Sep 04 01:31:43 PM UTC 24 | Sep 04 01:31:47 PM UTC 24 | 348429432 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2586931789 | Sep 04 01:31:44 PM UTC 24 | Sep 04 01:31:48 PM UTC 24 | 1527717518 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.4141714927 | Sep 04 01:31:47 PM UTC 24 | Sep 04 01:31:49 PM UTC 24 | 484814614 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4151605518 | Sep 04 01:31:47 PM UTC 24 | Sep 04 01:31:50 PM UTC 24 | 4463390357 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.1460464173 | Sep 04 01:31:46 PM UTC 24 | Sep 04 01:31:50 PM UTC 24 | 816698548 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2424377036 | Sep 04 01:31:43 PM UTC 24 | Sep 04 01:31:51 PM UTC 24 | 7788616048 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.2564694234 | Sep 04 01:31:48 PM UTC 24 | Sep 04 01:31:51 PM UTC 24 | 480545155 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.919486407 | Sep 04 01:31:48 PM UTC 24 | Sep 04 01:31:51 PM UTC 24 | 437661501 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.2519785310 | Sep 04 01:31:49 PM UTC 24 | Sep 04 01:31:52 PM UTC 24 | 331114144 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.4290793266 | Sep 04 01:31:49 PM UTC 24 | Sep 04 01:31:52 PM UTC 24 | 848164346 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.265143497 | Sep 04 01:31:50 PM UTC 24 | Sep 04 01:31:53 PM UTC 24 | 308733882 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1375636791 | Sep 04 01:31:48 PM UTC 24 | Sep 04 01:31:54 PM UTC 24 | 1348921461 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1869368405 | Sep 04 01:31:51 PM UTC 24 | Sep 04 01:31:54 PM UTC 24 | 459803944 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.2609449411 | Sep 04 01:31:52 PM UTC 24 | Sep 04 01:31:55 PM UTC 24 | 468514232 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.4286003042 | Sep 04 01:31:52 PM UTC 24 | Sep 04 01:31:55 PM UTC 24 | 602739908 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1782847235 | Sep 04 01:31:51 PM UTC 24 | Sep 04 01:31:55 PM UTC 24 | 706479733 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1091162645 | Sep 04 01:31:51 PM UTC 24 | Sep 04 01:31:56 PM UTC 24 | 2543240088 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2418087281 | Sep 04 01:31:54 PM UTC 24 | Sep 04 01:31:56 PM UTC 24 | 335684751 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2068690490 | Sep 04 01:31:54 PM UTC 24 | Sep 04 01:31:57 PM UTC 24 | 1154489432 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.707792606 | Sep 04 01:31:55 PM UTC 24 | Sep 04 01:31:57 PM UTC 24 | 467459825 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.3417728173 | Sep 04 01:31:55 PM UTC 24 | Sep 04 01:31:58 PM UTC 24 | 424155681 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.4154705236 | Sep 04 01:31:54 PM UTC 24 | Sep 04 01:31:59 PM UTC 24 | 385323300 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.777393133 | Sep 04 01:31:56 PM UTC 24 | Sep 04 01:31:59 PM UTC 24 | 361993732 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1795522697 | Sep 04 01:31:56 PM UTC 24 | Sep 04 01:31:59 PM UTC 24 | 343414186 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.2026014760 | Sep 04 01:31:57 PM UTC 24 | Sep 04 01:31:59 PM UTC 24 | 483901604 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1302470593 | Sep 04 01:31:56 PM UTC 24 | Sep 04 01:32:00 PM UTC 24 | 1777344771 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3256157297 | Sep 04 01:31:57 PM UTC 24 | Sep 04 01:32:00 PM UTC 24 | 1097435885 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.828318841 | Sep 04 01:31:57 PM UTC 24 | Sep 04 01:32:01 PM UTC 24 | 438809166 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1723951435 | Sep 04 01:31:58 PM UTC 24 | Sep 04 01:32:01 PM UTC 24 | 415737738 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2204524467 | Sep 04 01:31:52 PM UTC 24 | Sep 04 01:32:02 PM UTC 24 | 7931209836 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.1621128907 | Sep 04 01:31:59 PM UTC 24 | Sep 04 01:32:02 PM UTC 24 | 504810123 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.3667740285 | Sep 04 01:32:00 PM UTC 24 | Sep 04 01:32:02 PM UTC 24 | 318551292 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.1129621826 | Sep 04 01:31:58 PM UTC 24 | Sep 04 01:32:03 PM UTC 24 | 531274958 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4272513119 | Sep 04 01:32:01 PM UTC 24 | Sep 04 01:32:03 PM UTC 24 | 560483414 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1456719687 | Sep 04 01:32:02 PM UTC 24 | Sep 04 01:32:04 PM UTC 24 | 504758527 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.201715919 | Sep 04 01:32:01 PM UTC 24 | Sep 04 01:32:04 PM UTC 24 | 1240788628 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.1746017255 | Sep 04 01:32:02 PM UTC 24 | Sep 04 01:32:05 PM UTC 24 | 470280453 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.1237232073 | Sep 04 01:32:04 PM UTC 24 | Sep 04 01:32:06 PM UTC 24 | 576912126 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1916699067 | Sep 04 01:32:03 PM UTC 24 | Sep 04 01:32:06 PM UTC 24 | 372860694 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.857149684 | Sep 04 01:32:03 PM UTC 24 | Sep 04 01:32:06 PM UTC 24 | 654123224 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3403947320 | Sep 04 01:31:57 PM UTC 24 | Sep 04 01:32:07 PM UTC 24 | 4591893984 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3539263898 | Sep 04 01:32:01 PM UTC 24 | Sep 04 01:32:07 PM UTC 24 | 1953031537 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4231649037 | Sep 04 01:31:49 PM UTC 24 | Sep 04 01:32:07 PM UTC 24 | 7541380973 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2965097522 | Sep 04 01:32:05 PM UTC 24 | Sep 04 01:32:08 PM UTC 24 | 551789266 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.628674441 | Sep 04 01:32:05 PM UTC 24 | Sep 04 01:32:08 PM UTC 24 | 422775729 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2077256859 | Sep 04 01:32:02 PM UTC 24 | Sep 04 01:32:08 PM UTC 24 | 1293586928 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3654312759 | Sep 04 01:31:59 PM UTC 24 | Sep 04 01:32:08 PM UTC 24 | 7934266065 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.860997038 | Sep 04 01:32:08 PM UTC 24 | Sep 04 01:32:10 PM UTC 24 | 298781969 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1783709936 | Sep 04 01:32:08 PM UTC 24 | Sep 04 01:32:11 PM UTC 24 | 1301831718 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.206554776 | Sep 04 01:32:08 PM UTC 24 | Sep 04 01:32:11 PM UTC 24 | 512766516 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.1364824817 | Sep 04 01:32:09 PM UTC 24 | Sep 04 01:32:11 PM UTC 24 | 519551613 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3223960342 | Sep 04 01:32:09 PM UTC 24 | Sep 04 01:32:11 PM UTC 24 | 484088733 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.2879486037 | Sep 04 01:32:06 PM UTC 24 | Sep 04 01:32:12 PM UTC 24 | 706707668 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.3829842129 | Sep 04 01:32:09 PM UTC 24 | Sep 04 01:32:12 PM UTC 24 | 409662761 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.3523394348 | Sep 04 01:32:09 PM UTC 24 | Sep 04 01:32:13 PM UTC 24 | 367078781 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.2364563010 | Sep 04 01:32:12 PM UTC 24 | Sep 04 01:32:14 PM UTC 24 | 390013642 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1098387705 | Sep 04 01:32:09 PM UTC 24 | Sep 04 01:32:15 PM UTC 24 | 4598005085 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.4224946646 | Sep 04 01:32:12 PM UTC 24 | Sep 04 01:32:15 PM UTC 24 | 410492012 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1291977650 | Sep 04 01:32:12 PM UTC 24 | Sep 04 01:32:16 PM UTC 24 | 523803928 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.1604513608 | Sep 04 01:32:12 PM UTC 24 | Sep 04 01:32:16 PM UTC 24 | 885726406 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4274261749 | Sep 04 01:32:05 PM UTC 24 | Sep 04 01:32:17 PM UTC 24 | 2932925681 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3947996786 | Sep 04 01:32:14 PM UTC 24 | Sep 04 01:32:17 PM UTC 24 | 323415288 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.416858488 | Sep 04 01:32:13 PM UTC 24 | Sep 04 01:32:19 PM UTC 24 | 2219591232 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.1160575966 | Sep 04 01:32:17 PM UTC 24 | Sep 04 01:32:19 PM UTC 24 | 388026362 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.383104439 | Sep 04 01:32:17 PM UTC 24 | Sep 04 01:32:19 PM UTC 24 | 340812015 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.18831637 | Sep 04 01:32:17 PM UTC 24 | Sep 04 01:32:19 PM UTC 24 | 1974439061 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.3466421126 | Sep 04 01:32:15 PM UTC 24 | Sep 04 01:32:19 PM UTC 24 | 513509382 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4110677798 | Sep 04 01:32:04 PM UTC 24 | Sep 04 01:32:21 PM UTC 24 | 8170541255 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.522017886 | Sep 04 01:32:12 PM UTC 24 | Sep 04 01:32:21 PM UTC 24 | 8458830889 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1586085985 | Sep 04 01:32:18 PM UTC 24 | Sep 04 01:32:21 PM UTC 24 | 413844804 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.2723568241 | Sep 04 01:32:18 PM UTC 24 | Sep 04 01:32:21 PM UTC 24 | 599447251 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3365294440 | Sep 04 01:31:55 PM UTC 24 | Sep 04 01:32:22 PM UTC 24 | 8102546199 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.2988404902 | Sep 04 01:32:20 PM UTC 24 | Sep 04 01:32:22 PM UTC 24 | 374165934 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.3501739644 | Sep 04 01:32:20 PM UTC 24 | Sep 04 01:32:22 PM UTC 24 | 433126575 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2639948581 | Sep 04 01:32:20 PM UTC 24 | Sep 04 01:32:23 PM UTC 24 | 372374444 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.1956691106 | Sep 04 01:32:21 PM UTC 24 | Sep 04 01:32:24 PM UTC 24 | 377050177 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2823637719 | Sep 04 01:32:11 PM UTC 24 | Sep 04 01:32:24 PM UTC 24 | 2314370803 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.1615322501 | Sep 04 01:32:22 PM UTC 24 | Sep 04 01:32:24 PM UTC 24 | 389030978 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.888580249 | Sep 04 01:32:19 PM UTC 24 | Sep 04 01:32:25 PM UTC 24 | 8310173576 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.1256606833 | Sep 04 01:32:22 PM UTC 24 | Sep 04 01:32:25 PM UTC 24 | 430964770 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.3086459324 | Sep 04 01:32:23 PM UTC 24 | Sep 04 01:32:25 PM UTC 24 | 422708958 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.4133382217 | Sep 04 01:32:22 PM UTC 24 | Sep 04 01:32:26 PM UTC 24 | 480663095 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3624900107 | Sep 04 01:32:22 PM UTC 24 | Sep 04 01:32:26 PM UTC 24 | 486682273 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3076372103 | Sep 04 01:32:20 PM UTC 24 | Sep 04 01:32:26 PM UTC 24 | 2499834712 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4241900351 | Sep 04 01:32:01 PM UTC 24 | Sep 04 01:32:26 PM UTC 24 | 8417506535 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.2396290996 | Sep 04 01:32:23 PM UTC 24 | Sep 04 01:32:26 PM UTC 24 | 322247172 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1333927164 | Sep 04 01:32:24 PM UTC 24 | Sep 04 01:32:27 PM UTC 24 | 440341647 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2988966802 | Sep 04 01:32:25 PM UTC 24 | Sep 04 01:32:27 PM UTC 24 | 339226128 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.880082741 | Sep 04 01:32:25 PM UTC 24 | Sep 04 01:32:27 PM UTC 24 | 282688185 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.3372544946 | Sep 04 01:32:25 PM UTC 24 | Sep 04 01:32:27 PM UTC 24 | 333762040 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2751190460 | Sep 04 01:32:26 PM UTC 24 | Sep 04 01:32:28 PM UTC 24 | 460829849 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.2869032649 | Sep 04 01:32:26 PM UTC 24 | Sep 04 01:32:28 PM UTC 24 | 404285675 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2892691939 | Sep 04 01:32:27 PM UTC 24 | Sep 04 01:32:29 PM UTC 24 | 416147368 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.2218092644 | Sep 04 01:32:27 PM UTC 24 | Sep 04 01:32:29 PM UTC 24 | 443311850 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.1386189653 | Sep 04 01:32:27 PM UTC 24 | Sep 04 01:32:29 PM UTC 24 | 293830103 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.2082370606 | Sep 04 01:32:27 PM UTC 24 | Sep 04 01:32:29 PM UTC 24 | 484818468 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.752265065 | Sep 04 01:32:26 PM UTC 24 | Sep 04 01:32:29 PM UTC 24 | 434417153 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.1141621336 | Sep 04 01:32:27 PM UTC 24 | Sep 04 01:32:29 PM UTC 24 | 345481512 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.2502876699 | Sep 04 01:32:27 PM UTC 24 | Sep 04 01:32:29 PM UTC 24 | 476517327 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.797862125 | Sep 04 01:32:27 PM UTC 24 | Sep 04 01:32:29 PM UTC 24 | 285733418 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.3510858041 | Sep 04 01:32:27 PM UTC 24 | Sep 04 01:32:29 PM UTC 24 | 313740899 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.1760267248 | Sep 04 01:32:28 PM UTC 24 | Sep 04 01:32:30 PM UTC 24 | 510933570 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.70645082 | Sep 04 01:32:28 PM UTC 24 | Sep 04 01:32:30 PM UTC 24 | 385627039 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1292611626 | Sep 04 01:32:08 PM UTC 24 | Sep 04 01:32:31 PM UTC 24 | 7905613179 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.346193624 | Sep 04 01:32:30 PM UTC 24 | Sep 04 01:32:32 PM UTC 24 | 352871054 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.3406834329 | Sep 04 01:32:30 PM UTC 24 | Sep 04 01:32:32 PM UTC 24 | 388404132 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.2334028511 | Sep 04 01:32:30 PM UTC 24 | Sep 04 01:32:32 PM UTC 24 | 323423199 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.2415940712 | Sep 04 01:32:30 PM UTC 24 | Sep 04 01:32:32 PM UTC 24 | 504819167 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.337155639 | Sep 04 01:32:30 PM UTC 24 | Sep 04 01:32:33 PM UTC 24 | 403152583 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.93717087 | Sep 04 01:32:30 PM UTC 24 | Sep 04 01:32:33 PM UTC 24 | 377443369 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1616269717 | Sep 04 01:32:17 PM UTC 24 | Sep 04 01:32:34 PM UTC 24 | 8324506945 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.2381356382 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 439242882 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 01:32:34 PM UTC 24 |
| Finished | Sep 04 01:32:36 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381356382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2381356382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.2347247149 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6692471942 ps |
| CPU time | 40.51 seconds |
| Started | Sep 04 01:32:32 PM UTC 24 |
| Finished | Sep 04 01:33:14 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2347247149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.aon_timer_stress_all_with_rand_reset.2347247149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3889013127 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8354373682 ps |
| CPU time | 14.06 seconds |
| Started | Sep 04 01:30:34 PM UTC 24 |
| Finished | Sep 04 01:30:50 PM UTC 24 |
| Peak memory | 207424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889013127 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.3889013127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.3760031486 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10584527651 ps |
| CPU time | 50.79 seconds |
| Started | Sep 04 01:32:39 PM UTC 24 |
| Finished | Sep 04 01:33:31 PM UTC 24 |
| Peak memory | 219592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3760031486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 3.aon_timer_stress_all_with_rand_reset.3760031486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.2019956223 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 16584748530 ps |
| CPU time | 24.45 seconds |
| Started | Sep 04 01:34:57 PM UTC 24 |
| Finished | Sep 04 01:35:23 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019956223 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.2019956223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.2338651265 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 430339084 ps |
| CPU time | 1.76 seconds |
| Started | Sep 04 01:32:32 PM UTC 24 |
| Finished | Sep 04 01:32:35 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338651265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2338651265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3342098063 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 359640093 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 01:30:51 PM UTC 24 |
| Finished | Sep 04 01:30:53 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342098063 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.3342098063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.3386752967 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 154763043167 ps |
| CPU time | 242.25 seconds |
| Started | Sep 04 01:33:35 PM UTC 24 |
| Finished | Sep 04 01:37:42 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386752967 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.3386752967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.1487999749 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5900906473 ps |
| CPU time | 51.83 seconds |
| Started | Sep 04 01:33:54 PM UTC 24 |
| Finished | Sep 04 01:34:48 PM UTC 24 |
| Peak memory | 218076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1487999749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 12.aon_timer_stress_all_with_rand_reset.1487999749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.1320923663 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4865868991 ps |
| CPU time | 37.24 seconds |
| Started | Sep 04 01:34:48 PM UTC 24 |
| Finished | Sep 04 01:35:27 PM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1320923663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 18.aon_timer_stress_all_with_rand_reset.1320923663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.1656272103 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8464339058 ps |
| CPU time | 25.12 seconds |
| Started | Sep 04 01:32:31 PM UTC 24 |
| Finished | Sep 04 01:32:57 PM UTC 24 |
| Peak memory | 231228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656272103 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1656272103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.350873894 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 52271972793 ps |
| CPU time | 97.4 seconds |
| Started | Sep 04 01:37:22 PM UTC 24 |
| Finished | Sep 04 01:39:01 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350873894 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.350873894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/41.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.2013992488 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 89841445959 ps |
| CPU time | 34.05 seconds |
| Started | Sep 04 01:37:58 PM UTC 24 |
| Finished | Sep 04 01:38:33 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013992488 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.2013992488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/48.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.3965804866 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 21358792684 ps |
| CPU time | 27.73 seconds |
| Started | Sep 04 01:36:14 PM UTC 24 |
| Finished | Sep 04 01:36:43 PM UTC 24 |
| Peak memory | 218684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3965804866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 30.aon_timer_stress_all_with_rand_reset.3965804866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.2920175528 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 29112142190 ps |
| CPU time | 40.31 seconds |
| Started | Sep 04 01:35:03 PM UTC 24 |
| Finished | Sep 04 01:35:45 PM UTC 24 |
| Peak memory | 219472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2920175528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 20.aon_timer_stress_all_with_rand_reset.2920175528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.3145606065 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 297882997642 ps |
| CPU time | 291.66 seconds |
| Started | Sep 04 01:34:34 PM UTC 24 |
| Finished | Sep 04 01:39:29 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145606065 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.3145606065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.2666786265 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 8243092983 ps |
| CPU time | 41.26 seconds |
| Started | Sep 04 01:36:51 PM UTC 24 |
| Finished | Sep 04 01:37:34 PM UTC 24 |
| Peak memory | 219488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2666786265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 36.aon_timer_stress_all_with_rand_reset.2666786265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.3699414931 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 3593497754 ps |
| CPU time | 42.99 seconds |
| Started | Sep 04 01:33:49 PM UTC 24 |
| Finished | Sep 04 01:34:33 PM UTC 24 |
| Peak memory | 206548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3699414931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 11.aon_timer_stress_all_with_rand_reset.3699414931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.598687471 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 239352394950 ps |
| CPU time | 61.5 seconds |
| Started | Sep 04 01:36:33 PM UTC 24 |
| Finished | Sep 04 01:37:36 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598687471 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.598687471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/33.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.2471124383 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 117261553988 ps |
| CPU time | 42.41 seconds |
| Started | Sep 04 01:35:31 PM UTC 24 |
| Finished | Sep 04 01:36:15 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471124383 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.2471124383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/24.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.3192127566 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 275343271570 ps |
| CPU time | 198.6 seconds |
| Started | Sep 04 01:34:39 PM UTC 24 |
| Finished | Sep 04 01:38:00 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192127566 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.3192127566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.339002614 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 34614071323 ps |
| CPU time | 47.31 seconds |
| Started | Sep 04 01:35:58 PM UTC 24 |
| Finished | Sep 04 01:36:46 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339002614 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.339002614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/28.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.181031773 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 393855933704 ps |
| CPU time | 190.34 seconds |
| Started | Sep 04 01:37:48 PM UTC 24 |
| Finished | Sep 04 01:41:02 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181031773 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.181031773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/46.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.110450575 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 79937967230 ps |
| CPU time | 133.69 seconds |
| Started | Sep 04 01:33:44 PM UTC 24 |
| Finished | Sep 04 01:36:00 PM UTC 24 |
| Peak memory | 200848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110450575 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.110450575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.1791879105 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 133577596621 ps |
| CPU time | 20.38 seconds |
| Started | Sep 04 01:36:14 PM UTC 24 |
| Finished | Sep 04 01:36:36 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791879105 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.1791879105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/30.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.23981417 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3617761194 ps |
| CPU time | 31.67 seconds |
| Started | Sep 04 01:33:06 PM UTC 24 |
| Finished | Sep 04 01:33:39 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=23981417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 6.aon_timer_stress_all_with_rand_reset.23981417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.4055995703 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 260456228609 ps |
| CPU time | 433.38 seconds |
| Started | Sep 04 01:34:49 PM UTC 24 |
| Finished | Sep 04 01:42:08 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055995703 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.4055995703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.2717787089 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 122512791158 ps |
| CPU time | 61.77 seconds |
| Started | Sep 04 01:37:54 PM UTC 24 |
| Finished | Sep 04 01:38:57 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717787089 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.2717787089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/47.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.1626267655 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 58124983763 ps |
| CPU time | 75.5 seconds |
| Started | Sep 04 01:37:26 PM UTC 24 |
| Finished | Sep 04 01:38:44 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626267655 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.1626267655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/42.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.3955166407 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 67490564280 ps |
| CPU time | 85.19 seconds |
| Started | Sep 04 01:33:50 PM UTC 24 |
| Finished | Sep 04 01:35:17 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955166407 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.3955166407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.3860971937 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 265102312802 ps |
| CPU time | 102.08 seconds |
| Started | Sep 04 01:35:12 PM UTC 24 |
| Finished | Sep 04 01:36:56 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860971937 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.3860971937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/21.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.1798231946 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 55511593649 ps |
| CPU time | 74.47 seconds |
| Started | Sep 04 01:32:32 PM UTC 24 |
| Finished | Sep 04 01:33:48 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798231946 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.1798231946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.3478920695 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2078654603 ps |
| CPU time | 23.25 seconds |
| Started | Sep 04 01:34:38 PM UTC 24 |
| Finished | Sep 04 01:35:02 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3478920695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 17.aon_timer_stress_all_with_rand_reset.3478920695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.4047084501 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 118356921109 ps |
| CPU time | 153.73 seconds |
| Started | Sep 04 01:35:27 PM UTC 24 |
| Finished | Sep 04 01:38:03 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047084501 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.4047084501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/23.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.3672901945 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 8071641777 ps |
| CPU time | 41.03 seconds |
| Started | Sep 04 01:37:16 PM UTC 24 |
| Finished | Sep 04 01:37:59 PM UTC 24 |
| Peak memory | 206544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3672901945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 40.aon_timer_stress_all_with_rand_reset.3672901945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.3195515363 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 262940151711 ps |
| CPU time | 243.76 seconds |
| Started | Sep 04 01:37:43 PM UTC 24 |
| Finished | Sep 04 01:41:50 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195515363 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.3195515363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/45.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.2652190237 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4510598742 ps |
| CPU time | 19.05 seconds |
| Started | Sep 04 01:33:40 PM UTC 24 |
| Finished | Sep 04 01:34:00 PM UTC 24 |
| Peak memory | 206464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2652190237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 10.aon_timer_stress_all_with_rand_reset.2652190237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.3724426274 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 35885196881 ps |
| CPU time | 26.67 seconds |
| Started | Sep 04 01:33:56 PM UTC 24 |
| Finished | Sep 04 01:34:24 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724426274 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.3724426274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.4256871106 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 104483418683 ps |
| CPU time | 248.04 seconds |
| Started | Sep 04 01:33:26 PM UTC 24 |
| Finished | Sep 04 01:37:38 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256871106 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.4256871106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.2087279189 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 189074201300 ps |
| CPU time | 154.18 seconds |
| Started | Sep 04 01:34:28 PM UTC 24 |
| Finished | Sep 04 01:37:06 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087279189 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.2087279189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.1494142954 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 117116942681 ps |
| CPU time | 51.38 seconds |
| Started | Sep 04 01:36:17 PM UTC 24 |
| Finished | Sep 04 01:37:10 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494142954 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.1494142954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/31.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.3073600302 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7904193899 ps |
| CPU time | 17.91 seconds |
| Started | Sep 04 01:32:31 PM UTC 24 |
| Finished | Sep 04 01:32:50 PM UTC 24 |
| Peak memory | 206052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3073600302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.aon_timer_stress_all_with_rand_reset.3073600302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.3923229079 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 176237645184 ps |
| CPU time | 59.71 seconds |
| Started | Sep 04 01:37:02 PM UTC 24 |
| Finished | Sep 04 01:38:03 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923229079 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.3923229079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/38.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.2469499562 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 223011441938 ps |
| CPU time | 117.86 seconds |
| Started | Sep 04 01:38:00 PM UTC 24 |
| Finished | Sep 04 01:40:00 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469499562 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.2469499562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/49.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.1961236041 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 101690940567 ps |
| CPU time | 180.96 seconds |
| Started | Sep 04 01:33:09 PM UTC 24 |
| Finished | Sep 04 01:36:13 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961236041 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.1961236041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.2243782698 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 275812171745 ps |
| CPU time | 479.62 seconds |
| Started | Sep 04 01:32:31 PM UTC 24 |
| Finished | Sep 04 01:40:37 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243782698 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.2243782698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.2743035348 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 11253770401 ps |
| CPU time | 26.46 seconds |
| Started | Sep 04 01:35:03 PM UTC 24 |
| Finished | Sep 04 01:35:31 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743035348 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.2743035348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/20.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.1791697457 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 10917283383 ps |
| CPU time | 26.65 seconds |
| Started | Sep 04 01:36:21 PM UTC 24 |
| Finished | Sep 04 01:36:49 PM UTC 24 |
| Peak memory | 206524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1791697457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 32.aon_timer_stress_all_with_rand_reset.1791697457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.1493747948 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 336915972073 ps |
| CPU time | 598.95 seconds |
| Started | Sep 04 01:37:12 PM UTC 24 |
| Finished | Sep 04 01:47:18 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493747948 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.1493747948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/39.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.543807393 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 420602712 ps |
| CPU time | 1.27 seconds |
| Started | Sep 04 01:30:47 PM UTC 24 |
| Finished | Sep 04 01:30:49 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543807393 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.543807393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3451750226 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2490024849 ps |
| CPU time | 8.41 seconds |
| Started | Sep 04 01:30:51 PM UTC 24 |
| Finished | Sep 04 01:31:00 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451750226 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.3451750226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.1329919143 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 11467023510 ps |
| CPU time | 46.74 seconds |
| Started | Sep 04 01:34:04 PM UTC 24 |
| Finished | Sep 04 01:34:52 PM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1329919143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 13.aon_timer_stress_all_with_rand_reset.1329919143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.870183678 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 367317937784 ps |
| CPU time | 214.65 seconds |
| Started | Sep 04 01:32:39 PM UTC 24 |
| Finished | Sep 04 01:36:17 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870183678 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.870183678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.2175847442 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3478655916 ps |
| CPU time | 22.88 seconds |
| Started | Sep 04 01:36:47 PM UTC 24 |
| Finished | Sep 04 01:37:11 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2175847442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 35.aon_timer_stress_all_with_rand_reset.2175847442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.2432232373 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1875802496 ps |
| CPU time | 11.44 seconds |
| Started | Sep 04 01:37:11 PM UTC 24 |
| Finished | Sep 04 01:37:24 PM UTC 24 |
| Peak memory | 206340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2432232373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 39.aon_timer_stress_all_with_rand_reset.2432232373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.1350338580 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 235508009657 ps |
| CPU time | 288.82 seconds |
| Started | Sep 04 01:33:02 PM UTC 24 |
| Finished | Sep 04 01:37:55 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350338580 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.1350338580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.2325033659 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 113020771083 ps |
| CPU time | 103.53 seconds |
| Started | Sep 04 01:35:41 PM UTC 24 |
| Finished | Sep 04 01:37:26 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325033659 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.2325033659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/25.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.647578455 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 445128863301 ps |
| CPU time | 186.19 seconds |
| Started | Sep 04 01:36:56 PM UTC 24 |
| Finished | Sep 04 01:40:05 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647578455 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.647578455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/37.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.1358440557 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 393915089 ps |
| CPU time | 2.11 seconds |
| Started | Sep 04 01:34:08 PM UTC 24 |
| Finished | Sep 04 01:34:11 PM UTC 24 |
| Peak memory | 200840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358440557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1358440557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.2345479654 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 437771919 ps |
| CPU time | 1 seconds |
| Started | Sep 04 01:32:34 PM UTC 24 |
| Finished | Sep 04 01:32:36 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345479654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2345479654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.2230222904 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3060480650 ps |
| CPU time | 18.83 seconds |
| Started | Sep 04 01:35:38 PM UTC 24 |
| Finished | Sep 04 01:35:58 PM UTC 24 |
| Peak memory | 206580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2230222904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 25.aon_timer_stress_all_with_rand_reset.2230222904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.1129701364 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 3866845196 ps |
| CPU time | 23.49 seconds |
| Started | Sep 04 01:35:50 PM UTC 24 |
| Finished | Sep 04 01:36:15 PM UTC 24 |
| Peak memory | 206576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1129701364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 27.aon_timer_stress_all_with_rand_reset.1129701364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.3139677791 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 60644393286 ps |
| CPU time | 130.45 seconds |
| Started | Sep 04 01:37:16 PM UTC 24 |
| Finished | Sep 04 01:39:29 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139677791 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.3139677791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/40.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.3241926169 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 506920473 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 01:37:22 PM UTC 24 |
| Finished | Sep 04 01:37:24 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241926169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3241926169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/41.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.460282322 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 543286942 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:37:25 PM UTC 24 |
| Finished | Sep 04 01:37:28 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460282322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.460282322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/42.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.2501570433 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 11169937584 ps |
| CPU time | 20.77 seconds |
| Started | Sep 04 01:37:38 PM UTC 24 |
| Finished | Sep 04 01:38:00 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501570433 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.2501570433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/44.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.502097069 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 427022056 ps |
| CPU time | 1.61 seconds |
| Started | Sep 04 01:33:40 PM UTC 24 |
| Finished | Sep 04 01:33:43 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502097069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.502097069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.2637410010 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 449492628 ps |
| CPU time | 1.28 seconds |
| Started | Sep 04 01:35:16 PM UTC 24 |
| Finished | Sep 04 01:35:19 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637410010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2637410010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/22.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.3325016350 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 373347786 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 01:35:24 PM UTC 24 |
| Finished | Sep 04 01:35:26 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325016350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3325016350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/23.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.4236123696 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 343446825 ps |
| CPU time | 1.96 seconds |
| Started | Sep 04 01:32:48 PM UTC 24 |
| Finished | Sep 04 01:32:51 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236123696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.4236123696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.291054153 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 489398561 ps |
| CPU time | 1.86 seconds |
| Started | Sep 04 01:37:56 PM UTC 24 |
| Finished | Sep 04 01:37:59 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291054153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.291054153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/48.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.792560178 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2191382314 ps |
| CPU time | 24.63 seconds |
| Started | Sep 04 01:33:18 PM UTC 24 |
| Finished | Sep 04 01:33:44 PM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=792560178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 7.aon_timer_stress_all_with_rand_reset.792560178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.3143476870 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 492239605 ps |
| CPU time | 2.62 seconds |
| Started | Sep 04 01:35:30 PM UTC 24 |
| Finished | Sep 04 01:35:34 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143476870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3143476870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/24.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.2826465092 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 397540668 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 01:35:49 PM UTC 24 |
| Finished | Sep 04 01:35:51 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826465092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2826465092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/27.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.745990750 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3889968901 ps |
| CPU time | 25.36 seconds |
| Started | Sep 04 01:35:56 PM UTC 24 |
| Finished | Sep 04 01:36:23 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=745990750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.aon_timer_stress_all_with_rand_reset.745990750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.63774074 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 139793597977 ps |
| CPU time | 233.82 seconds |
| Started | Sep 04 01:36:05 PM UTC 24 |
| Finished | Sep 04 01:40:02 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63774074 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.63774074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/29.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.1410744836 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 483744312851 ps |
| CPU time | 202.19 seconds |
| Started | Sep 04 01:36:43 PM UTC 24 |
| Finished | Sep 04 01:40:08 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410744836 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.1410744836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/34.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.631452836 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 250949399315 ps |
| CPU time | 186.31 seconds |
| Started | Sep 04 01:36:52 PM UTC 24 |
| Finished | Sep 04 01:40:01 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631452836 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.631452836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/36.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.366189949 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2667793573 ps |
| CPU time | 25.2 seconds |
| Started | Sep 04 01:33:00 PM UTC 24 |
| Finished | Sep 04 01:33:26 PM UTC 24 |
| Peak memory | 216560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=366189949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.aon_timer_stress_all_with_rand_reset.366189949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.3774176031 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1634887101 ps |
| CPU time | 15.26 seconds |
| Started | Sep 04 01:33:34 PM UTC 24 |
| Finished | Sep 04 01:33:51 PM UTC 24 |
| Peak memory | 206628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3774176031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.aon_timer_stress_all_with_rand_reset.3774176031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.1179135584 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 366380796 ps |
| CPU time | 1.93 seconds |
| Started | Sep 04 01:36:50 PM UTC 24 |
| Finished | Sep 04 01:36:53 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179135584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1179135584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/36.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.308967915 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 385129270 ps |
| CPU time | 1.81 seconds |
| Started | Sep 04 01:36:54 PM UTC 24 |
| Finished | Sep 04 01:36:57 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308967915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.308967915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/37.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.3106291405 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 517958627 ps |
| CPU time | 1.39 seconds |
| Started | Sep 04 01:37:15 PM UTC 24 |
| Finished | Sep 04 01:37:18 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106291405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3106291405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/40.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.2759223296 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 197299307931 ps |
| CPU time | 82.47 seconds |
| Started | Sep 04 01:37:30 PM UTC 24 |
| Finished | Sep 04 01:38:55 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759223296 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.2759223296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/43.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.3868729533 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 352927937 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 01:37:36 PM UTC 24 |
| Finished | Sep 04 01:37:38 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868729533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3868729533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/44.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.1714340854 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1454053874 ps |
| CPU time | 13.22 seconds |
| Started | Sep 04 01:37:57 PM UTC 24 |
| Finished | Sep 04 01:38:11 PM UTC 24 |
| Peak memory | 201176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1714340854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 48.aon_timer_stress_all_with_rand_reset.1714340854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.2547585198 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1935316675 ps |
| CPU time | 8.89 seconds |
| Started | Sep 04 01:34:33 PM UTC 24 |
| Finished | Sep 04 01:34:43 PM UTC 24 |
| Peak memory | 217048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2547585198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 16.aon_timer_stress_all_with_rand_reset.2547585198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.2205265501 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 509682293 ps |
| CPU time | 1.29 seconds |
| Started | Sep 04 01:35:37 PM UTC 24 |
| Finished | Sep 04 01:35:40 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205265501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2205265501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/25.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.1229867630 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1514069229 ps |
| CPU time | 9.67 seconds |
| Started | Sep 04 01:36:02 PM UTC 24 |
| Finished | Sep 04 01:36:13 PM UTC 24 |
| Peak memory | 206412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1229867630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 29.aon_timer_stress_all_with_rand_reset.1229867630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.1829204815 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 456773298 ps |
| CPU time | 1.51 seconds |
| Started | Sep 04 01:36:21 PM UTC 24 |
| Finished | Sep 04 01:36:23 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829204815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1829204815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/32.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.1463424727 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 53730225324 ps |
| CPU time | 45.9 seconds |
| Started | Sep 04 01:33:19 PM UTC 24 |
| Finished | Sep 04 01:34:07 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463424727 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.1463424727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.2720310232 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2816425688 ps |
| CPU time | 29.85 seconds |
| Started | Sep 04 01:32:34 PM UTC 24 |
| Finished | Sep 04 01:33:05 PM UTC 24 |
| Peak memory | 206716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2720310232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.aon_timer_stress_all_with_rand_reset.2720310232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.2387503979 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 4474498543 ps |
| CPU time | 10.37 seconds |
| Started | Sep 04 01:35:31 PM UTC 24 |
| Finished | Sep 04 01:35:43 PM UTC 24 |
| Peak memory | 216700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2387503979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 24.aon_timer_stress_all_with_rand_reset.2387503979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.3124643639 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 531675226 ps |
| CPU time | 1.41 seconds |
| Started | Sep 04 01:35:54 PM UTC 24 |
| Finished | Sep 04 01:35:57 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124643639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3124643639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/28.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.1411304559 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 7830385180 ps |
| CPU time | 19.72 seconds |
| Started | Sep 04 01:36:17 PM UTC 24 |
| Finished | Sep 04 01:36:38 PM UTC 24 |
| Peak memory | 206688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1411304559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 31.aon_timer_stress_all_with_rand_reset.1411304559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.281387879 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 278760576191 ps |
| CPU time | 299.07 seconds |
| Started | Sep 04 01:36:22 PM UTC 24 |
| Finished | Sep 04 01:41:26 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281387879 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.281387879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/32.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.2095381003 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 6170140610 ps |
| CPU time | 15.46 seconds |
| Started | Sep 04 01:37:01 PM UTC 24 |
| Finished | Sep 04 01:37:17 PM UTC 24 |
| Peak memory | 206488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2095381003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 38.aon_timer_stress_all_with_rand_reset.2095381003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.4087594288 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1097075162 ps |
| CPU time | 11.5 seconds |
| Started | Sep 04 01:37:22 PM UTC 24 |
| Finished | Sep 04 01:37:34 PM UTC 24 |
| Peak memory | 206460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4087594288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 41.aon_timer_stress_all_with_rand_reset.4087594288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.2318196395 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 526706700 ps |
| CPU time | 2.75 seconds |
| Started | Sep 04 01:37:46 PM UTC 24 |
| Finished | Sep 04 01:37:50 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318196395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2318196395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/46.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.263198414 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 574255295 ps |
| CPU time | 1.95 seconds |
| Started | Sep 04 01:32:59 PM UTC 24 |
| Finished | Sep 04 01:33:02 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263198414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.263198414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.1695882708 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3317647462 ps |
| CPU time | 33.81 seconds |
| Started | Sep 04 01:33:24 PM UTC 24 |
| Finished | Sep 04 01:33:59 PM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1695882708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 8.aon_timer_stress_all_with_rand_reset.1695882708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3316493173 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 8417066621 ps |
| CPU time | 19.88 seconds |
| Started | Sep 04 01:31:17 PM UTC 24 |
| Finished | Sep 04 01:31:38 PM UTC 24 |
| Peak memory | 206908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316493173 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.3316493173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.3796447907 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 603397160 ps |
| CPU time | 1.69 seconds |
| Started | Sep 04 01:34:01 PM UTC 24 |
| Finished | Sep 04 01:34:03 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796447907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3796447907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.3445293492 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 627311264 ps |
| CPU time | 1.66 seconds |
| Started | Sep 04 01:34:25 PM UTC 24 |
| Finished | Sep 04 01:34:28 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445293492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3445293492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.176954423 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 512949939 ps |
| CPU time | 2.41 seconds |
| Started | Sep 04 01:34:48 PM UTC 24 |
| Finished | Sep 04 01:34:52 PM UTC 24 |
| Peak memory | 200644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176954423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.176954423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.1538378304 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 585407221 ps |
| CPU time | 1.66 seconds |
| Started | Sep 04 01:35:02 PM UTC 24 |
| Finished | Sep 04 01:35:05 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538378304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1538378304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/20.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.3435039709 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 609915874 ps |
| CPU time | 2.6 seconds |
| Started | Sep 04 01:36:01 PM UTC 24 |
| Finished | Sep 04 01:36:04 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435039709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3435039709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/29.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.4201433318 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 612605812 ps |
| CPU time | 2.42 seconds |
| Started | Sep 04 01:36:13 PM UTC 24 |
| Finished | Sep 04 01:36:17 PM UTC 24 |
| Peak memory | 200840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201433318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4201433318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/30.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.3393235686 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 690107984 ps |
| CPU time | 1 seconds |
| Started | Sep 04 01:36:28 PM UTC 24 |
| Finished | Sep 04 01:36:30 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393235686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3393235686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/33.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.1332192526 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 142013301599 ps |
| CPU time | 52.26 seconds |
| Started | Sep 04 01:36:49 PM UTC 24 |
| Finished | Sep 04 01:37:43 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332192526 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.1332192526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/35.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.78300751 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 8216394120 ps |
| CPU time | 13.97 seconds |
| Started | Sep 04 01:36:54 PM UTC 24 |
| Finished | Sep 04 01:37:10 PM UTC 24 |
| Peak memory | 205376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=78300751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 37.aon_timer_stress_all_with_rand_reset.78300751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.3494975176 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 544701409 ps |
| CPU time | 2.77 seconds |
| Started | Sep 04 01:36:58 PM UTC 24 |
| Finished | Sep 04 01:37:01 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494975176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3494975176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/38.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.1103752886 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 576685156 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 01:37:10 PM UTC 24 |
| Finished | Sep 04 01:37:12 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103752886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1103752886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/39.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.4236800526 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 578529848 ps |
| CPU time | 1.76 seconds |
| Started | Sep 04 01:37:28 PM UTC 24 |
| Finished | Sep 04 01:37:31 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236800526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4236800526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/43.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.1006124144 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 415352780 ps |
| CPU time | 2.19 seconds |
| Started | Sep 04 01:37:51 PM UTC 24 |
| Finished | Sep 04 01:37:54 PM UTC 24 |
| Peak memory | 200572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006124144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1006124144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/47.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.3164721309 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 448135233 ps |
| CPU time | 1.94 seconds |
| Started | Sep 04 01:33:47 PM UTC 24 |
| Finished | Sep 04 01:33:50 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164721309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3164721309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.2846847082 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 538530552 ps |
| CPU time | 1.35 seconds |
| Started | Sep 04 01:33:53 PM UTC 24 |
| Finished | Sep 04 01:33:56 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846847082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2846847082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.426836603 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 490846918 ps |
| CPU time | 1.5 seconds |
| Started | Sep 04 01:34:52 PM UTC 24 |
| Finished | Sep 04 01:34:55 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426836603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.426836603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.511197029 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 518568504 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 01:35:10 PM UTC 24 |
| Finished | Sep 04 01:35:13 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511197029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.511197029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/21.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.2228671218 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4572505477 ps |
| CPU time | 17 seconds |
| Started | Sep 04 01:35:12 PM UTC 24 |
| Finished | Sep 04 01:35:31 PM UTC 24 |
| Peak memory | 206552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2228671218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 21.aon_timer_stress_all_with_rand_reset.2228671218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.3859708675 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 577865544 ps |
| CPU time | 2.52 seconds |
| Started | Sep 04 01:35:44 PM UTC 24 |
| Finished | Sep 04 01:35:47 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859708675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3859708675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/26.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.2489506960 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 474279998 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 01:32:37 PM UTC 24 |
| Finished | Sep 04 01:32:39 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489506960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2489506960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.747087351 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 610769352 ps |
| CPU time | 1.33 seconds |
| Started | Sep 04 01:36:17 PM UTC 24 |
| Finished | Sep 04 01:36:20 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747087351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.747087351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/31.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.3094805762 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 374808755 ps |
| CPU time | 1.59 seconds |
| Started | Sep 04 01:36:47 PM UTC 24 |
| Finished | Sep 04 01:36:49 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094805762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3094805762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/35.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.3227781116 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2308961699 ps |
| CPU time | 25.93 seconds |
| Started | Sep 04 01:37:37 PM UTC 24 |
| Finished | Sep 04 01:38:04 PM UTC 24 |
| Peak memory | 216964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3227781116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 44.aon_timer_stress_all_with_rand_reset.3227781116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.267073525 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 578312268 ps |
| CPU time | 2.74 seconds |
| Started | Sep 04 01:37:42 PM UTC 24 |
| Finished | Sep 04 01:37:46 PM UTC 24 |
| Peak memory | 200644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267073525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.267073525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/45.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.3382295477 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 14957134709 ps |
| CPU time | 14.82 seconds |
| Started | Sep 04 01:37:46 PM UTC 24 |
| Finished | Sep 04 01:38:02 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3382295477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 46.aon_timer_stress_all_with_rand_reset.3382295477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.3767813341 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 341895599 ps |
| CPU time | 1.85 seconds |
| Started | Sep 04 01:33:16 PM UTC 24 |
| Finished | Sep 04 01:33:18 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767813341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3767813341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.2006080920 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 153631543066 ps |
| CPU time | 80.91 seconds |
| Started | Sep 04 01:34:04 PM UTC 24 |
| Finished | Sep 04 01:35:26 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006080920 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.2006080920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.3691787042 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 129014430425 ps |
| CPU time | 154.31 seconds |
| Started | Sep 04 01:34:20 PM UTC 24 |
| Finished | Sep 04 01:36:57 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691787042 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.3691787042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.2336910009 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 452870699 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 01:34:31 PM UTC 24 |
| Finished | Sep 04 01:34:34 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336910009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2336910009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.2141018320 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 7223133254 ps |
| CPU time | 18.93 seconds |
| Started | Sep 04 01:36:31 PM UTC 24 |
| Finished | Sep 04 01:36:51 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2141018320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 33.aon_timer_stress_all_with_rand_reset.2141018320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.1037195899 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 445212163 ps |
| CPU time | 0.99 seconds |
| Started | Sep 04 01:36:39 PM UTC 24 |
| Finished | Sep 04 01:36:42 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037195899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1037195899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/34.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.1869182158 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 302508271656 ps |
| CPU time | 50.23 seconds |
| Started | Sep 04 01:32:53 PM UTC 24 |
| Finished | Sep 04 01:33:44 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869182158 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.1869182158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.1876104559 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 473220799 ps |
| CPU time | 2.46 seconds |
| Started | Sep 04 01:37:59 PM UTC 24 |
| Finished | Sep 04 01:38:03 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876104559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1876104559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/49.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.1375442195 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 427137900 ps |
| CPU time | 2.2 seconds |
| Started | Sep 04 01:33:22 PM UTC 24 |
| Finished | Sep 04 01:33:25 PM UTC 24 |
| Peak memory | 200568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375442195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1375442195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.1906604656 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 583749115 ps |
| CPU time | 1.02 seconds |
| Started | Sep 04 01:33:32 PM UTC 24 |
| Finished | Sep 04 01:33:34 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906604656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1906604656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3172729115 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 7186664806 ps |
| CPU time | 19.05 seconds |
| Started | Sep 04 01:30:50 PM UTC 24 |
| Finished | Sep 04 01:31:10 PM UTC 24 |
| Peak memory | 205856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172729115 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.3172729115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.223791298 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 962735232 ps |
| CPU time | 3.69 seconds |
| Started | Sep 04 01:30:46 PM UTC 24 |
| Finished | Sep 04 01:30:50 PM UTC 24 |
| Peak memory | 203248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223791298 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.223791298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2792456306 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 510034277 ps |
| CPU time | 1.69 seconds |
| Started | Sep 04 01:30:54 PM UTC 24 |
| Finished | Sep 04 01:30:57 PM UTC 24 |
| Peak memory | 206952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2792456306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim er_csr_mem_rw_with_rand_reset.2792456306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.1830474899 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 365261718 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 01:30:35 PM UTC 24 |
| Finished | Sep 04 01:30:38 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830474899 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1830474899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1908245894 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 278457279 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 01:30:42 PM UTC 24 |
| Finished | Sep 04 01:30:44 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908245894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.1908245894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.713279906 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 354122956 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 01:30:39 PM UTC 24 |
| Finished | Sep 04 01:30:40 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713279906 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.713279906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.492746406 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 591789706 ps |
| CPU time | 5.7 seconds |
| Started | Sep 04 01:30:28 PM UTC 24 |
| Finished | Sep 04 01:30:35 PM UTC 24 |
| Peak memory | 207172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492746406 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.492746406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2342337142 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 678994160 ps |
| CPU time | 1.54 seconds |
| Started | Sep 04 01:31:14 PM UTC 24 |
| Finished | Sep 04 01:31:16 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342337142 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.2342337142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2590529000 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 464444139 ps |
| CPU time | 3.08 seconds |
| Started | Sep 04 01:31:13 PM UTC 24 |
| Finished | Sep 04 01:31:17 PM UTC 24 |
| Peak memory | 205528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590529000 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.2590529000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3302398262 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 779752356 ps |
| CPU time | 1.46 seconds |
| Started | Sep 04 01:31:10 PM UTC 24 |
| Finished | Sep 04 01:31:13 PM UTC 24 |
| Peak memory | 199736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302398262 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.3302398262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2545540190 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 403270063 ps |
| CPU time | 1.35 seconds |
| Started | Sep 04 01:31:16 PM UTC 24 |
| Finished | Sep 04 01:31:18 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2545540190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim er_csr_mem_rw_with_rand_reset.2545540190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.1303012918 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 433499500 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 01:31:12 PM UTC 24 |
| Finished | Sep 04 01:31:14 PM UTC 24 |
| Peak memory | 201896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303012918 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1303012918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.2910597196 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 387304081 ps |
| CPU time | 1.4 seconds |
| Started | Sep 04 01:31:03 PM UTC 24 |
| Finished | Sep 04 01:31:06 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910597196 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2910597196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.344515171 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 435617466 ps |
| CPU time | 1.52 seconds |
| Started | Sep 04 01:31:09 PM UTC 24 |
| Finished | Sep 04 01:31:12 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344515171 -assert nopostproc + UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.344515171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3251772917 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 428834500 ps |
| CPU time | 1 seconds |
| Started | Sep 04 01:31:06 PM UTC 24 |
| Finished | Sep 04 01:31:08 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251772917 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.3251772917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2723702607 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1902994300 ps |
| CPU time | 3.36 seconds |
| Started | Sep 04 01:31:15 PM UTC 24 |
| Finished | Sep 04 01:31:19 PM UTC 24 |
| Peak memory | 205624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723702607 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.2723702607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.717367279 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 576905108 ps |
| CPU time | 4.34 seconds |
| Started | Sep 04 01:30:57 PM UTC 24 |
| Finished | Sep 04 01:31:02 PM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717367279 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.717367279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3228355478 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4005944797 ps |
| CPU time | 8.48 seconds |
| Started | Sep 04 01:31:01 PM UTC 24 |
| Finished | Sep 04 01:31:11 PM UTC 24 |
| Peak memory | 206648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228355478 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.3228355478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1795522697 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 343414186 ps |
| CPU time | 1.94 seconds |
| Started | Sep 04 01:31:56 PM UTC 24 |
| Finished | Sep 04 01:31:59 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1795522697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_ti mer_csr_mem_rw_with_rand_reset.1795522697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.707792606 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 467459825 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 01:31:55 PM UTC 24 |
| Finished | Sep 04 01:31:57 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707792606 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.707792606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.3417728173 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 424155681 ps |
| CPU time | 1.61 seconds |
| Started | Sep 04 01:31:55 PM UTC 24 |
| Finished | Sep 04 01:31:58 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417728173 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3417728173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1302470593 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1777344771 ps |
| CPU time | 2.79 seconds |
| Started | Sep 04 01:31:56 PM UTC 24 |
| Finished | Sep 04 01:32:00 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302470593 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.1302470593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.4154705236 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 385323300 ps |
| CPU time | 3.8 seconds |
| Started | Sep 04 01:31:54 PM UTC 24 |
| Finished | Sep 04 01:31:59 PM UTC 24 |
| Peak memory | 207024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154705236 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4154705236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3365294440 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 8102546199 ps |
| CPU time | 25.48 seconds |
| Started | Sep 04 01:31:55 PM UTC 24 |
| Finished | Sep 04 01:32:22 PM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365294440 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.3365294440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1723951435 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 415737738 ps |
| CPU time | 1.32 seconds |
| Started | Sep 04 01:31:58 PM UTC 24 |
| Finished | Sep 04 01:32:01 PM UTC 24 |
| Peak memory | 205296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1723951435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_ti mer_csr_mem_rw_with_rand_reset.1723951435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.2026014760 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 483901604 ps |
| CPU time | 1 seconds |
| Started | Sep 04 01:31:57 PM UTC 24 |
| Finished | Sep 04 01:31:59 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026014760 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2026014760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.828318841 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 438809166 ps |
| CPU time | 2.2 seconds |
| Started | Sep 04 01:31:57 PM UTC 24 |
| Finished | Sep 04 01:32:01 PM UTC 24 |
| Peak memory | 201468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828318841 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.828318841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3256157297 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1097435885 ps |
| CPU time | 1.69 seconds |
| Started | Sep 04 01:31:57 PM UTC 24 |
| Finished | Sep 04 01:32:00 PM UTC 24 |
| Peak memory | 201964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256157297 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.3256157297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.777393133 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 361993732 ps |
| CPU time | 1.62 seconds |
| Started | Sep 04 01:31:56 PM UTC 24 |
| Finished | Sep 04 01:31:59 PM UTC 24 |
| Peak memory | 206888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777393133 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.777393133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3403947320 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4591893984 ps |
| CPU time | 8.29 seconds |
| Started | Sep 04 01:31:57 PM UTC 24 |
| Finished | Sep 04 01:32:07 PM UTC 24 |
| Peak memory | 206668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403947320 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.3403947320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4272513119 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 560483414 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 01:32:01 PM UTC 24 |
| Finished | Sep 04 01:32:03 PM UTC 24 |
| Peak memory | 205268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4272513119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_ti mer_csr_mem_rw_with_rand_reset.4272513119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.3667740285 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 318551292 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 01:32:00 PM UTC 24 |
| Finished | Sep 04 01:32:02 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667740285 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3667740285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.1621128907 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 504810123 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 01:31:59 PM UTC 24 |
| Finished | Sep 04 01:32:02 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621128907 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1621128907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3539263898 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1953031537 ps |
| CPU time | 5.2 seconds |
| Started | Sep 04 01:32:01 PM UTC 24 |
| Finished | Sep 04 01:32:07 PM UTC 24 |
| Peak memory | 205368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539263898 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.3539263898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.1129621826 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 531274958 ps |
| CPU time | 3.25 seconds |
| Started | Sep 04 01:31:58 PM UTC 24 |
| Finished | Sep 04 01:32:03 PM UTC 24 |
| Peak memory | 207040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129621826 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1129621826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3654312759 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 7934266065 ps |
| CPU time | 7.62 seconds |
| Started | Sep 04 01:31:59 PM UTC 24 |
| Finished | Sep 04 01:32:08 PM UTC 24 |
| Peak memory | 207004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654312759 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.3654312759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1916699067 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 372860694 ps |
| CPU time | 2.21 seconds |
| Started | Sep 04 01:32:03 PM UTC 24 |
| Finished | Sep 04 01:32:06 PM UTC 24 |
| Peak memory | 205752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1916699067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti mer_csr_mem_rw_with_rand_reset.1916699067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.1746017255 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 470280453 ps |
| CPU time | 1.96 seconds |
| Started | Sep 04 01:32:02 PM UTC 24 |
| Finished | Sep 04 01:32:05 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746017255 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1746017255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1456719687 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 504758527 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 01:32:02 PM UTC 24 |
| Finished | Sep 04 01:32:04 PM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456719687 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1456719687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2077256859 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1293586928 ps |
| CPU time | 4.99 seconds |
| Started | Sep 04 01:32:02 PM UTC 24 |
| Finished | Sep 04 01:32:08 PM UTC 24 |
| Peak memory | 203308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077256859 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.2077256859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.201715919 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1240788628 ps |
| CPU time | 2.7 seconds |
| Started | Sep 04 01:32:01 PM UTC 24 |
| Finished | Sep 04 01:32:04 PM UTC 24 |
| Peak memory | 207144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201715919 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.201715919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4241900351 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 8417506535 ps |
| CPU time | 24.25 seconds |
| Started | Sep 04 01:32:01 PM UTC 24 |
| Finished | Sep 04 01:32:26 PM UTC 24 |
| Peak memory | 206828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241900351 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.4241900351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.628674441 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 422775729 ps |
| CPU time | 1.27 seconds |
| Started | Sep 04 01:32:05 PM UTC 24 |
| Finished | Sep 04 01:32:08 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=628674441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_tim er_csr_mem_rw_with_rand_reset.628674441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2965097522 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 551789266 ps |
| CPU time | 1.43 seconds |
| Started | Sep 04 01:32:05 PM UTC 24 |
| Finished | Sep 04 01:32:08 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965097522 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2965097522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.1237232073 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 576912126 ps |
| CPU time | 0.95 seconds |
| Started | Sep 04 01:32:04 PM UTC 24 |
| Finished | Sep 04 01:32:06 PM UTC 24 |
| Peak memory | 199652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237232073 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1237232073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4274261749 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2932925681 ps |
| CPU time | 10.19 seconds |
| Started | Sep 04 01:32:05 PM UTC 24 |
| Finished | Sep 04 01:32:17 PM UTC 24 |
| Peak memory | 205424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274261749 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.4274261749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.857149684 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 654123224 ps |
| CPU time | 2.49 seconds |
| Started | Sep 04 01:32:03 PM UTC 24 |
| Finished | Sep 04 01:32:06 PM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857149684 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.857149684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4110677798 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 8170541255 ps |
| CPU time | 15.45 seconds |
| Started | Sep 04 01:32:04 PM UTC 24 |
| Finished | Sep 04 01:32:21 PM UTC 24 |
| Peak memory | 207180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110677798 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.4110677798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3223960342 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 484088733 ps |
| CPU time | 1.36 seconds |
| Started | Sep 04 01:32:09 PM UTC 24 |
| Finished | Sep 04 01:32:11 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3223960342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti mer_csr_mem_rw_with_rand_reset.3223960342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.206554776 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 512766516 ps |
| CPU time | 2.38 seconds |
| Started | Sep 04 01:32:08 PM UTC 24 |
| Finished | Sep 04 01:32:11 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206554776 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.206554776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.860997038 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 298781969 ps |
| CPU time | 1.26 seconds |
| Started | Sep 04 01:32:08 PM UTC 24 |
| Finished | Sep 04 01:32:10 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860997038 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.860997038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1783709936 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1301831718 ps |
| CPU time | 2.11 seconds |
| Started | Sep 04 01:32:08 PM UTC 24 |
| Finished | Sep 04 01:32:11 PM UTC 24 |
| Peak memory | 203512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783709936 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.1783709936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.2879486037 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 706707668 ps |
| CPU time | 4.03 seconds |
| Started | Sep 04 01:32:06 PM UTC 24 |
| Finished | Sep 04 01:32:12 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879486037 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2879486037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1292611626 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 7905613179 ps |
| CPU time | 21.98 seconds |
| Started | Sep 04 01:32:08 PM UTC 24 |
| Finished | Sep 04 01:32:31 PM UTC 24 |
| Peak memory | 206988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292611626 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.1292611626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1291977650 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 523803928 ps |
| CPU time | 2.62 seconds |
| Started | Sep 04 01:32:12 PM UTC 24 |
| Finished | Sep 04 01:32:16 PM UTC 24 |
| Peak memory | 204524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1291977650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti mer_csr_mem_rw_with_rand_reset.1291977650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.3829842129 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 409662761 ps |
| CPU time | 2.14 seconds |
| Started | Sep 04 01:32:09 PM UTC 24 |
| Finished | Sep 04 01:32:12 PM UTC 24 |
| Peak memory | 203444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829842129 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3829842129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.1364824817 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 519551613 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 01:32:09 PM UTC 24 |
| Finished | Sep 04 01:32:11 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364824817 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1364824817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2823637719 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2314370803 ps |
| CPU time | 11.47 seconds |
| Started | Sep 04 01:32:11 PM UTC 24 |
| Finished | Sep 04 01:32:24 PM UTC 24 |
| Peak memory | 205496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823637719 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.2823637719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.3523394348 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 367078781 ps |
| CPU time | 3.72 seconds |
| Started | Sep 04 01:32:09 PM UTC 24 |
| Finished | Sep 04 01:32:13 PM UTC 24 |
| Peak memory | 206964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523394348 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3523394348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1098387705 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 4598005085 ps |
| CPU time | 5.26 seconds |
| Started | Sep 04 01:32:09 PM UTC 24 |
| Finished | Sep 04 01:32:15 PM UTC 24 |
| Peak memory | 206752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098387705 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.1098387705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3947996786 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 323415288 ps |
| CPU time | 1.47 seconds |
| Started | Sep 04 01:32:14 PM UTC 24 |
| Finished | Sep 04 01:32:17 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3947996786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti mer_csr_mem_rw_with_rand_reset.3947996786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.4224946646 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 410492012 ps |
| CPU time | 2.14 seconds |
| Started | Sep 04 01:32:12 PM UTC 24 |
| Finished | Sep 04 01:32:15 PM UTC 24 |
| Peak memory | 203444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224946646 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.4224946646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.2364563010 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 390013642 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 01:32:12 PM UTC 24 |
| Finished | Sep 04 01:32:14 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364563010 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2364563010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.416858488 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2219591232 ps |
| CPU time | 4.16 seconds |
| Started | Sep 04 01:32:13 PM UTC 24 |
| Finished | Sep 04 01:32:19 PM UTC 24 |
| Peak memory | 205420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416858488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.416858488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.1604513608 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 885726406 ps |
| CPU time | 2.71 seconds |
| Started | Sep 04 01:32:12 PM UTC 24 |
| Finished | Sep 04 01:32:16 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604513608 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1604513608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.522017886 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 8458830889 ps |
| CPU time | 7.7 seconds |
| Started | Sep 04 01:32:12 PM UTC 24 |
| Finished | Sep 04 01:32:21 PM UTC 24 |
| Peak memory | 206060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522017886 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.522017886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1586085985 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 413844804 ps |
| CPU time | 2.31 seconds |
| Started | Sep 04 01:32:18 PM UTC 24 |
| Finished | Sep 04 01:32:21 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1586085985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_ti mer_csr_mem_rw_with_rand_reset.1586085985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.1160575966 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 388026362 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 01:32:17 PM UTC 24 |
| Finished | Sep 04 01:32:19 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160575966 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1160575966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.383104439 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 340812015 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 01:32:17 PM UTC 24 |
| Finished | Sep 04 01:32:19 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383104439 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.383104439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.18831637 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1974439061 ps |
| CPU time | 1.39 seconds |
| Started | Sep 04 01:32:17 PM UTC 24 |
| Finished | Sep 04 01:32:19 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18831637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.18831637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.3466421126 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 513509382 ps |
| CPU time | 2.85 seconds |
| Started | Sep 04 01:32:15 PM UTC 24 |
| Finished | Sep 04 01:32:19 PM UTC 24 |
| Peak memory | 207028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466421126 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3466421126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1616269717 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 8324506945 ps |
| CPU time | 16.67 seconds |
| Started | Sep 04 01:32:17 PM UTC 24 |
| Finished | Sep 04 01:32:34 PM UTC 24 |
| Peak memory | 206920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616269717 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.1616269717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2639948581 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 372374444 ps |
| CPU time | 1.75 seconds |
| Started | Sep 04 01:32:20 PM UTC 24 |
| Finished | Sep 04 01:32:23 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2639948581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti mer_csr_mem_rw_with_rand_reset.2639948581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.2988404902 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 374165934 ps |
| CPU time | 1.01 seconds |
| Started | Sep 04 01:32:20 PM UTC 24 |
| Finished | Sep 04 01:32:22 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988404902 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2988404902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.3501739644 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 433126575 ps |
| CPU time | 1.43 seconds |
| Started | Sep 04 01:32:20 PM UTC 24 |
| Finished | Sep 04 01:32:22 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501739644 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3501739644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3076372103 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2499834712 ps |
| CPU time | 5.05 seconds |
| Started | Sep 04 01:32:20 PM UTC 24 |
| Finished | Sep 04 01:32:26 PM UTC 24 |
| Peak memory | 205420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076372103 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.3076372103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.2723568241 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 599447251 ps |
| CPU time | 2.45 seconds |
| Started | Sep 04 01:32:18 PM UTC 24 |
| Finished | Sep 04 01:32:21 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723568241 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2723568241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.888580249 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 8310173576 ps |
| CPU time | 4.66 seconds |
| Started | Sep 04 01:32:19 PM UTC 24 |
| Finished | Sep 04 01:32:25 PM UTC 24 |
| Peak memory | 206876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888580249 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.888580249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.197836981 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 558698880 ps |
| CPU time | 1.44 seconds |
| Started | Sep 04 01:31:21 PM UTC 24 |
| Finished | Sep 04 01:31:24 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197836981 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.197836981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4274077064 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6496723965 ps |
| CPU time | 3.87 seconds |
| Started | Sep 04 01:31:20 PM UTC 24 |
| Finished | Sep 04 01:31:25 PM UTC 24 |
| Peak memory | 205724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274077064 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.4274077064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1211263578 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 938630408 ps |
| CPU time | 1.54 seconds |
| Started | Sep 04 01:31:20 PM UTC 24 |
| Finished | Sep 04 01:31:23 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211263578 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.1211263578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2478680813 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 485466943 ps |
| CPU time | 1.34 seconds |
| Started | Sep 04 01:31:23 PM UTC 24 |
| Finished | Sep 04 01:31:25 PM UTC 24 |
| Peak memory | 205860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2478680813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_tim er_csr_mem_rw_with_rand_reset.2478680813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1097629760 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 392424108 ps |
| CPU time | 2.07 seconds |
| Started | Sep 04 01:31:20 PM UTC 24 |
| Finished | Sep 04 01:31:23 PM UTC 24 |
| Peak memory | 201456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097629760 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1097629760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.3013598329 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 497736563 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 01:31:18 PM UTC 24 |
| Finished | Sep 04 01:31:20 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013598329 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3013598329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3620766930 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 467855233 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 01:31:19 PM UTC 24 |
| Finished | Sep 04 01:31:21 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620766930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.3620766930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.2393486832 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 345010713 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 01:31:19 PM UTC 24 |
| Finished | Sep 04 01:31:21 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393486832 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.2393486832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4244903397 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1279007938 ps |
| CPU time | 2.5 seconds |
| Started | Sep 04 01:31:21 PM UTC 24 |
| Finished | Sep 04 01:31:25 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244903397 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.4244903397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2446749052 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 964143649 ps |
| CPU time | 2.42 seconds |
| Started | Sep 04 01:31:16 PM UTC 24 |
| Finished | Sep 04 01:31:19 PM UTC 24 |
| Peak memory | 207008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446749052 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2446749052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.1956691106 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 377050177 ps |
| CPU time | 1.44 seconds |
| Started | Sep 04 01:32:21 PM UTC 24 |
| Finished | Sep 04 01:32:24 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956691106 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1956691106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/20.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.1256606833 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 430964770 ps |
| CPU time | 1.68 seconds |
| Started | Sep 04 01:32:22 PM UTC 24 |
| Finished | Sep 04 01:32:25 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256606833 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1256606833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/21.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3624900107 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 486682273 ps |
| CPU time | 2.62 seconds |
| Started | Sep 04 01:32:22 PM UTC 24 |
| Finished | Sep 04 01:32:26 PM UTC 24 |
| Peak memory | 203508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624900107 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3624900107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/22.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.1615322501 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 389030978 ps |
| CPU time | 1.01 seconds |
| Started | Sep 04 01:32:22 PM UTC 24 |
| Finished | Sep 04 01:32:24 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615322501 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1615322501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/23.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.4133382217 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 480663095 ps |
| CPU time | 2.42 seconds |
| Started | Sep 04 01:32:22 PM UTC 24 |
| Finished | Sep 04 01:32:26 PM UTC 24 |
| Peak memory | 201524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133382217 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4133382217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/24.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.2396290996 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 322247172 ps |
| CPU time | 1.79 seconds |
| Started | Sep 04 01:32:23 PM UTC 24 |
| Finished | Sep 04 01:32:26 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396290996 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2396290996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/25.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.3086459324 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 422708958 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 01:32:23 PM UTC 24 |
| Finished | Sep 04 01:32:25 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086459324 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3086459324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/26.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1333927164 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 440341647 ps |
| CPU time | 2.07 seconds |
| Started | Sep 04 01:32:24 PM UTC 24 |
| Finished | Sep 04 01:32:27 PM UTC 24 |
| Peak memory | 201268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333927164 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1333927164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/27.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2988966802 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 339226128 ps |
| CPU time | 0.94 seconds |
| Started | Sep 04 01:32:25 PM UTC 24 |
| Finished | Sep 04 01:32:27 PM UTC 24 |
| Peak memory | 199576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988966802 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2988966802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/28.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.880082741 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 282688185 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 01:32:25 PM UTC 24 |
| Finished | Sep 04 01:32:27 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880082741 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.880082741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/29.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2780907788 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 440608475 ps |
| CPU time | 2.47 seconds |
| Started | Sep 04 01:31:28 PM UTC 24 |
| Finished | Sep 04 01:31:32 PM UTC 24 |
| Peak memory | 203396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780907788 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.2780907788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2987739851 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 7014594182 ps |
| CPU time | 10 seconds |
| Started | Sep 04 01:31:28 PM UTC 24 |
| Finished | Sep 04 01:31:39 PM UTC 24 |
| Peak memory | 205652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987739851 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.2987739851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3443766890 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 805298862 ps |
| CPU time | 2.13 seconds |
| Started | Sep 04 01:31:26 PM UTC 24 |
| Finished | Sep 04 01:31:29 PM UTC 24 |
| Peak memory | 201220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443766890 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.3443766890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2364288270 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 409791021 ps |
| CPU time | 1.62 seconds |
| Started | Sep 04 01:31:29 PM UTC 24 |
| Finished | Sep 04 01:31:32 PM UTC 24 |
| Peak memory | 206888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2364288270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim er_csr_mem_rw_with_rand_reset.2364288270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.4048528045 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 333831031 ps |
| CPU time | 1.43 seconds |
| Started | Sep 04 01:31:26 PM UTC 24 |
| Finished | Sep 04 01:31:28 PM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048528045 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4048528045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3547345650 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 423401126 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 01:31:25 PM UTC 24 |
| Finished | Sep 04 01:31:27 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547345650 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3547345650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1420889985 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 338136171 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:31:26 PM UTC 24 |
| Finished | Sep 04 01:31:28 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420889985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.1420889985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.458958028 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 435378399 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 01:31:25 PM UTC 24 |
| Finished | Sep 04 01:31:27 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458958028 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.458958028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1454695935 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1414920222 ps |
| CPU time | 2.86 seconds |
| Started | Sep 04 01:31:28 PM UTC 24 |
| Finished | Sep 04 01:31:32 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454695935 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.1454695935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2824805190 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 556632996 ps |
| CPU time | 2.81 seconds |
| Started | Sep 04 01:31:24 PM UTC 24 |
| Finished | Sep 04 01:31:27 PM UTC 24 |
| Peak memory | 206820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824805190 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2824805190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2253855927 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8489718126 ps |
| CPU time | 8.53 seconds |
| Started | Sep 04 01:31:25 PM UTC 24 |
| Finished | Sep 04 01:31:34 PM UTC 24 |
| Peak memory | 207336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253855927 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.2253855927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.3372544946 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 333762040 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 01:32:25 PM UTC 24 |
| Finished | Sep 04 01:32:27 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372544946 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3372544946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/30.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.2869032649 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 404285675 ps |
| CPU time | 1.45 seconds |
| Started | Sep 04 01:32:26 PM UTC 24 |
| Finished | Sep 04 01:32:28 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869032649 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2869032649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/31.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.752265065 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 434417153 ps |
| CPU time | 2.42 seconds |
| Started | Sep 04 01:32:26 PM UTC 24 |
| Finished | Sep 04 01:32:29 PM UTC 24 |
| Peak memory | 201468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752265065 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.752265065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/32.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2751190460 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 460829849 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 01:32:26 PM UTC 24 |
| Finished | Sep 04 01:32:28 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751190460 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2751190460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/33.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2892691939 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 416147368 ps |
| CPU time | 1 seconds |
| Started | Sep 04 01:32:27 PM UTC 24 |
| Finished | Sep 04 01:32:29 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892691939 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2892691939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/34.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.2082370606 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 484818468 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 01:32:27 PM UTC 24 |
| Finished | Sep 04 01:32:29 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082370606 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2082370606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/35.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.2218092644 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 443311850 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 01:32:27 PM UTC 24 |
| Finished | Sep 04 01:32:29 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218092644 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2218092644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/36.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.1386189653 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 293830103 ps |
| CPU time | 0.95 seconds |
| Started | Sep 04 01:32:27 PM UTC 24 |
| Finished | Sep 04 01:32:29 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386189653 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1386189653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/37.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.2502876699 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 476517327 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 01:32:27 PM UTC 24 |
| Finished | Sep 04 01:32:29 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502876699 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2502876699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/38.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.3510858041 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 313740899 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 01:32:27 PM UTC 24 |
| Finished | Sep 04 01:32:29 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510858041 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3510858041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/39.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2252749138 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 661846443 ps |
| CPU time | 1.76 seconds |
| Started | Sep 04 01:31:36 PM UTC 24 |
| Finished | Sep 04 01:31:39 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252749138 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.2252749138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4220045476 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 5873269297 ps |
| CPU time | 5.79 seconds |
| Started | Sep 04 01:31:36 PM UTC 24 |
| Finished | Sep 04 01:31:43 PM UTC 24 |
| Peak memory | 205852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220045476 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.4220045476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4264616621 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1275744751 ps |
| CPU time | 3.06 seconds |
| Started | Sep 04 01:31:34 PM UTC 24 |
| Finished | Sep 04 01:31:38 PM UTC 24 |
| Peak memory | 203396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264616621 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.4264616621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2830675384 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 417547742 ps |
| CPU time | 2.5 seconds |
| Started | Sep 04 01:31:39 PM UTC 24 |
| Finished | Sep 04 01:31:43 PM UTC 24 |
| Peak memory | 205428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2830675384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim er_csr_mem_rw_with_rand_reset.2830675384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.1690275062 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 294780836 ps |
| CPU time | 1.35 seconds |
| Started | Sep 04 01:31:36 PM UTC 24 |
| Finished | Sep 04 01:31:38 PM UTC 24 |
| Peak memory | 201956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690275062 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1690275062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.458496085 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 430278313 ps |
| CPU time | 1 seconds |
| Started | Sep 04 01:31:32 PM UTC 24 |
| Finished | Sep 04 01:31:34 PM UTC 24 |
| Peak memory | 199756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458496085 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.458496085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2411504396 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 393534240 ps |
| CPU time | 0.95 seconds |
| Started | Sep 04 01:31:33 PM UTC 24 |
| Finished | Sep 04 01:31:36 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411504396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.2411504396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.178798566 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 315320684 ps |
| CPU time | 1.64 seconds |
| Started | Sep 04 01:31:32 PM UTC 24 |
| Finished | Sep 04 01:31:35 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178798566 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.178798566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1501534071 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1231117874 ps |
| CPU time | 1.9 seconds |
| Started | Sep 04 01:31:37 PM UTC 24 |
| Finished | Sep 04 01:31:40 PM UTC 24 |
| Peak memory | 201968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501534071 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.1501534071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.2383550466 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 406782140 ps |
| CPU time | 2.58 seconds |
| Started | Sep 04 01:31:29 PM UTC 24 |
| Finished | Sep 04 01:31:33 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383550466 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2383550466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3224652764 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4480835394 ps |
| CPU time | 15.2 seconds |
| Started | Sep 04 01:31:30 PM UTC 24 |
| Finished | Sep 04 01:31:47 PM UTC 24 |
| Peak memory | 206776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224652764 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.3224652764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.1141621336 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 345481512 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 01:32:27 PM UTC 24 |
| Finished | Sep 04 01:32:29 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141621336 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1141621336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/40.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.797862125 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 285733418 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 01:32:27 PM UTC 24 |
| Finished | Sep 04 01:32:29 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797862125 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.797862125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/41.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.1760267248 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 510933570 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 01:32:28 PM UTC 24 |
| Finished | Sep 04 01:32:30 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760267248 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1760267248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/42.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.70645082 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 385627039 ps |
| CPU time | 0.95 seconds |
| Started | Sep 04 01:32:28 PM UTC 24 |
| Finished | Sep 04 01:32:30 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70645082 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.70645082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/43.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.346193624 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 352871054 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 01:32:30 PM UTC 24 |
| Finished | Sep 04 01:32:32 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346193624 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.346193624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/44.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.337155639 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 403152583 ps |
| CPU time | 2.03 seconds |
| Started | Sep 04 01:32:30 PM UTC 24 |
| Finished | Sep 04 01:32:33 PM UTC 24 |
| Peak memory | 201404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337155639 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.337155639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/45.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.2415940712 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 504819167 ps |
| CPU time | 1.42 seconds |
| Started | Sep 04 01:32:30 PM UTC 24 |
| Finished | Sep 04 01:32:32 PM UTC 24 |
| Peak memory | 201792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415940712 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2415940712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/46.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.3406834329 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 388404132 ps |
| CPU time | 1.03 seconds |
| Started | Sep 04 01:32:30 PM UTC 24 |
| Finished | Sep 04 01:32:32 PM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406834329 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3406834329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/47.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.2334028511 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 323423199 ps |
| CPU time | 0.99 seconds |
| Started | Sep 04 01:32:30 PM UTC 24 |
| Finished | Sep 04 01:32:32 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334028511 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2334028511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/48.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.93717087 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 377443369 ps |
| CPU time | 2.06 seconds |
| Started | Sep 04 01:32:30 PM UTC 24 |
| Finished | Sep 04 01:32:33 PM UTC 24 |
| Peak memory | 203248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93717087 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.93717087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/49.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.601727608 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 468637699 ps |
| CPU time | 1.32 seconds |
| Started | Sep 04 01:31:41 PM UTC 24 |
| Finished | Sep 04 01:31:44 PM UTC 24 |
| Peak memory | 204016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=601727608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_time r_csr_mem_rw_with_rand_reset.601727608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.1791914979 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 451540114 ps |
| CPU time | 1.67 seconds |
| Started | Sep 04 01:31:40 PM UTC 24 |
| Finished | Sep 04 01:31:43 PM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791914979 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1791914979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.1722937548 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 324626066 ps |
| CPU time | 1 seconds |
| Started | Sep 04 01:31:40 PM UTC 24 |
| Finished | Sep 04 01:31:42 PM UTC 24 |
| Peak memory | 199260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722937548 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1722937548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.596657299 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1284693554 ps |
| CPU time | 3.05 seconds |
| Started | Sep 04 01:31:41 PM UTC 24 |
| Finished | Sep 04 01:31:45 PM UTC 24 |
| Peak memory | 203508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596657299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.596657299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.1172709012 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 904506284 ps |
| CPU time | 2.88 seconds |
| Started | Sep 04 01:31:39 PM UTC 24 |
| Finished | Sep 04 01:31:43 PM UTC 24 |
| Peak memory | 207040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172709012 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1172709012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2034933482 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4480643372 ps |
| CPU time | 3.87 seconds |
| Started | Sep 04 01:31:39 PM UTC 24 |
| Finished | Sep 04 01:31:44 PM UTC 24 |
| Peak memory | 206244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034933482 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.2034933482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2177012086 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 405173289 ps |
| CPU time | 1.5 seconds |
| Started | Sep 04 01:31:44 PM UTC 24 |
| Finished | Sep 04 01:31:47 PM UTC 24 |
| Peak memory | 205332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2177012086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_tim er_csr_mem_rw_with_rand_reset.2177012086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.839071738 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 461664048 ps |
| CPU time | 1.63 seconds |
| Started | Sep 04 01:31:44 PM UTC 24 |
| Finished | Sep 04 01:31:47 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839071738 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.839071738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2271573501 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 527236667 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 01:31:43 PM UTC 24 |
| Finished | Sep 04 01:31:45 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271573501 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2271573501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2586931789 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1527717518 ps |
| CPU time | 2.14 seconds |
| Started | Sep 04 01:31:44 PM UTC 24 |
| Finished | Sep 04 01:31:48 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586931789 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.2586931789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3852773922 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 348429432 ps |
| CPU time | 3.06 seconds |
| Started | Sep 04 01:31:43 PM UTC 24 |
| Finished | Sep 04 01:31:47 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852773922 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3852773922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2424377036 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 7788616048 ps |
| CPU time | 6.07 seconds |
| Started | Sep 04 01:31:43 PM UTC 24 |
| Finished | Sep 04 01:31:51 PM UTC 24 |
| Peak memory | 207048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424377036 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.2424377036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.919486407 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 437661501 ps |
| CPU time | 2.34 seconds |
| Started | Sep 04 01:31:48 PM UTC 24 |
| Finished | Sep 04 01:31:51 PM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=919486407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_time r_csr_mem_rw_with_rand_reset.919486407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.2564694234 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 480545155 ps |
| CPU time | 2.32 seconds |
| Started | Sep 04 01:31:48 PM UTC 24 |
| Finished | Sep 04 01:31:51 PM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564694234 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2564694234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.4141714927 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 484814614 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 01:31:47 PM UTC 24 |
| Finished | Sep 04 01:31:49 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141714927 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4141714927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1375636791 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1348921461 ps |
| CPU time | 4.95 seconds |
| Started | Sep 04 01:31:48 PM UTC 24 |
| Finished | Sep 04 01:31:54 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375636791 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.1375636791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.1460464173 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 816698548 ps |
| CPU time | 3.8 seconds |
| Started | Sep 04 01:31:46 PM UTC 24 |
| Finished | Sep 04 01:31:50 PM UTC 24 |
| Peak memory | 207028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460464173 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1460464173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4151605518 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4463390357 ps |
| CPU time | 2.35 seconds |
| Started | Sep 04 01:31:47 PM UTC 24 |
| Finished | Sep 04 01:31:50 PM UTC 24 |
| Peak memory | 205440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151605518 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.4151605518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1869368405 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 459803944 ps |
| CPU time | 1.47 seconds |
| Started | Sep 04 01:31:51 PM UTC 24 |
| Finished | Sep 04 01:31:54 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1869368405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim er_csr_mem_rw_with_rand_reset.1869368405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.265143497 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 308733882 ps |
| CPU time | 1.96 seconds |
| Started | Sep 04 01:31:50 PM UTC 24 |
| Finished | Sep 04 01:31:53 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265143497 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.265143497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.2519785310 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 331114144 ps |
| CPU time | 1.87 seconds |
| Started | Sep 04 01:31:49 PM UTC 24 |
| Finished | Sep 04 01:31:52 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519785310 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2519785310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1091162645 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2543240088 ps |
| CPU time | 3.16 seconds |
| Started | Sep 04 01:31:51 PM UTC 24 |
| Finished | Sep 04 01:31:56 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091162645 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.1091162645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.4290793266 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 848164346 ps |
| CPU time | 2.33 seconds |
| Started | Sep 04 01:31:49 PM UTC 24 |
| Finished | Sep 04 01:31:52 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290793266 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4290793266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4231649037 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 7541380973 ps |
| CPU time | 17.17 seconds |
| Started | Sep 04 01:31:49 PM UTC 24 |
| Finished | Sep 04 01:32:07 PM UTC 24 |
| Peak memory | 207012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231649037 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.4231649037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2418087281 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 335684751 ps |
| CPU time | 1.65 seconds |
| Started | Sep 04 01:31:54 PM UTC 24 |
| Finished | Sep 04 01:31:56 PM UTC 24 |
| Peak memory | 206888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2418087281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_tim er_csr_mem_rw_with_rand_reset.2418087281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.4286003042 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 602739908 ps |
| CPU time | 0.95 seconds |
| Started | Sep 04 01:31:52 PM UTC 24 |
| Finished | Sep 04 01:31:55 PM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286003042 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4286003042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.2609449411 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 468514232 ps |
| CPU time | 1 seconds |
| Started | Sep 04 01:31:52 PM UTC 24 |
| Finished | Sep 04 01:31:55 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609449411 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2609449411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2068690490 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1154489432 ps |
| CPU time | 1.77 seconds |
| Started | Sep 04 01:31:54 PM UTC 24 |
| Finished | Sep 04 01:31:57 PM UTC 24 |
| Peak memory | 201968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068690490 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.2068690490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1782847235 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 706479733 ps |
| CPU time | 2.96 seconds |
| Started | Sep 04 01:31:51 PM UTC 24 |
| Finished | Sep 04 01:31:55 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782847235 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1782847235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2204524467 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 7931209836 ps |
| CPU time | 7.96 seconds |
| Started | Sep 04 01:31:52 PM UTC 24 |
| Finished | Sep 04 01:32:02 PM UTC 24 |
| Peak memory | 206908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204524467 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.2204524467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.377840034 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 580675991 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 01:32:31 PM UTC 24 |
| Finished | Sep 04 01:32:33 PM UTC 24 |
| Peak memory | 199988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377840034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.377840034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.2847550082 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 41658921629 ps |
| CPU time | 45.6 seconds |
| Started | Sep 04 01:32:31 PM UTC 24 |
| Finished | Sep 04 01:33:18 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847550082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2847550082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1118907570 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 565880833 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 01:32:31 PM UTC 24 |
| Finished | Sep 04 01:32:33 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118907570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1118907570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/0.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.1044271687 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 51756724795 ps |
| CPU time | 107.6 seconds |
| Started | Sep 04 01:32:32 PM UTC 24 |
| Finished | Sep 04 01:34:22 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044271687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1044271687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.2457859107 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4330684063 ps |
| CPU time | 3.34 seconds |
| Started | Sep 04 01:32:33 PM UTC 24 |
| Finished | Sep 04 01:32:38 PM UTC 24 |
| Peak memory | 231340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457859107 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2457859107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.708594364 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 436817771 ps |
| CPU time | 1.31 seconds |
| Started | Sep 04 01:32:32 PM UTC 24 |
| Finished | Sep 04 01:32:35 PM UTC 24 |
| Peak memory | 198988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708594364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.708594364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/1.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.3766989706 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 37894608534 ps |
| CPU time | 39.01 seconds |
| Started | Sep 04 01:33:38 PM UTC 24 |
| Finished | Sep 04 01:34:19 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766989706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3766989706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.772098165 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 446830608 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 01:33:35 PM UTC 24 |
| Finished | Sep 04 01:33:38 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772098165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.772098165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/10.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.1653104924 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 25979733162 ps |
| CPU time | 47.7 seconds |
| Started | Sep 04 01:33:45 PM UTC 24 |
| Finished | Sep 04 01:34:34 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653104924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1653104924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.2742314004 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 594649143 ps |
| CPU time | 2.94 seconds |
| Started | Sep 04 01:33:45 PM UTC 24 |
| Finished | Sep 04 01:33:49 PM UTC 24 |
| Peak memory | 200592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742314004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2742314004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/11.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.3041256637 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 36710286099 ps |
| CPU time | 11.17 seconds |
| Started | Sep 04 01:33:52 PM UTC 24 |
| Finished | Sep 04 01:34:04 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041256637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3041256637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.3520661510 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 427220458 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 01:33:51 PM UTC 24 |
| Finished | Sep 04 01:33:53 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520661510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3520661510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/12.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.2159865245 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 54775970083 ps |
| CPU time | 19.31 seconds |
| Started | Sep 04 01:34:00 PM UTC 24 |
| Finished | Sep 04 01:34:21 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159865245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2159865245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.2082073484 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 431901490 ps |
| CPU time | 2.09 seconds |
| Started | Sep 04 01:33:59 PM UTC 24 |
| Finished | Sep 04 01:34:02 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082073484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2082073484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/13.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.3205454709 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 10150563402 ps |
| CPU time | 22.16 seconds |
| Started | Sep 04 01:34:08 PM UTC 24 |
| Finished | Sep 04 01:34:31 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205454709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3205454709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.1075961976 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 381829208 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 01:34:05 PM UTC 24 |
| Finished | Sep 04 01:34:07 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075961976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1075961976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.2220397080 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 22778959444 ps |
| CPU time | 37.01 seconds |
| Started | Sep 04 01:34:23 PM UTC 24 |
| Finished | Sep 04 01:35:01 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220397080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2220397080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.1323133047 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 477389770 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 01:34:22 PM UTC 24 |
| Finished | Sep 04 01:34:25 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323133047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1323133047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.2022784324 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 43530649265 ps |
| CPU time | 11.7 seconds |
| Started | Sep 04 01:34:31 PM UTC 24 |
| Finished | Sep 04 01:34:44 PM UTC 24 |
| Peak memory | 200672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022784324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2022784324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.3490886709 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 546605199 ps |
| CPU time | 2.13 seconds |
| Started | Sep 04 01:34:29 PM UTC 24 |
| Finished | Sep 04 01:34:33 PM UTC 24 |
| Peak memory | 200572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490886709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3490886709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/16.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.513232535 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 428658797 ps |
| CPU time | 2.27 seconds |
| Started | Sep 04 01:34:35 PM UTC 24 |
| Finished | Sep 04 01:34:38 PM UTC 24 |
| Peak memory | 200692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513232535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.513232535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.354796448 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 61211659156 ps |
| CPU time | 92.62 seconds |
| Started | Sep 04 01:34:35 PM UTC 24 |
| Finished | Sep 04 01:36:09 PM UTC 24 |
| Peak memory | 200484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354796448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.354796448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.2165838144 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 459197839 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 01:34:35 PM UTC 24 |
| Finished | Sep 04 01:34:37 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165838144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2165838144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/17.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.3247964813 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5077076531 ps |
| CPU time | 14.16 seconds |
| Started | Sep 04 01:34:45 PM UTC 24 |
| Finished | Sep 04 01:35:00 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247964813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3247964813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.1393386396 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 382505280 ps |
| CPU time | 2.06 seconds |
| Started | Sep 04 01:34:44 PM UTC 24 |
| Finished | Sep 04 01:34:47 PM UTC 24 |
| Peak memory | 200564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393386396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1393386396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/18.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.667485524 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 48977675695 ps |
| CPU time | 12.62 seconds |
| Started | Sep 04 01:34:52 PM UTC 24 |
| Finished | Sep 04 01:35:07 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667485524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.667485524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.607953917 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 465228314 ps |
| CPU time | 1.51 seconds |
| Started | Sep 04 01:34:50 PM UTC 24 |
| Finished | Sep 04 01:34:53 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607953917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.607953917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.2973619829 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 6128912519 ps |
| CPU time | 26.36 seconds |
| Started | Sep 04 01:34:54 PM UTC 24 |
| Finished | Sep 04 01:35:21 PM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2973619829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 19.aon_timer_stress_all_with_rand_reset.2973619829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.718688754 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 50543403173 ps |
| CPU time | 48.2 seconds |
| Started | Sep 04 01:32:34 PM UTC 24 |
| Finished | Sep 04 01:33:23 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718688754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.718688754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.2363801775 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8179257189 ps |
| CPU time | 8.31 seconds |
| Started | Sep 04 01:32:35 PM UTC 24 |
| Finished | Sep 04 01:32:44 PM UTC 24 |
| Peak memory | 231228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363801775 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2363801775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.1305301572 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 15829730055 ps |
| CPU time | 33.55 seconds |
| Started | Sep 04 01:35:02 PM UTC 24 |
| Finished | Sep 04 01:35:37 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305301572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1305301572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/20.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.3883889699 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 532534202 ps |
| CPU time | 2.43 seconds |
| Started | Sep 04 01:34:58 PM UTC 24 |
| Finished | Sep 04 01:35:02 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883889699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3883889699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/20.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.542696130 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5754129900 ps |
| CPU time | 3.29 seconds |
| Started | Sep 04 01:35:07 PM UTC 24 |
| Finished | Sep 04 01:35:11 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542696130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.542696130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/21.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.3844973658 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 478312735 ps |
| CPU time | 2.32 seconds |
| Started | Sep 04 01:35:06 PM UTC 24 |
| Finished | Sep 04 01:35:09 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844973658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3844973658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/21.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.1360023918 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 19345263389 ps |
| CPU time | 55.48 seconds |
| Started | Sep 04 01:35:13 PM UTC 24 |
| Finished | Sep 04 01:36:11 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360023918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1360023918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/22.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.667223736 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 595565183 ps |
| CPU time | 1.65 seconds |
| Started | Sep 04 01:35:12 PM UTC 24 |
| Finished | Sep 04 01:35:15 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667223736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.667223736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/22.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.2739727636 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 9270090984 ps |
| CPU time | 24.45 seconds |
| Started | Sep 04 01:35:17 PM UTC 24 |
| Finished | Sep 04 01:35:43 PM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2739727636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 22.aon_timer_stress_all_with_rand_reset.2739727636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.1898872147 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 15362772907 ps |
| CPU time | 31.52 seconds |
| Started | Sep 04 01:35:24 PM UTC 24 |
| Finished | Sep 04 01:35:57 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898872147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1898872147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/23.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.2309588957 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 637560010 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 01:35:22 PM UTC 24 |
| Finished | Sep 04 01:35:24 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309588957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2309588957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/23.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.4118572895 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2028826524 ps |
| CPU time | 18.66 seconds |
| Started | Sep 04 01:35:25 PM UTC 24 |
| Finished | Sep 04 01:35:45 PM UTC 24 |
| Peak memory | 218004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4118572895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 23.aon_timer_stress_all_with_rand_reset.4118572895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.1997584204 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 45739882943 ps |
| CPU time | 47.17 seconds |
| Started | Sep 04 01:35:28 PM UTC 24 |
| Finished | Sep 04 01:36:17 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997584204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1997584204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/24.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.768126463 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 580802825 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 01:35:27 PM UTC 24 |
| Finished | Sep 04 01:35:29 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768126463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.768126463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/24.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.2151443267 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 15264451410 ps |
| CPU time | 11.15 seconds |
| Started | Sep 04 01:35:37 PM UTC 24 |
| Finished | Sep 04 01:35:50 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151443267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2151443267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/25.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.1559721538 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 416059385 ps |
| CPU time | 2.06 seconds |
| Started | Sep 04 01:35:34 PM UTC 24 |
| Finished | Sep 04 01:35:37 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559721538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1559721538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/25.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.924961413 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1286447756 ps |
| CPU time | 3.14 seconds |
| Started | Sep 04 01:35:44 PM UTC 24 |
| Finished | Sep 04 01:35:48 PM UTC 24 |
| Peak memory | 200564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924961413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.924961413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/26.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.315788626 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 533898501 ps |
| CPU time | 2.74 seconds |
| Started | Sep 04 01:35:43 PM UTC 24 |
| Finished | Sep 04 01:35:46 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315788626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.315788626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/26.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.1713182703 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 40811310242 ps |
| CPU time | 47.45 seconds |
| Started | Sep 04 01:35:48 PM UTC 24 |
| Finished | Sep 04 01:36:37 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713182703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1713182703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/27.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.3059594985 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 463362396 ps |
| CPU time | 2.17 seconds |
| Started | Sep 04 01:35:47 PM UTC 24 |
| Finished | Sep 04 01:35:50 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059594985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3059594985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/27.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.81740621 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 38061426858 ps |
| CPU time | 22.02 seconds |
| Started | Sep 04 01:35:53 PM UTC 24 |
| Finished | Sep 04 01:36:17 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81740621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.81740621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/28.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.3841101715 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 579394401 ps |
| CPU time | 2.56 seconds |
| Started | Sep 04 01:35:52 PM UTC 24 |
| Finished | Sep 04 01:35:56 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841101715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3841101715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/28.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.478290082 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 35706967070 ps |
| CPU time | 82.34 seconds |
| Started | Sep 04 01:36:00 PM UTC 24 |
| Finished | Sep 04 01:37:24 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478290082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.478290082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/29.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.104899607 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 362248105 ps |
| CPU time | 2.15 seconds |
| Started | Sep 04 01:35:58 PM UTC 24 |
| Finished | Sep 04 01:36:01 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104899607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.104899607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/29.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.1258648282 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 17813129135 ps |
| CPU time | 36.43 seconds |
| Started | Sep 04 01:32:37 PM UTC 24 |
| Finished | Sep 04 01:33:15 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258648282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1258648282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.183234881 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4317283799 ps |
| CPU time | 4.66 seconds |
| Started | Sep 04 01:32:40 PM UTC 24 |
| Finished | Sep 04 01:32:46 PM UTC 24 |
| Peak memory | 231272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183234881 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.183234881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.2699985757 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 582762892 ps |
| CPU time | 1.5 seconds |
| Started | Sep 04 01:32:36 PM UTC 24 |
| Finished | Sep 04 01:32:39 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699985757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2699985757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/3.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.3035577827 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 12754456172 ps |
| CPU time | 31.4 seconds |
| Started | Sep 04 01:36:12 PM UTC 24 |
| Finished | Sep 04 01:36:45 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035577827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3035577827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/30.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.2593568245 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 458196191 ps |
| CPU time | 2.26 seconds |
| Started | Sep 04 01:36:10 PM UTC 24 |
| Finished | Sep 04 01:36:13 PM UTC 24 |
| Peak memory | 200564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593568245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2593568245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/30.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.247303805 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 21572330720 ps |
| CPU time | 32.11 seconds |
| Started | Sep 04 01:36:15 PM UTC 24 |
| Finished | Sep 04 01:36:49 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247303805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.247303805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/31.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.2692370235 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 437467400 ps |
| CPU time | 2.44 seconds |
| Started | Sep 04 01:36:15 PM UTC 24 |
| Finished | Sep 04 01:36:19 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692370235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2692370235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/31.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.3465848434 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 25332327236 ps |
| CPU time | 32.49 seconds |
| Started | Sep 04 01:36:20 PM UTC 24 |
| Finished | Sep 04 01:36:53 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465848434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3465848434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/32.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.1416662702 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 459736980 ps |
| CPU time | 1 seconds |
| Started | Sep 04 01:36:18 PM UTC 24 |
| Finished | Sep 04 01:36:20 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416662702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1416662702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/32.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.2131831068 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 12575781259 ps |
| CPU time | 7.12 seconds |
| Started | Sep 04 01:36:24 PM UTC 24 |
| Finished | Sep 04 01:36:32 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131831068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2131831068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/33.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.1508455558 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 469881649 ps |
| CPU time | 2.37 seconds |
| Started | Sep 04 01:36:24 PM UTC 24 |
| Finished | Sep 04 01:36:27 PM UTC 24 |
| Peak memory | 200564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508455558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1508455558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/33.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.252059433 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 29399674790 ps |
| CPU time | 42.12 seconds |
| Started | Sep 04 01:36:37 PM UTC 24 |
| Finished | Sep 04 01:37:21 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252059433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.252059433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/34.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.808106203 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 513280858 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 01:36:36 PM UTC 24 |
| Finished | Sep 04 01:36:39 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808106203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.808106203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/34.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.2638480338 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3082298746 ps |
| CPU time | 3.24 seconds |
| Started | Sep 04 01:36:46 PM UTC 24 |
| Finished | Sep 04 01:36:50 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638480338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2638480338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/35.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.851327128 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 602407408 ps |
| CPU time | 1.26 seconds |
| Started | Sep 04 01:36:44 PM UTC 24 |
| Finished | Sep 04 01:36:46 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851327128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.851327128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/35.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.868240998 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 14463649169 ps |
| CPU time | 24.56 seconds |
| Started | Sep 04 01:36:50 PM UTC 24 |
| Finished | Sep 04 01:37:16 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868240998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.868240998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/36.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.3426987444 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 522000020 ps |
| CPU time | 2.34 seconds |
| Started | Sep 04 01:36:50 PM UTC 24 |
| Finished | Sep 04 01:36:53 PM UTC 24 |
| Peak memory | 200564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426987444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3426987444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/36.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.562583200 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 38479267185 ps |
| CPU time | 19.14 seconds |
| Started | Sep 04 01:36:53 PM UTC 24 |
| Finished | Sep 04 01:37:14 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562583200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.562583200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/37.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.3483127338 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 453333724 ps |
| CPU time | 1.67 seconds |
| Started | Sep 04 01:36:52 PM UTC 24 |
| Finished | Sep 04 01:36:55 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483127338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3483127338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/37.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.2301017159 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 32043395510 ps |
| CPU time | 16.23 seconds |
| Started | Sep 04 01:36:58 PM UTC 24 |
| Finished | Sep 04 01:37:15 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301017159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2301017159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/38.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.3648671727 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 505573811 ps |
| CPU time | 1.25 seconds |
| Started | Sep 04 01:36:58 PM UTC 24 |
| Finished | Sep 04 01:37:00 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648671727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3648671727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/38.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.1803623600 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 13959822326 ps |
| CPU time | 11.14 seconds |
| Started | Sep 04 01:37:10 PM UTC 24 |
| Finished | Sep 04 01:37:22 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803623600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1803623600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/39.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.2266439948 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 473609277 ps |
| CPU time | 2.32 seconds |
| Started | Sep 04 01:37:06 PM UTC 24 |
| Finished | Sep 04 01:37:09 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266439948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2266439948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/39.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.3425073538 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 40870205327 ps |
| CPU time | 70.62 seconds |
| Started | Sep 04 01:32:46 PM UTC 24 |
| Finished | Sep 04 01:33:59 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425073538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3425073538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.4246903017 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7726661554 ps |
| CPU time | 3.66 seconds |
| Started | Sep 04 01:32:54 PM UTC 24 |
| Finished | Sep 04 01:32:58 PM UTC 24 |
| Peak memory | 231368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246903017 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.4246903017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.2855680686 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 372060280 ps |
| CPU time | 1.34 seconds |
| Started | Sep 04 01:32:45 PM UTC 24 |
| Finished | Sep 04 01:32:48 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855680686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2855680686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.3133690705 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4314677009 ps |
| CPU time | 29.42 seconds |
| Started | Sep 04 01:32:51 PM UTC 24 |
| Finished | Sep 04 01:33:21 PM UTC 24 |
| Peak memory | 217984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3133690705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 4.aon_timer_stress_all_with_rand_reset.3133690705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.1499755348 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 40225724324 ps |
| CPU time | 5.94 seconds |
| Started | Sep 04 01:37:14 PM UTC 24 |
| Finished | Sep 04 01:37:21 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499755348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1499755348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/40.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.1761622552 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 544155057 ps |
| CPU time | 1.63 seconds |
| Started | Sep 04 01:37:13 PM UTC 24 |
| Finished | Sep 04 01:37:16 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761622552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1761622552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/40.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.1593387833 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 34811134452 ps |
| CPU time | 57.37 seconds |
| Started | Sep 04 01:37:19 PM UTC 24 |
| Finished | Sep 04 01:38:17 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593387833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1593387833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/41.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.875392970 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 692664654 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:37:19 PM UTC 24 |
| Finished | Sep 04 01:37:21 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875392970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.875392970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/41.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.1731086311 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 28370263839 ps |
| CPU time | 18.19 seconds |
| Started | Sep 04 01:37:25 PM UTC 24 |
| Finished | Sep 04 01:37:45 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731086311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1731086311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/42.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.2233014811 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 400036953 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 01:37:23 PM UTC 24 |
| Finished | Sep 04 01:37:25 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233014811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2233014811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/42.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.1272841986 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2669958218 ps |
| CPU time | 21.68 seconds |
| Started | Sep 04 01:37:25 PM UTC 24 |
| Finished | Sep 04 01:37:49 PM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1272841986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 42.aon_timer_stress_all_with_rand_reset.1272841986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.3543651606 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 51013426057 ps |
| CPU time | 29.85 seconds |
| Started | Sep 04 01:37:27 PM UTC 24 |
| Finished | Sep 04 01:37:59 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543651606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3543651606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/43.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.3672645845 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 535462954 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 01:37:27 PM UTC 24 |
| Finished | Sep 04 01:37:30 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672645845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3672645845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/43.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.856285751 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 13003706178 ps |
| CPU time | 19.12 seconds |
| Started | Sep 04 01:37:35 PM UTC 24 |
| Finished | Sep 04 01:37:55 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856285751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.856285751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/44.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.3324183585 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 381731704 ps |
| CPU time | 2.07 seconds |
| Started | Sep 04 01:37:32 PM UTC 24 |
| Finished | Sep 04 01:37:36 PM UTC 24 |
| Peak memory | 200568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324183585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3324183585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/44.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.2861742059 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3895557580 ps |
| CPU time | 1.92 seconds |
| Started | Sep 04 01:37:39 PM UTC 24 |
| Finished | Sep 04 01:37:42 PM UTC 24 |
| Peak memory | 199300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861742059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2861742059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/45.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.3424423853 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 527194921 ps |
| CPU time | 2.76 seconds |
| Started | Sep 04 01:37:39 PM UTC 24 |
| Finished | Sep 04 01:37:43 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424423853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3424423853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/45.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.4223258409 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 8069259009 ps |
| CPU time | 3.27 seconds |
| Started | Sep 04 01:37:44 PM UTC 24 |
| Finished | Sep 04 01:37:49 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223258409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4223258409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/46.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.3686092105 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 479240235 ps |
| CPU time | 2.48 seconds |
| Started | Sep 04 01:37:43 PM UTC 24 |
| Finished | Sep 04 01:37:47 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686092105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3686092105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/46.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.1030555876 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 29223490629 ps |
| CPU time | 5.01 seconds |
| Started | Sep 04 01:37:50 PM UTC 24 |
| Finished | Sep 04 01:37:56 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030555876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1030555876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/47.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.2320633067 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 476762455 ps |
| CPU time | 1.52 seconds |
| Started | Sep 04 01:37:49 PM UTC 24 |
| Finished | Sep 04 01:37:52 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320633067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2320633067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/47.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.2644357380 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1034024653 ps |
| CPU time | 8.99 seconds |
| Started | Sep 04 01:37:51 PM UTC 24 |
| Finished | Sep 04 01:38:01 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2644357380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 47.aon_timer_stress_all_with_rand_reset.2644357380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.614880762 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 47568151216 ps |
| CPU time | 38.99 seconds |
| Started | Sep 04 01:37:56 PM UTC 24 |
| Finished | Sep 04 01:38:36 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614880762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.614880762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/48.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.186314948 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 522899764 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 01:37:55 PM UTC 24 |
| Finished | Sep 04 01:37:57 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186314948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.186314948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/48.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.3116803179 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 28470644016 ps |
| CPU time | 49.92 seconds |
| Started | Sep 04 01:37:59 PM UTC 24 |
| Finished | Sep 04 01:38:51 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116803179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3116803179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/49.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.3473762384 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 503503835 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 01:37:58 PM UTC 24 |
| Finished | Sep 04 01:38:00 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473762384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3473762384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/49.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.2460326767 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 56059491059 ps |
| CPU time | 130.77 seconds |
| Started | Sep 04 01:32:59 PM UTC 24 |
| Finished | Sep 04 01:35:12 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460326767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2460326767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.970416059 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 624987404 ps |
| CPU time | 1.43 seconds |
| Started | Sep 04 01:32:59 PM UTC 24 |
| Finished | Sep 04 01:33:01 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970416059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.970416059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/5.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.2439400242 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 572015610 ps |
| CPU time | 1.81 seconds |
| Started | Sep 04 01:33:06 PM UTC 24 |
| Finished | Sep 04 01:33:09 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439400242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2439400242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.2538593426 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 56521273549 ps |
| CPU time | 39.78 seconds |
| Started | Sep 04 01:33:05 PM UTC 24 |
| Finished | Sep 04 01:33:46 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538593426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2538593426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.3689362051 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 399240811 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 01:33:03 PM UTC 24 |
| Finished | Sep 04 01:33:05 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689362051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3689362051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/6.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.3956435253 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 20561895646 ps |
| CPU time | 17.25 seconds |
| Started | Sep 04 01:33:16 PM UTC 24 |
| Finished | Sep 04 01:33:34 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956435253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3956435253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.792823277 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 471060107 ps |
| CPU time | 1.29 seconds |
| Started | Sep 04 01:33:14 PM UTC 24 |
| Finished | Sep 04 01:33:17 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792823277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.792823277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/7.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.1754861912 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 27542193997 ps |
| CPU time | 15.18 seconds |
| Started | Sep 04 01:33:22 PM UTC 24 |
| Finished | Sep 04 01:33:38 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754861912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1754861912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.3871290986 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 516148674 ps |
| CPU time | 1.22 seconds |
| Started | Sep 04 01:33:19 PM UTC 24 |
| Finished | Sep 04 01:33:21 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871290986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3871290986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/8.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.2527826538 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 53801911876 ps |
| CPU time | 98.2 seconds |
| Started | Sep 04 01:33:31 PM UTC 24 |
| Finished | Sep 04 01:35:12 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527826538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2527826538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.2204490171 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 589335442 ps |
| CPU time | 2.68 seconds |
| Started | Sep 04 01:33:27 PM UTC 24 |
| Finished | Sep 04 01:33:31 PM UTC 24 |
| Peak memory | 200568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204490171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2204490171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/9.aon_timer_smoke/latest |
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