Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 20659 1 T2 10 T4 11 T5 10
bark[1] 150 1 T32 14 T85 26 T145 7
bark[2] 709 1 T25 45 T44 93 T88 21
bark[3] 514 1 T22 112 T76 104 T150 14
bark[4] 215 1 T20 14 T174 14 T88 21
bark[5] 403 1 T45 21 T47 181 T104 21
bark[6] 404 1 T44 26 T48 26 T95 21
bark[7] 452 1 T12 7 T43 77 T101 21
bark[8] 476 1 T43 120 T45 21 T112 21
bark[9] 344 1 T30 14 T22 14 T75 14
bark[10] 360 1 T46 47 T115 14 T158 48
bark[11] 284 1 T12 21 T191 14 T25 21
bark[12] 190 1 T6 14 T34 21 T185 14
bark[13] 321 1 T13 14 T22 21 T87 14
bark[14] 322 1 T34 21 T76 26 T118 21
bark[15] 377 1 T3 14 T153 14 T101 5
bark[16] 265 1 T43 5 T76 21 T121 30
bark[17] 393 1 T45 26 T101 7 T91 50
bark[18] 522 1 T12 21 T31 14 T19 21
bark[19] 285 1 T28 14 T164 12 T121 21
bark[20] 313 1 T144 21 T76 39 T102 21
bark[21] 453 1 T1 14 T12 5 T19 30
bark[22] 406 1 T22 21 T34 21 T48 94
bark[23] 297 1 T24 21 T46 14 T76 26
bark[24] 353 1 T17 26 T101 51 T76 146
bark[25] 146 1 T12 26 T142 14 T124 21
bark[26] 56 1 T118 14 T170 21 T113 21
bark[27] 297 1 T8 14 T112 42 T82 26
bark[28] 258 1 T50 14 T75 5 T163 47
bark[29] 717 1 T19 30 T22 21 T25 35
bark[30] 277 1 T25 21 T77 14 T124 21
bark[31] 505 1 T187 14 T47 251 T75 21
bark_0 4786 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 20107 1 T2 9 T4 10 T5 9
bite[1] 201 1 T46 21 T176 13 T135 60
bite[2] 197 1 T17 26 T22 21 T25 45
bite[3] 495 1 T34 21 T181 13 T101 30
bite[4] 466 1 T31 13 T34 21 T25 13
bite[5] 153 1 T25 21 T92 21 T91 21
bite[6] 110 1 T124 21 T162 43 T198 6
bite[7] 361 1 T44 72 T187 13 T101 13
bite[8] 323 1 T25 21 T45 21 T46 46
bite[9] 180 1 T101 51 T112 21 T137 21
bite[10] 225 1 T13 13 T76 103 T104 26
bite[11] 376 1 T30 13 T19 30 T185 13
bite[12] 103 1 T112 21 T164 4 T199 4
bite[13] 283 1 T22 13 T45 21 T115 13
bite[14] 444 1 T3 13 T8 13 T43 119
bite[15] 367 1 T44 85 T45 26 T158 47
bite[16] 463 1 T12 6 T19 21 T76 39
bite[17] 402 1 T6 13 T20 13 T75 13
bite[18] 251 1 T12 4 T28 13 T112 42
bite[19] 433 1 T47 180 T91 49 T118 6
bite[20] 971 1 T12 21 T22 21 T34 21
bite[21] 294 1 T12 25 T191 13 T76 21
bite[22] 353 1 T1 13 T134 13 T48 25
bite[23] 551 1 T22 111 T139 13 T177 69
bite[24] 189 1 T22 21 T126 21 T77 6
bite[25] 444 1 T50 13 T75 117 T144 21
bite[26] 338 1 T137 13 T163 21 T180 6
bite[27] 203 1 T174 13 T101 6 T88 21
bite[28] 598 1 T43 4 T101 130 T200 6
bite[29] 593 1 T47 250 T75 21 T101 21
bite[30] 499 1 T19 30 T32 13 T43 76
bite[31] 226 1 T12 21 T24 21 T153 13
bite_0 5310 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31011 1 T1 21 T2 17 T3 21
auto[1] 5498 1 T4 7 T7 7 T14 7


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 496 1 T10 9 T201 9 T24 28
prescale[1] 408 1 T17 21 T202 9 T34 45
prescale[2] 327 1 T43 2 T88 19 T203 9
prescale[3] 315 1 T22 50 T24 28 T44 2
prescale[4] 513 1 T18 9 T204 9 T48 2
prescale[5] 367 1 T17 2 T43 2 T76 23
prescale[6] 498 1 T45 43 T47 24 T144 23
prescale[7] 379 1 T17 2 T158 2 T205 9
prescale[8] 325 1 T12 2 T16 9 T43 2
prescale[9] 413 1 T34 2 T43 2 T45 19
prescale[10] 619 1 T17 80 T49 9 T206 9
prescale[11] 553 1 T22 2 T25 53 T45 2
prescale[12] 177 1 T76 2 T88 2 T164 66
prescale[13] 514 1 T22 33 T34 2 T47 115
prescale[14] 373 1 T17 19 T24 79 T207 9
prescale[15] 304 1 T208 9 T24 19 T43 2
prescale[16] 251 1 T47 2 T48 9 T75 2
prescale[17] 654 1 T22 62 T45 101 T47 2
prescale[18] 255 1 T48 28 T92 32 T91 19
prescale[19] 327 1 T34 11 T92 19 T91 4
prescale[20] 476 1 T22 2 T24 19 T47 2
prescale[21] 558 1 T45 19 T47 2 T48 119
prescale[22] 1036 1 T47 2 T48 2 T76 139
prescale[23] 336 1 T17 2 T25 24 T101 9
prescale[24] 639 1 T19 37 T92 33 T91 2
prescale[25] 522 1 T24 19 T43 12 T44 2
prescale[26] 332 1 T22 2 T24 19 T25 28
prescale[27] 221 1 T34 30 T45 19 T144 24
prescale[28] 475 1 T22 26 T45 39 T92 19
prescale[29] 616 1 T17 9 T19 91 T44 2
prescale[30] 436 1 T51 9 T209 9 T19 19
prescale[31] 463 1 T210 9 T47 30 T211 9
prescale_0 22331 1 T1 21 T2 17 T3 21


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24998 1 T1 21 T2 17 T3 9
auto[1] 11511 1 T3 12 T4 9 T7 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 36509 1 T1 21 T2 17 T3 21


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 20612 1 T1 1 T2 12 T3 1
wkup[1] 190 1 T101 26 T103 15 T137 21
wkup[2] 184 1 T44 30 T45 15 T75 21
wkup[3] 146 1 T75 15 T76 21 T104 26
wkup[4] 105 1 T44 21 T113 21 T111 21
wkup[5] 254 1 T43 21 T101 21 T164 21
wkup[6] 269 1 T43 6 T45 21 T88 25
wkup[7] 261 1 T47 21 T158 21 T104 21
wkup[8] 131 1 T19 15 T101 8 T91 21
wkup[9] 277 1 T48 30 T112 21 T77 21
wkup[10] 174 1 T90 21 T149 15 T156 21
wkup[11] 133 1 T76 21 T166 21 T154 15
wkup[12] 183 1 T164 6 T126 21 T118 21
wkup[13] 158 1 T200 8 T148 21 T179 15
wkup[14] 207 1 T25 15 T101 21 T112 21
wkup[15] 218 1 T158 26 T76 21 T104 21
wkup[16] 240 1 T17 21 T45 26 T75 21
wkup[17] 280 1 T45 21 T181 15 T75 15
wkup[18] 129 1 T91 21 T118 21 T78 15
wkup[19] 199 1 T25 21 T44 21 T112 21
wkup[20] 210 1 T17 21 T101 6 T158 21
wkup[21] 221 1 T12 21 T101 21 T104 21
wkup[22] 93 1 T101 15 T104 21 T152 15
wkup[23] 157 1 T25 21 T48 52 T101 21
wkup[24] 129 1 T185 15 T88 21 T135 24
wkup[25] 253 1 T101 30 T121 26 T118 26
wkup[26] 291 1 T6 15 T112 21 T128 15
wkup[27] 317 1 T22 15 T46 21 T112 21
wkup[28] 194 1 T17 26 T46 15 T76 39
wkup[29] 130 1 T148 30 T183 8 T77 21
wkup[30] 252 1 T47 26 T158 21 T124 21
wkup[31] 177 1 T45 21 T101 21 T96 30
wkup[32] 200 1 T22 21 T101 44 T119 21
wkup[33] 211 1 T88 21 T91 21 T133 15
wkup[34] 190 1 T32 15 T34 21 T43 26
wkup[35] 234 1 T19 21 T25 21 T47 30
wkup[36] 203 1 T153 15 T164 21 T118 26
wkup[37] 154 1 T8 15 T30 15 T45 21
wkup[38] 239 1 T174 15 T92 21 T91 21
wkup[39] 78 1 T34 21 T46 15 T170 21
wkup[40] 164 1 T19 30 T47 21 T102 21
wkup[41] 309 1 T34 15 T25 21 T46 21
wkup[42] 223 1 T12 8 T20 15 T31 15
wkup[43] 285 1 T25 21 T47 21 T76 21
wkup[44] 173 1 T3 15 T47 21 T144 21
wkup[45] 284 1 T12 21 T22 21 T45 6
wkup[46] 202 1 T43 21 T45 21 T47 21
wkup[47] 81 1 T22 21 T160 15 T122 15
wkup[48] 150 1 T1 15 T50 15 T45 21
wkup[49] 198 1 T12 21 T43 21 T148 26
wkup[50] 180 1 T19 21 T148 21 T137 21
wkup[51] 177 1 T199 6 T77 30 T166 21
wkup[52] 249 1 T22 63 T43 21 T115 15
wkup[53] 171 1 T12 6 T13 15 T28 15
wkup[54] 283 1 T24 21 T25 21 T44 42
wkup[55] 131 1 T191 15 T77 30 T120 21
wkup[56] 302 1 T12 21 T47 15 T200 8
wkup[57] 140 1 T34 21 T47 26 T118 30
wkup[58] 127 1 T12 21 T19 30 T139 15
wkup[59] 115 1 T112 21 T102 26 T148 26
wkup[60] 201 1 T75 6 T92 21 T132 15
wkup[61] 139 1 T116 15 T126 21 T79 40
wkup[62] 93 1 T121 30 T118 21 T165 21
wkup[63] 125 1 T134 15 T97 21 T99 26
wkup_0 3724 1 T1 5 T2 5 T3 5

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