| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.64 | 99.33 | 95.61 | 100.00 | 98.40 | 99.51 | 45.02 |
| T167 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.1364793659 | Sep 09 09:01:36 PM UTC 24 | Sep 09 09:22:47 PM UTC 24 | 650405756392 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.1216532167 | Sep 09 09:03:24 PM UTC 24 | Sep 09 09:03:27 PM UTC 24 | 293302495 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.3553696522 | Sep 09 09:03:24 PM UTC 24 | Sep 09 09:03:29 PM UTC 24 | 476915082 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.1099618680 | Sep 09 09:03:26 PM UTC 24 | Sep 09 09:03:29 PM UTC 24 | 305143745 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2036989293 | Sep 09 09:03:27 PM UTC 24 | Sep 09 09:03:30 PM UTC 24 | 486504759 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3312138452 | Sep 09 09:03:27 PM UTC 24 | Sep 09 09:03:31 PM UTC 24 | 614766271 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.562837670 | Sep 09 09:03:29 PM UTC 24 | Sep 09 09:03:33 PM UTC 24 | 508215773 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2702696156 | Sep 09 09:03:31 PM UTC 24 | Sep 09 09:03:33 PM UTC 24 | 513797429 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3097814226 | Sep 09 09:03:31 PM UTC 24 | Sep 09 09:03:36 PM UTC 24 | 1297673737 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1507682882 | Sep 09 09:03:32 PM UTC 24 | Sep 09 09:03:36 PM UTC 24 | 564871440 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.413524370 | Sep 09 09:03:34 PM UTC 24 | Sep 09 09:03:38 PM UTC 24 | 671938126 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.1403684892 | Sep 09 09:03:36 PM UTC 24 | Sep 09 09:03:38 PM UTC 24 | 415520089 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.562358935 | Sep 09 09:03:36 PM UTC 24 | Sep 09 09:03:38 PM UTC 24 | 319735373 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2364435979 | Sep 09 09:03:37 PM UTC 24 | Sep 09 09:03:39 PM UTC 24 | 542139512 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2961817085 | Sep 09 09:03:34 PM UTC 24 | Sep 09 09:03:39 PM UTC 24 | 4536328375 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2365780590 | Sep 09 09:03:29 PM UTC 24 | Sep 09 09:03:41 PM UTC 24 | 7124025801 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.1997724858 | Sep 09 09:03:39 PM UTC 24 | Sep 09 09:03:42 PM UTC 24 | 362102994 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2177589148 | Sep 09 09:03:38 PM UTC 24 | Sep 09 09:03:42 PM UTC 24 | 756199515 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2795801475 | Sep 09 09:03:40 PM UTC 24 | Sep 09 09:03:43 PM UTC 24 | 390112216 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4157717084 | Sep 09 09:03:41 PM UTC 24 | Sep 09 09:03:44 PM UTC 24 | 542087156 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.4150033444 | Sep 09 09:03:41 PM UTC 24 | Sep 09 09:03:45 PM UTC 24 | 336804501 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.3662912185 | Sep 09 09:03:44 PM UTC 24 | Sep 09 09:03:46 PM UTC 24 | 345427559 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.2945790311 | Sep 09 09:03:44 PM UTC 24 | Sep 09 09:03:47 PM UTC 24 | 377426021 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2142695223 | Sep 09 09:03:40 PM UTC 24 | Sep 09 09:03:47 PM UTC 24 | 1204851107 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3757293433 | Sep 09 09:03:45 PM UTC 24 | Sep 09 09:03:47 PM UTC 24 | 326277556 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1146143057 | Sep 09 09:03:45 PM UTC 24 | Sep 09 09:03:48 PM UTC 24 | 428487423 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1947641792 | Sep 09 09:03:43 PM UTC 24 | Sep 09 09:03:49 PM UTC 24 | 4119714101 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3952552447 | Sep 09 09:03:47 PM UTC 24 | Sep 09 09:03:50 PM UTC 24 | 367751971 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3196321374 | Sep 09 09:03:45 PM UTC 24 | Sep 09 09:03:51 PM UTC 24 | 1147121345 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1750845688 | Sep 09 09:03:48 PM UTC 24 | Sep 09 09:03:51 PM UTC 24 | 344444738 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.1172226314 | Sep 09 09:03:49 PM UTC 24 | Sep 09 09:03:51 PM UTC 24 | 398035113 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2379338365 | Sep 09 09:03:24 PM UTC 24 | Sep 09 09:03:51 PM UTC 24 | 7689565641 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.1763725980 | Sep 09 09:03:48 PM UTC 24 | Sep 09 09:03:51 PM UTC 24 | 602408021 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.3537567863 | Sep 09 09:03:49 PM UTC 24 | Sep 09 09:03:51 PM UTC 24 | 354869091 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1600522108 | Sep 09 09:03:50 PM UTC 24 | Sep 09 09:03:53 PM UTC 24 | 389449335 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3773086753 | Sep 09 09:03:48 PM UTC 24 | Sep 09 09:03:54 PM UTC 24 | 982180792 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3550819086 | Sep 09 09:03:51 PM UTC 24 | Sep 09 09:03:54 PM UTC 24 | 863575871 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2769014679 | Sep 09 09:03:46 PM UTC 24 | Sep 09 09:03:54 PM UTC 24 | 6997839431 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.612229463 | Sep 09 09:03:53 PM UTC 24 | Sep 09 09:03:55 PM UTC 24 | 361665732 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.168323709 | Sep 09 09:03:53 PM UTC 24 | Sep 09 09:03:55 PM UTC 24 | 445854943 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.438040027 | Sep 09 09:03:53 PM UTC 24 | Sep 09 09:03:56 PM UTC 24 | 530218325 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3911526343 | Sep 09 09:03:53 PM UTC 24 | Sep 09 09:03:56 PM UTC 24 | 2885130944 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.537118031 | Sep 09 09:03:48 PM UTC 24 | Sep 09 09:03:57 PM UTC 24 | 8211576412 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.223156240 | Sep 09 09:03:54 PM UTC 24 | Sep 09 09:03:58 PM UTC 24 | 421009532 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.4059702485 | Sep 09 09:03:55 PM UTC 24 | Sep 09 09:03:59 PM UTC 24 | 362690912 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.669418713 | Sep 09 09:03:55 PM UTC 24 | Sep 09 09:03:59 PM UTC 24 | 374828074 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3108764319 | Sep 09 09:03:56 PM UTC 24 | Sep 09 09:03:59 PM UTC 24 | 309054102 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1174565067 | Sep 09 09:03:56 PM UTC 24 | Sep 09 09:04:00 PM UTC 24 | 833292531 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1264727912 | Sep 09 09:03:53 PM UTC 24 | Sep 09 09:04:00 PM UTC 24 | 7258768511 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3677224503 | Sep 09 09:03:56 PM UTC 24 | Sep 09 09:04:01 PM UTC 24 | 496339937 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1587106774 | Sep 09 09:03:59 PM UTC 24 | Sep 09 09:04:02 PM UTC 24 | 768927070 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.246529379 | Sep 09 09:03:58 PM UTC 24 | Sep 09 09:04:02 PM UTC 24 | 390045095 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.896600798 | Sep 09 09:04:01 PM UTC 24 | Sep 09 09:04:03 PM UTC 24 | 476772536 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.1810373494 | Sep 09 09:03:59 PM UTC 24 | Sep 09 09:04:03 PM UTC 24 | 546940487 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.769086612 | Sep 09 09:03:39 PM UTC 24 | Sep 09 09:04:04 PM UTC 24 | 7277180970 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.1447864287 | Sep 09 09:04:01 PM UTC 24 | Sep 09 09:04:04 PM UTC 24 | 379024190 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2065568942 | Sep 09 09:04:02 PM UTC 24 | Sep 09 09:04:05 PM UTC 24 | 420089271 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2846234067 | Sep 09 09:04:03 PM UTC 24 | Sep 09 09:04:05 PM UTC 24 | 314233376 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1142068721 | Sep 09 09:04:01 PM UTC 24 | Sep 09 09:04:05 PM UTC 24 | 1321516890 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.940076586 | Sep 09 09:04:04 PM UTC 24 | Sep 09 09:04:06 PM UTC 24 | 409636380 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.7900763 | Sep 09 09:04:02 PM UTC 24 | Sep 09 09:04:07 PM UTC 24 | 547330768 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1863339752 | Sep 09 09:04:04 PM UTC 24 | Sep 09 09:04:07 PM UTC 24 | 1292931592 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3698943662 | Sep 09 09:03:58 PM UTC 24 | Sep 09 09:04:08 PM UTC 24 | 2418378520 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.88238532 | Sep 09 09:04:06 PM UTC 24 | Sep 09 09:04:09 PM UTC 24 | 318772802 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2109648484 | Sep 09 09:04:05 PM UTC 24 | Sep 09 09:04:09 PM UTC 24 | 430689403 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.3715455763 | Sep 09 09:04:06 PM UTC 24 | Sep 09 09:04:09 PM UTC 24 | 364257375 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1050091201 | Sep 09 09:04:06 PM UTC 24 | Sep 09 09:04:10 PM UTC 24 | 1520196549 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.674487920 | Sep 09 09:04:05 PM UTC 24 | Sep 09 09:04:10 PM UTC 24 | 1875926051 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1167517828 | Sep 09 09:03:56 PM UTC 24 | Sep 09 09:04:10 PM UTC 24 | 7030241485 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2925513071 | Sep 09 09:03:55 PM UTC 24 | Sep 09 09:04:11 PM UTC 24 | 4582704870 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.1119341793 | Sep 09 09:04:09 PM UTC 24 | Sep 09 09:04:11 PM UTC 24 | 438808279 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2298594321 | Sep 09 09:04:07 PM UTC 24 | Sep 09 09:04:11 PM UTC 24 | 468777262 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.642808800 | Sep 09 09:04:03 PM UTC 24 | Sep 09 09:04:12 PM UTC 24 | 8449817793 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.4003115150 | Sep 09 09:04:10 PM UTC 24 | Sep 09 09:04:12 PM UTC 24 | 398602914 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2487659344 | Sep 09 09:04:10 PM UTC 24 | Sep 09 09:04:12 PM UTC 24 | 605496218 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3242267490 | Sep 09 09:04:01 PM UTC 24 | Sep 09 09:04:12 PM UTC 24 | 8568438109 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.1169528789 | Sep 09 09:04:08 PM UTC 24 | Sep 09 09:04:13 PM UTC 24 | 480852687 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1581426236 | Sep 09 09:04:05 PM UTC 24 | Sep 09 09:04:14 PM UTC 24 | 4232855964 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.2554479534 | Sep 09 09:04:11 PM UTC 24 | Sep 09 09:04:14 PM UTC 24 | 512166483 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.658383795 | Sep 09 09:04:11 PM UTC 24 | Sep 09 09:04:14 PM UTC 24 | 397599796 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.2650665319 | Sep 09 09:04:11 PM UTC 24 | Sep 09 09:04:15 PM UTC 24 | 656028136 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.631264944 | Sep 09 09:04:12 PM UTC 24 | Sep 09 09:04:15 PM UTC 24 | 353896370 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1399014653 | Sep 09 09:04:11 PM UTC 24 | Sep 09 09:04:15 PM UTC 24 | 8414102822 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2869384260 | Sep 09 09:04:10 PM UTC 24 | Sep 09 09:04:16 PM UTC 24 | 1137953316 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.618979002 | Sep 09 09:04:12 PM UTC 24 | Sep 09 09:04:16 PM UTC 24 | 960411076 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.1422939203 | Sep 09 09:04:13 PM UTC 24 | Sep 09 09:04:17 PM UTC 24 | 489703263 ps | ||
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| T421 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.141144098 | Sep 09 09:04:37 PM UTC 24 | Sep 09 09:04:39 PM UTC 24 | 492028758 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.2979078990 | Sep 09 09:04:37 PM UTC 24 | Sep 09 09:04:39 PM UTC 24 | 543859846 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.3925848527 | Sep 09 09:04:38 PM UTC 24 | Sep 09 09:04:40 PM UTC 24 | 460311522 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.1895167004 | Sep 09 09:04:38 PM UTC 24 | Sep 09 09:04:41 PM UTC 24 | 504191877 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.172711559 | Sep 09 09:04:38 PM UTC 24 | Sep 09 09:04:41 PM UTC 24 | 286359628 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4145084721 | Sep 09 09:04:25 PM UTC 24 | Sep 09 09:04:42 PM UTC 24 | 8331470900 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.103474052 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 346346161 ps |
| CPU time | 1.81 seconds |
| Started | Sep 09 08:59:23 PM UTC 24 |
| Finished | Sep 09 08:59:26 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103474052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.103474052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.2808957556 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1831868464 ps |
| CPU time | 7.98 seconds |
| Started | Sep 09 08:59:19 PM UTC 24 |
| Finished | Sep 09 08:59:28 PM UTC 24 |
| Peak memory | 206424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2808957556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.aon_timer_stress_all_with_rand_reset.2808957556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.4027997418 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10355202493 ps |
| CPU time | 22.56 seconds |
| Started | Sep 09 08:59:41 PM UTC 24 |
| Finished | Sep 09 09:00:05 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4027997418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.aon_timer_stress_all_with_rand_reset.4027997418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2961817085 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4536328375 ps |
| CPU time | 4.38 seconds |
| Started | Sep 09 09:03:34 PM UTC 24 |
| Finished | Sep 09 09:03:39 PM UTC 24 |
| Peak memory | 206424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961817085 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.2961817085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.2309726734 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5601984253 ps |
| CPU time | 35.52 seconds |
| Started | Sep 09 08:59:35 PM UTC 24 |
| Finished | Sep 09 09:00:12 PM UTC 24 |
| Peak memory | 206760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2309726734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 7.aon_timer_stress_all_with_rand_reset.2309726734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.3913165395 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 108236110845 ps |
| CPU time | 75.29 seconds |
| Started | Sep 09 09:00:07 PM UTC 24 |
| Finished | Sep 09 09:01:24 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913165395 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.3913165395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2795801475 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 390112216 ps |
| CPU time | 1.69 seconds |
| Started | Sep 09 09:03:40 PM UTC 24 |
| Finished | Sep 09 09:03:43 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795801475 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.2795801475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.1862093250 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 9743360329 ps |
| CPU time | 35.35 seconds |
| Started | Sep 09 08:59:52 PM UTC 24 |
| Finished | Sep 09 09:00:29 PM UTC 24 |
| Peak memory | 206808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1862093250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 11.aon_timer_stress_all_with_rand_reset.1862093250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.4076005166 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 38006838326 ps |
| CPU time | 11.19 seconds |
| Started | Sep 09 09:01:47 PM UTC 24 |
| Finished | Sep 09 09:01:59 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076005166 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.4076005166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/30.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.3780668297 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 209701169743 ps |
| CPU time | 188.67 seconds |
| Started | Sep 09 09:02:31 PM UTC 24 |
| Finished | Sep 09 09:05:43 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780668297 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.3780668297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/38.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.1533932297 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8317565698 ps |
| CPU time | 6.71 seconds |
| Started | Sep 09 08:59:19 PM UTC 24 |
| Finished | Sep 09 08:59:27 PM UTC 24 |
| Peak memory | 231164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533932297 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1533932297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.3522378651 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 6973967219 ps |
| CPU time | 22.59 seconds |
| Started | Sep 09 09:02:37 PM UTC 24 |
| Finished | Sep 09 09:03:01 PM UTC 24 |
| Peak memory | 215372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3522378651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 39.aon_timer_stress_all_with_rand_reset.3522378651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.3617738771 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 7816245616 ps |
| CPU time | 29.41 seconds |
| Started | Sep 09 09:02:45 PM UTC 24 |
| Finished | Sep 09 09:03:16 PM UTC 24 |
| Peak memory | 206644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3617738771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 40.aon_timer_stress_all_with_rand_reset.3617738771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.2105962683 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 20415761303 ps |
| CPU time | 37.44 seconds |
| Started | Sep 09 09:00:15 PM UTC 24 |
| Finished | Sep 09 09:00:54 PM UTC 24 |
| Peak memory | 206636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2105962683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 16.aon_timer_stress_all_with_rand_reset.2105962683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.829930123 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 30477966063 ps |
| CPU time | 43.33 seconds |
| Started | Sep 09 09:00:50 PM UTC 24 |
| Finished | Sep 09 09:01:35 PM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=829930123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 21.aon_timer_stress_all_with_rand_reset.829930123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.2645906313 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 16323954617 ps |
| CPU time | 39.49 seconds |
| Started | Sep 09 08:59:38 PM UTC 24 |
| Finished | Sep 09 09:00:19 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2645906313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 8.aon_timer_stress_all_with_rand_reset.2645906313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.2124556242 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 105202774447 ps |
| CPU time | 38.08 seconds |
| Started | Sep 09 08:59:30 PM UTC 24 |
| Finished | Sep 09 09:00:10 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124556242 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.2124556242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.3999707678 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 13579343582 ps |
| CPU time | 41.25 seconds |
| Started | Sep 09 09:03:23 PM UTC 24 |
| Finished | Sep 09 09:04:06 PM UTC 24 |
| Peak memory | 214048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3999707678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 49.aon_timer_stress_all_with_rand_reset.3999707678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.1739269601 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 39526809000 ps |
| CPU time | 104.9 seconds |
| Started | Sep 09 08:59:40 PM UTC 24 |
| Finished | Sep 09 09:01:27 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739269601 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.1739269601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.477034023 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 110900801172 ps |
| CPU time | 41.77 seconds |
| Started | Sep 09 09:02:14 PM UTC 24 |
| Finished | Sep 09 09:02:58 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477034023 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.477034023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/36.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.894495168 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 96429268177 ps |
| CPU time | 38.86 seconds |
| Started | Sep 09 09:02:09 PM UTC 24 |
| Finished | Sep 09 09:02:49 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894495168 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.894495168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/35.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.1278862276 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 80090180699 ps |
| CPU time | 70.11 seconds |
| Started | Sep 09 09:02:48 PM UTC 24 |
| Finished | Sep 09 09:04:00 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278862276 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.1278862276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/41.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.793678428 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11918295715 ps |
| CPU time | 36.71 seconds |
| Started | Sep 09 08:59:23 PM UTC 24 |
| Finished | Sep 09 09:00:02 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=793678428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.aon_timer_stress_all_with_rand_reset.793678428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.1469385175 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 33150690287 ps |
| CPU time | 49.51 seconds |
| Started | Sep 09 09:00:57 PM UTC 24 |
| Finished | Sep 09 09:01:48 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469385175 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.1469385175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/22.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.3234442397 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 8536152845 ps |
| CPU time | 30.96 seconds |
| Started | Sep 09 09:02:50 PM UTC 24 |
| Finished | Sep 09 09:03:23 PM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3234442397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 42.aon_timer_stress_all_with_rand_reset.3234442397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.3799282225 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3585795652 ps |
| CPU time | 38.64 seconds |
| Started | Sep 09 09:03:09 PM UTC 24 |
| Finished | Sep 09 09:03:49 PM UTC 24 |
| Peak memory | 206548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3799282225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 46.aon_timer_stress_all_with_rand_reset.3799282225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.1839422375 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 15246100476 ps |
| CPU time | 43.21 seconds |
| Started | Sep 09 09:01:01 PM UTC 24 |
| Finished | Sep 09 09:01:46 PM UTC 24 |
| Peak memory | 215556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1839422375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 23.aon_timer_stress_all_with_rand_reset.1839422375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.1912921010 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 14793616344 ps |
| CPU time | 44.15 seconds |
| Started | Sep 09 08:59:59 PM UTC 24 |
| Finished | Sep 09 09:00:44 PM UTC 24 |
| Peak memory | 218560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1912921010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 12.aon_timer_stress_all_with_rand_reset.1912921010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.3845462825 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 52481490881 ps |
| CPU time | 123.32 seconds |
| Started | Sep 09 09:00:39 PM UTC 24 |
| Finished | Sep 09 09:02:45 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845462825 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.3845462825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/20.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.4099854750 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 5884904193 ps |
| CPU time | 20.89 seconds |
| Started | Sep 09 09:01:24 PM UTC 24 |
| Finished | Sep 09 09:01:47 PM UTC 24 |
| Peak memory | 206520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4099854750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 26.aon_timer_stress_all_with_rand_reset.4099854750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.153712425 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3930367521 ps |
| CPU time | 38 seconds |
| Started | Sep 09 08:59:30 PM UTC 24 |
| Finished | Sep 09 09:00:10 PM UTC 24 |
| Peak memory | 214052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=153712425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.aon_timer_stress_all_with_rand_reset.153712425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.4180007370 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 83989188840 ps |
| CPU time | 196.19 seconds |
| Started | Sep 09 09:01:24 PM UTC 24 |
| Finished | Sep 09 09:04:44 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180007370 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.4180007370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/26.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.3224587184 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2742678029 ps |
| CPU time | 15.22 seconds |
| Started | Sep 09 09:01:42 PM UTC 24 |
| Finished | Sep 09 09:01:59 PM UTC 24 |
| Peak memory | 206672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3224587184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 29.aon_timer_stress_all_with_rand_reset.3224587184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.3700140293 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 175736471642 ps |
| CPU time | 29.74 seconds |
| Started | Sep 09 08:59:27 PM UTC 24 |
| Finished | Sep 09 08:59:58 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700140293 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.3700140293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.155496221 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 33065518232 ps |
| CPU time | 53.79 seconds |
| Started | Sep 09 09:01:52 PM UTC 24 |
| Finished | Sep 09 09:02:47 PM UTC 24 |
| Peak memory | 203156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=155496221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.aon_timer_stress_all_with_rand_reset.155496221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.4110432634 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 174689745086 ps |
| CPU time | 345.2 seconds |
| Started | Sep 09 09:01:57 PM UTC 24 |
| Finished | Sep 09 09:07:46 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110432634 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.4110432634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/33.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.3982491185 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 355076115 ps |
| CPU time | 2.02 seconds |
| Started | Sep 09 08:59:40 PM UTC 24 |
| Finished | Sep 09 08:59:43 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982491185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3982491185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.194143374 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 38722907472 ps |
| CPU time | 79.38 seconds |
| Started | Sep 09 09:00:13 PM UTC 24 |
| Finished | Sep 09 09:01:34 PM UTC 24 |
| Peak memory | 200596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194143374 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.194143374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.510796439 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 205344987874 ps |
| CPU time | 62.76 seconds |
| Started | Sep 09 09:00:22 PM UTC 24 |
| Finished | Sep 09 09:01:27 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510796439 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.510796439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.3174623358 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 6218168409 ps |
| CPU time | 31.8 seconds |
| Started | Sep 09 09:01:35 PM UTC 24 |
| Finished | Sep 09 09:02:08 PM UTC 24 |
| Peak memory | 214516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3174623358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 28.aon_timer_stress_all_with_rand_reset.3174623358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.416030467 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 367187031326 ps |
| CPU time | 130.86 seconds |
| Started | Sep 09 09:03:10 PM UTC 24 |
| Finished | Sep 09 09:05:23 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416030467 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.416030467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/46.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.1553258996 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 118992167612 ps |
| CPU time | 233.34 seconds |
| Started | Sep 09 09:03:15 PM UTC 24 |
| Finished | Sep 09 09:07:12 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553258996 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.1553258996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/47.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.786890742 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 128731469440 ps |
| CPU time | 180.17 seconds |
| Started | Sep 09 08:59:45 PM UTC 24 |
| Finished | Sep 09 09:02:48 PM UTC 24 |
| Peak memory | 200892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786890742 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.786890742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.1838168405 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2981538092 ps |
| CPU time | 25.69 seconds |
| Started | Sep 09 08:59:45 PM UTC 24 |
| Finished | Sep 09 09:00:12 PM UTC 24 |
| Peak memory | 215996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1838168405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 10.aon_timer_stress_all_with_rand_reset.1838168405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.416362003 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 153142955086 ps |
| CPU time | 55.81 seconds |
| Started | Sep 09 08:59:59 PM UTC 24 |
| Finished | Sep 09 09:00:56 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416362003 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.416362003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.1186704547 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 234431929291 ps |
| CPU time | 373.81 seconds |
| Started | Sep 09 09:00:17 PM UTC 24 |
| Finished | Sep 09 09:06:36 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186704547 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.1186704547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.3552072077 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 317914922908 ps |
| CPU time | 376.71 seconds |
| Started | Sep 09 08:59:23 PM UTC 24 |
| Finished | Sep 09 09:05:45 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552072077 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.3552072077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.3590560050 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 66113987338 ps |
| CPU time | 66.73 seconds |
| Started | Sep 09 09:01:52 PM UTC 24 |
| Finished | Sep 09 09:03:00 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590560050 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.3590560050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/32.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.2326879290 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 545851732439 ps |
| CPU time | 246.69 seconds |
| Started | Sep 09 09:02:52 PM UTC 24 |
| Finished | Sep 09 09:07:02 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326879290 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.2326879290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/42.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.1051916213 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 9229358074 ps |
| CPU time | 37.77 seconds |
| Started | Sep 09 09:00:21 PM UTC 24 |
| Finished | Sep 09 09:01:00 PM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1051916213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 17.aon_timer_stress_all_with_rand_reset.1051916213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.1043685200 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 15754932716 ps |
| CPU time | 35.38 seconds |
| Started | Sep 09 09:01:48 PM UTC 24 |
| Finished | Sep 09 09:02:25 PM UTC 24 |
| Peak memory | 214308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1043685200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 31.aon_timer_stress_all_with_rand_reset.1043685200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.702822412 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 11270908609 ps |
| CPU time | 26.32 seconds |
| Started | Sep 09 09:03:16 PM UTC 24 |
| Finished | Sep 09 09:03:44 PM UTC 24 |
| Peak memory | 206772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=702822412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 48.aon_timer_stress_all_with_rand_reset.702822412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.907068641 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 257631491013 ps |
| CPU time | 419.51 seconds |
| Started | Sep 09 08:59:52 PM UTC 24 |
| Finished | Sep 09 09:06:57 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907068641 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.907068641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.2878323186 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 5502864445 ps |
| CPU time | 37.43 seconds |
| Started | Sep 09 09:02:07 PM UTC 24 |
| Finished | Sep 09 09:02:46 PM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2878323186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 35.aon_timer_stress_all_with_rand_reset.2878323186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.773885141 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6712240167 ps |
| CPU time | 42.57 seconds |
| Started | Sep 09 08:59:27 PM UTC 24 |
| Finished | Sep 09 09:00:11 PM UTC 24 |
| Peak memory | 206732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=773885141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.aon_timer_stress_all_with_rand_reset.773885141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3097814226 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1297673737 ps |
| CPU time | 3.86 seconds |
| Started | Sep 09 09:03:31 PM UTC 24 |
| Finished | Sep 09 09:03:36 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097814226 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.3097814226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.788537089 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 137727419199 ps |
| CPU time | 175.75 seconds |
| Started | Sep 09 09:00:27 PM UTC 24 |
| Finished | Sep 09 09:03:25 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788537089 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.788537089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.1232871676 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 4645027562 ps |
| CPU time | 41.57 seconds |
| Started | Sep 09 09:01:06 PM UTC 24 |
| Finished | Sep 09 09:01:49 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1232871676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 24.aon_timer_stress_all_with_rand_reset.1232871676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.1935149125 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 98120351079 ps |
| CPU time | 163.2 seconds |
| Started | Sep 09 09:02:23 PM UTC 24 |
| Finished | Sep 09 09:05:09 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935149125 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.1935149125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/37.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.4097590233 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 169936414682 ps |
| CPU time | 75.72 seconds |
| Started | Sep 09 08:59:41 PM UTC 24 |
| Finished | Sep 09 09:00:59 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097590233 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.4097590233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.1414886058 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 497681583158 ps |
| CPU time | 454.29 seconds |
| Started | Sep 09 09:01:09 PM UTC 24 |
| Finished | Sep 09 09:08:49 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414886058 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.1414886058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/24.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.2666207981 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 482657027130 ps |
| CPU time | 45.04 seconds |
| Started | Sep 09 09:01:49 PM UTC 24 |
| Finished | Sep 09 09:02:36 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666207981 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.2666207981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/31.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.1328117924 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4841163247 ps |
| CPU time | 14.46 seconds |
| Started | Sep 09 09:00:13 PM UTC 24 |
| Finished | Sep 09 09:00:28 PM UTC 24 |
| Peak memory | 218616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1328117924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 15.aon_timer_stress_all_with_rand_reset.1328117924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.3528763116 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 512363925 ps |
| CPU time | 2.43 seconds |
| Started | Sep 09 09:00:49 PM UTC 24 |
| Finished | Sep 09 09:00:53 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528763116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3528763116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/21.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.2272720557 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 515549827 ps |
| CPU time | 1.35 seconds |
| Started | Sep 09 09:00:55 PM UTC 24 |
| Finished | Sep 09 09:00:57 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272720557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2272720557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/22.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.317658082 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 501389161 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 09:00:59 PM UTC 24 |
| Finished | Sep 09 09:01:02 PM UTC 24 |
| Peak memory | 199372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317658082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.317658082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/23.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.2074375494 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 570660861 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 09:01:28 PM UTC 24 |
| Finished | Sep 09 09:01:31 PM UTC 24 |
| Peak memory | 200772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074375494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2074375494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/27.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.1940789525 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5741621710 ps |
| CPU time | 34.31 seconds |
| Started | Sep 09 09:01:46 PM UTC 24 |
| Finished | Sep 09 09:02:21 PM UTC 24 |
| Peak memory | 214348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1940789525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 30.aon_timer_stress_all_with_rand_reset.1940789525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.2258391407 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 10591579963 ps |
| CPU time | 10.45 seconds |
| Started | Sep 09 09:02:39 PM UTC 24 |
| Finished | Sep 09 09:02:51 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258391407 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.2258391407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/39.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.1828732047 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 431365765 ps |
| CPU time | 1.34 seconds |
| Started | Sep 09 09:00:36 PM UTC 24 |
| Finished | Sep 09 09:00:39 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828732047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1828732047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/20.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.961249494 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 379092932 ps |
| CPU time | 1.35 seconds |
| Started | Sep 09 09:01:06 PM UTC 24 |
| Finished | Sep 09 09:01:08 PM UTC 24 |
| Peak memory | 199372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961249494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.961249494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/24.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.2273718871 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 540355445 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 09:01:23 PM UTC 24 |
| Finished | Sep 09 09:01:25 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273718871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2273718871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/26.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.1637225220 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 73550951035 ps |
| CPU time | 65.45 seconds |
| Started | Sep 09 08:59:24 PM UTC 24 |
| Finished | Sep 09 09:00:31 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637225220 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.1637225220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.4115792218 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 492751597 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 09:02:11 PM UTC 24 |
| Finished | Sep 09 09:02:13 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115792218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.4115792218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/36.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.4265152140 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3360841583 ps |
| CPU time | 26.18 seconds |
| Started | Sep 09 09:02:48 PM UTC 24 |
| Finished | Sep 09 09:03:16 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4265152140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 41.aon_timer_stress_all_with_rand_reset.4265152140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.3925994361 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 114350843404 ps |
| CPU time | 219.59 seconds |
| Started | Sep 09 09:03:19 PM UTC 24 |
| Finished | Sep 09 09:07:01 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925994361 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.3925994361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/48.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.2973439437 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 452049743681 ps |
| CPU time | 802.79 seconds |
| Started | Sep 09 09:03:23 PM UTC 24 |
| Finished | Sep 09 09:16:55 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973439437 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.2973439437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/49.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.2457739354 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 153018302506 ps |
| CPU time | 143.29 seconds |
| Started | Sep 09 08:59:32 PM UTC 24 |
| Finished | Sep 09 09:01:58 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457739354 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.2457739354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.2038366601 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 530518625 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 08:59:19 PM UTC 24 |
| Finished | Sep 09 08:59:21 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038366601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2038366601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.2254845913 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 193395973996 ps |
| CPU time | 43.53 seconds |
| Started | Sep 09 08:59:19 PM UTC 24 |
| Finished | Sep 09 09:00:04 PM UTC 24 |
| Peak memory | 202676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254845913 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.2254845913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.1485136169 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 555870631 ps |
| CPU time | 1.61 seconds |
| Started | Sep 09 08:59:45 PM UTC 24 |
| Finished | Sep 09 08:59:47 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485136169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1485136169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.3905160635 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 346243069 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 08:59:57 PM UTC 24 |
| Finished | Sep 09 08:59:59 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905160635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3905160635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.1834330230 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 579844384 ps |
| CPU time | 2.79 seconds |
| Started | Sep 09 09:00:09 PM UTC 24 |
| Finished | Sep 09 09:00:13 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834330230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1834330230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.3252030496 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 477742965 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 09:00:11 PM UTC 24 |
| Finished | Sep 09 09:00:14 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252030496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3252030496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.957308469 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 579180004136 ps |
| CPU time | 534.48 seconds |
| Started | Sep 09 09:01:17 PM UTC 24 |
| Finished | Sep 09 09:10:17 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957308469 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.957308469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/25.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.3277289174 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 284989932935 ps |
| CPU time | 107.45 seconds |
| Started | Sep 09 09:01:29 PM UTC 24 |
| Finished | Sep 09 09:03:19 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277289174 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.3277289174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/27.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.2462632901 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 195224076748 ps |
| CPU time | 267.63 seconds |
| Started | Sep 09 09:01:44 PM UTC 24 |
| Finished | Sep 09 09:06:15 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462632901 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.2462632901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/29.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.4116097359 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 488448543 ps |
| CPU time | 1.45 seconds |
| Started | Sep 09 09:02:45 PM UTC 24 |
| Finished | Sep 09 09:02:47 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116097359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4116097359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/40.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.3235664488 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 224734096497 ps |
| CPU time | 401.69 seconds |
| Started | Sep 09 09:03:06 PM UTC 24 |
| Finished | Sep 09 09:09:52 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235664488 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.3235664488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/45.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.2965853289 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13199387334 ps |
| CPU time | 47.64 seconds |
| Started | Sep 09 08:59:32 PM UTC 24 |
| Finished | Sep 09 09:00:22 PM UTC 24 |
| Peak memory | 219340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2965853289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 6.aon_timer_stress_all_with_rand_reset.2965853289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.2826147337 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 561771480 ps |
| CPU time | 2.84 seconds |
| Started | Sep 09 09:00:29 PM UTC 24 |
| Finished | Sep 09 09:00:33 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826147337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2826147337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.3995144611 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 255361126809 ps |
| CPU time | 489.15 seconds |
| Started | Sep 09 09:01:01 PM UTC 24 |
| Finished | Sep 09 09:09:17 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995144611 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.3995144611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/23.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.290716016 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 538250251 ps |
| CPU time | 1.7 seconds |
| Started | Sep 09 09:01:50 PM UTC 24 |
| Finished | Sep 09 09:01:53 PM UTC 24 |
| Peak memory | 199372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290716016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.290716016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/32.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.1383872992 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 43803043693 ps |
| CPU time | 29.7 seconds |
| Started | Sep 09 09:02:02 PM UTC 24 |
| Finished | Sep 09 09:02:33 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383872992 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.1383872992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/34.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.1291629430 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 402036139 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 09:02:07 PM UTC 24 |
| Finished | Sep 09 09:02:09 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291629430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1291629430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/35.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.1383747920 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 144970065441 ps |
| CPU time | 202.18 seconds |
| Started | Sep 09 09:02:57 PM UTC 24 |
| Finished | Sep 09 09:06:22 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383747920 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.1383747920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/43.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.3581834782 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 9687048025 ps |
| CPU time | 17.43 seconds |
| Started | Sep 09 09:02:56 PM UTC 24 |
| Finished | Sep 09 09:03:14 PM UTC 24 |
| Peak memory | 219528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3581834782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 43.aon_timer_stress_all_with_rand_reset.3581834782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.846225010 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 785786644029 ps |
| CPU time | 69.9 seconds |
| Started | Sep 09 09:03:01 PM UTC 24 |
| Finished | Sep 09 09:04:13 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846225010 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.846225010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/44.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.3497130956 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2482917130 ps |
| CPU time | 20.69 seconds |
| Started | Sep 09 09:03:01 PM UTC 24 |
| Finished | Sep 09 09:03:23 PM UTC 24 |
| Peak memory | 206684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3497130956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 44.aon_timer_stress_all_with_rand_reset.3497130956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.3963850839 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 451374179 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:03:04 PM UTC 24 |
| Finished | Sep 09 09:03:06 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963850839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3963850839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/45.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.322944921 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 6422998906 ps |
| CPU time | 39.9 seconds |
| Started | Sep 09 09:00:07 PM UTC 24 |
| Finished | Sep 09 09:00:48 PM UTC 24 |
| Peak memory | 223212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=322944921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.aon_timer_stress_all_with_rand_reset.322944921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.2203624745 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 168573390291 ps |
| CPU time | 283.91 seconds |
| Started | Sep 09 09:00:30 PM UTC 24 |
| Finished | Sep 09 09:05:18 PM UTC 24 |
| Peak memory | 200832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203624745 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.2203624745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.2155546998 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 42883137307 ps |
| CPU time | 28.33 seconds |
| Started | Sep 09 09:00:53 PM UTC 24 |
| Finished | Sep 09 09:01:22 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155546998 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.2155546998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/21.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.1827601846 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 576744724 ps |
| CPU time | 1.9 seconds |
| Started | Sep 09 09:01:13 PM UTC 24 |
| Finished | Sep 09 09:01:16 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827601846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1827601846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/25.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.1478337356 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1538466451 ps |
| CPU time | 7.68 seconds |
| Started | Sep 09 09:02:14 PM UTC 24 |
| Finished | Sep 09 09:02:23 PM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1478337356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 36.aon_timer_stress_all_with_rand_reset.1478337356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.2063153392 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 12166295449 ps |
| CPU time | 29.63 seconds |
| Started | Sep 09 09:02:29 PM UTC 24 |
| Finished | Sep 09 09:03:00 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2063153392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 38.aon_timer_stress_all_with_rand_reset.2063153392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.3141165665 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 557925529 ps |
| CPU time | 2.5 seconds |
| Started | Sep 09 09:02:50 PM UTC 24 |
| Finished | Sep 09 09:02:54 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141165665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3141165665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/42.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.765252693 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 426777995 ps |
| CPU time | 2.09 seconds |
| Started | Sep 09 09:03:01 PM UTC 24 |
| Finished | Sep 09 09:03:04 PM UTC 24 |
| Peak memory | 200572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765252693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.765252693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/44.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.2998065383 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 353327776 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 08:59:32 PM UTC 24 |
| Finished | Sep 09 08:59:35 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998065383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2998065383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.2886778803 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3266358805 ps |
| CPU time | 26.87 seconds |
| Started | Sep 09 09:00:10 PM UTC 24 |
| Finished | Sep 09 09:00:38 PM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2886778803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 14.aon_timer_stress_all_with_rand_reset.2886778803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.2566408057 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 554670676 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 09:02:46 PM UTC 24 |
| Finished | Sep 09 09:02:48 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566408057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2566408057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/41.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.1878795690 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 511894723 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 09:03:20 PM UTC 24 |
| Finished | Sep 09 09:03:22 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878795690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1878795690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/49.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.537118031 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 8211576412 ps |
| CPU time | 7.91 seconds |
| Started | Sep 09 09:03:48 PM UTC 24 |
| Finished | Sep 09 09:03:57 PM UTC 24 |
| Peak memory | 206900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537118031 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.537118031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.890388665 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 704625291 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 08:59:19 PM UTC 24 |
| Finished | Sep 09 08:59:21 PM UTC 24 |
| Peak memory | 199964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890388665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.890388665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.1895894902 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 407179045 ps |
| CPU time | 1.81 seconds |
| Started | Sep 09 08:59:21 PM UTC 24 |
| Finished | Sep 09 08:59:24 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895894902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1895894902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.3104374468 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 521971438 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 09:01:46 PM UTC 24 |
| Finished | Sep 09 09:01:48 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104374468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3104374468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/30.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.3979048724 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 500169233 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 09:01:54 PM UTC 24 |
| Finished | Sep 09 09:01:56 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979048724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3979048724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/33.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.2108347528 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 11976469114 ps |
| CPU time | 39.79 seconds |
| Started | Sep 09 09:02:21 PM UTC 24 |
| Finished | Sep 09 09:03:02 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2108347528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 37.aon_timer_stress_all_with_rand_reset.2108347528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.2852454792 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 525577255 ps |
| CPU time | 2.66 seconds |
| Started | Sep 09 09:02:27 PM UTC 24 |
| Finished | Sep 09 09:02:31 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852454792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2852454792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/38.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.2059598030 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 403694704 ps |
| CPU time | 1.16 seconds |
| Started | Sep 09 08:59:27 PM UTC 24 |
| Finished | Sep 09 08:59:29 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059598030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2059598030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.1976789219 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 210454074733 ps |
| CPU time | 325.97 seconds |
| Started | Sep 09 08:59:21 PM UTC 24 |
| Finished | Sep 09 09:04:51 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976789219 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.1976789219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.2535810555 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 633479414 ps |
| CPU time | 2.05 seconds |
| Started | Sep 09 09:00:15 PM UTC 24 |
| Finished | Sep 09 09:00:18 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535810555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2535810555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.1623008806 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 596480599 ps |
| CPU time | 1.39 seconds |
| Started | Sep 09 09:00:20 PM UTC 24 |
| Finished | Sep 09 09:00:23 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623008806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1623008806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.3981005411 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 566776319 ps |
| CPU time | 1.38 seconds |
| Started | Sep 09 09:00:25 PM UTC 24 |
| Finished | Sep 09 09:00:28 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981005411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3981005411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.817728861 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2716698547 ps |
| CPU time | 18.56 seconds |
| Started | Sep 09 09:00:26 PM UTC 24 |
| Finished | Sep 09 09:00:45 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=817728861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 18.aon_timer_stress_all_with_rand_reset.817728861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.402701041 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3456507010 ps |
| CPU time | 33.5 seconds |
| Started | Sep 09 09:00:30 PM UTC 24 |
| Finished | Sep 09 09:01:05 PM UTC 24 |
| Peak memory | 219724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=402701041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 19.aon_timer_stress_all_with_rand_reset.402701041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.2146930664 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3132261514 ps |
| CPU time | 11.11 seconds |
| Started | Sep 09 08:59:21 PM UTC 24 |
| Finished | Sep 09 08:59:33 PM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2146930664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.aon_timer_stress_all_with_rand_reset.2146930664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.3986595193 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 485363719 ps |
| CPU time | 1.82 seconds |
| Started | Sep 09 09:01:35 PM UTC 24 |
| Finished | Sep 09 09:01:38 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986595193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3986595193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/28.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.1364793659 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 650405756392 ps |
| CPU time | 1257.7 seconds |
| Started | Sep 09 09:01:36 PM UTC 24 |
| Finished | Sep 09 09:22:47 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364793659 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.1364793659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/28.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.3356272366 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 579667619 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 08:59:23 PM UTC 24 |
| Finished | Sep 09 08:59:26 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356272366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3356272366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.1765606844 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 426275113 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 09:01:48 PM UTC 24 |
| Finished | Sep 09 09:01:50 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765606844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1765606844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/31.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.2760790544 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 568832603 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 09:02:00 PM UTC 24 |
| Finished | Sep 09 09:02:02 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760790544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2760790544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/34.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.3448134884 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 430336754 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 09:02:18 PM UTC 24 |
| Finished | Sep 09 09:02:20 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448134884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3448134884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/37.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.3847712327 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 447580213 ps |
| CPU time | 1.75 seconds |
| Started | Sep 09 09:03:08 PM UTC 24 |
| Finished | Sep 09 09:03:11 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847712327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3847712327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/46.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.3605776222 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 459515440 ps |
| CPU time | 1.63 seconds |
| Started | Sep 09 09:03:16 PM UTC 24 |
| Finished | Sep 09 09:03:19 PM UTC 24 |
| Peak memory | 199428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605776222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3605776222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/48.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.89900980 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 128426857201 ps |
| CPU time | 115 seconds |
| Started | Sep 09 08:59:35 PM UTC 24 |
| Finished | Sep 09 09:01:32 PM UTC 24 |
| Peak memory | 200620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89900980 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.89900980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.942331961 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 447795702 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 08:59:38 PM UTC 24 |
| Finished | Sep 09 08:59:40 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942331961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.942331961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.158423457 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4478882220 ps |
| CPU time | 9.1 seconds |
| Started | Sep 09 09:04:15 PM UTC 24 |
| Finished | Sep 09 09:04:25 PM UTC 24 |
| Peak memory | 206928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158423457 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.158423457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.726000216 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 588021828 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 08:59:50 PM UTC 24 |
| Finished | Sep 09 08:59:52 PM UTC 24 |
| Peak memory | 199372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726000216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.726000216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.3625691400 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2055427093 ps |
| CPU time | 27.27 seconds |
| Started | Sep 09 09:01:15 PM UTC 24 |
| Finished | Sep 09 09:01:44 PM UTC 24 |
| Peak memory | 203016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3625691400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 25.aon_timer_stress_all_with_rand_reset.3625691400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.1905994924 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 385119826 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 09:01:42 PM UTC 24 |
| Finished | Sep 09 09:01:45 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905994924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1905994924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/29.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.2163157454 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 14767314090 ps |
| CPU time | 13.31 seconds |
| Started | Sep 09 09:01:55 PM UTC 24 |
| Finished | Sep 09 09:02:09 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2163157454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 33.aon_timer_stress_all_with_rand_reset.2163157454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.2632290601 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 430927180 ps |
| CPU time | 2.41 seconds |
| Started | Sep 09 08:59:35 PM UTC 24 |
| Finished | Sep 09 08:59:38 PM UTC 24 |
| Peak memory | 200772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632290601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2632290601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2702696156 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 513797429 ps |
| CPU time | 1.34 seconds |
| Started | Sep 09 09:03:31 PM UTC 24 |
| Finished | Sep 09 09:03:33 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702696156 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.2702696156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2365780590 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 7124025801 ps |
| CPU time | 10.02 seconds |
| Started | Sep 09 09:03:29 PM UTC 24 |
| Finished | Sep 09 09:03:41 PM UTC 24 |
| Peak memory | 205916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365780590 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.2365780590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3312138452 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 614766271 ps |
| CPU time | 2.76 seconds |
| Started | Sep 09 09:03:27 PM UTC 24 |
| Finished | Sep 09 09:03:31 PM UTC 24 |
| Peak memory | 203260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312138452 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.3312138452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1507682882 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 564871440 ps |
| CPU time | 2.64 seconds |
| Started | Sep 09 09:03:32 PM UTC 24 |
| Finished | Sep 09 09:03:36 PM UTC 24 |
| Peak memory | 205504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1507682882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim er_csr_mem_rw_with_rand_reset.1507682882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.562837670 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 508215773 ps |
| CPU time | 2.38 seconds |
| Started | Sep 09 09:03:29 PM UTC 24 |
| Finished | Sep 09 09:03:33 PM UTC 24 |
| Peak memory | 203324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562837670 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.562837670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.1216532167 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 293302495 ps |
| CPU time | 1.6 seconds |
| Started | Sep 09 09:03:24 PM UTC 24 |
| Finished | Sep 09 09:03:27 PM UTC 24 |
| Peak memory | 200620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216532167 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1216532167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2036989293 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 486504759 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 09:03:27 PM UTC 24 |
| Finished | Sep 09 09:03:30 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036989293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.2036989293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.1099618680 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 305143745 ps |
| CPU time | 1.85 seconds |
| Started | Sep 09 09:03:26 PM UTC 24 |
| Finished | Sep 09 09:03:29 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099618680 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.1099618680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.3553696522 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 476915082 ps |
| CPU time | 3.55 seconds |
| Started | Sep 09 09:03:24 PM UTC 24 |
| Finished | Sep 09 09:03:29 PM UTC 24 |
| Peak memory | 207168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553696522 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3553696522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2379338365 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7689565641 ps |
| CPU time | 26.05 seconds |
| Started | Sep 09 09:03:24 PM UTC 24 |
| Finished | Sep 09 09:03:51 PM UTC 24 |
| Peak memory | 206728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379338365 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.2379338365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.769086612 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 7277180970 ps |
| CPU time | 23.28 seconds |
| Started | Sep 09 09:03:39 PM UTC 24 |
| Finished | Sep 09 09:04:04 PM UTC 24 |
| Peak memory | 205720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769086612 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.769086612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2177589148 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 756199515 ps |
| CPU time | 3.23 seconds |
| Started | Sep 09 09:03:38 PM UTC 24 |
| Finished | Sep 09 09:03:42 PM UTC 24 |
| Peak memory | 203192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177589148 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.2177589148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4157717084 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 542087156 ps |
| CPU time | 1.61 seconds |
| Started | Sep 09 09:03:41 PM UTC 24 |
| Finished | Sep 09 09:03:44 PM UTC 24 |
| Peak memory | 206888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4157717084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim er_csr_mem_rw_with_rand_reset.4157717084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.1997724858 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 362102994 ps |
| CPU time | 1.98 seconds |
| Started | Sep 09 09:03:39 PM UTC 24 |
| Finished | Sep 09 09:03:42 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997724858 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1997724858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.562358935 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 319735373 ps |
| CPU time | 1.07 seconds |
| Started | Sep 09 09:03:36 PM UTC 24 |
| Finished | Sep 09 09:03:38 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562358935 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.562358935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2364435979 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 542139512 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 09:03:37 PM UTC 24 |
| Finished | Sep 09 09:03:39 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364435979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.2364435979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.1403684892 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 415520089 ps |
| CPU time | 0.83 seconds |
| Started | Sep 09 09:03:36 PM UTC 24 |
| Finished | Sep 09 09:03:38 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403684892 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.1403684892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2142695223 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1204851107 ps |
| CPU time | 5.94 seconds |
| Started | Sep 09 09:03:40 PM UTC 24 |
| Finished | Sep 09 09:03:47 PM UTC 24 |
| Peak memory | 203312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142695223 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.2142695223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.413524370 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 671938126 ps |
| CPU time | 2.86 seconds |
| Started | Sep 09 09:03:34 PM UTC 24 |
| Finished | Sep 09 09:03:38 PM UTC 24 |
| Peak memory | 207032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413524370 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.413524370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2070582270 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 496308955 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 09:04:15 PM UTC 24 |
| Finished | Sep 09 09:04:17 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2070582270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_ti mer_csr_mem_rw_with_rand_reset.2070582270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.1422939203 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 489703263 ps |
| CPU time | 1.71 seconds |
| Started | Sep 09 09:04:13 PM UTC 24 |
| Finished | Sep 09 09:04:17 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422939203 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1422939203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.1756309841 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 515526788 ps |
| CPU time | 2.37 seconds |
| Started | Sep 09 09:04:13 PM UTC 24 |
| Finished | Sep 09 09:04:17 PM UTC 24 |
| Peak memory | 203504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756309841 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1756309841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.546402970 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3001867401 ps |
| CPU time | 6.61 seconds |
| Started | Sep 09 09:04:14 PM UTC 24 |
| Finished | Sep 09 09:04:22 PM UTC 24 |
| Peak memory | 205424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546402970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.546402970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.858653543 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 583719466 ps |
| CPU time | 3.39 seconds |
| Started | Sep 09 09:04:12 PM UTC 24 |
| Finished | Sep 09 09:04:17 PM UTC 24 |
| Peak memory | 207008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858653543 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.858653543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.61331918 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 9086307652 ps |
| CPU time | 13.97 seconds |
| Started | Sep 09 09:04:13 PM UTC 24 |
| Finished | Sep 09 09:04:29 PM UTC 24 |
| Peak memory | 207136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61331918 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.61331918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.600955209 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 394056145 ps |
| CPU time | 2.2 seconds |
| Started | Sep 09 09:04:16 PM UTC 24 |
| Finished | Sep 09 09:04:19 PM UTC 24 |
| Peak memory | 205432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=600955209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_tim er_csr_mem_rw_with_rand_reset.600955209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.4106479254 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 356642007 ps |
| CPU time | 1.87 seconds |
| Started | Sep 09 09:04:16 PM UTC 24 |
| Finished | Sep 09 09:04:19 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106479254 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4106479254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.981936923 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 531984940 ps |
| CPU time | 1.25 seconds |
| Started | Sep 09 09:04:16 PM UTC 24 |
| Finished | Sep 09 09:04:18 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981936923 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.981936923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3633333218 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1189452805 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 09:04:16 PM UTC 24 |
| Finished | Sep 09 09:04:18 PM UTC 24 |
| Peak memory | 201964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633333218 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.3633333218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2896423653 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 487397120 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 09:04:15 PM UTC 24 |
| Finished | Sep 09 09:04:17 PM UTC 24 |
| Peak memory | 206992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896423653 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2896423653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3238636120 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 453211042 ps |
| CPU time | 2.25 seconds |
| Started | Sep 09 09:04:18 PM UTC 24 |
| Finished | Sep 09 09:04:22 PM UTC 24 |
| Peak memory | 205624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3238636120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_ti mer_csr_mem_rw_with_rand_reset.3238636120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.739641129 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 424475568 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 09:04:17 PM UTC 24 |
| Finished | Sep 09 09:04:19 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739641129 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.739641129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.3136403413 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 342337673 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 09:04:17 PM UTC 24 |
| Finished | Sep 09 09:04:19 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136403413 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3136403413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4033335632 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3044195611 ps |
| CPU time | 3.01 seconds |
| Started | Sep 09 09:04:18 PM UTC 24 |
| Finished | Sep 09 09:04:22 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033335632 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.4033335632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.893405065 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 585860047 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 09:04:17 PM UTC 24 |
| Finished | Sep 09 09:04:20 PM UTC 24 |
| Peak memory | 207000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893405065 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.893405065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.534240925 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4404658057 ps |
| CPU time | 3.91 seconds |
| Started | Sep 09 09:04:17 PM UTC 24 |
| Finished | Sep 09 09:04:22 PM UTC 24 |
| Peak memory | 206804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534240925 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.534240925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.747334725 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 450455390 ps |
| CPU time | 1.99 seconds |
| Started | Sep 09 09:04:21 PM UTC 24 |
| Finished | Sep 09 09:04:24 PM UTC 24 |
| Peak memory | 203624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=747334725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_tim er_csr_mem_rw_with_rand_reset.747334725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2717855077 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 451422013 ps |
| CPU time | 2.36 seconds |
| Started | Sep 09 09:04:20 PM UTC 24 |
| Finished | Sep 09 09:04:23 PM UTC 24 |
| Peak memory | 203184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717855077 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2717855077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.3083866099 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 474053773 ps |
| CPU time | 1.4 seconds |
| Started | Sep 09 09:04:19 PM UTC 24 |
| Finished | Sep 09 09:04:22 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083866099 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3083866099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2631509909 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1160806152 ps |
| CPU time | 2.69 seconds |
| Started | Sep 09 09:04:20 PM UTC 24 |
| Finished | Sep 09 09:04:23 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631509909 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.2631509909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.1174332318 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 374128619 ps |
| CPU time | 3.21 seconds |
| Started | Sep 09 09:04:18 PM UTC 24 |
| Finished | Sep 09 09:04:23 PM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174332318 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1174332318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3046190350 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 8354564624 ps |
| CPU time | 5.9 seconds |
| Started | Sep 09 09:04:18 PM UTC 24 |
| Finished | Sep 09 09:04:25 PM UTC 24 |
| Peak memory | 207132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046190350 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.3046190350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.973063954 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 351761135 ps |
| CPU time | 1.4 seconds |
| Started | Sep 09 09:04:23 PM UTC 24 |
| Finished | Sep 09 09:04:25 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=973063954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_tim er_csr_mem_rw_with_rand_reset.973063954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.101657624 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 332840413 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 09:04:23 PM UTC 24 |
| Finished | Sep 09 09:04:25 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101657624 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.101657624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.3622768855 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 492413138 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 09:04:22 PM UTC 24 |
| Finished | Sep 09 09:04:24 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622768855 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3622768855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3586485666 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2260679263 ps |
| CPU time | 4.91 seconds |
| Started | Sep 09 09:04:23 PM UTC 24 |
| Finished | Sep 09 09:04:29 PM UTC 24 |
| Peak memory | 205688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586485666 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.3586485666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.993777818 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 436829431 ps |
| CPU time | 4.57 seconds |
| Started | Sep 09 09:04:21 PM UTC 24 |
| Finished | Sep 09 09:04:26 PM UTC 24 |
| Peak memory | 206884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993777818 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.993777818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3094345896 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4446049695 ps |
| CPU time | 3.39 seconds |
| Started | Sep 09 09:04:21 PM UTC 24 |
| Finished | Sep 09 09:04:25 PM UTC 24 |
| Peak memory | 205420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094345896 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.3094345896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2055894167 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 392674078 ps |
| CPU time | 1.44 seconds |
| Started | Sep 09 09:04:24 PM UTC 24 |
| Finished | Sep 09 09:04:27 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2055894167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti mer_csr_mem_rw_with_rand_reset.2055894167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.344402780 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 418498324 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 09:04:23 PM UTC 24 |
| Finished | Sep 09 09:04:26 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344402780 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.344402780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.3097312810 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 403608573 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 09:04:23 PM UTC 24 |
| Finished | Sep 09 09:04:25 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097312810 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3097312810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3576563498 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1311146381 ps |
| CPU time | 2.41 seconds |
| Started | Sep 09 09:04:24 PM UTC 24 |
| Finished | Sep 09 09:04:28 PM UTC 24 |
| Peak memory | 203308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576563498 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.3576563498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.415822421 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 426448186 ps |
| CPU time | 2.54 seconds |
| Started | Sep 09 09:04:23 PM UTC 24 |
| Finished | Sep 09 09:04:27 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415822421 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.415822421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3899434484 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 8491643452 ps |
| CPU time | 5.25 seconds |
| Started | Sep 09 09:04:23 PM UTC 24 |
| Finished | Sep 09 09:04:29 PM UTC 24 |
| Peak memory | 207056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899434484 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.3899434484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1287178341 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 516287228 ps |
| CPU time | 2.49 seconds |
| Started | Sep 09 09:04:27 PM UTC 24 |
| Finished | Sep 09 09:04:30 PM UTC 24 |
| Peak memory | 205496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1287178341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti mer_csr_mem_rw_with_rand_reset.1287178341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.1872898289 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 484732389 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 09:04:26 PM UTC 24 |
| Finished | Sep 09 09:04:29 PM UTC 24 |
| Peak memory | 201336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872898289 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1872898289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.1307834486 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 462046701 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 09:04:26 PM UTC 24 |
| Finished | Sep 09 09:04:28 PM UTC 24 |
| Peak memory | 201676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307834486 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1307834486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1431642084 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1314219079 ps |
| CPU time | 3.61 seconds |
| Started | Sep 09 09:04:27 PM UTC 24 |
| Finished | Sep 09 09:04:31 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431642084 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.1431642084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.4008978011 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 456140743 ps |
| CPU time | 3.1 seconds |
| Started | Sep 09 09:04:24 PM UTC 24 |
| Finished | Sep 09 09:04:28 PM UTC 24 |
| Peak memory | 207132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008978011 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4008978011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4145084721 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 8331470900 ps |
| CPU time | 15.83 seconds |
| Started | Sep 09 09:04:25 PM UTC 24 |
| Finished | Sep 09 09:04:42 PM UTC 24 |
| Peak memory | 207264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145084721 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.4145084721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2062627948 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 735792194 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 09:04:28 PM UTC 24 |
| Finished | Sep 09 09:04:30 PM UTC 24 |
| Peak memory | 206356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2062627948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti mer_csr_mem_rw_with_rand_reset.2062627948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.1253587136 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 468330502 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 09:04:28 PM UTC 24 |
| Finished | Sep 09 09:04:31 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253587136 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1253587136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.3476665219 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 451574645 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 09:04:27 PM UTC 24 |
| Finished | Sep 09 09:04:29 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476665219 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3476665219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.31529851 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1700429908 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 09:04:28 PM UTC 24 |
| Finished | Sep 09 09:04:31 PM UTC 24 |
| Peak memory | 203580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31529851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.31529851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.2601600234 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 820928276 ps |
| CPU time | 2.29 seconds |
| Started | Sep 09 09:04:27 PM UTC 24 |
| Finished | Sep 09 09:04:30 PM UTC 24 |
| Peak memory | 207352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601600234 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2601600234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.387644899 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4332048712 ps |
| CPU time | 2.98 seconds |
| Started | Sep 09 09:04:27 PM UTC 24 |
| Finished | Sep 09 09:04:31 PM UTC 24 |
| Peak memory | 205796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387644899 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.387644899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.475680920 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 421726510 ps |
| CPU time | 2.57 seconds |
| Started | Sep 09 09:04:29 PM UTC 24 |
| Finished | Sep 09 09:04:33 PM UTC 24 |
| Peak memory | 205504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=475680920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_tim er_csr_mem_rw_with_rand_reset.475680920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.1979021305 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 454525858 ps |
| CPU time | 2.04 seconds |
| Started | Sep 09 09:04:29 PM UTC 24 |
| Finished | Sep 09 09:04:32 PM UTC 24 |
| Peak memory | 203320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979021305 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1979021305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.436891915 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 315027605 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:04:29 PM UTC 24 |
| Finished | Sep 09 09:04:31 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436891915 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.436891915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.582734934 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1368207946 ps |
| CPU time | 4.63 seconds |
| Started | Sep 09 09:04:29 PM UTC 24 |
| Finished | Sep 09 09:04:35 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582734934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.582734934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1662928689 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 562882528 ps |
| CPU time | 2.76 seconds |
| Started | Sep 09 09:04:28 PM UTC 24 |
| Finished | Sep 09 09:04:32 PM UTC 24 |
| Peak memory | 207096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662928689 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1662928689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2545563147 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4734525655 ps |
| CPU time | 3.75 seconds |
| Started | Sep 09 09:04:29 PM UTC 24 |
| Finished | Sep 09 09:04:34 PM UTC 24 |
| Peak memory | 206160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545563147 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.2545563147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.578649109 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 537382172 ps |
| CPU time | 1.6 seconds |
| Started | Sep 09 09:04:32 PM UTC 24 |
| Finished | Sep 09 09:04:35 PM UTC 24 |
| Peak memory | 206336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=578649109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_tim er_csr_mem_rw_with_rand_reset.578649109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.169838506 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 479068734 ps |
| CPU time | 1.76 seconds |
| Started | Sep 09 09:04:32 PM UTC 24 |
| Finished | Sep 09 09:04:35 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169838506 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.169838506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.2363664551 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 492887655 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:04:31 PM UTC 24 |
| Finished | Sep 09 09:04:33 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363664551 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2363664551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.113242822 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2567625935 ps |
| CPU time | 1.66 seconds |
| Started | Sep 09 09:04:32 PM UTC 24 |
| Finished | Sep 09 09:04:35 PM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113242822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.113242822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.1680972596 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 464418395 ps |
| CPU time | 2.41 seconds |
| Started | Sep 09 09:04:30 PM UTC 24 |
| Finished | Sep 09 09:04:34 PM UTC 24 |
| Peak memory | 206588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680972596 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1680972596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3824325701 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4600368624 ps |
| CPU time | 4.23 seconds |
| Started | Sep 09 09:04:30 PM UTC 24 |
| Finished | Sep 09 09:04:36 PM UTC 24 |
| Peak memory | 205124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824325701 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.3824325701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3952552447 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 367751971 ps |
| CPU time | 1.66 seconds |
| Started | Sep 09 09:03:47 PM UTC 24 |
| Finished | Sep 09 09:03:50 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952552447 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.3952552447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2769014679 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 6997839431 ps |
| CPU time | 7.01 seconds |
| Started | Sep 09 09:03:46 PM UTC 24 |
| Finished | Sep 09 09:03:54 PM UTC 24 |
| Peak memory | 205980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769014679 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.2769014679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3196321374 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1147121345 ps |
| CPU time | 4.86 seconds |
| Started | Sep 09 09:03:45 PM UTC 24 |
| Finished | Sep 09 09:03:51 PM UTC 24 |
| Peak memory | 203192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196321374 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.3196321374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1750845688 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 344444738 ps |
| CPU time | 2.16 seconds |
| Started | Sep 09 09:03:48 PM UTC 24 |
| Finished | Sep 09 09:03:51 PM UTC 24 |
| Peak memory | 205504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1750845688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_tim er_csr_mem_rw_with_rand_reset.1750845688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1146143057 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 428487423 ps |
| CPU time | 1.79 seconds |
| Started | Sep 09 09:03:45 PM UTC 24 |
| Finished | Sep 09 09:03:48 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146143057 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1146143057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.2945790311 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 377426021 ps |
| CPU time | 2.16 seconds |
| Started | Sep 09 09:03:44 PM UTC 24 |
| Finished | Sep 09 09:03:47 PM UTC 24 |
| Peak memory | 201460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945790311 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2945790311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3757293433 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 326277556 ps |
| CPU time | 1.67 seconds |
| Started | Sep 09 09:03:45 PM UTC 24 |
| Finished | Sep 09 09:03:47 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757293433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.3757293433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.3662912185 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 345427559 ps |
| CPU time | 1.33 seconds |
| Started | Sep 09 09:03:44 PM UTC 24 |
| Finished | Sep 09 09:03:46 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662912185 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.3662912185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3773086753 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 982180792 ps |
| CPU time | 4.67 seconds |
| Started | Sep 09 09:03:48 PM UTC 24 |
| Finished | Sep 09 09:03:54 PM UTC 24 |
| Peak memory | 203576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773086753 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.3773086753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.4150033444 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 336804501 ps |
| CPU time | 2.63 seconds |
| Started | Sep 09 09:03:41 PM UTC 24 |
| Finished | Sep 09 09:03:45 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150033444 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4150033444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1947641792 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4119714101 ps |
| CPU time | 4.23 seconds |
| Started | Sep 09 09:03:43 PM UTC 24 |
| Finished | Sep 09 09:03:49 PM UTC 24 |
| Peak memory | 206824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947641792 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.1947641792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.289201474 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 378670359 ps |
| CPU time | 1.93 seconds |
| Started | Sep 09 09:04:32 PM UTC 24 |
| Finished | Sep 09 09:04:35 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289201474 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.289201474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/20.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.111246087 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 433861000 ps |
| CPU time | 1.54 seconds |
| Started | Sep 09 09:04:32 PM UTC 24 |
| Finished | Sep 09 09:04:35 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111246087 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.111246087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/21.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.930128864 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 514216263 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 09:04:32 PM UTC 24 |
| Finished | Sep 09 09:04:34 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930128864 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.930128864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/22.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.2629875300 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 355233207 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 09:04:32 PM UTC 24 |
| Finished | Sep 09 09:04:34 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629875300 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2629875300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/23.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.1402294561 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 331967591 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 09:04:32 PM UTC 24 |
| Finished | Sep 09 09:04:34 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402294561 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1402294561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/24.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.3353434791 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 413860115 ps |
| CPU time | 1.63 seconds |
| Started | Sep 09 09:04:32 PM UTC 24 |
| Finished | Sep 09 09:04:35 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353434791 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3353434791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/25.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.704440433 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 391889950 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 09:04:33 PM UTC 24 |
| Finished | Sep 09 09:04:36 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704440433 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.704440433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/26.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.3411546425 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 410110169 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 09:04:33 PM UTC 24 |
| Finished | Sep 09 09:04:36 PM UTC 24 |
| Peak memory | 201516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411546425 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3411546425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/27.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.1640678373 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 413884754 ps |
| CPU time | 0.84 seconds |
| Started | Sep 09 09:04:33 PM UTC 24 |
| Finished | Sep 09 09:04:35 PM UTC 24 |
| Peak memory | 199412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640678373 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1640678373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/28.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.1557272608 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 302185160 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 09:04:34 PM UTC 24 |
| Finished | Sep 09 09:04:36 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557272608 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1557272608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/29.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.168323709 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 445854943 ps |
| CPU time | 1.61 seconds |
| Started | Sep 09 09:03:53 PM UTC 24 |
| Finished | Sep 09 09:03:55 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168323709 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.168323709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1264727912 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 7258768511 ps |
| CPU time | 6.7 seconds |
| Started | Sep 09 09:03:53 PM UTC 24 |
| Finished | Sep 09 09:04:00 PM UTC 24 |
| Peak memory | 205652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264727912 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.1264727912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3550819086 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 863575871 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 09:03:51 PM UTC 24 |
| Finished | Sep 09 09:03:54 PM UTC 24 |
| Peak memory | 199736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550819086 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.3550819086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.438040027 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 530218325 ps |
| CPU time | 1.78 seconds |
| Started | Sep 09 09:03:53 PM UTC 24 |
| Finished | Sep 09 09:03:56 PM UTC 24 |
| Peak memory | 205596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=438040027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_time r_csr_mem_rw_with_rand_reset.438040027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.612229463 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 361665732 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 09:03:53 PM UTC 24 |
| Finished | Sep 09 09:03:55 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612229463 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.612229463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.1172226314 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 398035113 ps |
| CPU time | 1.05 seconds |
| Started | Sep 09 09:03:49 PM UTC 24 |
| Finished | Sep 09 09:03:51 PM UTC 24 |
| Peak memory | 201840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172226314 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1172226314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1600522108 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 389449335 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:03:50 PM UTC 24 |
| Finished | Sep 09 09:03:53 PM UTC 24 |
| Peak memory | 199856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600522108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.1600522108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.3537567863 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 354869091 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:03:49 PM UTC 24 |
| Finished | Sep 09 09:03:51 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537567863 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.3537567863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3911526343 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2885130944 ps |
| CPU time | 1.87 seconds |
| Started | Sep 09 09:03:53 PM UTC 24 |
| Finished | Sep 09 09:03:56 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911526343 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.3911526343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.1763725980 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 602408021 ps |
| CPU time | 2.24 seconds |
| Started | Sep 09 09:03:48 PM UTC 24 |
| Finished | Sep 09 09:03:51 PM UTC 24 |
| Peak memory | 207264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763725980 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1763725980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.694555397 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 359400407 ps |
| CPU time | 2.05 seconds |
| Started | Sep 09 09:04:34 PM UTC 24 |
| Finished | Sep 09 09:04:38 PM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694555397 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.694555397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/30.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.531094404 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 312327793 ps |
| CPU time | 0.75 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:37 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531094404 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.531094404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/31.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.2046976094 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 428172131 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:38 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046976094 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2046976094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/32.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.3465325786 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 450513383 ps |
| CPU time | 2.27 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:39 PM UTC 24 |
| Peak memory | 201520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465325786 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3465325786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/33.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.3132153371 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 542867214 ps |
| CPU time | 0.9 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:38 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132153371 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3132153371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/34.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.352894304 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 327062996 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:38 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352894304 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.352894304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/35.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.2419979199 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 430279998 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:39 PM UTC 24 |
| Peak memory | 201456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419979199 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2419979199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/36.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.3139721046 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 478106591 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:38 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139721046 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3139721046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/37.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.3529386432 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 294444073 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:38 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529386432 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3529386432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/38.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.1446105345 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 375724977 ps |
| CPU time | 1.74 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:39 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446105345 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1446105345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/39.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.246529379 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 390045095 ps |
| CPU time | 2.2 seconds |
| Started | Sep 09 09:03:58 PM UTC 24 |
| Finished | Sep 09 09:04:02 PM UTC 24 |
| Peak memory | 203324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246529379 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.246529379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1167517828 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 7030241485 ps |
| CPU time | 11.5 seconds |
| Started | Sep 09 09:03:56 PM UTC 24 |
| Finished | Sep 09 09:04:10 PM UTC 24 |
| Peak memory | 205916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167517828 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.1167517828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1174565067 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 833292531 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 09:03:56 PM UTC 24 |
| Finished | Sep 09 09:04:00 PM UTC 24 |
| Peak memory | 201784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174565067 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.1174565067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1587106774 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 768927070 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 09:03:59 PM UTC 24 |
| Finished | Sep 09 09:04:02 PM UTC 24 |
| Peak memory | 206952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1587106774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim er_csr_mem_rw_with_rand_reset.1587106774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.3108764319 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 309054102 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:03:56 PM UTC 24 |
| Finished | Sep 09 09:03:59 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108764319 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3108764319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.669418713 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 374828074 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 09:03:55 PM UTC 24 |
| Finished | Sep 09 09:03:59 PM UTC 24 |
| Peak memory | 201212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669418713 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.669418713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3677224503 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 496339937 ps |
| CPU time | 2.49 seconds |
| Started | Sep 09 09:03:56 PM UTC 24 |
| Finished | Sep 09 09:04:01 PM UTC 24 |
| Peak memory | 201012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677224503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.3677224503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.4059702485 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 362690912 ps |
| CPU time | 1.98 seconds |
| Started | Sep 09 09:03:55 PM UTC 24 |
| Finished | Sep 09 09:03:59 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059702485 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.4059702485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3698943662 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 2418378520 ps |
| CPU time | 7.73 seconds |
| Started | Sep 09 09:03:58 PM UTC 24 |
| Finished | Sep 09 09:04:08 PM UTC 24 |
| Peak memory | 205496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698943662 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.3698943662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.223156240 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 421009532 ps |
| CPU time | 2.99 seconds |
| Started | Sep 09 09:03:54 PM UTC 24 |
| Finished | Sep 09 09:03:58 PM UTC 24 |
| Peak memory | 207208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223156240 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.223156240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2925513071 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 4582704870 ps |
| CPU time | 13.75 seconds |
| Started | Sep 09 09:03:55 PM UTC 24 |
| Finished | Sep 09 09:04:11 PM UTC 24 |
| Peak memory | 205504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925513071 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.2925513071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.3425721385 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 439405042 ps |
| CPU time | 0.88 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:38 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425721385 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3425721385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/40.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.64928452 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 353701179 ps |
| CPU time | 1.86 seconds |
| Started | Sep 09 09:04:36 PM UTC 24 |
| Finished | Sep 09 09:04:39 PM UTC 24 |
| Peak memory | 201840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64928452 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.64928452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/41.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2088372269 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 551090216 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 09:04:37 PM UTC 24 |
| Finished | Sep 09 09:04:39 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088372269 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2088372269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/42.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2189585901 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 348056286 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 09:04:37 PM UTC 24 |
| Finished | Sep 09 09:04:39 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189585901 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2189585901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/43.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.141144098 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 492028758 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 09:04:37 PM UTC 24 |
| Finished | Sep 09 09:04:39 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141144098 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.141144098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/44.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.204919758 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 370980833 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:04:37 PM UTC 24 |
| Finished | Sep 09 09:04:39 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204919758 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.204919758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/45.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.2979078990 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 543859846 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 09:04:37 PM UTC 24 |
| Finished | Sep 09 09:04:39 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979078990 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2979078990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/46.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.172711559 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 286359628 ps |
| CPU time | 1.72 seconds |
| Started | Sep 09 09:04:38 PM UTC 24 |
| Finished | Sep 09 09:04:41 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172711559 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.172711559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/47.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.3925848527 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 460311522 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 09:04:38 PM UTC 24 |
| Finished | Sep 09 09:04:40 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925848527 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3925848527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/48.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.1895167004 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 504191877 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 09:04:38 PM UTC 24 |
| Finished | Sep 09 09:04:41 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895167004 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1895167004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/49.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2065568942 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 420089271 ps |
| CPU time | 1.66 seconds |
| Started | Sep 09 09:04:02 PM UTC 24 |
| Finished | Sep 09 09:04:05 PM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2065568942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_tim er_csr_mem_rw_with_rand_reset.2065568942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.896600798 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 476772536 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:04:01 PM UTC 24 |
| Finished | Sep 09 09:04:03 PM UTC 24 |
| Peak memory | 199684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896600798 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.896600798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.1447864287 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 379024190 ps |
| CPU time | 2.06 seconds |
| Started | Sep 09 09:04:01 PM UTC 24 |
| Finished | Sep 09 09:04:04 PM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447864287 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1447864287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1142068721 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1321516890 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 09:04:01 PM UTC 24 |
| Finished | Sep 09 09:04:05 PM UTC 24 |
| Peak memory | 203384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142068721 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.1142068721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.1810373494 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 546940487 ps |
| CPU time | 2.57 seconds |
| Started | Sep 09 09:03:59 PM UTC 24 |
| Finished | Sep 09 09:04:03 PM UTC 24 |
| Peak memory | 207264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810373494 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1810373494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3242267490 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 8568438109 ps |
| CPU time | 10.37 seconds |
| Started | Sep 09 09:04:01 PM UTC 24 |
| Finished | Sep 09 09:04:12 PM UTC 24 |
| Peak memory | 207028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242267490 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.3242267490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2109648484 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 430689403 ps |
| CPU time | 2.31 seconds |
| Started | Sep 09 09:04:05 PM UTC 24 |
| Finished | Sep 09 09:04:09 PM UTC 24 |
| Peak memory | 205940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2109648484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_tim er_csr_mem_rw_with_rand_reset.2109648484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.940076586 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 409636380 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 09:04:04 PM UTC 24 |
| Finished | Sep 09 09:04:06 PM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940076586 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.940076586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2846234067 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 314233376 ps |
| CPU time | 1.3 seconds |
| Started | Sep 09 09:04:03 PM UTC 24 |
| Finished | Sep 09 09:04:05 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846234067 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2846234067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1863339752 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1292931592 ps |
| CPU time | 2.08 seconds |
| Started | Sep 09 09:04:04 PM UTC 24 |
| Finished | Sep 09 09:04:07 PM UTC 24 |
| Peak memory | 203448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863339752 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.1863339752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.7900763 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 547330768 ps |
| CPU time | 3.75 seconds |
| Started | Sep 09 09:04:02 PM UTC 24 |
| Finished | Sep 09 09:04:07 PM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7900763 -assert nopostproc +UVM_TESTNAME=aon_time r_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.7900763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.642808800 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 8449817793 ps |
| CPU time | 7.82 seconds |
| Started | Sep 09 09:04:03 PM UTC 24 |
| Finished | Sep 09 09:04:12 PM UTC 24 |
| Peak memory | 207276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642808800 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.642808800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2298594321 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 468777262 ps |
| CPU time | 2.42 seconds |
| Started | Sep 09 09:04:07 PM UTC 24 |
| Finished | Sep 09 09:04:11 PM UTC 24 |
| Peak memory | 205428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2298594321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim er_csr_mem_rw_with_rand_reset.2298594321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.88238532 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 318772802 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:04:06 PM UTC 24 |
| Finished | Sep 09 09:04:09 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88238532 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.88238532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.3715455763 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 364257375 ps |
| CPU time | 1.84 seconds |
| Started | Sep 09 09:04:06 PM UTC 24 |
| Finished | Sep 09 09:04:09 PM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715455763 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3715455763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1050091201 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1520196549 ps |
| CPU time | 1.92 seconds |
| Started | Sep 09 09:04:06 PM UTC 24 |
| Finished | Sep 09 09:04:10 PM UTC 24 |
| Peak memory | 201904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050091201 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.1050091201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.674487920 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1875926051 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 09:04:05 PM UTC 24 |
| Finished | Sep 09 09:04:10 PM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674487920 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.674487920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1581426236 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4232855964 ps |
| CPU time | 7.48 seconds |
| Started | Sep 09 09:04:05 PM UTC 24 |
| Finished | Sep 09 09:04:14 PM UTC 24 |
| Peak memory | 207060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581426236 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.1581426236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2487659344 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 605496218 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 09:04:10 PM UTC 24 |
| Finished | Sep 09 09:04:12 PM UTC 24 |
| Peak memory | 205980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2487659344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim er_csr_mem_rw_with_rand_reset.2487659344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.4003115150 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 398602914 ps |
| CPU time | 1.07 seconds |
| Started | Sep 09 09:04:10 PM UTC 24 |
| Finished | Sep 09 09:04:12 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003115150 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.4003115150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.1119341793 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 438808279 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 09:04:09 PM UTC 24 |
| Finished | Sep 09 09:04:11 PM UTC 24 |
| Peak memory | 201840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119341793 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1119341793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2869384260 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1137953316 ps |
| CPU time | 4.67 seconds |
| Started | Sep 09 09:04:10 PM UTC 24 |
| Finished | Sep 09 09:04:16 PM UTC 24 |
| Peak memory | 203272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869384260 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.2869384260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.1169528789 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 480852687 ps |
| CPU time | 4.64 seconds |
| Started | Sep 09 09:04:08 PM UTC 24 |
| Finished | Sep 09 09:04:13 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169528789 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1169528789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1505857746 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 8433922195 ps |
| CPU time | 11.96 seconds |
| Started | Sep 09 09:04:09 PM UTC 24 |
| Finished | Sep 09 09:04:22 PM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505857746 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.1505857746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.631264944 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 353896370 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 09:04:12 PM UTC 24 |
| Finished | Sep 09 09:04:15 PM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=631264944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_time r_csr_mem_rw_with_rand_reset.631264944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.2554479534 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 512166483 ps |
| CPU time | 1.71 seconds |
| Started | Sep 09 09:04:11 PM UTC 24 |
| Finished | Sep 09 09:04:14 PM UTC 24 |
| Peak memory | 201836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554479534 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2554479534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.658383795 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 397599796 ps |
| CPU time | 2.13 seconds |
| Started | Sep 09 09:04:11 PM UTC 24 |
| Finished | Sep 09 09:04:14 PM UTC 24 |
| Peak memory | 201468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658383795 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.658383795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.618979002 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 960411076 ps |
| CPU time | 2.5 seconds |
| Started | Sep 09 09:04:12 PM UTC 24 |
| Finished | Sep 09 09:04:16 PM UTC 24 |
| Peak memory | 203572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618979002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.618979002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.2650665319 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 656028136 ps |
| CPU time | 2.73 seconds |
| Started | Sep 09 09:04:11 PM UTC 24 |
| Finished | Sep 09 09:04:15 PM UTC 24 |
| Peak memory | 207040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650665319 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2650665319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1399014653 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 8414102822 ps |
| CPU time | 2.95 seconds |
| Started | Sep 09 09:04:11 PM UTC 24 |
| Finished | Sep 09 09:04:15 PM UTC 24 |
| Peak memory | 207076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399014653 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.1399014653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.849017115 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 59113309696 ps |
| CPU time | 23.61 seconds |
| Started | Sep 09 08:59:19 PM UTC 24 |
| Finished | Sep 09 08:59:44 PM UTC 24 |
| Peak memory | 200612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849017115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.849017115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.3967019179 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 544292345 ps |
| CPU time | 1.79 seconds |
| Started | Sep 09 08:59:19 PM UTC 24 |
| Finished | Sep 09 08:59:22 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967019179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3967019179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/0.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.2943003749 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8478583592 ps |
| CPU time | 13.6 seconds |
| Started | Sep 09 08:59:19 PM UTC 24 |
| Finished | Sep 09 08:59:34 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943003749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2943003749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.1376474262 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4220824211 ps |
| CPU time | 6.83 seconds |
| Started | Sep 09 08:59:21 PM UTC 24 |
| Finished | Sep 09 08:59:29 PM UTC 24 |
| Peak memory | 230852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376474262 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1376474262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.4196788601 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 556540454 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 08:59:19 PM UTC 24 |
| Finished | Sep 09 08:59:21 PM UTC 24 |
| Peak memory | 199224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196788601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.4196788601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.34141569 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 14160177265 ps |
| CPU time | 16.76 seconds |
| Started | Sep 09 08:59:45 PM UTC 24 |
| Finished | Sep 09 09:00:03 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34141569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.34141569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.1065837501 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 368643967 ps |
| CPU time | 1.27 seconds |
| Started | Sep 09 08:59:43 PM UTC 24 |
| Finished | Sep 09 08:59:45 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065837501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1065837501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/10.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.2381368638 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 18321269215 ps |
| CPU time | 34.99 seconds |
| Started | Sep 09 08:59:48 PM UTC 24 |
| Finished | Sep 09 09:00:24 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381368638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2381368638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.423127718 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 443098555 ps |
| CPU time | 2.48 seconds |
| Started | Sep 09 08:59:46 PM UTC 24 |
| Finished | Sep 09 08:59:49 PM UTC 24 |
| Peak memory | 200568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423127718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.423127718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/11.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.1340340434 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2470434340 ps |
| CPU time | 3.1 seconds |
| Started | Sep 09 08:59:53 PM UTC 24 |
| Finished | Sep 09 08:59:58 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340340434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1340340434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.2506155664 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 655461865 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 08:59:53 PM UTC 24 |
| Finished | Sep 09 08:59:55 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506155664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2506155664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/12.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.3175504708 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 720603780 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 09:00:07 PM UTC 24 |
| Finished | Sep 09 09:00:09 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175504708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3175504708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.2152468648 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 5773658080 ps |
| CPU time | 9.06 seconds |
| Started | Sep 09 09:00:07 PM UTC 24 |
| Finished | Sep 09 09:00:17 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152468648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2152468648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.615416988 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 423704192 ps |
| CPU time | 1 seconds |
| Started | Sep 09 09:00:00 PM UTC 24 |
| Finished | Sep 09 09:00:02 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615416988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.615416988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/13.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.1180412716 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 39989174279 ps |
| CPU time | 15.77 seconds |
| Started | Sep 09 09:00:07 PM UTC 24 |
| Finished | Sep 09 09:00:24 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180412716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1180412716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.2140766529 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 418202897 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:00:07 PM UTC 24 |
| Finished | Sep 09 09:00:09 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140766529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2140766529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.217917079 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1310246638 ps |
| CPU time | 1.62 seconds |
| Started | Sep 09 09:00:10 PM UTC 24 |
| Finished | Sep 09 09:00:13 PM UTC 24 |
| Peak memory | 199364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217917079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.217917079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.1457490991 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 546035465 ps |
| CPU time | 2.22 seconds |
| Started | Sep 09 09:00:10 PM UTC 24 |
| Finished | Sep 09 09:00:14 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457490991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1457490991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/15.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.1557831588 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 36962054859 ps |
| CPU time | 56.73 seconds |
| Started | Sep 09 09:00:14 PM UTC 24 |
| Finished | Sep 09 09:01:12 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557831588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1557831588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.3213311357 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 568441305 ps |
| CPU time | 1.67 seconds |
| Started | Sep 09 09:00:14 PM UTC 24 |
| Finished | Sep 09 09:00:16 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213311357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3213311357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/16.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.970231183 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 32837272064 ps |
| CPU time | 5.83 seconds |
| Started | Sep 09 09:00:19 PM UTC 24 |
| Finished | Sep 09 09:00:26 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970231183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.970231183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.2657098294 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 402693656 ps |
| CPU time | 1.26 seconds |
| Started | Sep 09 09:00:18 PM UTC 24 |
| Finished | Sep 09 09:00:20 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657098294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2657098294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/17.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.4050571732 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 39579526644 ps |
| CPU time | 27.6 seconds |
| Started | Sep 09 09:00:24 PM UTC 24 |
| Finished | Sep 09 09:00:53 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050571732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4050571732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.2525656287 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 522685103 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 09:00:23 PM UTC 24 |
| Finished | Sep 09 09:00:25 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525656287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2525656287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/18.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.3261560571 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 20793317929 ps |
| CPU time | 31.94 seconds |
| Started | Sep 09 09:00:29 PM UTC 24 |
| Finished | Sep 09 09:01:02 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261560571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3261560571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.3914054155 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 391156625 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 09:00:27 PM UTC 24 |
| Finished | Sep 09 09:00:29 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914054155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3914054155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/19.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.2807809898 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11245554246 ps |
| CPU time | 10.64 seconds |
| Started | Sep 09 08:59:21 PM UTC 24 |
| Finished | Sep 09 08:59:33 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807809898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2807809898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.57634814 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4248778266 ps |
| CPU time | 7.71 seconds |
| Started | Sep 09 08:59:23 PM UTC 24 |
| Finished | Sep 09 08:59:32 PM UTC 24 |
| Peak memory | 230932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57634814 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.57634814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.2563655178 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 613888177 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 08:59:21 PM UTC 24 |
| Finished | Sep 09 08:59:23 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563655178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2563655178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/2.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.2335767771 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 38762452665 ps |
| CPU time | 65.9 seconds |
| Started | Sep 09 09:00:33 PM UTC 24 |
| Finished | Sep 09 09:01:41 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335767771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2335767771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/20.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.363747187 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 341439104 ps |
| CPU time | 1.99 seconds |
| Started | Sep 09 09:00:32 PM UTC 24 |
| Finished | Sep 09 09:00:35 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363747187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.363747187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/20.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.2289210336 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5615283082 ps |
| CPU time | 14.55 seconds |
| Started | Sep 09 09:00:39 PM UTC 24 |
| Finished | Sep 09 09:00:55 PM UTC 24 |
| Peak memory | 213984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2289210336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 20.aon_timer_stress_all_with_rand_reset.2289210336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.2259198923 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 26054526323 ps |
| CPU time | 24.43 seconds |
| Started | Sep 09 09:00:46 PM UTC 24 |
| Finished | Sep 09 09:01:12 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259198923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2259198923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/21.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.941441764 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 555167894 ps |
| CPU time | 2.5 seconds |
| Started | Sep 09 09:00:45 PM UTC 24 |
| Finished | Sep 09 09:00:49 PM UTC 24 |
| Peak memory | 200568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941441764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.941441764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/21.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.1646495374 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 54837395439 ps |
| CPU time | 95.04 seconds |
| Started | Sep 09 09:00:54 PM UTC 24 |
| Finished | Sep 09 09:02:31 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646495374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1646495374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/22.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.2542602250 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 395103598 ps |
| CPU time | 2.18 seconds |
| Started | Sep 09 09:00:54 PM UTC 24 |
| Finished | Sep 09 09:00:57 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542602250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2542602250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/22.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.3325305450 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5951749823 ps |
| CPU time | 23.19 seconds |
| Started | Sep 09 09:00:56 PM UTC 24 |
| Finished | Sep 09 09:01:20 PM UTC 24 |
| Peak memory | 222920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3325305450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 22.aon_timer_stress_all_with_rand_reset.3325305450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.3396960760 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 25949952566 ps |
| CPU time | 42 seconds |
| Started | Sep 09 09:00:58 PM UTC 24 |
| Finished | Sep 09 09:01:42 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396960760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3396960760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/23.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.3496442216 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 401922468 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 09:00:58 PM UTC 24 |
| Finished | Sep 09 09:01:00 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496442216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3496442216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/23.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.2837488285 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 10248253446 ps |
| CPU time | 6 seconds |
| Started | Sep 09 09:01:02 PM UTC 24 |
| Finished | Sep 09 09:01:10 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837488285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2837488285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/24.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.3394968905 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 633032369 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:01:02 PM UTC 24 |
| Finished | Sep 09 09:01:05 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394968905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3394968905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/24.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.638683504 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 17614358626 ps |
| CPU time | 10.91 seconds |
| Started | Sep 09 09:01:13 PM UTC 24 |
| Finished | Sep 09 09:01:25 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638683504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.638683504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/25.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.2212405856 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 588308454 ps |
| CPU time | 2.89 seconds |
| Started | Sep 09 09:01:11 PM UTC 24 |
| Finished | Sep 09 09:01:15 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212405856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2212405856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/25.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.567481556 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 26412724146 ps |
| CPU time | 47.78 seconds |
| Started | Sep 09 09:01:21 PM UTC 24 |
| Finished | Sep 09 09:02:11 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567481556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.567481556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/26.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.859821231 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 439920068 ps |
| CPU time | 1.2 seconds |
| Started | Sep 09 09:01:21 PM UTC 24 |
| Finished | Sep 09 09:01:23 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859821231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.859821231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/26.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.832783543 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 5433466506 ps |
| CPU time | 17.96 seconds |
| Started | Sep 09 09:01:27 PM UTC 24 |
| Finished | Sep 09 09:01:46 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832783543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.832783543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/27.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.2335642609 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 427098041 ps |
| CPU time | 1.42 seconds |
| Started | Sep 09 09:01:26 PM UTC 24 |
| Finished | Sep 09 09:01:28 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335642609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2335642609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/27.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.437476010 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 40631373492 ps |
| CPU time | 10.85 seconds |
| Started | Sep 09 09:01:33 PM UTC 24 |
| Finished | Sep 09 09:01:45 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437476010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.437476010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/28.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.536716655 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 377257902 ps |
| CPU time | 1.42 seconds |
| Started | Sep 09 09:01:32 PM UTC 24 |
| Finished | Sep 09 09:01:34 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536716655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.536716655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/28.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.879344742 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 570243915 ps |
| CPU time | 1.95 seconds |
| Started | Sep 09 09:01:41 PM UTC 24 |
| Finished | Sep 09 09:01:44 PM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879344742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.879344742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/29.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.1134976968 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 377524434 ps |
| CPU time | 1.62 seconds |
| Started | Sep 09 09:01:39 PM UTC 24 |
| Finished | Sep 09 09:01:42 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134976968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1134976968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/29.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.492468537 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 20481424999 ps |
| CPU time | 18.86 seconds |
| Started | Sep 09 08:59:23 PM UTC 24 |
| Finished | Sep 09 08:59:44 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492468537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.492468537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.3900537875 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4345571759 ps |
| CPU time | 13.55 seconds |
| Started | Sep 09 08:59:24 PM UTC 24 |
| Finished | Sep 09 08:59:39 PM UTC 24 |
| Peak memory | 231192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900537875 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3900537875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.718573937 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2334118179 ps |
| CPU time | 4.49 seconds |
| Started | Sep 09 09:01:45 PM UTC 24 |
| Finished | Sep 09 09:01:50 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718573937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.718573937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/30.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.1704744277 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 500451302 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 09:01:45 PM UTC 24 |
| Finished | Sep 09 09:01:47 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704744277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1704744277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/30.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.1515570141 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 37348901743 ps |
| CPU time | 52.39 seconds |
| Started | Sep 09 09:01:48 PM UTC 24 |
| Finished | Sep 09 09:02:42 PM UTC 24 |
| Peak memory | 200836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515570141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1515570141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/31.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.1248105639 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 540524997 ps |
| CPU time | 2.34 seconds |
| Started | Sep 09 09:01:47 PM UTC 24 |
| Finished | Sep 09 09:01:50 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248105639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1248105639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/31.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.1829968692 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 48075528024 ps |
| CPU time | 87.39 seconds |
| Started | Sep 09 09:01:49 PM UTC 24 |
| Finished | Sep 09 09:03:19 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829968692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1829968692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/32.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.1606661572 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 449268516 ps |
| CPU time | 1.31 seconds |
| Started | Sep 09 09:01:49 PM UTC 24 |
| Finished | Sep 09 09:01:52 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606661572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1606661572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/32.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.1161483609 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 28631035807 ps |
| CPU time | 19.46 seconds |
| Started | Sep 09 09:01:53 PM UTC 24 |
| Finished | Sep 09 09:02:13 PM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161483609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1161483609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/33.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.417954358 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 402362156 ps |
| CPU time | 1.59 seconds |
| Started | Sep 09 09:01:52 PM UTC 24 |
| Finished | Sep 09 09:01:54 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417954358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.417954358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/33.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.2650801514 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 33796683323 ps |
| CPU time | 63.12 seconds |
| Started | Sep 09 09:01:59 PM UTC 24 |
| Finished | Sep 09 09:03:04 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650801514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2650801514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/34.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.3890875843 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 441255147 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 09:01:59 PM UTC 24 |
| Finished | Sep 09 09:02:01 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890875843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3890875843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/34.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.2326678944 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 4870246666 ps |
| CPU time | 26.12 seconds |
| Started | Sep 09 09:02:00 PM UTC 24 |
| Finished | Sep 09 09:02:28 PM UTC 24 |
| Peak memory | 213976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2326678944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 34.aon_timer_stress_all_with_rand_reset.2326678944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.1591873178 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 59227926343 ps |
| CPU time | 46.55 seconds |
| Started | Sep 09 09:02:07 PM UTC 24 |
| Finished | Sep 09 09:02:55 PM UTC 24 |
| Peak memory | 200692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591873178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1591873178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/35.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.4082161715 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 399934594 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:02:03 PM UTC 24 |
| Finished | Sep 09 09:02:05 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082161715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.4082161715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/35.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.2429562216 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 47160163589 ps |
| CPU time | 55.27 seconds |
| Started | Sep 09 09:02:10 PM UTC 24 |
| Finished | Sep 09 09:03:07 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429562216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2429562216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/36.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.3582583064 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 554124085 ps |
| CPU time | 2.61 seconds |
| Started | Sep 09 09:02:10 PM UTC 24 |
| Finished | Sep 09 09:02:14 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582583064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3582583064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/36.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.2727826454 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 31571645960 ps |
| CPU time | 27.84 seconds |
| Started | Sep 09 09:02:14 PM UTC 24 |
| Finished | Sep 09 09:02:44 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727826454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2727826454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/37.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.2028137931 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 371588942 ps |
| CPU time | 1.42 seconds |
| Started | Sep 09 09:02:14 PM UTC 24 |
| Finished | Sep 09 09:02:17 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028137931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2028137931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/37.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.4260867913 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 26268280776 ps |
| CPU time | 18.39 seconds |
| Started | Sep 09 09:02:26 PM UTC 24 |
| Finished | Sep 09 09:02:45 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260867913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.4260867913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/38.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.1958774432 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 440123214 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 09:02:24 PM UTC 24 |
| Finished | Sep 09 09:02:26 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958774432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1958774432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/38.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.3336424584 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 589039821 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 09:02:36 PM UTC 24 |
| Finished | Sep 09 09:02:38 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336424584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3336424584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/39.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.274573172 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 19082281485 ps |
| CPU time | 53.19 seconds |
| Started | Sep 09 09:02:34 PM UTC 24 |
| Finished | Sep 09 09:03:29 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274573172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.274573172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/39.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.439378744 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 616360858 ps |
| CPU time | 2.61 seconds |
| Started | Sep 09 09:02:32 PM UTC 24 |
| Finished | Sep 09 09:02:36 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439378744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.439378744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/39.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.270871515 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1178183947 ps |
| CPU time | 2.99 seconds |
| Started | Sep 09 08:59:24 PM UTC 24 |
| Finished | Sep 09 08:59:28 PM UTC 24 |
| Peak memory | 200772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270871515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.270871515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.2296696593 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4300322377 ps |
| CPU time | 7.65 seconds |
| Started | Sep 09 08:59:28 PM UTC 24 |
| Finished | Sep 09 08:59:37 PM UTC 24 |
| Peak memory | 231280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296696593 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2296696593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.679928565 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 401549074 ps |
| CPU time | 1.23 seconds |
| Started | Sep 09 08:59:24 PM UTC 24 |
| Finished | Sep 09 08:59:26 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679928565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.679928565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/4.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.2159563667 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 8295172013 ps |
| CPU time | 19.83 seconds |
| Started | Sep 09 09:02:43 PM UTC 24 |
| Finished | Sep 09 09:03:04 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159563667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2159563667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/40.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.374993718 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 365940736 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:02:42 PM UTC 24 |
| Finished | Sep 09 09:02:44 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374993718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.374993718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/40.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.3160066016 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 238530398010 ps |
| CPU time | 417.55 seconds |
| Started | Sep 09 09:02:45 PM UTC 24 |
| Finished | Sep 09 09:09:48 PM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160066016 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.3160066016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/40.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.2592862926 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 20182190890 ps |
| CPU time | 23.08 seconds |
| Started | Sep 09 09:02:46 PM UTC 24 |
| Finished | Sep 09 09:03:10 PM UTC 24 |
| Peak memory | 200900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592862926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2592862926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/41.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.2903056779 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 510107338 ps |
| CPU time | 2.38 seconds |
| Started | Sep 09 09:02:46 PM UTC 24 |
| Finished | Sep 09 09:02:49 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903056779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2903056779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/41.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.44078077 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 39111647777 ps |
| CPU time | 50.16 seconds |
| Started | Sep 09 09:02:49 PM UTC 24 |
| Finished | Sep 09 09:03:41 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44078077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.44078077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/42.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.4150310985 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 419593360 ps |
| CPU time | 1.95 seconds |
| Started | Sep 09 09:02:48 PM UTC 24 |
| Finished | Sep 09 09:02:51 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150310985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.4150310985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/42.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.2132125847 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 361618704 ps |
| CPU time | 1.36 seconds |
| Started | Sep 09 09:02:56 PM UTC 24 |
| Finished | Sep 09 09:02:58 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132125847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2132125847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/43.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.2026417004 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 38899481221 ps |
| CPU time | 62.98 seconds |
| Started | Sep 09 09:02:55 PM UTC 24 |
| Finished | Sep 09 09:03:59 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026417004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2026417004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/43.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.3648745064 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 424726336 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 09:02:52 PM UTC 24 |
| Finished | Sep 09 09:02:55 PM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648745064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3648745064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/43.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.399531506 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 7580866393 ps |
| CPU time | 8.87 seconds |
| Started | Sep 09 09:02:59 PM UTC 24 |
| Finished | Sep 09 09:03:09 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399531506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.399531506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/44.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.446386785 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 431764930 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 09:02:58 PM UTC 24 |
| Finished | Sep 09 09:03:00 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446386785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.446386785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/44.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.1752081050 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 45960359082 ps |
| CPU time | 83.26 seconds |
| Started | Sep 09 09:03:03 PM UTC 24 |
| Finished | Sep 09 09:04:28 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752081050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1752081050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/45.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.2136528566 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 448209318 ps |
| CPU time | 1.96 seconds |
| Started | Sep 09 09:03:02 PM UTC 24 |
| Finished | Sep 09 09:03:05 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136528566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2136528566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/45.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.3533463840 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 6911764681 ps |
| CPU time | 5.71 seconds |
| Started | Sep 09 09:03:08 PM UTC 24 |
| Finished | Sep 09 09:03:15 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533463840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3533463840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/46.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.1102899631 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 562837914 ps |
| CPU time | 2.08 seconds |
| Started | Sep 09 09:03:07 PM UTC 24 |
| Finished | Sep 09 09:03:10 PM UTC 24 |
| Peak memory | 200764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102899631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1102899631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/46.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.1580259145 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 523937477 ps |
| CPU time | 2.34 seconds |
| Started | Sep 09 09:03:11 PM UTC 24 |
| Finished | Sep 09 09:03:14 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580259145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1580259145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/47.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.4164628101 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 13449056898 ps |
| CPU time | 22.6 seconds |
| Started | Sep 09 09:03:11 PM UTC 24 |
| Finished | Sep 09 09:03:35 PM UTC 24 |
| Peak memory | 200708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164628101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.4164628101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/47.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.4163339988 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 404065293 ps |
| CPU time | 1.73 seconds |
| Started | Sep 09 09:03:11 PM UTC 24 |
| Finished | Sep 09 09:03:14 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163339988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4163339988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/47.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.2740897217 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 3128865496 ps |
| CPU time | 27.96 seconds |
| Started | Sep 09 09:03:14 PM UTC 24 |
| Finished | Sep 09 09:03:43 PM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2740897217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 47.aon_timer_stress_all_with_rand_reset.2740897217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.2139167774 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 33833871180 ps |
| CPU time | 59.57 seconds |
| Started | Sep 09 09:03:15 PM UTC 24 |
| Finished | Sep 09 09:04:17 PM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139167774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2139167774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/48.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.2216844011 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 514149710 ps |
| CPU time | 1.74 seconds |
| Started | Sep 09 09:03:15 PM UTC 24 |
| Finished | Sep 09 09:03:18 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216844011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2216844011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/48.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.2476657047 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1054201478 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 09:03:20 PM UTC 24 |
| Finished | Sep 09 09:03:22 PM UTC 24 |
| Peak memory | 199620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476657047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2476657047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/49.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.1946222163 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 470134239 ps |
| CPU time | 2.19 seconds |
| Started | Sep 09 09:03:20 PM UTC 24 |
| Finished | Sep 09 09:03:23 PM UTC 24 |
| Peak memory | 200564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946222163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1946222163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/49.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.4053678492 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 555554303 ps |
| CPU time | 1.79 seconds |
| Started | Sep 09 08:59:28 PM UTC 24 |
| Finished | Sep 09 08:59:31 PM UTC 24 |
| Peak memory | 199432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053678492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.4053678492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.4052160947 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 20856040362 ps |
| CPU time | 6.17 seconds |
| Started | Sep 09 08:59:28 PM UTC 24 |
| Finished | Sep 09 08:59:35 PM UTC 24 |
| Peak memory | 200624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052160947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4052160947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.227670578 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 545406704 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 08:59:28 PM UTC 24 |
| Finished | Sep 09 08:59:30 PM UTC 24 |
| Peak memory | 199312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227670578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.227670578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/5.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.1087294757 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 39383111684 ps |
| CPU time | 21.28 seconds |
| Started | Sep 09 08:59:30 PM UTC 24 |
| Finished | Sep 09 08:59:53 PM UTC 24 |
| Peak memory | 200700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087294757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1087294757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.55357126 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 473758208 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 08:59:30 PM UTC 24 |
| Finished | Sep 09 08:59:32 PM UTC 24 |
| Peak memory | 199364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55357126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.55357126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/6.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.307953808 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 19074494171 ps |
| CPU time | 32.1 seconds |
| Started | Sep 09 08:59:35 PM UTC 24 |
| Finished | Sep 09 09:00:08 PM UTC 24 |
| Peak memory | 200628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307953808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.307953808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.1202501085 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 470415035 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 08:59:35 PM UTC 24 |
| Finished | Sep 09 08:59:36 PM UTC 24 |
| Peak memory | 199244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202501085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1202501085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/7.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.3288629931 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 733008060 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 08:59:37 PM UTC 24 |
| Finished | Sep 09 08:59:39 PM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288629931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3288629931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.1382948920 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 521243517 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 08:59:37 PM UTC 24 |
| Finished | Sep 09 08:59:39 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382948920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1382948920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/8.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.570226023 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 61227925501 ps |
| CPU time | 24.18 seconds |
| Started | Sep 09 08:59:40 PM UTC 24 |
| Finished | Sep 09 09:00:06 PM UTC 24 |
| Peak memory | 200828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570226023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.570226023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.1768056054 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 438812631 ps |
| CPU time | 0.9 seconds |
| Started | Sep 09 08:59:40 PM UTC 24 |
| Finished | Sep 09 08:59:42 PM UTC 24 |
| Peak memory | 199304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768056054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1768056054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/9.aon_timer_smoke/latest |
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