Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	17283	1			T1	11		T3	12		T4	10
bark[1]	302	1			T148	68		T125	26		T193	5
bark[2]	222	1			T16	30		T85	14		T87	21
bark[3]	363	1			T16	21		T112	30		T184	14
bark[4]	526	1			T18	21		T68	179		T99	26
bark[5]	558	1			T19	21		T33	95		T96	14
bark[6]	152	1			T33	26		T106	14		T97	26
bark[7]	294	1			T22	14		T33	21		T36	21
bark[8]	68	1			T13	5		T36	21		T143	21
bark[9]	294	1			T36	21		T37	21		T68	21
bark[10]	211	1			T6	7		T13	14		T32	47
bark[11]	554	1			T36	21		T82	21		T88	327
bark[12]	231	1			T167	14		T119	42		T134	21
bark[13]	303	1			T86	21		T71	21		T161	47
bark[14]	228	1			T30	5		T18	26		T116	14
bark[15]	441	1			T23	14		T16	30		T18	42
bark[16]	220	1			T126	14		T37	26		T69	7
bark[17]	124	1			T127	26		T86	21		T87	14
bark[18]	140	1			T13	21		T14	5		T92	21
bark[19]	260	1			T10	14		T125	30		T119	21
bark[20]	563	1			T35	26		T112	30		T148	26
bark[21]	310	1			T13	85		T16	14		T34	21
bark[22]	344	1			T35	35		T153	14		T69	112
bark[23]	395	1			T87	40		T176	14		T97	21
bark[24]	316	1			T131	14		T132	21		T194	7
bark[25]	289	1			T7	14		T17	52		T43	14
bark[26]	223	1			T35	5		T148	21		T99	7
bark[27]	165	1			T6	7		T36	5		T68	64
bark[28]	253	1			T32	7		T87	40		T134	21
bark[29]	159	1			T2	14		T17	26		T185	14
bark[30]	443	1			T16	30		T41	14		T112	21
bark[31]	215	1			T18	30		T19	21		T87	26
bark_0	4551	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	17067	1			T1	10		T3	11		T4	9
bite[1]	210	1			T2	13		T112	13		T86	21
bite[2]	522	1			T13	13		T18	42		T36	21
bite[3]	240	1			T10	13		T148	26		T125	25
bite[4]	193	1			T93	13		T68	21		T86	26
bite[5]	315	1			T18	30		T37	25		T148	68
bite[6]	167	1			T16	30		T17	52		T167	13
bite[7]	164	1			T33	21		T35	25		T70	6
bite[8]	222	1			T68	63		T69	6		T113	25
bite[9]	538	1			T13	84		T35	34		T142	13
bite[10]	280	1			T13	12		T106	13		T82	21
bite[11]	514	1			T13	21		T14	4		T16	13
bite[12]	292	1			T30	4		T112	30		T71	21
bite[13]	199	1			T16	30		T112	30		T86	21
bite[14]	410	1			T32	46		T36	21		T87	40
bite[15]	540	1			T6	6		T16	30		T33	21
bite[16]	266	1			T17	26		T18	26		T132	21
bite[17]	96	1			T99	6		T119	42		T123	21
bite[18]	342	1			T35	4		T69	6		T70	187
bite[19]	246	1			T22	13		T126	13		T124	13
bite[20]	413	1			T37	21		T68	178		T69	111
bite[21]	160	1			T40	13		T19	21		T154	21
bite[22]	231	1			T18	21		T43	13		T123	21
bite[23]	356	1			T153	13		T130	13		T168	6
bite[24]	296	1			T41	13		T36	21		T131	13
bite[25]	199	1			T87	13		T88	49		T136	26
bite[26]	418	1			T23	13		T33	25		T87	26
bite[27]	180	1			T171	13		T119	21		T83	4
bite[28]	86	1			T6	6		T36	21		T193	4
bite[29]	244	1			T16	21		T185	13		T34	21
bite[30]	398	1			T96	13		T162	13		T118	221
bite[31]	207	1			T7	13		T32	14		T148	21
bite_0	4989	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26649

1

T1

18

T2

21

T3

19

auto[1]

4351

1

T6

7

T13

104

T67

7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	573	1			T5	9		T13	19		T18	9
prescale[1]	355	1			T195	9		T99	150		T87	24
prescale[2]	444	1			T17	49		T42	9		T99	19
prescale[3]	436	1			T35	2		T148	19		T69	2
prescale[4]	192	1			T196	9		T19	19		T125	2
prescale[5]	204	1			T13	2		T18	23		T35	2
prescale[6]	484	1			T34	139		T36	36		T125	2
prescale[7]	473	1			T39	9		T33	77		T34	75
prescale[8]	693	1			T6	2		T36	2		T123	30
prescale[9]	324	1			T35	2		T36	2		T68	14
prescale[10]	240	1			T32	51		T197	9		T68	40
prescale[11]	374	1			T3	9		T75	9		T99	19
prescale[12]	406	1			T8	9		T30	2		T19	14
prescale[13]	526	1			T33	2		T34	19		T68	19
prescale[14]	268	1			T6	2		T35	2		T99	36
prescale[15]	557	1			T14	12		T19	23		T99	161
prescale[16]	377	1			T6	2		T33	14		T194	2
prescale[17]	404	1			T13	2		T68	30		T86	40
prescale[18]	541	1			T34	49		T148	24		T127	2
prescale[19]	267	1			T32	2		T119	19		T134	40
prescale[20]	146	1			T18	19		T132	9		T70	9
prescale[21]	346	1			T34	2		T36	2		T198	9
prescale[22]	436	1			T18	19		T34	37		T125	2
prescale[23]	404	1			T13	2		T32	2		T34	19
prescale[24]	412	1			T13	2		T34	30		T69	36
prescale[25]	281	1			T68	2		T127	2		T82	46
prescale[26]	388	1			T37	2		T99	40		T86	53
prescale[27]	425	1			T6	2		T13	45		T14	12
prescale[28]	228	1			T83	2		T199	9		T88	2
prescale[29]	262	1			T16	23		T35	2		T69	19
prescale[30]	401	1			T14	2		T18	49		T200	9
prescale[31]	473	1			T13	64		T201	9		T33	2
prescale_0	18660	1			T1	18		T2	21		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20595

1

T1

9

T2

21

T3

19

auto[1]

10405

1

T1

9

T5

10

T6

132

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

31000

1

T1

18

T2

21

T3

19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	17452	1			T1	13		T2	1		T3	14
wkup[1]	310	1			T13	21		T19	21		T33	21
wkup[2]	73	1			T23	15		T150	6		T129	21
wkup[3]	78	1			T92	30		T202	6		T89	21
wkup[4]	157	1			T33	15		T99	30		T86	21
wkup[5]	249	1			T69	8		T127	30		T86	21
wkup[6]	84	1			T33	21		T35	6		T68	21
wkup[7]	165	1			T99	30		T194	8		T184	15
wkup[8]	228	1			T17	31		T33	21		T127	56
wkup[9]	160	1			T142	15		T97	21		T108	21
wkup[10]	277	1			T99	21		T69	8		T127	21
wkup[11]	103	1			T19	21		T99	21		T97	21
wkup[12]	218	1			T13	12		T68	21		T168	21
wkup[13]	165	1			T32	42		T185	15		T134	30
wkup[14]	178	1			T16	30		T134	21		T88	42
wkup[15]	192	1			T16	30		T36	21		T92	21
wkup[16]	53	1			T32	8		T129	21		T80	24
wkup[17]	210	1			T6	8		T22	15		T33	21
wkup[18]	68	1			T86	21		T88	21		T114	26
wkup[19]	154	1			T125	30		T119	21		T115	26
wkup[20]	223	1			T17	21		T112	30		T86	30
wkup[21]	50	1			T99	8		T122	21		T141	21
wkup[22]	252	1			T13	21		T16	30		T19	21
wkup[23]	179	1			T35	21		T37	21		T99	31
wkup[24]	83	1			T34	42		T117	26		T175	15
wkup[25]	232	1			T17	26		T34	30		T87	21
wkup[26]	172	1			T2	15		T68	26		T134	21
wkup[27]	136	1			T83	26		T174	15		T118	21
wkup[28]	102	1			T13	15		T33	15		T132	21
wkup[29]	84	1			T123	21		T168	21		T110	21
wkup[30]	133	1			T36	15		T87	21		T71	26
wkup[31]	116	1			T6	8		T16	15		T132	21
wkup[32]	161	1			T69	21		T71	21		T88	21
wkup[33]	168	1			T36	6		T124	15		T68	21
wkup[34]	147	1			T13	21		T30	6		T125	21
wkup[35]	68	1			T68	21		T150	26		T103	21
wkup[36]	100	1			T87	15		T123	26		T140	15
wkup[37]	211	1			T112	21		T69	21		T127	21
wkup[38]	150	1			T13	6		T18	26		T101	21
wkup[39]	129	1			T13	21		T148	30		T178	15
wkup[40]	150	1			T18	21		T41	15		T99	21
wkup[41]	125	1			T18	21		T171	15		T71	21
wkup[42]	177	1			T16	30		T36	15		T69	21
wkup[43]	101	1			T183	21		T158	24		T103	30
wkup[44]	198	1			T13	21		T70	29		T82	21
wkup[45]	161	1			T7	15		T125	21		T99	21
wkup[46]	192	1			T34	21		T131	15		T68	21
wkup[47]	158	1			T68	15		T83	6		T134	21
wkup[48]	167	1			T36	21		T99	21		T134	21
wkup[49]	180	1			T99	21		T70	21		T82	21
wkup[50]	137	1			T43	15		T36	30		T96	15
wkup[51]	274	1			T18	21		T36	21		T37	21
wkup[52]	121	1			T126	15		T112	30		T193	21
wkup[53]	119	1			T13	15		T33	26		T153	15
wkup[54]	63	1			T16	21		T36	21		T118	21
wkup[55]	197	1			T18	21		T85	15		T176	15
wkup[56]	238	1			T112	30		T93	15		T99	21
wkup[57]	101	1			T34	20		T71	15		T136	21
wkup[58]	257	1			T14	6		T112	15		T148	21
wkup[59]	158	1			T18	21		T168	8		T88	36
wkup[60]	159	1			T10	15		T33	21		T160	15
wkup[61]	203	1			T40	15		T69	26		T70	21
wkup[62]	131	1			T34	21		T123	21		T155	21
wkup[63]	194	1			T148	21		T119	21		T70	42
wkup_0	3569	1			T1	5		T2	5		T3	5