Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.16 99.33 95.61 100.00 98.40 99.51 42.14


Total test records in report: 422
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T288 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1143504004 Sep 11 05:05:34 PM UTC 24 Sep 11 05:05:36 PM UTC 24 369787887 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.3376563255 Sep 11 05:05:34 PM UTC 24 Sep 11 05:05:36 PM UTC 24 499140310 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.2935453366 Sep 11 05:05:33 PM UTC 24 Sep 11 05:05:36 PM UTC 24 319365059 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.3639367137 Sep 11 05:05:33 PM UTC 24 Sep 11 05:05:36 PM UTC 24 547933428 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.349832073 Sep 11 05:05:34 PM UTC 24 Sep 11 05:05:36 PM UTC 24 475169449 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3249316654 Sep 11 05:05:34 PM UTC 24 Sep 11 05:05:37 PM UTC 24 525386255 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.1798685867 Sep 11 05:05:35 PM UTC 24 Sep 11 05:05:38 PM UTC 24 511846588 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.1848143251 Sep 11 05:05:34 PM UTC 24 Sep 11 05:05:38 PM UTC 24 483352599 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3184740271 Sep 11 05:05:35 PM UTC 24 Sep 11 05:05:38 PM UTC 24 430400357 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.807786735 Sep 11 05:05:34 PM UTC 24 Sep 11 05:05:39 PM UTC 24 8766081961 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.933407604 Sep 11 05:05:33 PM UTC 24 Sep 11 05:05:40 PM UTC 24 4293059429 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2539885389 Sep 11 05:05:34 PM UTC 24 Sep 11 05:05:40 PM UTC 24 7278834804 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.3210980054 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:40 PM UTC 24 528015091 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.3366744472 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:40 PM UTC 24 530866780 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.3665662426 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:41 PM UTC 24 458467421 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.3209863828 Sep 11 05:05:39 PM UTC 24 Sep 11 05:05:41 PM UTC 24 452724943 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1785415424 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:41 PM UTC 24 741938215 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3967258358 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:41 PM UTC 24 516539435 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3288752252 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:41 PM UTC 24 888351526 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1503819892 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:41 PM UTC 24 499580445 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.379824382 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:42 PM UTC 24 708362348 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2692488938 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:42 PM UTC 24 436293849 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1709278731 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:43 PM UTC 24 1980904690 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2069828441 Sep 11 05:05:34 PM UTC 24 Sep 11 05:05:43 PM UTC 24 2851767720 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3299908740 Sep 11 05:05:41 PM UTC 24 Sep 11 05:05:43 PM UTC 24 350249025 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3371779559 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:43 PM UTC 24 5551569978 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.1516519964 Sep 11 05:05:41 PM UTC 24 Sep 11 05:05:43 PM UTC 24 438570043 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3086101809 Sep 11 05:05:40 PM UTC 24 Sep 11 05:05:43 PM UTC 24 440303682 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.1801974580 Sep 11 05:05:41 PM UTC 24 Sep 11 05:05:43 PM UTC 24 459290905 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4117896788 Sep 11 05:05:42 PM UTC 24 Sep 11 05:05:44 PM UTC 24 572214822 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.4180027852 Sep 11 05:05:42 PM UTC 24 Sep 11 05:05:44 PM UTC 24 493930642 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1370743725 Sep 11 05:05:40 PM UTC 24 Sep 11 05:05:44 PM UTC 24 1394433046 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.1508711304 Sep 11 05:05:42 PM UTC 24 Sep 11 05:05:44 PM UTC 24 463244138 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3659876332 Sep 11 05:05:42 PM UTC 24 Sep 11 05:05:44 PM UTC 24 560340347 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3197196587 Sep 11 05:05:42 PM UTC 24 Sep 11 05:05:45 PM UTC 24 441034655 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.1216781514 Sep 11 05:05:42 PM UTC 24 Sep 11 05:05:45 PM UTC 24 487046032 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.213372483 Sep 11 05:05:43 PM UTC 24 Sep 11 05:05:45 PM UTC 24 1085487154 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2979484515 Sep 11 05:05:43 PM UTC 24 Sep 11 05:05:46 PM UTC 24 279561948 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.2891349767 Sep 11 05:05:43 PM UTC 24 Sep 11 05:05:46 PM UTC 24 510565315 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3780813506 Sep 11 05:05:42 PM UTC 24 Sep 11 05:05:46 PM UTC 24 1191201836 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1069427781 Sep 11 05:05:43 PM UTC 24 Sep 11 05:05:46 PM UTC 24 302146121 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.1034469507 Sep 11 05:05:44 PM UTC 24 Sep 11 05:05:46 PM UTC 24 320483833 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3907348078 Sep 11 05:05:38 PM UTC 24 Sep 11 05:05:47 PM UTC 24 8762161097 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4130440856 Sep 11 05:05:45 PM UTC 24 Sep 11 05:05:47 PM UTC 24 608176213 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2325102172 Sep 11 05:05:45 PM UTC 24 Sep 11 05:05:47 PM UTC 24 525395042 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1864552773 Sep 11 05:05:42 PM UTC 24 Sep 11 05:05:48 PM UTC 24 7015833003 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1473487699 Sep 11 05:05:45 PM UTC 24 Sep 11 05:05:48 PM UTC 24 1219805659 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3336123765 Sep 11 05:05:46 PM UTC 24 Sep 11 05:05:48 PM UTC 24 463413708 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.1682729097 Sep 11 05:05:46 PM UTC 24 Sep 11 05:05:48 PM UTC 24 343321523 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.3198411258 Sep 11 05:05:46 PM UTC 24 Sep 11 05:05:48 PM UTC 24 456586106 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.1103682914 Sep 11 05:05:45 PM UTC 24 Sep 11 05:05:49 PM UTC 24 860758027 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.3388254983 Sep 11 05:05:46 PM UTC 24 Sep 11 05:05:49 PM UTC 24 403688831 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.2208548671 Sep 11 05:05:46 PM UTC 24 Sep 11 05:05:49 PM UTC 24 298036732 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3691273860 Sep 11 05:05:42 PM UTC 24 Sep 11 05:05:49 PM UTC 24 1313795371 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2291463280 Sep 11 05:05:47 PM UTC 24 Sep 11 05:05:49 PM UTC 24 421603020 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2657312861 Sep 11 05:05:48 PM UTC 24 Sep 11 05:05:50 PM UTC 24 426061153 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.2454531558 Sep 11 05:05:48 PM UTC 24 Sep 11 05:05:50 PM UTC 24 341170860 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3698596251 Sep 11 05:05:46 PM UTC 24 Sep 11 05:05:50 PM UTC 24 575791199 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.721952154 Sep 11 05:05:48 PM UTC 24 Sep 11 05:05:50 PM UTC 24 442702658 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.1433485802 Sep 11 05:05:49 PM UTC 24 Sep 11 05:05:51 PM UTC 24 354499741 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.938857610 Sep 11 05:05:46 PM UTC 24 Sep 11 05:05:51 PM UTC 24 1627719193 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3401914855 Sep 11 05:05:46 PM UTC 24 Sep 11 05:05:51 PM UTC 24 911386835 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.3440143770 Sep 11 05:05:48 PM UTC 24 Sep 11 05:05:51 PM UTC 24 358471659 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1195678179 Sep 11 05:05:46 PM UTC 24 Sep 11 05:05:51 PM UTC 24 8138795232 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.308669292 Sep 11 05:05:49 PM UTC 24 Sep 11 05:05:51 PM UTC 24 840214671 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3263695476 Sep 11 05:05:48 PM UTC 24 Sep 11 05:05:52 PM UTC 24 1335938323 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.928815062 Sep 11 05:05:49 PM UTC 24 Sep 11 05:05:52 PM UTC 24 1606386651 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.3305901619 Sep 11 05:05:49 PM UTC 24 Sep 11 05:05:52 PM UTC 24 508330461 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3842278005 Sep 11 05:05:46 PM UTC 24 Sep 11 05:05:52 PM UTC 24 4588897281 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.4107420953 Sep 11 05:05:49 PM UTC 24 Sep 11 05:05:53 PM UTC 24 515191932 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.2942041975 Sep 11 05:05:51 PM UTC 24 Sep 11 05:05:53 PM UTC 24 455613081 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1293244146 Sep 11 05:05:51 PM UTC 24 Sep 11 05:05:53 PM UTC 24 4256065440 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.1237904887 Sep 11 05:05:51 PM UTC 24 Sep 11 05:05:53 PM UTC 24 417530035 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.3598720874 Sep 11 05:05:49 PM UTC 24 Sep 11 05:05:53 PM UTC 24 397503062 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.2408258361 Sep 11 05:05:51 PM UTC 24 Sep 11 05:05:53 PM UTC 24 350761634 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.1206142337 Sep 11 05:05:51 PM UTC 24 Sep 11 05:05:53 PM UTC 24 263215512 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4204145646 Sep 11 05:05:48 PM UTC 24 Sep 11 05:05:53 PM UTC 24 4365307423 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.3310671083 Sep 11 05:05:51 PM UTC 24 Sep 11 05:05:54 PM UTC 24 375180243 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.562599444 Sep 11 05:05:51 PM UTC 24 Sep 11 05:05:54 PM UTC 24 503049987 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.2668029994 Sep 11 05:06:04 PM UTC 24 Sep 11 05:06:07 PM UTC 24 414108854 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1172452459 Sep 11 05:05:53 PM UTC 24 Sep 11 05:05:55 PM UTC 24 500622267 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.848516557 Sep 11 05:05:53 PM UTC 24 Sep 11 05:05:55 PM UTC 24 500790088 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.298265543 Sep 11 05:05:51 PM UTC 24 Sep 11 05:05:55 PM UTC 24 1343783370 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.1643201305 Sep 11 05:05:53 PM UTC 24 Sep 11 05:05:55 PM UTC 24 265751863 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3611987857 Sep 11 05:05:52 PM UTC 24 Sep 11 05:05:55 PM UTC 24 1295047839 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.468996179 Sep 11 05:05:53 PM UTC 24 Sep 11 05:05:55 PM UTC 24 1318852718 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2116155292 Sep 11 05:05:53 PM UTC 24 Sep 11 05:05:55 PM UTC 24 405946351 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.2693968852 Sep 11 05:05:53 PM UTC 24 Sep 11 05:05:55 PM UTC 24 388911694 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.751239658 Sep 11 05:05:41 PM UTC 24 Sep 11 05:05:56 PM UTC 24 7755017288 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.2686238173 Sep 11 05:05:53 PM UTC 24 Sep 11 05:05:57 PM UTC 24 591829682 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.328534290 Sep 11 05:05:53 PM UTC 24 Sep 11 05:05:57 PM UTC 24 408104167 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1011522194 Sep 11 05:05:55 PM UTC 24 Sep 11 05:05:57 PM UTC 24 501099135 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3013835272 Sep 11 05:05:55 PM UTC 24 Sep 11 05:05:57 PM UTC 24 347009935 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.1252010186 Sep 11 05:05:54 PM UTC 24 Sep 11 05:05:57 PM UTC 24 290867890 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3900399708 Sep 11 05:05:43 PM UTC 24 Sep 11 05:05:57 PM UTC 24 7847604564 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.1672191291 Sep 11 05:05:55 PM UTC 24 Sep 11 05:05:58 PM UTC 24 399836556 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3714875875 Sep 11 05:05:53 PM UTC 24 Sep 11 05:05:58 PM UTC 24 4610682427 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1789781804 Sep 11 05:05:56 PM UTC 24 Sep 11 05:05:58 PM UTC 24 683981652 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.856510845 Sep 11 05:05:55 PM UTC 24 Sep 11 05:05:58 PM UTC 24 426588951 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.4162505781 Sep 11 05:05:56 PM UTC 24 Sep 11 05:05:58 PM UTC 24 558654481 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3742314171 Sep 11 05:05:49 PM UTC 24 Sep 11 05:05:58 PM UTC 24 4795774290 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.713931122 Sep 11 05:05:56 PM UTC 24 Sep 11 05:05:58 PM UTC 24 415638299 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3662484245 Sep 11 05:05:55 PM UTC 24 Sep 11 05:05:58 PM UTC 24 1711924233 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.2173582407 Sep 11 05:05:55 PM UTC 24 Sep 11 05:05:58 PM UTC 24 469040920 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.3548165557 Sep 11 05:05:56 PM UTC 24 Sep 11 05:05:58 PM UTC 24 374997081 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.5704213 Sep 11 05:05:56 PM UTC 24 Sep 11 05:05:58 PM UTC 24 394549855 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3368848932 Sep 11 05:05:55 PM UTC 24 Sep 11 05:05:58 PM UTC 24 1393839893 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1947618910 Sep 11 05:05:54 PM UTC 24 Sep 11 05:05:59 PM UTC 24 1501774915 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.786206758 Sep 11 05:05:56 PM UTC 24 Sep 11 05:05:59 PM UTC 24 2116559747 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.2697492885 Sep 11 05:05:56 PM UTC 24 Sep 11 05:05:59 PM UTC 24 665829463 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.2006035028 Sep 11 05:05:58 PM UTC 24 Sep 11 05:05:59 PM UTC 24 323937906 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.3265040591 Sep 11 05:05:58 PM UTC 24 Sep 11 05:06:00 PM UTC 24 402852004 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2960645813 Sep 11 05:05:57 PM UTC 24 Sep 11 05:06:00 PM UTC 24 346092483 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3403226876 Sep 11 05:05:57 PM UTC 24 Sep 11 05:06:01 PM UTC 24 2497890139 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.2707371545 Sep 11 05:05:58 PM UTC 24 Sep 11 05:06:01 PM UTC 24 554269919 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2989704256 Sep 11 05:05:59 PM UTC 24 Sep 11 05:06:02 PM UTC 24 2124963369 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2617230901 Sep 11 05:05:53 PM UTC 24 Sep 11 05:06:02 PM UTC 24 8127802750 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.2740588191 Sep 11 05:06:05 PM UTC 24 Sep 11 05:06:07 PM UTC 24 275116970 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1381356212 Sep 11 05:05:58 PM UTC 24 Sep 11 05:06:02 PM UTC 24 4094654904 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.4257253262 Sep 11 05:06:01 PM UTC 24 Sep 11 05:06:03 PM UTC 24 364098806 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.749157314 Sep 11 05:06:01 PM UTC 24 Sep 11 05:06:03 PM UTC 24 557617402 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3460793325 Sep 11 05:05:51 PM UTC 24 Sep 11 05:06:03 PM UTC 24 8391930538 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3481771236 Sep 11 05:06:00 PM UTC 24 Sep 11 05:06:03 PM UTC 24 397592507 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1129230081 Sep 11 05:05:55 PM UTC 24 Sep 11 05:06:03 PM UTC 24 4210124047 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.585161577 Sep 11 05:06:00 PM UTC 24 Sep 11 05:06:03 PM UTC 24 432612707 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1808010767 Sep 11 05:06:00 PM UTC 24 Sep 11 05:06:03 PM UTC 24 455630135 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.2561208643 Sep 11 05:06:00 PM UTC 24 Sep 11 05:06:03 PM UTC 24 445818718 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.3810349884 Sep 11 05:06:01 PM UTC 24 Sep 11 05:06:03 PM UTC 24 551355318 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.3977198614 Sep 11 05:06:00 PM UTC 24 Sep 11 05:06:04 PM UTC 24 595963895 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.3627996737 Sep 11 05:06:00 PM UTC 24 Sep 11 05:06:04 PM UTC 24 470307475 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.3556391211 Sep 11 05:06:02 PM UTC 24 Sep 11 05:06:04 PM UTC 24 332498389 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.1612927731 Sep 11 05:06:02 PM UTC 24 Sep 11 05:06:04 PM UTC 24 402078453 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.3130985891 Sep 11 05:06:02 PM UTC 24 Sep 11 05:06:04 PM UTC 24 363479857 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1858231353 Sep 11 05:06:01 PM UTC 24 Sep 11 05:06:04 PM UTC 24 1027907552 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1350775750 Sep 11 05:06:02 PM UTC 24 Sep 11 05:06:05 PM UTC 24 361267459 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2826230454 Sep 11 05:06:00 PM UTC 24 Sep 11 05:06:05 PM UTC 24 4074551754 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.251316329 Sep 11 05:05:56 PM UTC 24 Sep 11 05:06:05 PM UTC 24 4633154179 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3029559518 Sep 11 05:05:40 PM UTC 24 Sep 11 05:06:06 PM UTC 24 13970411523 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.3943959609 Sep 11 05:06:02 PM UTC 24 Sep 11 05:06:06 PM UTC 24 293614953 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3571765477 Sep 11 05:06:04 PM UTC 24 Sep 11 05:06:06 PM UTC 24 386945130 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.3067648173 Sep 11 05:06:04 PM UTC 24 Sep 11 05:06:06 PM UTC 24 346545494 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4253564551 Sep 11 05:06:00 PM UTC 24 Sep 11 05:06:06 PM UTC 24 1278158429 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2423706510 Sep 11 05:06:00 PM UTC 24 Sep 11 05:06:07 PM UTC 24 8260713407 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.4071281065 Sep 11 05:06:04 PM UTC 24 Sep 11 05:06:07 PM UTC 24 463073301 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.618896653 Sep 11 05:06:04 PM UTC 24 Sep 11 05:06:07 PM UTC 24 429393725 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.2220615442 Sep 11 05:06:04 PM UTC 24 Sep 11 05:06:07 PM UTC 24 303170166 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.238330075 Sep 11 05:06:04 PM UTC 24 Sep 11 05:06:07 PM UTC 24 283844016 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.686677972 Sep 11 05:06:05 PM UTC 24 Sep 11 05:06:07 PM UTC 24 508366722 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.2220188770 Sep 11 05:06:04 PM UTC 24 Sep 11 05:06:07 PM UTC 24 358027306 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.14995252 Sep 11 05:06:04 PM UTC 24 Sep 11 05:06:07 PM UTC 24 366339828 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.2574566558 Sep 11 05:06:04 PM UTC 24 Sep 11 05:06:07 PM UTC 24 530747879 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.3717071032 Sep 11 05:06:05 PM UTC 24 Sep 11 05:06:07 PM UTC 24 371116941 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.65277686 Sep 11 05:06:05 PM UTC 24 Sep 11 05:06:07 PM UTC 24 347859826 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.3887074819 Sep 11 05:06:05 PM UTC 24 Sep 11 05:06:08 PM UTC 24 325919856 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.361836930 Sep 11 05:05:45 PM UTC 24 Sep 11 05:06:08 PM UTC 24 8006177800 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3692995534 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:09 PM UTC 24 382227504 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.80088752 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:09 PM UTC 24 425497340 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.203501536 Sep 11 05:06:02 PM UTC 24 Sep 11 05:06:09 PM UTC 24 1982154261 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.3441495494 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:09 PM UTC 24 392229945 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.2735932703 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:09 PM UTC 24 387014123 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.3943721180 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:09 PM UTC 24 509010711 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2235055211 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:09 PM UTC 24 319281843 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.2543364165 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:09 PM UTC 24 444429704 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.2221618032 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:09 PM UTC 24 469433032 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.2008625758 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:09 PM UTC 24 404313595 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3573997247 Sep 11 05:05:55 PM UTC 24 Sep 11 05:06:09 PM UTC 24 8097289416 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2600519912 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:10 PM UTC 24 284138917 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.2730240569 Sep 11 05:06:07 PM UTC 24 Sep 11 05:06:10 PM UTC 24 468803733 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.206957217 Sep 11 05:06:08 PM UTC 24 Sep 11 05:06:10 PM UTC 24 379078009 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3583425484 Sep 11 05:06:02 PM UTC 24 Sep 11 05:06:10 PM UTC 24 4297748927 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.516136420 Sep 11 05:06:09 PM UTC 24 Sep 11 05:06:11 PM UTC 24 435728054 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.4223255381 Sep 11 05:06:09 PM UTC 24 Sep 11 05:06:11 PM UTC 24 364893991 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.2629083625
Short name T6
Test name
Test status
Simulation time 2541604875 ps
CPU time 27.76 seconds
Started Sep 11 03:38:22 PM UTC 24
Finished Sep 11 03:38:51 PM UTC 24
Peak memory 215496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2629083625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.aon_timer_stress_all_with_rand_reset.2629083625
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.601433959
Short name T13
Test name
Test status
Simulation time 5014492173 ps
CPU time 26.49 seconds
Started Sep 11 03:39:25 PM UTC 24
Finished Sep 11 03:39:53 PM UTC 24
Peak memory 218236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=601433959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.aon_timer_stress_all_with_rand_reset.601433959
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.807786735
Short name T27
Test name
Test status
Simulation time 8766081961 ps
CPU time 4.1 seconds
Started Sep 11 05:05:34 PM UTC 24
Finished Sep 11 05:05:39 PM UTC 24
Peak memory 207004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807786735 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.807786735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.3718773511
Short name T16
Test name
Test status
Simulation time 41852685291 ps
CPU time 21.76 seconds
Started Sep 11 03:40:24 PM UTC 24
Finished Sep 11 03:40:47 PM UTC 24
Peak memory 200696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718773511 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.3718773511
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.3209863828
Short name T44
Test name
Test status
Simulation time 452724943 ps
CPU time 1.2 seconds
Started Sep 11 05:05:39 PM UTC 24
Finished Sep 11 05:05:41 PM UTC 24
Peak memory 201888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209863828 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3209863828
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.907900406
Short name T88
Test name
Test status
Simulation time 86578130874 ps
CPU time 68.19 seconds
Started Sep 11 03:45:18 PM UTC 24
Finished Sep 11 03:46:29 PM UTC 24
Peak memory 206460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=907900406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.aon_timer_stress_all_with_rand_reset.907900406
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.4291373211
Short name T97
Test name
Test status
Simulation time 89965161127 ps
CPU time 71.08 seconds
Started Sep 11 03:45:30 PM UTC 24
Finished Sep 11 03:46:43 PM UTC 24
Peak memory 200692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291373211 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.4291373211
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/24.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.1435448851
Short name T123
Test name
Test status
Simulation time 118821846390 ps
CPU time 91.81 seconds
Started Sep 11 03:43:43 PM UTC 24
Finished Sep 11 03:45:17 PM UTC 24
Peak memory 200620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435448851 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.1435448851
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.2673034596
Short name T10
Test name
Test status
Simulation time 543366043 ps
CPU time 1.13 seconds
Started Sep 11 03:39:22 PM UTC 24
Finished Sep 11 03:39:24 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673034596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2673034596
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.1149826333
Short name T118
Test name
Test status
Simulation time 5214292795 ps
CPU time 52.27 seconds
Started Sep 11 03:47:22 PM UTC 24
Finished Sep 11 03:48:16 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1149826333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 34.aon_timer_stress_all_with_rand_reset.1149826333
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.1136083347
Short name T11
Test name
Test status
Simulation time 4313447130 ps
CPU time 4.17 seconds
Started Sep 11 03:38:35 PM UTC 24
Finished Sep 11 03:38:40 PM UTC 24
Peak memory 231252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136083347 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1136083347
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.748215112
Short name T86
Test name
Test status
Simulation time 102691733995 ps
CPU time 37.75 seconds
Started Sep 11 03:43:15 PM UTC 24
Finished Sep 11 03:43:54 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748215112 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.748215112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.1454456284
Short name T80
Test name
Test status
Simulation time 253362261762 ps
CPU time 257.96 seconds
Started Sep 11 03:49:15 PM UTC 24
Finished Sep 11 03:53:36 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454456284 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.1454456284
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/45.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.1854763270
Short name T136
Test name
Test status
Simulation time 53305103218 ps
CPU time 26.88 seconds
Started Sep 11 03:46:22 PM UTC 24
Finished Sep 11 03:46:50 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854763270 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.1854763270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/28.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.2044469256
Short name T36
Test name
Test status
Simulation time 4917829366 ps
CPU time 44.85 seconds
Started Sep 11 03:41:35 PM UTC 24
Finished Sep 11 03:42:21 PM UTC 24
Peak memory 206524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2044469256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 8.aon_timer_stress_all_with_rand_reset.2044469256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.2826531510
Short name T113
Test name
Test status
Simulation time 9204338432 ps
CPU time 75.59 seconds
Started Sep 11 03:47:07 PM UTC 24
Finished Sep 11 03:48:24 PM UTC 24
Peak memory 215372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2826531510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 33.aon_timer_stress_all_with_rand_reset.2826531510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.2391185315
Short name T89
Test name
Test status
Simulation time 47486895598 ps
CPU time 37.94 seconds
Started Sep 11 03:49:52 PM UTC 24
Finished Sep 11 03:50:31 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391185315 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.2391185315
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/49.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.4018234742
Short name T127
Test name
Test status
Simulation time 9628758689 ps
CPU time 28.79 seconds
Started Sep 11 03:43:14 PM UTC 24
Finished Sep 11 03:43:44 PM UTC 24
Peak memory 218972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4018234742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 16.aon_timer_stress_all_with_rand_reset.4018234742
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.1772358631
Short name T112
Test name
Test status
Simulation time 15077860672 ps
CPU time 47.7 seconds
Started Sep 11 03:41:29 PM UTC 24
Finished Sep 11 03:42:18 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772358631 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.1772358631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.213921880
Short name T33
Test name
Test status
Simulation time 4332253202 ps
CPU time 27.76 seconds
Started Sep 11 03:41:27 PM UTC 24
Finished Sep 11 03:41:56 PM UTC 24
Peak memory 218288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=213921880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 7.aon_timer_stress_all_with_rand_reset.213921880
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.279100783
Short name T100
Test name
Test status
Simulation time 299054390500 ps
CPU time 433.15 seconds
Started Sep 11 03:42:28 PM UTC 24
Finished Sep 11 03:49:47 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279100783 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.279100783
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.283506105
Short name T87
Test name
Test status
Simulation time 57051422466 ps
CPU time 77.52 seconds
Started Sep 11 03:42:50 PM UTC 24
Finished Sep 11 03:44:09 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283506105 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.283506105
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.802135013
Short name T103
Test name
Test status
Simulation time 215103954882 ps
CPU time 109.84 seconds
Started Sep 11 03:49:37 PM UTC 24
Finished Sep 11 03:51:29 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802135013 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.802135013
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/47.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.446434749
Short name T71
Test name
Test status
Simulation time 5290128099 ps
CPU time 17.27 seconds
Started Sep 11 03:45:59 PM UTC 24
Finished Sep 11 03:46:18 PM UTC 24
Peak memory 211860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=446434749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.aon_timer_stress_all_with_rand_reset.446434749
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.2658714242
Short name T129
Test name
Test status
Simulation time 280370505510 ps
CPU time 458.04 seconds
Started Sep 11 03:45:40 PM UTC 24
Finished Sep 11 03:53:24 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658714242 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.2658714242
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/25.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.1271672096
Short name T151
Test name
Test status
Simulation time 295935953321 ps
CPU time 558.89 seconds
Started Sep 11 03:45:22 PM UTC 24
Finished Sep 11 03:54:48 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271672096 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.1271672096
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/23.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.596995082
Short name T111
Test name
Test status
Simulation time 8388836890 ps
CPU time 24.98 seconds
Started Sep 11 03:46:55 PM UTC 24
Finished Sep 11 03:47:22 PM UTC 24
Peak memory 206628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=596995082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 32.aon_timer_stress_all_with_rand_reset.596995082
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.3016360591
Short name T144
Test name
Test status
Simulation time 135450904811 ps
CPU time 44.49 seconds
Started Sep 11 03:47:25 PM UTC 24
Finished Sep 11 03:48:11 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016360591 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.3016360591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/34.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.1820753907
Short name T91
Test name
Test status
Simulation time 228205087893 ps
CPU time 423.89 seconds
Started Sep 11 03:41:46 PM UTC 24
Finished Sep 11 03:48:56 PM UTC 24
Peak memory 200824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820753907 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.1820753907
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.202145357
Short name T99
Test name
Test status
Simulation time 17681795066 ps
CPU time 65.58 seconds
Started Sep 11 03:42:27 PM UTC 24
Finished Sep 11 03:43:35 PM UTC 24
Peak memory 206760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=202145357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 12.aon_timer_stress_all_with_rand_reset.202145357
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.3180527540
Short name T68
Test name
Test status
Simulation time 7912257791 ps
CPU time 15.41 seconds
Started Sep 11 03:42:35 PM UTC 24
Finished Sep 11 03:42:51 PM UTC 24
Peak memory 206636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3180527540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 13.aon_timer_stress_all_with_rand_reset.3180527540
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.1885593179
Short name T107
Test name
Test status
Simulation time 82485466166 ps
CPU time 55.18 seconds
Started Sep 11 03:48:49 PM UTC 24
Finished Sep 11 03:49:45 PM UTC 24
Peak memory 200620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885593179 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.1885593179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/42.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.837050393
Short name T82
Test name
Test status
Simulation time 191288274632 ps
CPU time 132.65 seconds
Started Sep 11 03:44:07 PM UTC 24
Finished Sep 11 03:46:22 PM UTC 24
Peak memory 200752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837050393 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.837050393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/18.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.2688774264
Short name T101
Test name
Test status
Simulation time 297550710474 ps
CPU time 472.01 seconds
Started Sep 11 03:39:28 PM UTC 24
Finished Sep 11 03:47:25 PM UTC 24
Peak memory 200760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688774264 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.2688774264
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.680404984
Short name T90
Test name
Test status
Simulation time 230254303247 ps
CPU time 507.97 seconds
Started Sep 11 03:45:59 PM UTC 24
Finished Sep 11 03:54:33 PM UTC 24
Peak memory 200696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680404984 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.680404984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/26.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.1090910527
Short name T78
Test name
Test status
Simulation time 120699403423 ps
CPU time 46.52 seconds
Started Sep 11 03:49:23 PM UTC 24
Finished Sep 11 03:50:11 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090910527 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.1090910527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/46.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.570685299
Short name T70
Test name
Test status
Simulation time 15502459045 ps
CPU time 20.59 seconds
Started Sep 11 03:44:14 PM UTC 24
Finished Sep 11 03:44:36 PM UTC 24
Peak memory 214776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=570685299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 19.aon_timer_stress_all_with_rand_reset.570685299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.3686463462
Short name T92
Test name
Test status
Simulation time 27665302455 ps
CPU time 30.21 seconds
Started Sep 11 03:46:08 PM UTC 24
Finished Sep 11 03:46:39 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686463462 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.3686463462
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/27.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.3211655834
Short name T134
Test name
Test status
Simulation time 206716433261 ps
CPU time 67.88 seconds
Started Sep 11 03:44:23 PM UTC 24
Finished Sep 11 03:45:33 PM UTC 24
Peak memory 200756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211655834 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.3211655834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/20.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.2853539124
Short name T108
Test name
Test status
Simulation time 1917368088 ps
CPU time 13.84 seconds
Started Sep 11 03:46:28 PM UTC 24
Finished Sep 11 03:46:44 PM UTC 24
Peak memory 217036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2853539124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.aon_timer_stress_all_with_rand_reset.2853539124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.1341918235
Short name T79
Test name
Test status
Simulation time 155417920342 ps
CPU time 179.87 seconds
Started Sep 11 03:48:25 PM UTC 24
Finished Sep 11 03:51:27 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341918235 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.1341918235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/39.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.1369846329
Short name T141
Test name
Test status
Simulation time 459582854017 ps
CPU time 602.5 seconds
Started Sep 11 03:41:38 PM UTC 24
Finished Sep 11 03:51:48 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369846329 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.1369846329
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.594184370
Short name T18
Test name
Test status
Simulation time 339778387800 ps
CPU time 170.57 seconds
Started Sep 11 03:38:25 PM UTC 24
Finished Sep 11 03:41:19 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594184370 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.594184370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.3286732104
Short name T156
Test name
Test status
Simulation time 10230466533 ps
CPU time 38.55 seconds
Started Sep 11 03:46:49 PM UTC 24
Finished Sep 11 03:47:29 PM UTC 24
Peak memory 213988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3286732104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 31.aon_timer_stress_all_with_rand_reset.3286732104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.41657949
Short name T19
Test name
Test status
Simulation time 339979433855 ps
CPU time 39.94 seconds
Started Sep 11 03:41:07 PM UTC 24
Finished Sep 11 03:41:48 PM UTC 24
Peak memory 200812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41657949 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.41657949
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.1262420684
Short name T135
Test name
Test status
Simulation time 73838886766 ps
CPU time 116.39 seconds
Started Sep 11 03:46:30 PM UTC 24
Finished Sep 11 03:48:29 PM UTC 24
Peak memory 200628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262420684 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.1262420684
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/29.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.267078662
Short name T121
Test name
Test status
Simulation time 106270619383 ps
CPU time 85.2 seconds
Started Sep 11 03:46:51 PM UTC 24
Finished Sep 11 03:48:18 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267078662 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.267078662
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/31.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.3257717004
Short name T115
Test name
Test status
Simulation time 89502200989 ps
CPU time 48.68 seconds
Started Sep 11 03:47:13 PM UTC 24
Finished Sep 11 03:48:03 PM UTC 24
Peak memory 200692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257717004 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.3257717004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/33.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.2241685460
Short name T145
Test name
Test status
Simulation time 176785400424 ps
CPU time 322.69 seconds
Started Sep 11 03:48:14 PM UTC 24
Finished Sep 11 03:53:40 PM UTC 24
Peak memory 200692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241685460 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.2241685460
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/38.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.3875348807
Short name T125
Test name
Test status
Simulation time 4964326586 ps
CPU time 28.31 seconds
Started Sep 11 03:42:44 PM UTC 24
Finished Sep 11 03:43:14 PM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3875348807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 14.aon_timer_stress_all_with_rand_reset.3875348807
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.3477864272
Short name T150
Test name
Test status
Simulation time 17524094292 ps
CPU time 59.56 seconds
Started Sep 11 03:47:43 PM UTC 24
Finished Sep 11 03:48:44 PM UTC 24
Peak memory 218520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3477864272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 36.aon_timer_stress_all_with_rand_reset.3477864272
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.1972093211
Short name T94
Test name
Test status
Simulation time 2827779070 ps
CPU time 22.12 seconds
Started Sep 11 03:49:52 PM UTC 24
Finished Sep 11 03:50:15 PM UTC 24
Peak memory 217432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1972093211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 49.aon_timer_stress_all_with_rand_reset.1972093211
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.3303623549
Short name T132
Test name
Test status
Simulation time 228681740737 ps
CPU time 313.3 seconds
Started Sep 11 03:38:52 PM UTC 24
Finished Sep 11 03:44:10 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303623549 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.3303623549
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.1708459657
Short name T102
Test name
Test status
Simulation time 2318843406 ps
CPU time 21.25 seconds
Started Sep 11 03:49:45 PM UTC 24
Finished Sep 11 03:50:07 PM UTC 24
Peak memory 206524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1708459657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 48.aon_timer_stress_all_with_rand_reset.1708459657
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.4189934191
Short name T119
Test name
Test status
Simulation time 97087832966 ps
CPU time 77.38 seconds
Started Sep 11 03:43:00 PM UTC 24
Finished Sep 11 03:44:19 PM UTC 24
Peak memory 200620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189934191 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.4189934191
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.1124123882
Short name T32
Test name
Test status
Simulation time 5331979116 ps
CPU time 44.4 seconds
Started Sep 11 03:40:36 PM UTC 24
Finished Sep 11 03:41:22 PM UTC 24
Peak memory 215432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1124123882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 4.aon_timer_stress_all_with_rand_reset.1124123882
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.2715811167
Short name T114
Test name
Test status
Simulation time 48524618514 ps
CPU time 140.78 seconds
Started Sep 11 03:49:06 PM UTC 24
Finished Sep 11 03:51:30 PM UTC 24
Peak memory 200884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715811167 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.2715811167
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/44.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.2810872785
Short name T83
Test name
Test status
Simulation time 4297395352 ps
CPU time 53.32 seconds
Started Sep 11 03:44:22 PM UTC 24
Finished Sep 11 03:45:17 PM UTC 24
Peak memory 214168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2810872785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 20.aon_timer_stress_all_with_rand_reset.2810872785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.3471388908
Short name T95
Test name
Test status
Simulation time 8116785486 ps
CPU time 24.97 seconds
Started Sep 11 03:49:22 PM UTC 24
Finished Sep 11 03:49:48 PM UTC 24
Peak memory 219632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3471388908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 46.aon_timer_stress_all_with_rand_reset.3471388908
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.3671815378
Short name T77
Test name
Test status
Simulation time 399454781438 ps
CPU time 319.92 seconds
Started Sep 11 03:42:00 PM UTC 24
Finished Sep 11 03:47:24 PM UTC 24
Peak memory 200692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671815378 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.3671815378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.341592558
Short name T142
Test name
Test status
Simulation time 413592758 ps
CPU time 1.25 seconds
Started Sep 11 03:43:40 PM UTC 24
Finished Sep 11 03:43:42 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341592558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.341592558
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.2840124206
Short name T106
Test name
Test status
Simulation time 580227191 ps
CPU time 1.94 seconds
Started Sep 11 03:44:37 PM UTC 24
Finished Sep 11 03:44:40 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840124206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2840124206
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/21.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.3417356783
Short name T117
Test name
Test status
Simulation time 4772167151 ps
CPU time 44.92 seconds
Started Sep 11 03:47:56 PM UTC 24
Finished Sep 11 03:48:43 PM UTC 24
Peak memory 215232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3417356783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 37.aon_timer_stress_all_with_rand_reset.3417356783
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.3465810882
Short name T98
Test name
Test status
Simulation time 416782716 ps
CPU time 1.36 seconds
Started Sep 11 03:48:10 PM UTC 24
Finished Sep 11 03:48:13 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465810882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3465810882
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/38.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.1657001843
Short name T84
Test name
Test status
Simulation time 445924184511 ps
CPU time 192.65 seconds
Started Sep 11 03:48:37 PM UTC 24
Finished Sep 11 03:51:53 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657001843 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.1657001843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/41.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.3540927487
Short name T126
Test name
Test status
Simulation time 427539362 ps
CPU time 1.17 seconds
Started Sep 11 03:40:52 PM UTC 24
Finished Sep 11 03:40:54 PM UTC 24
Peak memory 199420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540927487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3540927487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.396275502
Short name T131
Test name
Test status
Simulation time 442154862 ps
CPU time 1.46 seconds
Started Sep 11 03:42:34 PM UTC 24
Finished Sep 11 03:42:36 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396275502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.396275502
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.3380793360
Short name T93
Test name
Test status
Simulation time 598785439 ps
CPU time 1.29 seconds
Started Sep 11 03:42:41 PM UTC 24
Finished Sep 11 03:42:43 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380793360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3380793360
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.238496472
Short name T109
Test name
Test status
Simulation time 279522348970 ps
CPU time 494.64 seconds
Started Sep 11 03:44:59 PM UTC 24
Finished Sep 11 03:53:20 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238496472 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.238496472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/22.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.4148151582
Short name T147
Test name
Test status
Simulation time 433917496874 ps
CPU time 730.31 seconds
Started Sep 11 03:46:44 PM UTC 24
Finished Sep 11 03:59:02 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148151582 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.4148151582
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/30.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.463244460
Short name T163
Test name
Test status
Simulation time 22447615617 ps
CPU time 29.73 seconds
Started Sep 11 03:48:13 PM UTC 24
Finished Sep 11 03:48:44 PM UTC 24
Peak memory 211828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=463244460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 38.aon_timer_stress_all_with_rand_reset.463244460
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.1525549560
Short name T105
Test name
Test status
Simulation time 617574552 ps
CPU time 1.07 seconds
Started Sep 11 03:49:03 PM UTC 24
Finished Sep 11 03:49:05 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525549560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1525549560
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/44.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.902684124
Short name T122
Test name
Test status
Simulation time 4123913317 ps
CPU time 22.52 seconds
Started Sep 11 03:49:12 PM UTC 24
Finished Sep 11 03:49:36 PM UTC 24
Peak memory 210044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=902684124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 45.aon_timer_stress_all_with_rand_reset.902684124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.608353680
Short name T110
Test name
Test status
Simulation time 238217676953 ps
CPU time 455.92 seconds
Started Sep 11 03:41:21 PM UTC 24
Finished Sep 11 03:49:02 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608353680 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.608353680
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.3375864409
Short name T124
Test name
Test status
Simulation time 442317920 ps
CPU time 1.01 seconds
Started Sep 11 03:42:26 PM UTC 24
Finished Sep 11 03:42:28 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375864409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3375864409
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.3796454384
Short name T96
Test name
Test status
Simulation time 371536803 ps
CPU time 1.85 seconds
Started Sep 11 03:42:55 PM UTC 24
Finished Sep 11 03:42:58 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796454384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3796454384
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.1704861057
Short name T69
Test name
Test status
Simulation time 14707615965 ps
CPU time 40.09 seconds
Started Sep 11 03:42:59 PM UTC 24
Finished Sep 11 03:43:41 PM UTC 24
Peak memory 206508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1704861057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 15.aon_timer_stress_all_with_rand_reset.1704861057
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.3169251810
Short name T116
Test name
Test status
Simulation time 577740779 ps
CPU time 1.28 seconds
Started Sep 11 03:44:54 PM UTC 24
Finished Sep 11 03:44:56 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169251810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3169251810
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/22.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.1305242655
Short name T139
Test name
Test status
Simulation time 122322573962 ps
CPU time 46.42 seconds
Started Sep 11 03:47:33 PM UTC 24
Finished Sep 11 03:48:20 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305242655 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.1305242655
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/35.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.858537408
Short name T148
Test name
Test status
Simulation time 84819405104 ps
CPU time 30.31 seconds
Started Sep 11 03:42:22 PM UTC 24
Finished Sep 11 03:42:54 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858537408 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.858537408
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.2844784740
Short name T37
Test name
Test status
Simulation time 3360752103 ps
CPU time 13.04 seconds
Started Sep 11 03:42:19 PM UTC 24
Finished Sep 11 03:42:33 PM UTC 24
Peak memory 206460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2844784740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 11.aon_timer_stress_all_with_rand_reset.2844784740
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.3502088688
Short name T146
Test name
Test status
Simulation time 426382514 ps
CPU time 1.78 seconds
Started Sep 11 03:44:11 PM UTC 24
Finished Sep 11 03:44:14 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502088688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3502088688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.2976224326
Short name T130
Test name
Test status
Simulation time 509794263 ps
CPU time 2.41 seconds
Started Sep 11 03:45:18 PM UTC 24
Finished Sep 11 03:45:22 PM UTC 24
Peak memory 200764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976224326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2976224326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/23.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.4273135054
Short name T120
Test name
Test status
Simulation time 585744661 ps
CPU time 1.19 seconds
Started Sep 11 03:46:55 PM UTC 24
Finished Sep 11 03:46:58 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273135054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4273135054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/32.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.1432273550
Short name T158
Test name
Test status
Simulation time 44410426637 ps
CPU time 36.6 seconds
Started Sep 11 03:46:59 PM UTC 24
Finished Sep 11 03:47:37 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432273550 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.1432273550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/32.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.3664573827
Short name T137
Test name
Test status
Simulation time 477614471 ps
CPU time 2.3 seconds
Started Sep 11 03:47:28 PM UTC 24
Finished Sep 11 03:47:32 PM UTC 24
Peak memory 200560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664573827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3664573827
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/35.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.2566939047
Short name T81
Test name
Test status
Simulation time 187643509710 ps
CPU time 248.83 seconds
Started Sep 11 03:47:44 PM UTC 24
Finished Sep 11 03:51:56 PM UTC 24
Peak memory 200692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566939047 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.2566939047
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/36.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.3928673557
Short name T23
Test name
Test status
Simulation time 441406677 ps
CPU time 1.97 seconds
Started Sep 11 03:40:33 PM UTC 24
Finished Sep 11 03:40:36 PM UTC 24
Peak memory 199420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928673557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3928673557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.2909835929
Short name T104
Test name
Test status
Simulation time 516755366 ps
CPU time 1.66 seconds
Started Sep 11 03:48:26 PM UTC 24
Finished Sep 11 03:48:28 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909835929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2909835929
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/40.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.1550836708
Short name T143
Test name
Test status
Simulation time 269356593028 ps
CPU time 123 seconds
Started Sep 11 03:48:28 PM UTC 24
Finished Sep 11 03:50:33 PM UTC 24
Peak memory 200884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550836708 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.1550836708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/40.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.658821695
Short name T138
Test name
Test status
Simulation time 555140179 ps
CPU time 1.66 seconds
Started Sep 11 03:49:42 PM UTC 24
Finished Sep 11 03:49:44 PM UTC 24
Peak memory 199252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658821695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.658821695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/48.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.3047830786
Short name T22
Test name
Test status
Simulation time 551484547 ps
CPU time 1.01 seconds
Started Sep 11 03:40:16 PM UTC 24
Finished Sep 11 03:40:19 PM UTC 24
Peak memory 199420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047830786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3047830786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.1800276262
Short name T34
Test name
Test status
Simulation time 5906656353 ps
CPU time 14.95 seconds
Started Sep 11 03:41:59 PM UTC 24
Finished Sep 11 03:42:15 PM UTC 24
Peak memory 219080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1800276262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.aon_timer_stress_all_with_rand_reset.1800276262
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.2537122429
Short name T85
Test name
Test status
Simulation time 426569260 ps
CPU time 1.17 seconds
Started Sep 11 03:43:54 PM UTC 24
Finished Sep 11 03:43:57 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537122429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2537122429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/18.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.2055077506
Short name T168
Test name
Test status
Simulation time 7916450073 ps
CPU time 25.9 seconds
Started Sep 11 03:44:57 PM UTC 24
Finished Sep 11 03:45:24 PM UTC 24
Peak memory 215368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2055077506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 22.aon_timer_stress_all_with_rand_reset.2055077506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.2112138442
Short name T17
Test name
Test status
Simulation time 12245888783 ps
CPU time 10.49 seconds
Started Sep 11 03:40:37 PM UTC 24
Finished Sep 11 03:40:49 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112138442 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.2112138442
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.4164445307
Short name T173
Test name
Test status
Simulation time 146994041585 ps
CPU time 207.77 seconds
Started Sep 11 03:48:59 PM UTC 24
Finished Sep 11 03:52:30 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164445307 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.4164445307
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/43.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.752168817
Short name T128
Test name
Test status
Simulation time 382272820035 ps
CPU time 242.02 seconds
Started Sep 11 03:49:46 PM UTC 24
Finished Sep 11 03:53:52 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752168817 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.752168817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/48.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.1514357630
Short name T41
Test name
Test status
Simulation time 542631833 ps
CPU time 1.76 seconds
Started Sep 11 03:41:26 PM UTC 24
Finished Sep 11 03:41:28 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514357630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1514357630
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.1132691024
Short name T35
Test name
Test status
Simulation time 9430091659 ps
CPU time 32.69 seconds
Started Sep 11 03:41:43 PM UTC 24
Finished Sep 11 03:42:17 PM UTC 24
Peak memory 214596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1132691024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 9.aon_timer_stress_all_with_rand_reset.1132691024
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.2327119003
Short name T7
Test name
Test status
Simulation time 409998698 ps
CPU time 1.23 seconds
Started Sep 11 03:38:49 PM UTC 24
Finished Sep 11 03:38:51 PM UTC 24
Peak memory 199420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327119003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2327119003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.1481960776
Short name T171
Test name
Test status
Simulation time 597087095 ps
CPU time 1.19 seconds
Started Sep 11 03:42:19 PM UTC 24
Finished Sep 11 03:42:21 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481960776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1481960776
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.2797778811
Short name T155
Test name
Test status
Simulation time 119683447851 ps
CPU time 68.57 seconds
Started Sep 11 03:44:14 PM UTC 24
Finished Sep 11 03:45:24 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797778811 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.2797778811
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.1685992458
Short name T180
Test name
Test status
Simulation time 614204286 ps
CPU time 0.97 seconds
Started Sep 11 03:44:19 PM UTC 24
Finished Sep 11 03:44:21 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685992458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1685992458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/20.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.2441855441
Short name T160
Test name
Test status
Simulation time 486119804 ps
CPU time 1.3 seconds
Started Sep 11 03:46:04 PM UTC 24
Finished Sep 11 03:46:07 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441855441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2441855441
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/27.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.3889697500
Short name T176
Test name
Test status
Simulation time 530707441 ps
CPU time 1.85 seconds
Started Sep 11 03:46:21 PM UTC 24
Finished Sep 11 03:46:24 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889697500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3889697500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/28.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.3701213574
Short name T152
Test name
Test status
Simulation time 14457518018 ps
CPU time 54 seconds
Started Sep 11 03:47:31 PM UTC 24
Finished Sep 11 03:48:26 PM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3701213574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 35.aon_timer_stress_all_with_rand_reset.3701213574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.2937287458
Short name T170
Test name
Test status
Simulation time 564788850 ps
CPU time 1.24 seconds
Started Sep 11 03:49:09 PM UTC 24
Finished Sep 11 03:49:12 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937287458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2937287458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/45.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.3518440007
Short name T133
Test name
Test status
Simulation time 353178794 ps
CPU time 1.74 seconds
Started Sep 11 03:49:20 PM UTC 24
Finished Sep 11 03:49:22 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518440007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3518440007
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/46.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.2198670970
Short name T40
Test name
Test status
Simulation time 592647371 ps
CPU time 2.37 seconds
Started Sep 11 03:41:21 PM UTC 24
Finished Sep 11 03:41:24 PM UTC 24
Peak memory 200760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198670970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2198670970
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2423706510
Short name T189
Test name
Test status
Simulation time 8260713407 ps
CPU time 5.75 seconds
Started Sep 11 05:06:00 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 207056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423706510 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.2423706510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.3109617695
Short name T2
Test name
Test status
Simulation time 651047756 ps
CPU time 0.94 seconds
Started Sep 11 03:38:19 PM UTC 24
Finished Sep 11 03:38:21 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109617695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3109617695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.2133240433
Short name T153
Test name
Test status
Simulation time 374142235 ps
CPU time 1.15 seconds
Started Sep 11 03:43:11 PM UTC 24
Finished Sep 11 03:43:13 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133240433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2133240433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.3471488180
Short name T179
Test name
Test status
Simulation time 387113064 ps
CPU time 2 seconds
Started Sep 11 03:45:36 PM UTC 24
Finished Sep 11 03:45:39 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471488180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3471488180
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/25.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.375970853
Short name T140
Test name
Test status
Simulation time 345520242 ps
CPU time 1.75 seconds
Started Sep 11 03:45:58 PM UTC 24
Finished Sep 11 03:46:01 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375970853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.375970853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/26.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.2596305686
Short name T149
Test name
Test status
Simulation time 411963370 ps
CPU time 1.03 seconds
Started Sep 11 03:46:40 PM UTC 24
Finished Sep 11 03:46:42 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596305686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2596305686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/30.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.2003064486
Short name T164
Test name
Test status
Simulation time 461613727 ps
CPU time 1.27 seconds
Started Sep 11 03:46:49 PM UTC 24
Finished Sep 11 03:46:52 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003064486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2003064486
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/31.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.2099929542
Short name T162
Test name
Test status
Simulation time 553860314 ps
CPU time 1.13 seconds
Started Sep 11 03:47:22 PM UTC 24
Finished Sep 11 03:47:24 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099929542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2099929542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/34.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.449663384
Short name T174
Test name
Test status
Simulation time 522614622 ps
CPU time 1.57 seconds
Started Sep 11 03:47:56 PM UTC 24
Finished Sep 11 03:47:59 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449663384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.449663384
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/37.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.1431879956
Short name T177
Test name
Test status
Simulation time 253270407805 ps
CPU time 117.94 seconds
Started Sep 11 03:47:59 PM UTC 24
Finished Sep 11 03:49:59 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431879956 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.1431879956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/37.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.2404992320
Short name T157
Test name
Test status
Simulation time 461072282 ps
CPU time 2.2 seconds
Started Sep 11 03:48:33 PM UTC 24
Finished Sep 11 03:48:37 PM UTC 24
Peak memory 200764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404992320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2404992320
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/41.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.4016874755
Short name T72
Test name
Test status
Simulation time 3306664399 ps
CPU time 17.49 seconds
Started Sep 11 03:48:36 PM UTC 24
Finished Sep 11 03:48:55 PM UTC 24
Peak memory 219452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4016874755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 41.aon_timer_stress_all_with_rand_reset.4016874755
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.2128666767
Short name T175
Test name
Test status
Simulation time 508914822 ps
CPU time 2.55 seconds
Started Sep 11 03:48:45 PM UTC 24
Finished Sep 11 03:48:48 PM UTC 24
Peak memory 200636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128666767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2128666767
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/42.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.2715551719
Short name T169
Test name
Test status
Simulation time 2408916478 ps
CPU time 15.79 seconds
Started Sep 11 03:49:04 PM UTC 24
Finished Sep 11 03:49:22 PM UTC 24
Peak memory 206736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2715551719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 44.aon_timer_stress_all_with_rand_reset.2715551719
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.2948653594
Short name T172
Test name
Test status
Simulation time 484967350 ps
CPU time 1.21 seconds
Started Sep 11 03:49:29 PM UTC 24
Finished Sep 11 03:49:31 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948653594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2948653594
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/47.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.569940931
Short name T182
Test name
Test status
Simulation time 587602492 ps
CPU time 1.27 seconds
Started Sep 11 03:49:51 PM UTC 24
Finished Sep 11 03:49:53 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569940931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.569940931
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/49.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.2259085653
Short name T185
Test name
Test status
Simulation time 489044254 ps
CPU time 1.01 seconds
Started Sep 11 03:41:35 PM UTC 24
Finished Sep 11 03:41:37 PM UTC 24
Peak memory 199420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259085653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2259085653
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.1198245276
Short name T43
Test name
Test status
Simulation time 448094066 ps
CPU time 1.19 seconds
Started Sep 11 03:41:43 PM UTC 24
Finished Sep 11 03:41:45 PM UTC 24
Peak memory 199420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198245276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1198245276
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.4181924048
Short name T167
Test name
Test status
Simulation time 481396566 ps
CPU time 1.05 seconds
Started Sep 11 03:41:57 PM UTC 24
Finished Sep 11 03:41:59 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181924048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4181924048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.722776562
Short name T183
Test name
Test status
Simulation time 4019186838 ps
CPU time 24.57 seconds
Started Sep 11 03:46:22 PM UTC 24
Finished Sep 11 03:46:48 PM UTC 24
Peak memory 216416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=722776562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 28.aon_timer_stress_all_with_rand_reset.722776562
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.3737197227
Short name T181
Test name
Test status
Simulation time 389738774 ps
CPU time 1.11 seconds
Started Sep 11 03:46:27 PM UTC 24
Finished Sep 11 03:46:30 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737197227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3737197227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/29.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.879005469
Short name T161
Test name
Test status
Simulation time 4066495125 ps
CPU time 28.28 seconds
Started Sep 11 03:46:43 PM UTC 24
Finished Sep 11 03:47:13 PM UTC 24
Peak memory 217632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=879005469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 30.aon_timer_stress_all_with_rand_reset.879005469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.3434318644
Short name T165
Test name
Test status
Simulation time 490137920 ps
CPU time 2.18 seconds
Started Sep 11 03:47:40 PM UTC 24
Finished Sep 11 03:47:43 PM UTC 24
Peak memory 200636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434318644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3434318644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/36.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.220898696
Short name T159
Test name
Test status
Simulation time 396184995 ps
CPU time 1.46 seconds
Started Sep 11 03:48:56 PM UTC 24
Finished Sep 11 03:48:58 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220898696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.220898696
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/43.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3249316654
Short name T31
Test name
Test status
Simulation time 525386255 ps
CPU time 2.2 seconds
Started Sep 11 05:05:34 PM UTC 24
Finished Sep 11 05:05:37 PM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249316654 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.3249316654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2539885389
Short name T204
Test name
Test status
Simulation time 7278834804 ps
CPU time 5.46 seconds
Started Sep 11 05:05:34 PM UTC 24
Finished Sep 11 05:05:40 PM UTC 24
Peak memory 205640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539885389 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.2539885389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3338256777
Short name T25
Test name
Test status
Simulation time 1261619031 ps
CPU time 1.05 seconds
Started Sep 11 05:05:34 PM UTC 24
Finished Sep 11 05:05:36 PM UTC 24
Peak memory 201776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338256777 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.3338256777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.349832073
Short name T26
Test name
Test status
Simulation time 475169449 ps
CPU time 1.58 seconds
Started Sep 11 05:05:34 PM UTC 24
Finished Sep 11 05:05:36 PM UTC 24
Peak memory 204008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=349832073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_time
r_csr_mem_rw_with_rand_reset.349832073
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.358931375
Short name T24
Test name
Test status
Simulation time 363905756 ps
CPU time 0.81 seconds
Started Sep 11 05:05:34 PM UTC 24
Finished Sep 11 05:05:35 PM UTC 24
Peak memory 202624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358931375 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.358931375
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.701301141
Short name T287
Test name
Test status
Simulation time 521298750 ps
CPU time 1.09 seconds
Started Sep 11 05:05:33 PM UTC 24
Finished Sep 11 05:05:36 PM UTC 24
Peak memory 199784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701301141 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.701301141
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1143504004
Short name T288
Test name
Test status
Simulation time 369787887 ps
CPU time 1.1 seconds
Started Sep 11 05:05:34 PM UTC 24
Finished Sep 11 05:05:36 PM UTC 24
Peak memory 199864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143504004 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.1143504004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.2935453366
Short name T290
Test name
Test status
Simulation time 319365059 ps
CPU time 1.55 seconds
Started Sep 11 05:05:33 PM UTC 24
Finished Sep 11 05:05:36 PM UTC 24
Peak memory 199900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935453366 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.2935453366
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2069828441
Short name T58
Test name
Test status
Simulation time 2851767720 ps
CPU time 7.83 seconds
Started Sep 11 05:05:34 PM UTC 24
Finished Sep 11 05:05:43 PM UTC 24
Peak memory 205360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069828441 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.2069828441
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.3639367137
Short name T291
Test name
Test status
Simulation time 547933428 ps
CPU time 1.91 seconds
Started Sep 11 05:05:33 PM UTC 24
Finished Sep 11 05:05:36 PM UTC 24
Peak memory 206960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639367137 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3639367137
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.933407604
Short name T28
Test name
Test status
Simulation time 4293059429 ps
CPU time 5.46 seconds
Started Sep 11 05:05:33 PM UTC 24
Finished Sep 11 05:05:40 PM UTC 24
Peak memory 206608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933407604 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.933407604
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1785415424
Short name T64
Test name
Test status
Simulation time 741938215 ps
CPU time 2.09 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:41 PM UTC 24
Peak memory 203516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785415424 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.1785415424
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3371779559
Short name T45
Test name
Test status
Simulation time 5551569978 ps
CPU time 3.94 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:43 PM UTC 24
Peak memory 205640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371779559 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.3371779559
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3288752252
Short name T65
Test name
Test status
Simulation time 888351526 ps
CPU time 2.5 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:41 PM UTC 24
Peak memory 203260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288752252 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.3288752252
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1503819892
Short name T298
Test name
Test status
Simulation time 499580445 ps
CPU time 2.22 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:41 PM UTC 24
Peak memory 205496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1503819892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_csr_mem_rw_with_rand_reset.1503819892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.3366744472
Short name T56
Test name
Test status
Simulation time 530866780 ps
CPU time 1.46 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:40 PM UTC 24
Peak memory 201888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366744472 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3366744472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.3376563255
Short name T289
Test name
Test status
Simulation time 499140310 ps
CPU time 0.92 seconds
Started Sep 11 05:05:34 PM UTC 24
Finished Sep 11 05:05:36 PM UTC 24
Peak memory 199720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376563255 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3376563255
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3184740271
Short name T294
Test name
Test status
Simulation time 430400357 ps
CPU time 1.78 seconds
Started Sep 11 05:05:35 PM UTC 24
Finished Sep 11 05:05:38 PM UTC 24
Peak memory 199848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184740271 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.3184740271
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.1798685867
Short name T292
Test name
Test status
Simulation time 511846588 ps
CPU time 1.5 seconds
Started Sep 11 05:05:35 PM UTC 24
Finished Sep 11 05:05:38 PM UTC 24
Peak memory 199840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798685867 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.1798685867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1709278731
Short name T57
Test name
Test status
Simulation time 1980904690 ps
CPU time 3.56 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:43 PM UTC 24
Peak memory 205616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709278731 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.1709278731
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.1848143251
Short name T293
Test name
Test status
Simulation time 483352599 ps
CPU time 3.33 seconds
Started Sep 11 05:05:34 PM UTC 24
Finished Sep 11 05:05:38 PM UTC 24
Peak memory 206992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848143251 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1848143251
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1172452459
Short name T340
Test name
Test status
Simulation time 500622267 ps
CPU time 1.06 seconds
Started Sep 11 05:05:53 PM UTC 24
Finished Sep 11 05:05:55 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1172452459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_ti
mer_csr_mem_rw_with_rand_reset.1172452459
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.1237904887
Short name T51
Test name
Test status
Simulation time 417530035 ps
CPU time 1.03 seconds
Started Sep 11 05:05:51 PM UTC 24
Finished Sep 11 05:05:53 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237904887 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1237904887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.2942041975
Short name T331
Test name
Test status
Simulation time 455613081 ps
CPU time 0.92 seconds
Started Sep 11 05:05:51 PM UTC 24
Finished Sep 11 05:05:53 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942041975 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2942041975
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3611987857
Short name T343
Test name
Test status
Simulation time 1295047839 ps
CPU time 1.65 seconds
Started Sep 11 05:05:52 PM UTC 24
Finished Sep 11 05:05:55 PM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611987857 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.3611987857
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.3310671083
Short name T337
Test name
Test status
Simulation time 375180243 ps
CPU time 1.75 seconds
Started Sep 11 05:05:51 PM UTC 24
Finished Sep 11 05:05:54 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310671083 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3310671083
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3460793325
Short name T376
Test name
Test status
Simulation time 8391930538 ps
CPU time 10.54 seconds
Started Sep 11 05:05:51 PM UTC 24
Finished Sep 11 05:06:03 PM UTC 24
Peak memory 207264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460793325 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.3460793325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2116155292
Short name T345
Test name
Test status
Simulation time 405946351 ps
CPU time 1.76 seconds
Started Sep 11 05:05:53 PM UTC 24
Finished Sep 11 05:05:55 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2116155292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_ti
mer_csr_mem_rw_with_rand_reset.2116155292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.848516557
Short name T52
Test name
Test status
Simulation time 500790088 ps
CPU time 0.86 seconds
Started Sep 11 05:05:53 PM UTC 24
Finished Sep 11 05:05:55 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848516557 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.848516557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.1643201305
Short name T342
Test name
Test status
Simulation time 265751863 ps
CPU time 1.44 seconds
Started Sep 11 05:05:53 PM UTC 24
Finished Sep 11 05:05:55 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643201305 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1643201305
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.468996179
Short name T344
Test name
Test status
Simulation time 1318852718 ps
CPU time 1.77 seconds
Started Sep 11 05:05:53 PM UTC 24
Finished Sep 11 05:05:55 PM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468996179 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.468996179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.328534290
Short name T348
Test name
Test status
Simulation time 408104167 ps
CPU time 3 seconds
Started Sep 11 05:05:53 PM UTC 24
Finished Sep 11 05:05:57 PM UTC 24
Peak memory 207284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328534290 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.328534290
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3714875875
Short name T352
Test name
Test status
Simulation time 4610682427 ps
CPU time 4.21 seconds
Started Sep 11 05:05:53 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 206720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714875875 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.3714875875
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1011522194
Short name T349
Test name
Test status
Simulation time 501099135 ps
CPU time 1.41 seconds
Started Sep 11 05:05:55 PM UTC 24
Finished Sep 11 05:05:57 PM UTC 24
Peak memory 206996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1011522194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_ti
mer_csr_mem_rw_with_rand_reset.1011522194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.1252010186
Short name T351
Test name
Test status
Simulation time 290867890 ps
CPU time 1.57 seconds
Started Sep 11 05:05:54 PM UTC 24
Finished Sep 11 05:05:57 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252010186 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1252010186
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.2693968852
Short name T346
Test name
Test status
Simulation time 388911694 ps
CPU time 1.58 seconds
Started Sep 11 05:05:53 PM UTC 24
Finished Sep 11 05:05:55 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693968852 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2693968852
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1947618910
Short name T363
Test name
Test status
Simulation time 1501774915 ps
CPU time 3.17 seconds
Started Sep 11 05:05:54 PM UTC 24
Finished Sep 11 05:05:59 PM UTC 24
Peak memory 203312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947618910 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.1947618910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.2686238173
Short name T347
Test name
Test status
Simulation time 591829682 ps
CPU time 2.65 seconds
Started Sep 11 05:05:53 PM UTC 24
Finished Sep 11 05:05:57 PM UTC 24
Peak memory 206988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686238173 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2686238173
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2617230901
Short name T191
Test name
Test status
Simulation time 8127802750 ps
CPU time 7.91 seconds
Started Sep 11 05:05:53 PM UTC 24
Finished Sep 11 05:06:02 PM UTC 24
Peak memory 206992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617230901 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.2617230901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3013835272
Short name T350
Test name
Test status
Simulation time 347009935 ps
CPU time 1.13 seconds
Started Sep 11 05:05:55 PM UTC 24
Finished Sep 11 05:05:57 PM UTC 24
Peak memory 206292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3013835272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti
mer_csr_mem_rw_with_rand_reset.3013835272
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.1672191291
Short name T53
Test name
Test status
Simulation time 399836556 ps
CPU time 1.87 seconds
Started Sep 11 05:05:55 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672191291 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1672191291
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.856510845
Short name T354
Test name
Test status
Simulation time 426588951 ps
CPU time 2.22 seconds
Started Sep 11 05:05:55 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 201456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856510845 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.856510845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3368848932
Short name T362
Test name
Test status
Simulation time 1393839893 ps
CPU time 2.68 seconds
Started Sep 11 05:05:55 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 203632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368848932 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.3368848932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3662484245
Short name T358
Test name
Test status
Simulation time 1711924233 ps
CPU time 2.61 seconds
Started Sep 11 05:05:55 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 207064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662484245 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3662484245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1129230081
Short name T378
Test name
Test status
Simulation time 4210124047 ps
CPU time 7.28 seconds
Started Sep 11 05:05:55 PM UTC 24
Finished Sep 11 05:06:03 PM UTC 24
Peak memory 206676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129230081 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.1129230081
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1789781804
Short name T353
Test name
Test status
Simulation time 683981652 ps
CPU time 0.8 seconds
Started Sep 11 05:05:56 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1789781804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_ti
mer_csr_mem_rw_with_rand_reset.1789781804
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.4162505781
Short name T355
Test name
Test status
Simulation time 558654481 ps
CPU time 1.1 seconds
Started Sep 11 05:05:56 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162505781 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.4162505781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.5704213
Short name T361
Test name
Test status
Simulation time 394549855 ps
CPU time 1.44 seconds
Started Sep 11 05:05:56 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 199716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5704213 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.5704213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.786206758
Short name T364
Test name
Test status
Simulation time 2116559747 ps
CPU time 1.77 seconds
Started Sep 11 05:05:56 PM UTC 24
Finished Sep 11 05:05:59 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786206758 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.786206758
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.2173582407
Short name T359
Test name
Test status
Simulation time 469040920 ps
CPU time 2.4 seconds
Started Sep 11 05:05:55 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 207196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173582407 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2173582407
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3573997247
Short name T416
Test name
Test status
Simulation time 8097289416 ps
CPU time 13.5 seconds
Started Sep 11 05:05:55 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 206912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573997247 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.3573997247
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2960645813
Short name T368
Test name
Test status
Simulation time 346092483 ps
CPU time 1.4 seconds
Started Sep 11 05:05:57 PM UTC 24
Finished Sep 11 05:06:00 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2960645813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti
mer_csr_mem_rw_with_rand_reset.2960645813
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.3548165557
Short name T360
Test name
Test status
Simulation time 374997081 ps
CPU time 1.07 seconds
Started Sep 11 05:05:56 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548165557 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3548165557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.713931122
Short name T357
Test name
Test status
Simulation time 415638299 ps
CPU time 0.9 seconds
Started Sep 11 05:05:56 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 199784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713931122 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.713931122
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3403226876
Short name T369
Test name
Test status
Simulation time 2497890139 ps
CPU time 2.3 seconds
Started Sep 11 05:05:57 PM UTC 24
Finished Sep 11 05:06:01 PM UTC 24
Peak memory 205412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403226876 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.3403226876
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.2697492885
Short name T365
Test name
Test status
Simulation time 665829463 ps
CPU time 1.82 seconds
Started Sep 11 05:05:56 PM UTC 24
Finished Sep 11 05:05:59 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697492885 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2697492885
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.251316329
Short name T192
Test name
Test status
Simulation time 4633154179 ps
CPU time 8.18 seconds
Started Sep 11 05:05:56 PM UTC 24
Finished Sep 11 05:06:05 PM UTC 24
Peak memory 205524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251316329 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.251316329
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3481771236
Short name T377
Test name
Test status
Simulation time 397592507 ps
CPU time 1.17 seconds
Started Sep 11 05:06:00 PM UTC 24
Finished Sep 11 05:06:03 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3481771236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti
mer_csr_mem_rw_with_rand_reset.3481771236
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.3265040591
Short name T367
Test name
Test status
Simulation time 402852004 ps
CPU time 1.08 seconds
Started Sep 11 05:05:58 PM UTC 24
Finished Sep 11 05:06:00 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265040591 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3265040591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.2006035028
Short name T366
Test name
Test status
Simulation time 323937906 ps
CPU time 0.72 seconds
Started Sep 11 05:05:58 PM UTC 24
Finished Sep 11 05:05:59 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006035028 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2006035028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2989704256
Short name T371
Test name
Test status
Simulation time 2124963369 ps
CPU time 1.44 seconds
Started Sep 11 05:05:59 PM UTC 24
Finished Sep 11 05:06:02 PM UTC 24
Peak memory 204004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989704256 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.2989704256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.2707371545
Short name T370
Test name
Test status
Simulation time 554269919 ps
CPU time 2.84 seconds
Started Sep 11 05:05:58 PM UTC 24
Finished Sep 11 05:06:01 PM UTC 24
Peak memory 207020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707371545 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2707371545
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1381356212
Short name T373
Test name
Test status
Simulation time 4094654904 ps
CPU time 3.79 seconds
Started Sep 11 05:05:58 PM UTC 24
Finished Sep 11 05:06:02 PM UTC 24
Peak memory 205680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381356212 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.1381356212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1808010767
Short name T380
Test name
Test status
Simulation time 455630135 ps
CPU time 1.31 seconds
Started Sep 11 05:06:00 PM UTC 24
Finished Sep 11 05:06:03 PM UTC 24
Peak memory 206936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1808010767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti
mer_csr_mem_rw_with_rand_reset.1808010767
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.2561208643
Short name T54
Test name
Test status
Simulation time 445818718 ps
CPU time 1.33 seconds
Started Sep 11 05:06:00 PM UTC 24
Finished Sep 11 05:06:03 PM UTC 24
Peak memory 201792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561208643 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2561208643
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.585161577
Short name T379
Test name
Test status
Simulation time 432612707 ps
CPU time 1.31 seconds
Started Sep 11 05:06:00 PM UTC 24
Finished Sep 11 05:06:03 PM UTC 24
Peak memory 199784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585161577 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.585161577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4253564551
Short name T394
Test name
Test status
Simulation time 1278158429 ps
CPU time 4.47 seconds
Started Sep 11 05:06:00 PM UTC 24
Finished Sep 11 05:06:06 PM UTC 24
Peak memory 203300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253564551 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.4253564551
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.3977198614
Short name T382
Test name
Test status
Simulation time 595963895 ps
CPU time 2.11 seconds
Started Sep 11 05:06:00 PM UTC 24
Finished Sep 11 05:06:04 PM UTC 24
Peak memory 207092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977198614 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3977198614
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.749157314
Short name T375
Test name
Test status
Simulation time 557617402 ps
CPU time 0.82 seconds
Started Sep 11 05:06:01 PM UTC 24
Finished Sep 11 05:06:03 PM UTC 24
Peak memory 203944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=749157314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_tim
er_csr_mem_rw_with_rand_reset.749157314
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.3810349884
Short name T381
Test name
Test status
Simulation time 551355318 ps
CPU time 1.48 seconds
Started Sep 11 05:06:01 PM UTC 24
Finished Sep 11 05:06:03 PM UTC 24
Peak memory 201776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810349884 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3810349884
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.4257253262
Short name T374
Test name
Test status
Simulation time 364098806 ps
CPU time 0.79 seconds
Started Sep 11 05:06:01 PM UTC 24
Finished Sep 11 05:06:03 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257253262 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.4257253262
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/18.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1858231353
Short name T387
Test name
Test status
Simulation time 1027907552 ps
CPU time 2.64 seconds
Started Sep 11 05:06:01 PM UTC 24
Finished Sep 11 05:06:04 PM UTC 24
Peak memory 203376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858231353 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.1858231353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.3627996737
Short name T383
Test name
Test status
Simulation time 470307475 ps
CPU time 2 seconds
Started Sep 11 05:06:00 PM UTC 24
Finished Sep 11 05:06:04 PM UTC 24
Peak memory 206876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627996737 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3627996737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2826230454
Short name T389
Test name
Test status
Simulation time 4074551754 ps
CPU time 2.81 seconds
Started Sep 11 05:06:00 PM UTC 24
Finished Sep 11 05:06:05 PM UTC 24
Peak memory 206472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826230454 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.2826230454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1350775750
Short name T388
Test name
Test status
Simulation time 361267459 ps
CPU time 1.52 seconds
Started Sep 11 05:06:02 PM UTC 24
Finished Sep 11 05:06:05 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1350775750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti
mer_csr_mem_rw_with_rand_reset.1350775750
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.1612927731
Short name T385
Test name
Test status
Simulation time 402078453 ps
CPU time 1.1 seconds
Started Sep 11 05:06:02 PM UTC 24
Finished Sep 11 05:06:04 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612927731 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1612927731
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.3130985891
Short name T386
Test name
Test status
Simulation time 363479857 ps
CPU time 1.3 seconds
Started Sep 11 05:06:02 PM UTC 24
Finished Sep 11 05:06:04 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130985891 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3130985891
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.203501536
Short name T408
Test name
Test status
Simulation time 1982154261 ps
CPU time 5.95 seconds
Started Sep 11 05:06:02 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 203376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203501536 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.203501536
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.3943959609
Short name T391
Test name
Test status
Simulation time 293614953 ps
CPU time 3.1 seconds
Started Sep 11 05:06:02 PM UTC 24
Finished Sep 11 05:06:06 PM UTC 24
Peak memory 206988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943959609 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3943959609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3583425484
Short name T420
Test name
Test status
Simulation time 4297748927 ps
CPU time 7.64 seconds
Started Sep 11 05:06:02 PM UTC 24
Finished Sep 11 05:06:10 PM UTC 24
Peak memory 206640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583425484 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.3583425484
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3086101809
Short name T302
Test name
Test status
Simulation time 440303682 ps
CPU time 1.78 seconds
Started Sep 11 05:05:40 PM UTC 24
Finished Sep 11 05:05:43 PM UTC 24
Peak memory 201776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086101809 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.3086101809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3029559518
Short name T390
Test name
Test status
Simulation time 13970411523 ps
CPU time 23.96 seconds
Started Sep 11 05:05:40 PM UTC 24
Finished Sep 11 05:06:06 PM UTC 24
Peak memory 206036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029559518 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.3029559518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.379824382
Short name T66
Test name
Test status
Simulation time 708362348 ps
CPU time 2.24 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:42 PM UTC 24
Peak memory 201196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379824382 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.379824382
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3299908740
Short name T300
Test name
Test status
Simulation time 350249025 ps
CPU time 1.3 seconds
Started Sep 11 05:05:41 PM UTC 24
Finished Sep 11 05:05:43 PM UTC 24
Peak memory 203944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3299908740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_tim
er_csr_mem_rw_with_rand_reset.3299908740
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.3665662426
Short name T296
Test name
Test status
Simulation time 458467421 ps
CPU time 1.37 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:41 PM UTC 24
Peak memory 199720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665662426 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3665662426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3967258358
Short name T297
Test name
Test status
Simulation time 516539435 ps
CPU time 1.73 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:41 PM UTC 24
Peak memory 199848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967258358 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.3967258358
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.3210980054
Short name T295
Test name
Test status
Simulation time 528015091 ps
CPU time 0.99 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:40 PM UTC 24
Peak memory 199900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210980054 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.3210980054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1370743725
Short name T59
Test name
Test status
Simulation time 1394433046 ps
CPU time 2.71 seconds
Started Sep 11 05:05:40 PM UTC 24
Finished Sep 11 05:05:44 PM UTC 24
Peak memory 203376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370743725 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.1370743725
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2692488938
Short name T299
Test name
Test status
Simulation time 436293849 ps
CPU time 3.03 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:42 PM UTC 24
Peak memory 207128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692488938 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2692488938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3907348078
Short name T29
Test name
Test status
Simulation time 8762161097 ps
CPU time 7.38 seconds
Started Sep 11 05:05:38 PM UTC 24
Finished Sep 11 05:05:47 PM UTC 24
Peak memory 206960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907348078 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.3907348078
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.3556391211
Short name T384
Test name
Test status
Simulation time 332498389 ps
CPU time 0.79 seconds
Started Sep 11 05:06:02 PM UTC 24
Finished Sep 11 05:06:04 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556391211 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3556391211
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/20.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.3067648173
Short name T393
Test name
Test status
Simulation time 346545494 ps
CPU time 0.84 seconds
Started Sep 11 05:06:04 PM UTC 24
Finished Sep 11 05:06:06 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067648173 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3067648173
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/21.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3571765477
Short name T392
Test name
Test status
Simulation time 386945130 ps
CPU time 0.71 seconds
Started Sep 11 05:06:04 PM UTC 24
Finished Sep 11 05:06:06 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571765477 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3571765477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/22.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.618896653
Short name T396
Test name
Test status
Simulation time 429393725 ps
CPU time 0.83 seconds
Started Sep 11 05:06:04 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 201832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618896653 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.618896653
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/23.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.4071281065
Short name T395
Test name
Test status
Simulation time 463073301 ps
CPU time 0.95 seconds
Started Sep 11 05:06:04 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071281065 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4071281065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/24.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.2220615442
Short name T397
Test name
Test status
Simulation time 303170166 ps
CPU time 0.79 seconds
Started Sep 11 05:06:04 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220615442 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2220615442
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/25.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.2668029994
Short name T339
Test name
Test status
Simulation time 414108854 ps
CPU time 1.56 seconds
Started Sep 11 05:06:04 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668029994 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2668029994
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/26.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.2220188770
Short name T400
Test name
Test status
Simulation time 358027306 ps
CPU time 0.96 seconds
Started Sep 11 05:06:04 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220188770 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2220188770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/27.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.14995252
Short name T401
Test name
Test status
Simulation time 366339828 ps
CPU time 0.97 seconds
Started Sep 11 05:06:04 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14995252 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.14995252
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/28.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.2574566558
Short name T402
Test name
Test status
Simulation time 530747879 ps
CPU time 1.08 seconds
Started Sep 11 05:06:04 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574566558 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2574566558
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/29.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3659876332
Short name T47
Test name
Test status
Simulation time 560340347 ps
CPU time 1.43 seconds
Started Sep 11 05:05:42 PM UTC 24
Finished Sep 11 05:05:44 PM UTC 24
Peak memory 201776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659876332 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.3659876332
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1864552773
Short name T313
Test name
Test status
Simulation time 7015833003 ps
CPU time 4.54 seconds
Started Sep 11 05:05:42 PM UTC 24
Finished Sep 11 05:05:48 PM UTC 24
Peak memory 205640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864552773 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.1864552773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3780813506
Short name T309
Test name
Test status
Simulation time 1191201836 ps
CPU time 3.24 seconds
Started Sep 11 05:05:42 PM UTC 24
Finished Sep 11 05:05:46 PM UTC 24
Peak memory 203184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780813506 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.3780813506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3197196587
Short name T203
Test name
Test status
Simulation time 441034655 ps
CPU time 1.58 seconds
Started Sep 11 05:05:42 PM UTC 24
Finished Sep 11 05:05:45 PM UTC 24
Peak memory 203944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3197196587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_csr_mem_rw_with_rand_reset.3197196587
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.4180027852
Short name T46
Test name
Test status
Simulation time 493930642 ps
CPU time 0.79 seconds
Started Sep 11 05:05:42 PM UTC 24
Finished Sep 11 05:05:44 PM UTC 24
Peak memory 199900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180027852 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4180027852
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.1801974580
Short name T303
Test name
Test status
Simulation time 459290905 ps
CPU time 1.55 seconds
Started Sep 11 05:05:41 PM UTC 24
Finished Sep 11 05:05:43 PM UTC 24
Peak memory 199720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801974580 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1801974580
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4117896788
Short name T304
Test name
Test status
Simulation time 572214822 ps
CPU time 0.76 seconds
Started Sep 11 05:05:42 PM UTC 24
Finished Sep 11 05:05:44 PM UTC 24
Peak memory 199848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117896788 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.4117896788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.1508711304
Short name T305
Test name
Test status
Simulation time 463244138 ps
CPU time 1.57 seconds
Started Sep 11 05:05:42 PM UTC 24
Finished Sep 11 05:05:44 PM UTC 24
Peak memory 199900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508711304 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.1508711304
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3691273860
Short name T63
Test name
Test status
Simulation time 1313795371 ps
CPU time 5.85 seconds
Started Sep 11 05:05:42 PM UTC 24
Finished Sep 11 05:05:49 PM UTC 24
Peak memory 203376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691273860 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.3691273860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.1516519964
Short name T301
Test name
Test status
Simulation time 438570043 ps
CPU time 1.63 seconds
Started Sep 11 05:05:41 PM UTC 24
Finished Sep 11 05:05:43 PM UTC 24
Peak memory 206252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516519964 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1516519964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.751239658
Short name T188
Test name
Test status
Simulation time 7755017288 ps
CPU time 14.39 seconds
Started Sep 11 05:05:41 PM UTC 24
Finished Sep 11 05:05:56 PM UTC 24
Peak memory 206864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751239658 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.751239658
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.238330075
Short name T398
Test name
Test status
Simulation time 283844016 ps
CPU time 0.66 seconds
Started Sep 11 05:06:04 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 199784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238330075 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.238330075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/30.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.686677972
Short name T399
Test name
Test status
Simulation time 508366722 ps
CPU time 0.94 seconds
Started Sep 11 05:06:05 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 199784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686677972 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.686677972
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/31.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.2740588191
Short name T372
Test name
Test status
Simulation time 275116970 ps
CPU time 1.12 seconds
Started Sep 11 05:06:05 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740588191 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2740588191
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/32.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.3717071032
Short name T403
Test name
Test status
Simulation time 371116941 ps
CPU time 1.12 seconds
Started Sep 11 05:06:05 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717071032 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3717071032
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/33.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.65277686
Short name T404
Test name
Test status
Simulation time 347859826 ps
CPU time 1.1 seconds
Started Sep 11 05:06:05 PM UTC 24
Finished Sep 11 05:06:07 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65277686 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.65277686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/34.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.3887074819
Short name T405
Test name
Test status
Simulation time 325919856 ps
CPU time 1.44 seconds
Started Sep 11 05:06:05 PM UTC 24
Finished Sep 11 05:06:08 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887074819 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3887074819
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/35.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3692995534
Short name T406
Test name
Test status
Simulation time 382227504 ps
CPU time 0.74 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692995534 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3692995534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/36.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.3943721180
Short name T411
Test name
Test status
Simulation time 509010711 ps
CPU time 0.81 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943721180 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3943721180
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/37.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.2543364165
Short name T413
Test name
Test status
Simulation time 444429704 ps
CPU time 1.07 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543364165 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2543364165
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/38.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.2730240569
Short name T418
Test name
Test status
Simulation time 468803733 ps
CPU time 1.45 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:10 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730240569 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2730240569
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/39.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2325102172
Short name T312
Test name
Test status
Simulation time 525395042 ps
CPU time 1.29 seconds
Started Sep 11 05:05:45 PM UTC 24
Finished Sep 11 05:05:47 PM UTC 24
Peak memory 201776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325102172 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.2325102172
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.361836930
Short name T55
Test name
Test status
Simulation time 8006177800 ps
CPU time 22.42 seconds
Started Sep 11 05:05:45 PM UTC 24
Finished Sep 11 05:06:08 PM UTC 24
Peak memory 205572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361836930 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.361836930
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.213372483
Short name T48
Test name
Test status
Simulation time 1085487154 ps
CPU time 1.11 seconds
Started Sep 11 05:05:43 PM UTC 24
Finished Sep 11 05:05:45 PM UTC 24
Peak memory 201768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213372483 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.213372483
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4130440856
Short name T311
Test name
Test status
Simulation time 608176213 ps
CPU time 1.14 seconds
Started Sep 11 05:05:45 PM UTC 24
Finished Sep 11 05:05:47 PM UTC 24
Peak memory 204968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4130440856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim
er_csr_mem_rw_with_rand_reset.4130440856
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.1034469507
Short name T49
Test name
Test status
Simulation time 320483833 ps
CPU time 0.92 seconds
Started Sep 11 05:05:44 PM UTC 24
Finished Sep 11 05:05:46 PM UTC 24
Peak memory 201948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034469507 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1034469507
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.2891349767
Short name T308
Test name
Test status
Simulation time 510565315 ps
CPU time 1.47 seconds
Started Sep 11 05:05:43 PM UTC 24
Finished Sep 11 05:05:46 PM UTC 24
Peak memory 199720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891349767 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2891349767
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1069427781
Short name T310
Test name
Test status
Simulation time 302146121 ps
CPU time 1.74 seconds
Started Sep 11 05:05:43 PM UTC 24
Finished Sep 11 05:05:46 PM UTC 24
Peak memory 199820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069427781 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.1069427781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2979484515
Short name T307
Test name
Test status
Simulation time 279561948 ps
CPU time 1.22 seconds
Started Sep 11 05:05:43 PM UTC 24
Finished Sep 11 05:05:46 PM UTC 24
Peak memory 199876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979484515 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.2979484515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1473487699
Short name T60
Test name
Test status
Simulation time 1219805659 ps
CPU time 2.06 seconds
Started Sep 11 05:05:45 PM UTC 24
Finished Sep 11 05:05:48 PM UTC 24
Peak memory 203568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473487699 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.1473487699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.1216781514
Short name T306
Test name
Test status
Simulation time 487046032 ps
CPU time 1.71 seconds
Started Sep 11 05:05:42 PM UTC 24
Finished Sep 11 05:05:45 PM UTC 24
Peak memory 206956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216781514 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1216781514
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3900399708
Short name T190
Test name
Test status
Simulation time 7847604564 ps
CPU time 13.1 seconds
Started Sep 11 05:05:43 PM UTC 24
Finished Sep 11 05:05:57 PM UTC 24
Peak memory 207128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900399708 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.3900399708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.3441495494
Short name T409
Test name
Test status
Simulation time 392229945 ps
CPU time 0.81 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441495494 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3441495494
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/40.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.2008625758
Short name T415
Test name
Test status
Simulation time 404313595 ps
CPU time 1.12 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008625758 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2008625758
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/41.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2235055211
Short name T412
Test name
Test status
Simulation time 319281843 ps
CPU time 0.94 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 199760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235055211 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2235055211
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/42.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.2600519912
Short name T417
Test name
Test status
Simulation time 284138917 ps
CPU time 1.23 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:10 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600519912 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2600519912
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/43.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.80088752
Short name T407
Test name
Test status
Simulation time 425497340 ps
CPU time 0.61 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80088752 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.80088752
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/44.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.2221618032
Short name T414
Test name
Test status
Simulation time 469433032 ps
CPU time 0.85 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 199732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221618032 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2221618032
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/45.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.2735932703
Short name T410
Test name
Test status
Simulation time 387014123 ps
CPU time 0.59 seconds
Started Sep 11 05:06:07 PM UTC 24
Finished Sep 11 05:06:09 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735932703 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2735932703
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/46.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.206957217
Short name T419
Test name
Test status
Simulation time 379078009 ps
CPU time 1.01 seconds
Started Sep 11 05:06:08 PM UTC 24
Finished Sep 11 05:06:10 PM UTC 24
Peak memory 199784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206957217 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.206957217
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/47.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.4223255381
Short name T422
Test name
Test status
Simulation time 364893991 ps
CPU time 0.78 seconds
Started Sep 11 05:06:09 PM UTC 24
Finished Sep 11 05:06:11 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223255381 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.4223255381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/48.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.516136420
Short name T421
Test name
Test status
Simulation time 435728054 ps
CPU time 0.74 seconds
Started Sep 11 05:06:09 PM UTC 24
Finished Sep 11 05:06:11 PM UTC 24
Peak memory 199784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516136420 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.516136420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/49.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3336123765
Short name T314
Test name
Test status
Simulation time 463413708 ps
CPU time 0.94 seconds
Started Sep 11 05:05:46 PM UTC 24
Finished Sep 11 05:05:48 PM UTC 24
Peak memory 203944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3336123765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_tim
er_csr_mem_rw_with_rand_reset.3336123765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.3198411258
Short name T61
Test name
Test status
Simulation time 456586106 ps
CPU time 1.11 seconds
Started Sep 11 05:05:46 PM UTC 24
Finished Sep 11 05:05:48 PM UTC 24
Peak memory 201948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198411258 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3198411258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.1682729097
Short name T315
Test name
Test status
Simulation time 343321523 ps
CPU time 1.22 seconds
Started Sep 11 05:05:46 PM UTC 24
Finished Sep 11 05:05:48 PM UTC 24
Peak memory 199720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682729097 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1682729097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3401914855
Short name T325
Test name
Test status
Simulation time 911386835 ps
CPU time 3.33 seconds
Started Sep 11 05:05:46 PM UTC 24
Finished Sep 11 05:05:51 PM UTC 24
Peak memory 203504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401914855 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.3401914855
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.1103682914
Short name T316
Test name
Test status
Simulation time 860758027 ps
CPU time 2.8 seconds
Started Sep 11 05:05:45 PM UTC 24
Finished Sep 11 05:05:49 PM UTC 24
Peak memory 207020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103682914 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1103682914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3842278005
Short name T187
Test name
Test status
Simulation time 4588897281 ps
CPU time 4.76 seconds
Started Sep 11 05:05:46 PM UTC 24
Finished Sep 11 05:05:52 PM UTC 24
Peak memory 206784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842278005 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.3842278005
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2291463280
Short name T318
Test name
Test status
Simulation time 421603020 ps
CPU time 1.67 seconds
Started Sep 11 05:05:47 PM UTC 24
Finished Sep 11 05:05:49 PM UTC 24
Peak memory 203944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2291463280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_tim
er_csr_mem_rw_with_rand_reset.2291463280
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.2208548671
Short name T62
Test name
Test status
Simulation time 298036732 ps
CPU time 1.36 seconds
Started Sep 11 05:05:46 PM UTC 24
Finished Sep 11 05:05:49 PM UTC 24
Peak memory 199900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208548671 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2208548671
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.3388254983
Short name T317
Test name
Test status
Simulation time 403688831 ps
CPU time 1.24 seconds
Started Sep 11 05:05:46 PM UTC 24
Finished Sep 11 05:05:49 PM UTC 24
Peak memory 199720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388254983 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3388254983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.938857610
Short name T324
Test name
Test status
Simulation time 1627719193 ps
CPU time 3.22 seconds
Started Sep 11 05:05:46 PM UTC 24
Finished Sep 11 05:05:51 PM UTC 24
Peak memory 203308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938857610 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.938857610
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3698596251
Short name T321
Test name
Test status
Simulation time 575791199 ps
CPU time 2.85 seconds
Started Sep 11 05:05:46 PM UTC 24
Finished Sep 11 05:05:50 PM UTC 24
Peak memory 207092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698596251 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3698596251
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1195678179
Short name T186
Test name
Test status
Simulation time 8138795232 ps
CPU time 3.87 seconds
Started Sep 11 05:05:46 PM UTC 24
Finished Sep 11 05:05:51 PM UTC 24
Peak memory 207036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195678179 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.1195678179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2657312861
Short name T319
Test name
Test status
Simulation time 426061153 ps
CPU time 1.03 seconds
Started Sep 11 05:05:48 PM UTC 24
Finished Sep 11 05:05:50 PM UTC 24
Peak memory 203944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2657312861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim
er_csr_mem_rw_with_rand_reset.2657312861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.2454531558
Short name T320
Test name
Test status
Simulation time 341170860 ps
CPU time 1.18 seconds
Started Sep 11 05:05:48 PM UTC 24
Finished Sep 11 05:05:50 PM UTC 24
Peak memory 201888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454531558 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2454531558
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.721952154
Short name T322
Test name
Test status
Simulation time 442702658 ps
CPU time 1.71 seconds
Started Sep 11 05:05:48 PM UTC 24
Finished Sep 11 05:05:50 PM UTC 24
Peak memory 199784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721952154 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.721952154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3263695476
Short name T328
Test name
Test status
Simulation time 1335938323 ps
CPU time 2.78 seconds
Started Sep 11 05:05:48 PM UTC 24
Finished Sep 11 05:05:52 PM UTC 24
Peak memory 203380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263695476 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.3263695476
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.3440143770
Short name T326
Test name
Test status
Simulation time 358471659 ps
CPU time 2.21 seconds
Started Sep 11 05:05:48 PM UTC 24
Finished Sep 11 05:05:51 PM UTC 24
Peak memory 207020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440143770 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3440143770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4204145646
Short name T336
Test name
Test status
Simulation time 4365307423 ps
CPU time 4.69 seconds
Started Sep 11 05:05:48 PM UTC 24
Finished Sep 11 05:05:53 PM UTC 24
Peak memory 206552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204145646 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.4204145646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.308669292
Short name T327
Test name
Test status
Simulation time 840214671 ps
CPU time 1.3 seconds
Started Sep 11 05:05:49 PM UTC 24
Finished Sep 11 05:05:51 PM UTC 24
Peak memory 205856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=308669292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_time
r_csr_mem_rw_with_rand_reset.308669292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.3305901619
Short name T50
Test name
Test status
Simulation time 508330461 ps
CPU time 1.7 seconds
Started Sep 11 05:05:49 PM UTC 24
Finished Sep 11 05:05:52 PM UTC 24
Peak memory 201888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305901619 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3305901619
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.1433485802
Short name T323
Test name
Test status
Simulation time 354499741 ps
CPU time 0.73 seconds
Started Sep 11 05:05:49 PM UTC 24
Finished Sep 11 05:05:51 PM UTC 24
Peak memory 199720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433485802 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1433485802
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.928815062
Short name T329
Test name
Test status
Simulation time 1606386651 ps
CPU time 1.6 seconds
Started Sep 11 05:05:49 PM UTC 24
Finished Sep 11 05:05:52 PM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928815062 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.928815062
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.4107420953
Short name T330
Test name
Test status
Simulation time 515191932 ps
CPU time 2.68 seconds
Started Sep 11 05:05:49 PM UTC 24
Finished Sep 11 05:05:53 PM UTC 24
Peak memory 206992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107420953 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4107420953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3742314171
Short name T356
Test name
Test status
Simulation time 4795774290 ps
CPU time 8.12 seconds
Started Sep 11 05:05:49 PM UTC 24
Finished Sep 11 05:05:58 PM UTC 24
Peak memory 206832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742314171 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.3742314171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.562599444
Short name T338
Test name
Test status
Simulation time 503049987 ps
CPU time 2.11 seconds
Started Sep 11 05:05:51 PM UTC 24
Finished Sep 11 05:05:54 PM UTC 24
Peak memory 205856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=562599444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_time
r_csr_mem_rw_with_rand_reset.562599444
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.2408258361
Short name T334
Test name
Test status
Simulation time 350761634 ps
CPU time 1.41 seconds
Started Sep 11 05:05:51 PM UTC 24
Finished Sep 11 05:05:53 PM UTC 24
Peak memory 201948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408258361 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2408258361
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.1206142337
Short name T335
Test name
Test status
Simulation time 263215512 ps
CPU time 1.46 seconds
Started Sep 11 05:05:51 PM UTC 24
Finished Sep 11 05:05:53 PM UTC 24
Peak memory 199720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206142337 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1206142337
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.298265543
Short name T341
Test name
Test status
Simulation time 1343783370 ps
CPU time 3.11 seconds
Started Sep 11 05:05:51 PM UTC 24
Finished Sep 11 05:05:55 PM UTC 24
Peak memory 203372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298265543 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.298265543
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.3598720874
Short name T333
Test name
Test status
Simulation time 397503062 ps
CPU time 2.98 seconds
Started Sep 11 05:05:49 PM UTC 24
Finished Sep 11 05:05:53 PM UTC 24
Peak memory 207004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598720874 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3598720874
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1293244146
Short name T332
Test name
Test status
Simulation time 4256065440 ps
CPU time 1.27 seconds
Started Sep 11 05:05:51 PM UTC 24
Finished Sep 11 05:05:53 PM UTC 24
Peak memory 203820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293244146 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.1293244146
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.439718500
Short name T3
Test name
Test status
Simulation time 23060932037 ps
CPU time 41.16 seconds
Started Sep 11 03:37:51 PM UTC 24
Finished Sep 11 03:38:34 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439718500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.439718500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.650785710
Short name T1
Test name
Test status
Simulation time 586976752 ps
CPU time 1.07 seconds
Started Sep 11 03:37:48 PM UTC 24
Finished Sep 11 03:37:50 PM UTC 24
Peak memory 199980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650785710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.650785710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/0.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.3658546555
Short name T5
Test name
Test status
Simulation time 1198409480 ps
CPU time 3.49 seconds
Started Sep 11 03:38:44 PM UTC 24
Finished Sep 11 03:38:49 PM UTC 24
Peak memory 200548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658546555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3658546555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.4028862116
Short name T12
Test name
Test status
Simulation time 3882684551 ps
CPU time 6.22 seconds
Started Sep 11 03:39:10 PM UTC 24
Finished Sep 11 03:39:18 PM UTC 24
Peak memory 231224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028862116 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.4028862116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.1092944171
Short name T4
Test name
Test status
Simulation time 584809756 ps
CPU time 1.36 seconds
Started Sep 11 03:38:41 PM UTC 24
Finished Sep 11 03:38:43 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092944171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1092944171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/1.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.1935646397
Short name T198
Test name
Test status
Simulation time 28015998033 ps
CPU time 33.57 seconds
Started Sep 11 03:41:53 PM UTC 24
Finished Sep 11 03:42:27 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935646397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1935646397
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.1417233304
Short name T209
Test name
Test status
Simulation time 526480386 ps
CPU time 2.28 seconds
Started Sep 11 03:41:48 PM UTC 24
Finished Sep 11 03:41:52 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417233304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1417233304
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/10.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.2113622536
Short name T195
Test name
Test status
Simulation time 2330030498 ps
CPU time 6.18 seconds
Started Sep 11 03:42:18 PM UTC 24
Finished Sep 11 03:42:25 PM UTC 24
Peak memory 200612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113622536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2113622536
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.1378702571
Short name T210
Test name
Test status
Simulation time 412411474 ps
CPU time 1.46 seconds
Started Sep 11 03:42:16 PM UTC 24
Finished Sep 11 03:42:18 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378702571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1378702571
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/11.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.362074830
Short name T216
Test name
Test status
Simulation time 27617164616 ps
CPU time 21.64 seconds
Started Sep 11 03:42:26 PM UTC 24
Finished Sep 11 03:42:49 PM UTC 24
Peak memory 200456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362074830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.362074830
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.1666832855
Short name T211
Test name
Test status
Simulation time 377488670 ps
CPU time 1.97 seconds
Started Sep 11 03:42:22 PM UTC 24
Finished Sep 11 03:42:25 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666832855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1666832855
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/12.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.2363484212
Short name T200
Test name
Test status
Simulation time 59424335847 ps
CPU time 29.05 seconds
Started Sep 11 03:42:33 PM UTC 24
Finished Sep 11 03:43:03 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363484212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2363484212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.2858671268
Short name T214
Test name
Test status
Simulation time 491418181 ps
CPU time 2.14 seconds
Started Sep 11 03:42:29 PM UTC 24
Finished Sep 11 03:42:33 PM UTC 24
Peak memory 200752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858671268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2858671268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.2063284074
Short name T154
Test name
Test status
Simulation time 457383534381 ps
CPU time 216.81 seconds
Started Sep 11 03:42:37 PM UTC 24
Finished Sep 11 03:46:17 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063284074 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.2063284074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/13.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.852960419
Short name T218
Test name
Test status
Simulation time 7931128082 ps
CPU time 19.19 seconds
Started Sep 11 03:42:38 PM UTC 24
Finished Sep 11 03:42:58 PM UTC 24
Peak memory 200624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852960419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.852960419
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.4257950815
Short name T215
Test name
Test status
Simulation time 366877620 ps
CPU time 1.87 seconds
Started Sep 11 03:42:37 PM UTC 24
Finished Sep 11 03:42:40 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257950815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.4257950815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/14.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.526699167
Short name T8
Test name
Test status
Simulation time 23895052684 ps
CPU time 14.13 seconds
Started Sep 11 03:42:54 PM UTC 24
Finished Sep 11 03:43:10 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526699167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.526699167
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.3066718917
Short name T217
Test name
Test status
Simulation time 510177990 ps
CPU time 1.27 seconds
Started Sep 11 03:42:52 PM UTC 24
Finished Sep 11 03:42:55 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066718917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3066718917
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/15.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.614917288
Short name T221
Test name
Test status
Simulation time 22057653322 ps
CPU time 30.41 seconds
Started Sep 11 03:43:08 PM UTC 24
Finished Sep 11 03:43:39 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614917288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.614917288
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.1710241066
Short name T219
Test name
Test status
Simulation time 522097925 ps
CPU time 2.37 seconds
Started Sep 11 03:43:04 PM UTC 24
Finished Sep 11 03:43:07 PM UTC 24
Peak memory 200632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710241066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1710241066
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/16.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.3142326250
Short name T230
Test name
Test status
Simulation time 39913387611 ps
CPU time 81.38 seconds
Started Sep 11 03:43:39 PM UTC 24
Finished Sep 11 03:45:02 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142326250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3142326250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.775352928
Short name T220
Test name
Test status
Simulation time 605160273 ps
CPU time 0.99 seconds
Started Sep 11 03:43:36 PM UTC 24
Finished Sep 11 03:43:38 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775352928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.775352928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.1844105010
Short name T194
Test name
Test status
Simulation time 4481889915 ps
CPU time 29.43 seconds
Started Sep 11 03:43:42 PM UTC 24
Finished Sep 11 03:44:13 PM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1844105010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 17.aon_timer_stress_all_with_rand_reset.1844105010
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.1649115129
Short name T223
Test name
Test status
Simulation time 44460480168 ps
CPU time 17.18 seconds
Started Sep 11 03:43:47 PM UTC 24
Finished Sep 11 03:44:06 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649115129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1649115129
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/18.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.868004541
Short name T222
Test name
Test status
Simulation time 585620959 ps
CPU time 1.25 seconds
Started Sep 11 03:43:44 PM UTC 24
Finished Sep 11 03:43:47 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868004541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.868004541
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/18.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.3361689327
Short name T228
Test name
Test status
Simulation time 53051978696 ps
CPU time 37.57 seconds
Started Sep 11 03:44:11 PM UTC 24
Finished Sep 11 03:44:50 PM UTC 24
Peak memory 200752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361689327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3361689327
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.560186993
Short name T224
Test name
Test status
Simulation time 555122059 ps
CPU time 1.12 seconds
Started Sep 11 03:44:11 PM UTC 24
Finished Sep 11 03:44:13 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560186993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.560186993
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/19.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.2992974998
Short name T75
Test name
Test status
Simulation time 23000807633 ps
CPU time 62.79 seconds
Started Sep 11 03:39:19 PM UTC 24
Finished Sep 11 03:40:23 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992974998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2992974998
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.750184134
Short name T15
Test name
Test status
Simulation time 4248916576 ps
CPU time 2.21 seconds
Started Sep 11 03:39:54 PM UTC 24
Finished Sep 11 03:39:57 PM UTC 24
Peak memory 231156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750184134 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.750184134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.345357074
Short name T9
Test name
Test status
Simulation time 531948430 ps
CPU time 1.68 seconds
Started Sep 11 03:39:19 PM UTC 24
Finished Sep 11 03:39:21 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345357074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.345357074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/2.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.3503476709
Short name T226
Test name
Test status
Simulation time 2818832858 ps
CPU time 3.42 seconds
Started Sep 11 03:44:18 PM UTC 24
Finished Sep 11 03:44:23 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503476709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3503476709
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/20.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.1477915704
Short name T225
Test name
Test status
Simulation time 602073777 ps
CPU time 1.19 seconds
Started Sep 11 03:44:15 PM UTC 24
Finished Sep 11 03:44:17 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477915704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1477915704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/20.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.1756200109
Short name T199
Test name
Test status
Simulation time 36511079384 ps
CPU time 77.12 seconds
Started Sep 11 03:44:32 PM UTC 24
Finished Sep 11 03:45:51 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756200109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1756200109
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/21.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.1674147425
Short name T227
Test name
Test status
Simulation time 400512950 ps
CPU time 0.98 seconds
Started Sep 11 03:44:29 PM UTC 24
Finished Sep 11 03:44:31 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674147425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1674147425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/21.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.2344477260
Short name T193
Test name
Test status
Simulation time 1011673472 ps
CPU time 7.81 seconds
Started Sep 11 03:44:41 PM UTC 24
Finished Sep 11 03:44:50 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2344477260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 21.aon_timer_stress_all_with_rand_reset.2344477260
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.4060484059
Short name T233
Test name
Test status
Simulation time 50598681726 ps
CPU time 39.04 seconds
Started Sep 11 03:44:51 PM UTC 24
Finished Sep 11 03:45:32 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060484059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.4060484059
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/22.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.953225711
Short name T229
Test name
Test status
Simulation time 528985119 ps
CPU time 1.11 seconds
Started Sep 11 03:44:50 PM UTC 24
Finished Sep 11 03:44:53 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953225711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.953225711
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/22.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.1243712542
Short name T248
Test name
Test status
Simulation time 37321577012 ps
CPU time 105.96 seconds
Started Sep 11 03:45:06 PM UTC 24
Finished Sep 11 03:46:54 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243712542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1243712542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/23.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.4045233423
Short name T231
Test name
Test status
Simulation time 530749874 ps
CPU time 1.26 seconds
Started Sep 11 03:45:03 PM UTC 24
Finished Sep 11 03:45:05 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045233423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4045233423
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/23.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.2993182870
Short name T184
Test name
Test status
Simulation time 421935616 ps
CPU time 1.2 seconds
Started Sep 11 03:45:27 PM UTC 24
Finished Sep 11 03:45:30 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993182870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2993182870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/24.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.3648033567
Short name T234
Test name
Test status
Simulation time 4212497233 ps
CPU time 6.88 seconds
Started Sep 11 03:45:27 PM UTC 24
Finished Sep 11 03:45:35 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648033567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3648033567
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/24.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.2165777804
Short name T232
Test name
Test status
Simulation time 485418662 ps
CPU time 1 seconds
Started Sep 11 03:45:24 PM UTC 24
Finished Sep 11 03:45:27 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165777804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2165777804
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/24.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.265941241
Short name T237
Test name
Test status
Simulation time 6629713122 ps
CPU time 21.09 seconds
Started Sep 11 03:45:34 PM UTC 24
Finished Sep 11 03:45:57 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265941241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.265941241
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/25.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.2397199367
Short name T235
Test name
Test status
Simulation time 483195743 ps
CPU time 1.26 seconds
Started Sep 11 03:45:33 PM UTC 24
Finished Sep 11 03:45:36 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397199367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2397199367
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/25.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.3710510135
Short name T238
Test name
Test status
Simulation time 2294487777 ps
CPU time 25.36 seconds
Started Sep 11 03:45:36 PM UTC 24
Finished Sep 11 03:46:03 PM UTC 24
Peak memory 218396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3710510135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 25.aon_timer_stress_all_with_rand_reset.3710510135
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.3830425025
Short name T239
Test name
Test status
Simulation time 13993593967 ps
CPU time 7.22 seconds
Started Sep 11 03:45:56 PM UTC 24
Finished Sep 11 03:46:04 PM UTC 24
Peak memory 200880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830425025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3830425025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/26.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.3255375185
Short name T236
Test name
Test status
Simulation time 433862637 ps
CPU time 1.16 seconds
Started Sep 11 03:45:53 PM UTC 24
Finished Sep 11 03:45:55 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255375185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3255375185
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/26.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.1998072164
Short name T242
Test name
Test status
Simulation time 14967727158 ps
CPU time 20.96 seconds
Started Sep 11 03:46:03 PM UTC 24
Finished Sep 11 03:46:26 PM UTC 24
Peak memory 200612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998072164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1998072164
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/27.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.2872051919
Short name T240
Test name
Test status
Simulation time 594196896 ps
CPU time 2.37 seconds
Started Sep 11 03:46:01 PM UTC 24
Finished Sep 11 03:46:05 PM UTC 24
Peak memory 200624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872051919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2872051919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/27.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.3393288170
Short name T250
Test name
Test status
Simulation time 23609811366 ps
CPU time 38.97 seconds
Started Sep 11 03:46:19 PM UTC 24
Finished Sep 11 03:46:59 PM UTC 24
Peak memory 200612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393288170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3393288170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/28.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.1938875163
Short name T241
Test name
Test status
Simulation time 418306717 ps
CPU time 1.42 seconds
Started Sep 11 03:46:18 PM UTC 24
Finished Sep 11 03:46:20 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938875163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1938875163
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/28.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.828565286
Short name T245
Test name
Test status
Simulation time 5634426007 ps
CPU time 16.4 seconds
Started Sep 11 03:46:26 PM UTC 24
Finished Sep 11 03:46:44 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828565286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.828565286
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/29.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.4136086128
Short name T243
Test name
Test status
Simulation time 557367271 ps
CPU time 2.49 seconds
Started Sep 11 03:46:24 PM UTC 24
Finished Sep 11 03:46:28 PM UTC 24
Peak memory 200552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136086128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4136086128
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/29.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.2253225221
Short name T39
Test name
Test status
Simulation time 14023165147 ps
CPU time 11.7 seconds
Started Sep 11 03:40:02 PM UTC 24
Finished Sep 11 03:40:15 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253225221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2253225221
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.1412784785
Short name T20
Test name
Test status
Simulation time 8248382875 ps
CPU time 6.4 seconds
Started Sep 11 03:40:27 PM UTC 24
Finished Sep 11 03:40:35 PM UTC 24
Peak memory 231288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412784785 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1412784785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.1007069638
Short name T38
Test name
Test status
Simulation time 552391781 ps
CPU time 2.3 seconds
Started Sep 11 03:39:58 PM UTC 24
Finished Sep 11 03:40:01 PM UTC 24
Peak memory 200556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007069638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1007069638
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.4254346053
Short name T14
Test name
Test status
Simulation time 881959114 ps
CPU time 5.92 seconds
Started Sep 11 03:40:19 PM UTC 24
Finished Sep 11 03:40:26 PM UTC 24
Peak memory 214148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4254346053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 3.aon_timer_stress_all_with_rand_reset.4254346053
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.337428383
Short name T251
Test name
Test status
Simulation time 21913981639 ps
CPU time 25.15 seconds
Started Sep 11 03:46:35 PM UTC 24
Finished Sep 11 03:47:01 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337428383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.337428383
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/30.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.4183143779
Short name T244
Test name
Test status
Simulation time 510768473 ps
CPU time 1.24 seconds
Started Sep 11 03:46:31 PM UTC 24
Finished Sep 11 03:46:33 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183143779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.4183143779
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/30.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.3897981953
Short name T247
Test name
Test status
Simulation time 2197042492 ps
CPU time 7.21 seconds
Started Sep 11 03:46:45 PM UTC 24
Finished Sep 11 03:46:54 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897981953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3897981953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/31.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.949917582
Short name T246
Test name
Test status
Simulation time 541316542 ps
CPU time 2.18 seconds
Started Sep 11 03:46:45 PM UTC 24
Finished Sep 11 03:46:49 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949917582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.949917582
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/31.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.1705952720
Short name T254
Test name
Test status
Simulation time 18298769909 ps
CPU time 25.54 seconds
Started Sep 11 03:46:54 PM UTC 24
Finished Sep 11 03:47:21 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705952720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1705952720
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/32.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.2064066236
Short name T249
Test name
Test status
Simulation time 571450173 ps
CPU time 1.25 seconds
Started Sep 11 03:46:52 PM UTC 24
Finished Sep 11 03:46:55 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064066236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2064066236
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/32.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.1194532430
Short name T178
Test name
Test status
Simulation time 344036541 ps
CPU time 1.39 seconds
Started Sep 11 03:47:04 PM UTC 24
Finished Sep 11 03:47:06 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194532430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1194532430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/33.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.1091054525
Short name T258
Test name
Test status
Simulation time 45412086820 ps
CPU time 38.58 seconds
Started Sep 11 03:47:02 PM UTC 24
Finished Sep 11 03:47:42 PM UTC 24
Peak memory 200884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091054525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1091054525
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/33.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.201869469
Short name T252
Test name
Test status
Simulation time 619966491 ps
CPU time 1.8 seconds
Started Sep 11 03:47:00 PM UTC 24
Finished Sep 11 03:47:02 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201869469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.201869469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/33.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.1098631974
Short name T256
Test name
Test status
Simulation time 38847789219 ps
CPU time 14.69 seconds
Started Sep 11 03:47:20 PM UTC 24
Finished Sep 11 03:47:36 PM UTC 24
Peak memory 200612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098631974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1098631974
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/34.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.2543706860
Short name T253
Test name
Test status
Simulation time 374058731 ps
CPU time 1.14 seconds
Started Sep 11 03:47:17 PM UTC 24
Finished Sep 11 03:47:19 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543706860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2543706860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/34.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.4215768977
Short name T261
Test name
Test status
Simulation time 52400719677 ps
CPU time 27.21 seconds
Started Sep 11 03:47:26 PM UTC 24
Finished Sep 11 03:47:55 PM UTC 24
Peak memory 200612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215768977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4215768977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/35.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.2671948875
Short name T255
Test name
Test status
Simulation time 483756768 ps
CPU time 1.56 seconds
Started Sep 11 03:47:25 PM UTC 24
Finished Sep 11 03:47:28 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671948875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2671948875
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/35.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.2906669075
Short name T259
Test name
Test status
Simulation time 28368490691 ps
CPU time 4.71 seconds
Started Sep 11 03:47:38 PM UTC 24
Finished Sep 11 03:47:43 PM UTC 24
Peak memory 200624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906669075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2906669075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/36.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.3790440887
Short name T257
Test name
Test status
Simulation time 529086173 ps
CPU time 1.22 seconds
Started Sep 11 03:47:37 PM UTC 24
Finished Sep 11 03:47:39 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790440887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3790440887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/36.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.1777695275
Short name T263
Test name
Test status
Simulation time 44016254237 ps
CPU time 21.72 seconds
Started Sep 11 03:47:47 PM UTC 24
Finished Sep 11 03:48:10 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777695275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1777695275
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/37.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.930147170
Short name T260
Test name
Test status
Simulation time 376663520 ps
CPU time 1.44 seconds
Started Sep 11 03:47:44 PM UTC 24
Finished Sep 11 03:47:46 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930147170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.930147170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/37.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.785379762
Short name T265
Test name
Test status
Simulation time 13856542733 ps
CPU time 13.36 seconds
Started Sep 11 03:48:08 PM UTC 24
Finished Sep 11 03:48:23 PM UTC 24
Peak memory 200880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785379762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.785379762
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/38.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.4167127116
Short name T262
Test name
Test status
Simulation time 565680562 ps
CPU time 1.65 seconds
Started Sep 11 03:48:04 PM UTC 24
Finished Sep 11 03:48:07 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167127116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4167127116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/38.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.3738119533
Short name T166
Test name
Test status
Simulation time 605466574 ps
CPU time 2.69 seconds
Started Sep 11 03:48:20 PM UTC 24
Finished Sep 11 03:48:24 PM UTC 24
Peak memory 200636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738119533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3738119533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/39.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.1405537240
Short name T286
Test name
Test status
Simulation time 59438632802 ps
CPU time 178.41 seconds
Started Sep 11 03:48:19 PM UTC 24
Finished Sep 11 03:51:20 PM UTC 24
Peak memory 200820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405537240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1405537240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/39.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.3749282150
Short name T264
Test name
Test status
Simulation time 584208167 ps
CPU time 1.32 seconds
Started Sep 11 03:48:17 PM UTC 24
Finished Sep 11 03:48:19 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749282150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3749282150
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/39.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.3338902619
Short name T73
Test name
Test status
Simulation time 27220821515 ps
CPU time 41.4 seconds
Started Sep 11 03:48:21 PM UTC 24
Finished Sep 11 03:49:04 PM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3338902619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 39.aon_timer_stress_all_with_rand_reset.3338902619
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.2240183650
Short name T201
Test name
Test status
Simulation time 40079262560 ps
CPU time 68.28 seconds
Started Sep 11 03:40:32 PM UTC 24
Finished Sep 11 03:41:42 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240183650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2240183650
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.998702466
Short name T21
Test name
Test status
Simulation time 7779003991 ps
CPU time 23.57 seconds
Started Sep 11 03:40:41 PM UTC 24
Finished Sep 11 03:41:06 PM UTC 24
Peak memory 231224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998702466 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.998702466
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.461004611
Short name T76
Test name
Test status
Simulation time 573932432 ps
CPU time 1.31 seconds
Started Sep 11 03:40:29 PM UTC 24
Finished Sep 11 03:40:32 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461004611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.461004611
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/4.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.621483996
Short name T272
Test name
Test status
Simulation time 60511437007 ps
CPU time 35.7 seconds
Started Sep 11 03:48:25 PM UTC 24
Finished Sep 11 03:49:02 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621483996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.621483996
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/40.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.999975170
Short name T266
Test name
Test status
Simulation time 618222573 ps
CPU time 1.27 seconds
Started Sep 11 03:48:25 PM UTC 24
Finished Sep 11 03:48:27 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999975170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.999975170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/40.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.1271851609
Short name T202
Test name
Test status
Simulation time 12817564591 ps
CPU time 49.85 seconds
Started Sep 11 03:48:27 PM UTC 24
Finished Sep 11 03:49:18 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1271851609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 40.aon_timer_stress_all_with_rand_reset.1271851609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.16560935
Short name T268
Test name
Test status
Simulation time 4645051284 ps
CPU time 5.24 seconds
Started Sep 11 03:48:29 PM UTC 24
Finished Sep 11 03:48:35 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16560935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.16560935
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/41.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.3245434754
Short name T267
Test name
Test status
Simulation time 409906033 ps
CPU time 2.24 seconds
Started Sep 11 03:48:29 PM UTC 24
Finished Sep 11 03:48:32 PM UTC 24
Peak memory 200556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245434754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3245434754
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/41.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.351513878
Short name T271
Test name
Test status
Simulation time 40068243996 ps
CPU time 15.96 seconds
Started Sep 11 03:48:44 PM UTC 24
Finished Sep 11 03:49:02 PM UTC 24
Peak memory 200616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351513878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.351513878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/42.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.3116683359
Short name T269
Test name
Test status
Simulation time 555652154 ps
CPU time 2.51 seconds
Started Sep 11 03:48:43 PM UTC 24
Finished Sep 11 03:48:47 PM UTC 24
Peak memory 200552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116683359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3116683359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/42.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.3435375477
Short name T276
Test name
Test status
Simulation time 8993205794 ps
CPU time 17.74 seconds
Started Sep 11 03:48:56 PM UTC 24
Finished Sep 11 03:49:15 PM UTC 24
Peak memory 200692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435375477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3435375477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/43.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.1771904598
Short name T270
Test name
Test status
Simulation time 419393146 ps
CPU time 1.33 seconds
Started Sep 11 03:48:53 PM UTC 24
Finished Sep 11 03:48:55 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771904598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1771904598
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/43.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.358267598
Short name T74
Test name
Test status
Simulation time 1177125381 ps
CPU time 9.08 seconds
Started Sep 11 03:48:57 PM UTC 24
Finished Sep 11 03:49:07 PM UTC 24
Peak memory 214532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=358267598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 43.aon_timer_stress_all_with_rand_reset.358267598
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.1210992485
Short name T275
Test name
Test status
Simulation time 9129594004 ps
CPU time 9.61 seconds
Started Sep 11 03:49:03 PM UTC 24
Finished Sep 11 03:49:14 PM UTC 24
Peak memory 200752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210992485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1210992485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/44.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.3265265877
Short name T273
Test name
Test status
Simulation time 361621406 ps
CPU time 1.91 seconds
Started Sep 11 03:49:02 PM UTC 24
Finished Sep 11 03:49:05 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265265877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3265265877
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/44.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.419515145
Short name T278
Test name
Test status
Simulation time 9628199149 ps
CPU time 10.96 seconds
Started Sep 11 03:49:08 PM UTC 24
Finished Sep 11 03:49:21 PM UTC 24
Peak memory 200752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419515145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.419515145
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/45.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.1104311677
Short name T274
Test name
Test status
Simulation time 603985191 ps
CPU time 0.96 seconds
Started Sep 11 03:49:06 PM UTC 24
Finished Sep 11 03:49:08 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104311677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1104311677
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/45.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.1121816340
Short name T280
Test name
Test status
Simulation time 58745634098 ps
CPU time 8.51 seconds
Started Sep 11 03:49:19 PM UTC 24
Finished Sep 11 03:49:28 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121816340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1121816340
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/46.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.3059959833
Short name T277
Test name
Test status
Simulation time 452606176 ps
CPU time 1.81 seconds
Started Sep 11 03:49:16 PM UTC 24
Finished Sep 11 03:49:18 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059959833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3059959833
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/46.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.282103627
Short name T285
Test name
Test status
Simulation time 27280282430 ps
CPU time 60.09 seconds
Started Sep 11 03:49:26 PM UTC 24
Finished Sep 11 03:50:28 PM UTC 24
Peak memory 200880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282103627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.282103627
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/47.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.3784180003
Short name T279
Test name
Test status
Simulation time 618408351 ps
CPU time 1.1 seconds
Started Sep 11 03:49:23 PM UTC 24
Finished Sep 11 03:49:25 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784180003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3784180003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/47.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.3032532989
Short name T282
Test name
Test status
Simulation time 20464233741 ps
CPU time 6.81 seconds
Started Sep 11 03:49:42 PM UTC 24
Finished Sep 11 03:49:50 PM UTC 24
Peak memory 200580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032532989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3032532989
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/48.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.3428563734
Short name T281
Test name
Test status
Simulation time 390343289 ps
CPU time 2.09 seconds
Started Sep 11 03:49:38 PM UTC 24
Finished Sep 11 03:49:41 PM UTC 24
Peak memory 200752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428563734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3428563734
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/48.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.881318532
Short name T284
Test name
Test status
Simulation time 19900422047 ps
CPU time 15.8 seconds
Started Sep 11 03:49:51 PM UTC 24
Finished Sep 11 03:50:08 PM UTC 24
Peak memory 200880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881318532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.881318532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/49.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.3643867060
Short name T283
Test name
Test status
Simulation time 456678079 ps
CPU time 1.55 seconds
Started Sep 11 03:49:48 PM UTC 24
Finished Sep 11 03:49:50 PM UTC 24
Peak memory 199292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643867060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3643867060
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/49.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.4087769465
Short name T212
Test name
Test status
Simulation time 59692285746 ps
CPU time 95.04 seconds
Started Sep 11 03:40:49 PM UTC 24
Finished Sep 11 03:42:27 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087769465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4087769465
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.3311931009
Short name T67
Test name
Test status
Simulation time 775890348 ps
CPU time 1 seconds
Started Sep 11 03:40:48 PM UTC 24
Finished Sep 11 03:40:50 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311931009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3311931009
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.3295811712
Short name T30
Test name
Test status
Simulation time 3157329353 ps
CPU time 18.94 seconds
Started Sep 11 03:40:55 PM UTC 24
Finished Sep 11 03:41:15 PM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3295811712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 5.aon_timer_stress_all_with_rand_reset.3295811712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.547569025
Short name T213
Test name
Test status
Simulation time 42037989345 ps
CPU time 71.14 seconds
Started Sep 11 03:41:19 PM UTC 24
Finished Sep 11 03:42:32 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547569025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.547569025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.2349994269
Short name T205
Test name
Test status
Simulation time 501718477 ps
CPU time 0.9 seconds
Started Sep 11 03:41:16 PM UTC 24
Finished Sep 11 03:41:18 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349994269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2349994269
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/6.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.3424217728
Short name T42
Test name
Test status
Simulation time 4803888097 ps
CPU time 12.44 seconds
Started Sep 11 03:41:24 PM UTC 24
Finished Sep 11 03:41:38 PM UTC 24
Peak memory 200752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424217728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3424217728
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.3680057768
Short name T206
Test name
Test status
Simulation time 479730664 ps
CPU time 1.44 seconds
Started Sep 11 03:41:23 PM UTC 24
Finished Sep 11 03:41:26 PM UTC 24
Peak memory 199232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680057768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3680057768
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/7.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.2539253430
Short name T196
Test name
Test status
Simulation time 8492360127 ps
CPU time 6.29 seconds
Started Sep 11 03:41:35 PM UTC 24
Finished Sep 11 03:41:42 PM UTC 24
Peak memory 200688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539253430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2539253430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.997174891
Short name T207
Test name
Test status
Simulation time 392028040 ps
CPU time 1.61 seconds
Started Sep 11 03:41:31 PM UTC 24
Finished Sep 11 03:41:33 PM UTC 24
Peak memory 199300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997174891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.997174891
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/8.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.345788597
Short name T197
Test name
Test status
Simulation time 19828107279 ps
CPU time 53.04 seconds
Started Sep 11 03:41:42 PM UTC 24
Finished Sep 11 03:42:37 PM UTC 24
Peak memory 200816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345788597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.345788597
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.3615368061
Short name T208
Test name
Test status
Simulation time 364541454 ps
CPU time 2.06 seconds
Started Sep 11 03:41:39 PM UTC 24
Finished Sep 11 03:41:42 PM UTC 24
Peak memory 200824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615368061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3615368061
Directory /workspaces/repo/scratch/os_regression_2024_09_10/aon_timer-sim-vcs/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%