Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 18740 1 T2 10 T4 11 T6 11
bark[1] 449 1 T29 14 T46 21 T88 21
bark[2] 220 1 T35 21 T33 21 T93 7
bark[3] 407 1 T35 12 T30 21 T47 14
bark[4] 138 1 T101 21 T139 38 T98 30
bark[5] 187 1 T35 21 T30 21 T46 7
bark[6] 639 1 T129 26 T83 95 T100 21
bark[7] 221 1 T91 14 T88 26 T83 26
bark[8] 335 1 T3 14 T154 14 T48 40
bark[9] 229 1 T9 14 T13 14 T120 116
bark[10] 668 1 T32 107 T110 21 T119 21
bark[11] 252 1 T85 5 T83 60 T92 21
bark[12] 127 1 T52 14 T129 33 T88 21
bark[13] 555 1 T48 63 T50 21 T80 89
bark[14] 966 1 T7 14 T25 14 T26 45
bark[15] 364 1 T48 21 T93 21 T88 21
bark[16] 243 1 T1 14 T21 21 T127 14
bark[17] 594 1 T30 58 T48 43 T186 14
bark[18] 97 1 T110 21 T198 5 T149 5
bark[19] 953 1 T180 14 T50 750 T118 21
bark[20] 396 1 T34 21 T96 21 T83 77
bark[21] 482 1 T26 125 T53 14 T93 21
bark[22] 467 1 T26 7 T170 14 T34 21
bark[23] 175 1 T139 32 T124 21 T121 38
bark[24] 276 1 T37 14 T140 14 T110 21
bark[25] 158 1 T30 59 T110 21 T122 31
bark[26] 457 1 T16 14 T33 21 T34 21
bark[27] 133 1 T5 14 T47 21 T129 21
bark[28] 290 1 T39 14 T88 21 T107 21
bark[29] 390 1 T35 56 T47 7 T48 21
bark[30] 136 1 T35 21 T46 19 T164 7
bark[31] 631 1 T21 26 T50 21 T34 21
bark_0 4221 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 18297 1 T2 9 T4 10 T6 10
bite[1] 375 1 T16 13 T48 62 T110 21
bite[2] 429 1 T13 13 T21 21 T35 21
bite[3] 425 1 T5 13 T7 13 T21 25
bite[4] 332 1 T30 4 T82 21 T83 25
bite[5] 464 1 T30 21 T48 42 T80 88
bite[6] 114 1 T30 21 T88 26 T161 46
bite[7] 103 1 T46 18 T48 4 T129 26
bite[8] 970 1 T35 42 T110 47 T101 74
bite[9] 447 1 T26 6 T39 13 T88 21
bite[10] 350 1 T37 13 T46 21 T186 13
bite[11] 273 1 T33 49 T146 26 T85 26
bite[12] 107 1 T82 6 T129 32 T115 21
bite[13] 285 1 T88 42 T139 31 T122 21
bite[14] 562 1 T52 13 T30 21 T170 13
bite[15] 180 1 T180 13 T34 21 T100 26
bite[16] 300 1 T35 55 T49 46 T34 21
bite[17] 127 1 T103 63 T128 13 T105 21
bite[18] 280 1 T173 85 T85 6 T129 21
bite[19] 1202 1 T3 13 T33 21 T50 749
bite[20] 326 1 T46 6 T47 21 T48 42
bite[21] 529 1 T30 21 T48 35 T53 13
bite[22] 244 1 T181 13 T34 21 T146 21
bite[23] 686 1 T48 21 T88 21 T144 26
bite[24] 409 1 T26 124 T30 37 T110 21
bite[25] 289 1 T29 13 T32 21 T83 94
bite[26] 615 1 T1 13 T32 86 T34 21
bite[27] 135 1 T187 13 T119 21 T177 13
bite[28] 353 1 T35 6 T105 250 T147 21
bite[29] 355 1 T154 13 T33 21 T96 21
bite[30] 170 1 T9 13 T25 13 T190 13
bite[31] 175 1 T35 4 T47 13 T110 21
bite_0 4688 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31589 1 T1 21 T2 17 T3 21
auto[1] 3007 1 T4 7 T6 7 T15 7


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 476 1 T30 2 T47 19 T48 19
prescale[1] 431 1 T50 19 T82 36 T83 19
prescale[2] 529 1 T28 2 T146 40 T81 2
prescale[3] 335 1 T18 9 T199 9 T110 23
prescale[4] 1020 1 T35 19 T33 26 T34 46
prescale[5] 220 1 T50 19 T81 2 T198 2
prescale[6] 426 1 T28 2 T46 2 T80 2
prescale[7] 244 1 T200 9 T158 2 T129 19
prescale[8] 291 1 T201 9 T33 19 T50 57
prescale[9] 280 1 T35 26 T48 2 T80 2
prescale[10] 371 1 T49 9 T50 123 T202 9
prescale[11] 432 1 T47 81 T158 2 T198 19
prescale[12] 538 1 T50 21 T93 66 T85 49
prescale[13] 209 1 T26 2 T35 40 T47 2
prescale[14] 220 1 T50 19 T173 23 T158 2
prescale[15] 417 1 T46 2 T203 9 T204 9
prescale[16] 895 1 T19 9 T22 9 T50 109
prescale[17] 319 1 T21 2 T46 2 T33 19
prescale[18] 392 1 T48 2 T50 9 T80 2
prescale[19] 165 1 T27 9 T205 4 T129 23
prescale[20] 745 1 T17 9 T21 69 T33 19
prescale[21] 438 1 T33 23 T96 24 T144 2
prescale[22] 493 1 T49 4 T206 9 T83 2
prescale[23] 370 1 T28 2 T33 23 T173 19
prescale[24] 516 1 T50 49 T96 58 T205 2
prescale[25] 359 1 T32 14 T50 19 T93 70
prescale[26] 544 1 T28 2 T35 2 T50 109
prescale[27] 533 1 T207 9 T208 9 T158 2
prescale[28] 454 1 T35 185 T173 9 T82 2
prescale[29] 449 1 T30 2 T47 19 T33 42
prescale[30] 372 1 T21 2 T35 2 T30 2
prescale[31] 698 1 T48 2 T33 19 T205 2
prescale_0 20415 1 T1 21 T2 17 T3 21


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23181 1 T1 9 T2 17 T3 9
auto[1] 11415 1 T1 12 T3 12 T4 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 34596 1 T1 21 T2 17 T3 21


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 19777 1 T1 1 T2 12 T3 1
wkup[1] 129 1 T9 15 T30 21 T49 21
wkup[2] 296 1 T93 21 T129 21 T88 21
wkup[3] 118 1 T46 20 T92 6 T168 15
wkup[4] 130 1 T50 21 T93 21 T190 15
wkup[5] 101 1 T47 8 T50 21 T86 30
wkup[6] 108 1 T21 6 T107 30 T133 21
wkup[7] 120 1 T30 27 T34 21 T163 15
wkup[8] 165 1 T21 21 T33 21 T83 30
wkup[9] 231 1 T26 21 T129 21 T83 21
wkup[10] 319 1 T21 21 T35 102 T96 21
wkup[11] 175 1 T32 44 T173 21 T133 26
wkup[12] 156 1 T50 21 T107 21 T133 15
wkup[13] 135 1 T26 21 T50 30 T80 21
wkup[14] 214 1 T85 26 T83 21 T183 15
wkup[15] 177 1 T5 15 T28 21 T96 15
wkup[16] 178 1 T33 21 T93 21 T100 26
wkup[17] 215 1 T29 15 T82 21 T143 8
wkup[18] 209 1 T26 21 T30 21 T82 8
wkup[19] 128 1 T189 15 T110 30 T89 15
wkup[20] 181 1 T33 21 T96 21 T101 21
wkup[21] 222 1 T26 15 T161 26 T209 51
wkup[22] 216 1 T21 30 T30 21 T88 21
wkup[23] 176 1 T119 21 T139 21 T133 26
wkup[24] 199 1 T53 15 T186 15 T143 8
wkup[25] 151 1 T46 8 T173 21 T83 8
wkup[26] 137 1 T50 47 T86 21 T124 21
wkup[27] 100 1 T32 26 T100 21 T107 26
wkup[28] 176 1 T129 26 T133 42 T148 30
wkup[29] 120 1 T188 15 T133 63 T126 21
wkup[30] 120 1 T48 27 T158 21 T142 30
wkup[31] 182 1 T50 35 T96 21 T129 21
wkup[32] 246 1 T25 15 T26 8 T37 15
wkup[33] 126 1 T48 21 T110 21 T82 21
wkup[34] 182 1 T7 15 T105 39 T125 21
wkup[35] 253 1 T35 21 T93 29 T82 21
wkup[36] 257 1 T30 35 T173 21 T129 21
wkup[37] 173 1 T35 21 T48 39 T146 21
wkup[38] 270 1 T26 21 T35 21 T80 31
wkup[39] 217 1 T26 21 T32 21 T110 26
wkup[40] 203 1 T35 8 T146 21 T91 15
wkup[41] 116 1 T85 15 T150 15 T104 21
wkup[42] 223 1 T13 15 T48 25 T34 42
wkup[43] 200 1 T50 30 T158 21 T115 21
wkup[44] 299 1 T154 15 T35 21 T32 21
wkup[45] 63 1 T32 21 T82 21 T87 21
wkup[46] 155 1 T35 6 T130 15 T161 16
wkup[47] 133 1 T46 21 T49 21 T181 15
wkup[48] 217 1 T30 15 T88 26 T122 31
wkup[49] 187 1 T32 30 T133 56 T128 15
wkup[50] 232 1 T34 21 T82 21 T144 26
wkup[51] 280 1 T47 21 T180 15 T33 21
wkup[52] 73 1 T146 26 T153 21 T90 26
wkup[53] 177 1 T1 15 T48 21 T127 15
wkup[54] 185 1 T49 21 T107 21 T139 33
wkup[55] 279 1 T35 30 T48 35 T50 68
wkup[56] 222 1 T30 39 T47 15 T48 21
wkup[57] 243 1 T30 21 T170 15 T146 31
wkup[58] 84 1 T110 21 T88 21 T144 21
wkup[59] 125 1 T100 15 T117 15 T112 40
wkup[60] 203 1 T50 21 T96 21 T159 15
wkup[61] 128 1 T16 15 T119 21 T92 21
wkup[62] 284 1 T52 15 T39 15 T30 15
wkup[63] 246 1 T3 15 T30 21 T110 21
wkup_0 3254 1 T1 5 T2 5 T3 5

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