| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.58 | 99.32 | 95.61 | 100.00 | 98.38 | 99.51 | 44.64 |
| T288 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.2075071691 | Sep 18 09:01:38 PM UTC 24 | Sep 18 09:01:40 PM UTC 24 | 495103147 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2718189480 | Sep 18 09:01:39 PM UTC 24 | Sep 18 09:01:41 PM UTC 24 | 317996551 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.2516276176 | Sep 18 09:01:37 PM UTC 24 | Sep 18 09:01:41 PM UTC 24 | 437312199 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.508750294 | Sep 18 09:01:40 PM UTC 24 | Sep 18 09:01:43 PM UTC 24 | 837652629 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.1641422789 | Sep 18 09:01:41 PM UTC 24 | Sep 18 09:01:44 PM UTC 24 | 464935385 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1034747876 | Sep 18 09:01:42 PM UTC 24 | Sep 18 09:01:45 PM UTC 24 | 458312852 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1773821879 | Sep 18 09:01:42 PM UTC 24 | Sep 18 09:01:46 PM UTC 24 | 577445126 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.587499834 | Sep 18 09:01:45 PM UTC 24 | Sep 18 09:01:47 PM UTC 24 | 554508588 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.4065379442 | Sep 18 09:01:43 PM UTC 24 | Sep 18 09:01:47 PM UTC 24 | 675819517 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3104979738 | Sep 18 09:01:46 PM UTC 24 | Sep 18 09:01:49 PM UTC 24 | 320460439 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3862079071 | Sep 18 09:01:42 PM UTC 24 | Sep 18 09:01:49 PM UTC 24 | 2289867547 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2186052981 | Sep 18 09:01:48 PM UTC 24 | Sep 18 09:01:51 PM UTC 24 | 427321429 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2776222052 | Sep 18 09:02:15 PM UTC 24 | Sep 18 09:02:20 PM UTC 24 | 3962681920 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3133001436 | Sep 18 09:01:45 PM UTC 24 | Sep 18 09:01:51 PM UTC 24 | 4203308156 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.1760967848 | Sep 18 09:01:50 PM UTC 24 | Sep 18 09:01:52 PM UTC 24 | 464838224 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2839033605 | Sep 18 09:01:49 PM UTC 24 | Sep 18 09:01:53 PM UTC 24 | 1390413831 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2559558208 | Sep 18 09:01:52 PM UTC 24 | Sep 18 09:01:55 PM UTC 24 | 440747896 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3747332179 | Sep 18 09:01:53 PM UTC 24 | Sep 18 09:01:56 PM UTC 24 | 353640689 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2948448321 | Sep 18 09:01:54 PM UTC 24 | Sep 18 09:01:57 PM UTC 24 | 654615688 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1716551187 | Sep 18 09:01:50 PM UTC 24 | Sep 18 09:01:58 PM UTC 24 | 1214770022 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.4268445027 | Sep 18 09:01:56 PM UTC 24 | Sep 18 09:01:59 PM UTC 24 | 375172097 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3095109629 | Sep 18 09:01:58 PM UTC 24 | Sep 18 09:02:00 PM UTC 24 | 442056866 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.3213046753 | Sep 18 09:01:57 PM UTC 24 | Sep 18 09:02:00 PM UTC 24 | 451076264 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2195517578 | Sep 18 09:01:52 PM UTC 24 | Sep 18 09:02:01 PM UTC 24 | 3242529672 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1334626392 | Sep 18 09:01:59 PM UTC 24 | Sep 18 09:02:01 PM UTC 24 | 344821242 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1844440957 | Sep 18 09:01:59 PM UTC 24 | Sep 18 09:02:03 PM UTC 24 | 1066339752 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3041084019 | Sep 18 09:02:02 PM UTC 24 | Sep 18 09:02:04 PM UTC 24 | 586904107 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1092901988 | Sep 18 09:02:01 PM UTC 24 | Sep 18 09:02:05 PM UTC 24 | 1157550490 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2950374673 | Sep 18 09:01:55 PM UTC 24 | Sep 18 09:02:05 PM UTC 24 | 8335169489 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2680761077 | Sep 18 09:02:01 PM UTC 24 | Sep 18 09:02:05 PM UTC 24 | 484782070 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.805863323 | Sep 18 09:02:03 PM UTC 24 | Sep 18 09:02:05 PM UTC 24 | 288546562 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2254052470 | Sep 18 09:02:02 PM UTC 24 | Sep 18 09:02:05 PM UTC 24 | 687640501 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.1928498612 | Sep 18 09:02:04 PM UTC 24 | Sep 18 09:02:06 PM UTC 24 | 488118137 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3109595614 | Sep 18 09:02:05 PM UTC 24 | Sep 18 09:02:07 PM UTC 24 | 382624061 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4198088985 | Sep 18 09:01:41 PM UTC 24 | Sep 18 09:02:07 PM UTC 24 | 5216508905 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3491727835 | Sep 18 09:02:05 PM UTC 24 | Sep 18 09:02:08 PM UTC 24 | 879478451 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.2354897640 | Sep 18 09:02:06 PM UTC 24 | Sep 18 09:02:08 PM UTC 24 | 504494882 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2014517059 | Sep 18 09:02:06 PM UTC 24 | Sep 18 09:02:08 PM UTC 24 | 544512175 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2483659790 | Sep 18 09:02:06 PM UTC 24 | Sep 18 09:02:08 PM UTC 24 | 433977864 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.3179090534 | Sep 18 09:02:06 PM UTC 24 | Sep 18 09:02:09 PM UTC 24 | 426370975 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.44428067 | Sep 18 09:02:07 PM UTC 24 | Sep 18 09:02:09 PM UTC 24 | 632842555 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3540260461 | Sep 18 09:02:03 PM UTC 24 | Sep 18 09:02:09 PM UTC 24 | 8661585142 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1376702821 | Sep 18 09:02:00 PM UTC 24 | Sep 18 09:02:10 PM UTC 24 | 12479186181 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.429709457 | Sep 18 09:02:08 PM UTC 24 | Sep 18 09:02:10 PM UTC 24 | 458682902 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1711236807 | Sep 18 09:02:09 PM UTC 24 | Sep 18 09:02:11 PM UTC 24 | 1210621602 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.4105085137 | Sep 18 09:02:09 PM UTC 24 | Sep 18 09:02:12 PM UTC 24 | 378782232 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.696167426 | Sep 18 09:02:09 PM UTC 24 | Sep 18 09:02:12 PM UTC 24 | 471891513 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.929958642 | Sep 18 09:02:10 PM UTC 24 | Sep 18 09:02:12 PM UTC 24 | 729372395 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1556278952 | Sep 18 09:02:10 PM UTC 24 | Sep 18 09:02:12 PM UTC 24 | 342843344 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2026662621 | Sep 18 09:02:06 PM UTC 24 | Sep 18 09:02:13 PM UTC 24 | 11115836079 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.181564702 | Sep 18 09:02:11 PM UTC 24 | Sep 18 09:02:13 PM UTC 24 | 435805294 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.290577828 | Sep 18 09:02:11 PM UTC 24 | Sep 18 09:02:13 PM UTC 24 | 473090183 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.776471389 | Sep 18 09:02:11 PM UTC 24 | Sep 18 09:02:13 PM UTC 24 | 292677196 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.4121967769 | Sep 18 09:02:10 PM UTC 24 | Sep 18 09:02:14 PM UTC 24 | 454360956 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2651174726 | Sep 18 09:02:10 PM UTC 24 | Sep 18 09:02:14 PM UTC 24 | 1503127983 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.698662398 | Sep 18 09:02:13 PM UTC 24 | Sep 18 09:02:15 PM UTC 24 | 1061940779 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3067016031 | Sep 18 09:02:11 PM UTC 24 | Sep 18 09:02:15 PM UTC 24 | 2310116135 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.794145386 | Sep 18 09:02:09 PM UTC 24 | Sep 18 09:02:15 PM UTC 24 | 5107934846 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.62194172 | Sep 18 09:02:12 PM UTC 24 | Sep 18 09:02:15 PM UTC 24 | 449753790 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.3885135925 | Sep 18 09:02:13 PM UTC 24 | Sep 18 09:02:15 PM UTC 24 | 453930008 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2584889257 | Sep 18 09:02:14 PM UTC 24 | Sep 18 09:02:16 PM UTC 24 | 419959727 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3399447089 | Sep 18 09:02:12 PM UTC 24 | Sep 18 09:02:16 PM UTC 24 | 471514443 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.4119379709 | Sep 18 09:02:14 PM UTC 24 | Sep 18 09:02:17 PM UTC 24 | 568922901 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.2664993485 | Sep 18 09:02:15 PM UTC 24 | Sep 18 09:02:17 PM UTC 24 | 465025373 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1830698409 | Sep 18 09:02:07 PM UTC 24 | Sep 18 09:02:17 PM UTC 24 | 8798207338 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3375405116 | Sep 18 09:02:15 PM UTC 24 | Sep 18 09:02:17 PM UTC 24 | 419700873 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2352608962 | Sep 18 09:02:10 PM UTC 24 | Sep 18 09:02:18 PM UTC 24 | 8983335261 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.2733165099 | Sep 18 09:02:15 PM UTC 24 | Sep 18 09:02:18 PM UTC 24 | 333241762 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1069982868 | Sep 18 09:02:06 PM UTC 24 | Sep 18 09:02:18 PM UTC 24 | 2627155000 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.3647289671 | Sep 18 09:02:16 PM UTC 24 | Sep 18 09:02:18 PM UTC 24 | 512265130 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.1385374182 | Sep 18 09:02:16 PM UTC 24 | Sep 18 09:02:18 PM UTC 24 | 479393207 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1677721670 | Sep 18 09:02:16 PM UTC 24 | Sep 18 09:02:19 PM UTC 24 | 389495449 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.834403272 | Sep 18 09:02:16 PM UTC 24 | Sep 18 09:02:19 PM UTC 24 | 1261607200 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1017647512 | Sep 18 09:02:12 PM UTC 24 | Sep 18 09:02:19 PM UTC 24 | 8797728438 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.3199012796 | Sep 18 09:02:16 PM UTC 24 | Sep 18 09:02:20 PM UTC 24 | 357687692 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1834319733 | Sep 18 09:02:18 PM UTC 24 | Sep 18 09:02:20 PM UTC 24 | 470845974 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.2737989000 | Sep 18 09:02:18 PM UTC 24 | Sep 18 09:02:20 PM UTC 24 | 453976173 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3110406993 | Sep 18 09:02:18 PM UTC 24 | Sep 18 09:02:20 PM UTC 24 | 1337865142 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.559454537 | Sep 18 09:02:19 PM UTC 24 | Sep 18 09:02:21 PM UTC 24 | 394822318 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.2843188589 | Sep 18 09:02:18 PM UTC 24 | Sep 18 09:02:21 PM UTC 24 | 467435343 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1067026138 | Sep 18 09:02:17 PM UTC 24 | Sep 18 09:02:21 PM UTC 24 | 410676567 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.729650678 | Sep 18 09:02:19 PM UTC 24 | Sep 18 09:02:21 PM UTC 24 | 381856546 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.3499597032 | Sep 18 09:02:19 PM UTC 24 | Sep 18 09:02:22 PM UTC 24 | 410844965 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.898398894 | Sep 18 09:02:20 PM UTC 24 | Sep 18 09:02:22 PM UTC 24 | 410307449 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.3172213979 | Sep 18 09:02:19 PM UTC 24 | Sep 18 09:02:23 PM UTC 24 | 424394807 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3916712391 | Sep 18 09:02:20 PM UTC 24 | Sep 18 09:02:23 PM UTC 24 | 525534024 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.924643648 | Sep 18 09:02:35 PM UTC 24 | Sep 18 09:02:37 PM UTC 24 | 405297308 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.361691525 | Sep 18 09:02:20 PM UTC 24 | Sep 18 09:02:23 PM UTC 24 | 368765360 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.3483617431 | Sep 18 09:02:20 PM UTC 24 | Sep 18 09:02:23 PM UTC 24 | 330692543 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.250787519 | Sep 18 09:02:22 PM UTC 24 | Sep 18 09:02:24 PM UTC 24 | 514535830 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.903867173 | Sep 18 09:02:19 PM UTC 24 | Sep 18 09:02:24 PM UTC 24 | 1604111322 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.446323080 | Sep 18 09:02:22 PM UTC 24 | Sep 18 09:02:24 PM UTC 24 | 435710802 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3633471762 | Sep 18 09:02:22 PM UTC 24 | Sep 18 09:02:24 PM UTC 24 | 553275908 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2030009030 | Sep 18 09:02:20 PM UTC 24 | Sep 18 09:02:24 PM UTC 24 | 1493058318 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.2132818750 | Sep 18 09:02:22 PM UTC 24 | Sep 18 09:02:24 PM UTC 24 | 510551938 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3470157727 | Sep 18 09:02:20 PM UTC 24 | Sep 18 09:02:24 PM UTC 24 | 741491533 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3726087096 | Sep 18 09:02:15 PM UTC 24 | Sep 18 09:02:25 PM UTC 24 | 2354879444 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2580448145 | Sep 18 09:02:20 PM UTC 24 | Sep 18 09:02:25 PM UTC 24 | 9368316261 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.3980606037 | Sep 18 09:02:23 PM UTC 24 | Sep 18 09:02:25 PM UTC 24 | 500208058 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.187759701 | Sep 18 09:02:23 PM UTC 24 | Sep 18 09:02:25 PM UTC 24 | 497142765 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3565232574 | Sep 18 09:02:16 PM UTC 24 | Sep 18 09:02:26 PM UTC 24 | 8630336284 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.2235585476 | Sep 18 09:02:24 PM UTC 24 | Sep 18 09:02:26 PM UTC 24 | 431903997 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2300156390 | Sep 18 09:02:24 PM UTC 24 | Sep 18 09:02:27 PM UTC 24 | 496135400 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2351535969 | Sep 18 09:02:24 PM UTC 24 | Sep 18 09:02:27 PM UTC 24 | 1325717606 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1951957501 | Sep 18 09:02:24 PM UTC 24 | Sep 18 09:02:27 PM UTC 24 | 312468576 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3567329384 | Sep 18 09:02:24 PM UTC 24 | Sep 18 09:02:27 PM UTC 24 | 8833442664 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.3236237371 | Sep 18 09:02:35 PM UTC 24 | Sep 18 09:02:37 PM UTC 24 | 309612065 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.3657389946 | Sep 18 09:02:24 PM UTC 24 | Sep 18 09:02:27 PM UTC 24 | 1642394613 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.156037040 | Sep 18 09:02:25 PM UTC 24 | Sep 18 09:02:28 PM UTC 24 | 481153999 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.3815166094 | Sep 18 09:02:26 PM UTC 24 | Sep 18 09:02:28 PM UTC 24 | 429947368 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.2993263737 | Sep 18 09:02:26 PM UTC 24 | Sep 18 09:02:28 PM UTC 24 | 518712548 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.3092643847 | Sep 18 09:02:25 PM UTC 24 | Sep 18 09:02:28 PM UTC 24 | 289285641 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2328288480 | Sep 18 09:02:22 PM UTC 24 | Sep 18 09:02:28 PM UTC 24 | 1630459583 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3967679608 | Sep 18 09:02:25 PM UTC 24 | Sep 18 09:02:29 PM UTC 24 | 1428352028 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3355243705 | Sep 18 09:02:27 PM UTC 24 | Sep 18 09:02:29 PM UTC 24 | 496605359 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.612051004 | Sep 18 09:02:27 PM UTC 24 | Sep 18 09:02:29 PM UTC 24 | 508796103 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.682712041 | Sep 18 09:02:27 PM UTC 24 | Sep 18 09:02:30 PM UTC 24 | 312380929 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.418186873 | Sep 18 09:02:27 PM UTC 24 | Sep 18 09:02:30 PM UTC 24 | 1565593282 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2285763233 | Sep 18 09:02:28 PM UTC 24 | Sep 18 09:02:30 PM UTC 24 | 413640782 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.1155286709 | Sep 18 09:02:28 PM UTC 24 | Sep 18 09:02:31 PM UTC 24 | 358241679 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.771596944 | Sep 18 09:02:28 PM UTC 24 | Sep 18 09:02:31 PM UTC 24 | 503282116 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.1860465948 | Sep 18 09:02:27 PM UTC 24 | Sep 18 09:02:31 PM UTC 24 | 568741426 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.3772492868 | Sep 18 09:02:28 PM UTC 24 | Sep 18 09:02:32 PM UTC 24 | 545516980 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.1146437388 | Sep 18 09:02:30 PM UTC 24 | Sep 18 09:02:32 PM UTC 24 | 469062039 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1787099615 | Sep 18 09:02:29 PM UTC 24 | Sep 18 09:02:32 PM UTC 24 | 395329109 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3203132647 | Sep 18 09:02:27 PM UTC 24 | Sep 18 09:02:32 PM UTC 24 | 4446695091 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4175991665 | Sep 18 09:02:28 PM UTC 24 | Sep 18 09:02:33 PM UTC 24 | 1279118708 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.1190906675 | Sep 18 09:02:30 PM UTC 24 | Sep 18 09:02:33 PM UTC 24 | 458940878 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.3896762564 | Sep 18 09:02:31 PM UTC 24 | Sep 18 09:02:33 PM UTC 24 | 413580151 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2025781181 | Sep 18 09:02:19 PM UTC 24 | Sep 18 09:02:33 PM UTC 24 | 8092584045 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2913771145 | Sep 18 09:02:26 PM UTC 24 | Sep 18 09:02:33 PM UTC 24 | 8107921703 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1684197948 | Sep 18 09:02:29 PM UTC 24 | Sep 18 09:02:33 PM UTC 24 | 1188273262 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3669386330 | Sep 18 09:02:29 PM UTC 24 | Sep 18 09:02:34 PM UTC 24 | 1522170478 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3361424955 | Sep 18 09:02:31 PM UTC 24 | Sep 18 09:02:34 PM UTC 24 | 470639084 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.712913675 | Sep 18 09:02:28 PM UTC 24 | Sep 18 09:02:34 PM UTC 24 | 8341030087 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3317337163 | Sep 18 09:02:32 PM UTC 24 | Sep 18 09:02:34 PM UTC 24 | 483718353 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.3420096230 | Sep 18 09:02:32 PM UTC 24 | Sep 18 09:02:34 PM UTC 24 | 278423143 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1650528694 | Sep 18 09:02:32 PM UTC 24 | Sep 18 09:02:35 PM UTC 24 | 1194123033 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3267747648 | Sep 18 09:02:32 PM UTC 24 | Sep 18 09:02:35 PM UTC 24 | 387592596 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2362363946 | Sep 18 09:02:32 PM UTC 24 | Sep 18 09:02:35 PM UTC 24 | 449676717 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1690119588 | Sep 18 09:02:30 PM UTC 24 | Sep 18 09:02:35 PM UTC 24 | 2748351395 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.3694085388 | Sep 18 09:02:32 PM UTC 24 | Sep 18 09:02:35 PM UTC 24 | 367123096 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.3555441747 | Sep 18 09:02:32 PM UTC 24 | Sep 18 09:02:36 PM UTC 24 | 488926850 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.3692512043 | Sep 18 09:02:31 PM UTC 24 | Sep 18 09:02:36 PM UTC 24 | 791291617 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1283050549 | Sep 18 09:02:34 PM UTC 24 | Sep 18 09:02:36 PM UTC 24 | 351690260 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.1445453941 | Sep 18 09:02:34 PM UTC 24 | Sep 18 09:02:36 PM UTC 24 | 435035743 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4025186002 | Sep 18 09:02:31 PM UTC 24 | Sep 18 09:02:36 PM UTC 24 | 4252079178 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.830115035 | Sep 18 09:02:34 PM UTC 24 | Sep 18 09:02:36 PM UTC 24 | 448514339 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.4250542524 | Sep 18 09:02:34 PM UTC 24 | Sep 18 09:02:37 PM UTC 24 | 435508811 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.4017565603 | Sep 18 09:02:35 PM UTC 24 | Sep 18 09:02:37 PM UTC 24 | 531836223 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2995642001 | Sep 18 09:02:35 PM UTC 24 | Sep 18 09:02:37 PM UTC 24 | 463978393 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.3267296193 | Sep 18 09:02:35 PM UTC 24 | Sep 18 09:02:37 PM UTC 24 | 353094310 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.4222778917 | Sep 18 09:02:35 PM UTC 24 | Sep 18 09:02:37 PM UTC 24 | 302437523 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.1685341342 | Sep 18 09:02:35 PM UTC 24 | Sep 18 09:02:37 PM UTC 24 | 543347808 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2470696836 | Sep 18 09:02:18 PM UTC 24 | Sep 18 09:02:38 PM UTC 24 | 8701377966 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.4284740856 | Sep 18 09:02:35 PM UTC 24 | Sep 18 09:02:38 PM UTC 24 | 370915912 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.847140595 | Sep 18 09:02:36 PM UTC 24 | Sep 18 09:02:38 PM UTC 24 | 515204602 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.3884860357 | Sep 18 09:02:36 PM UTC 24 | Sep 18 09:02:38 PM UTC 24 | 329419621 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3318798021 | Sep 18 09:02:36 PM UTC 24 | Sep 18 09:02:38 PM UTC 24 | 516637342 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.2852914058 | Sep 18 09:02:36 PM UTC 24 | Sep 18 09:02:39 PM UTC 24 | 331521195 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.1159151111 | Sep 18 09:02:36 PM UTC 24 | Sep 18 09:02:39 PM UTC 24 | 283074360 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.3147790667 | Sep 18 09:02:37 PM UTC 24 | Sep 18 09:02:39 PM UTC 24 | 501538428 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.3360568924 | Sep 18 09:02:37 PM UTC 24 | Sep 18 09:02:39 PM UTC 24 | 315287413 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.3386097599 | Sep 18 09:02:36 PM UTC 24 | Sep 18 09:02:39 PM UTC 24 | 512247478 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.141630528 | Sep 18 09:02:36 PM UTC 24 | Sep 18 09:02:39 PM UTC 24 | 359622306 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1519366500 | Sep 18 09:02:20 PM UTC 24 | Sep 18 09:02:40 PM UTC 24 | 8585202699 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.1391907991 | Sep 18 09:02:38 PM UTC 24 | Sep 18 09:02:40 PM UTC 24 | 337666117 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.239200548 | Sep 18 09:02:38 PM UTC 24 | Sep 18 09:02:40 PM UTC 24 | 354099144 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.490672032 | Sep 18 09:02:38 PM UTC 24 | Sep 18 09:02:40 PM UTC 24 | 488421531 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.2549217178 | Sep 18 09:02:38 PM UTC 24 | Sep 18 09:02:40 PM UTC 24 | 276205631 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3180150735 | Sep 18 09:02:23 PM UTC 24 | Sep 18 09:02:41 PM UTC 24 | 8592175373 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.3673623964 | Sep 18 09:02:38 PM UTC 24 | Sep 18 09:02:41 PM UTC 24 | 438393690 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4123554588 | Sep 18 09:02:30 PM UTC 24 | Sep 18 09:02:46 PM UTC 24 | 8357735101 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.3651577790 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 418137497 ps |
| CPU time | 1.98 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:57:56 PM UTC 24 |
| Peak memory | 205780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651577790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3651577790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.963628979 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3149398042 ps |
| CPU time | 13.73 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:58:08 PM UTC 24 |
| Peak memory | 223024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=963628979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.aon_timer_stress_all_with_rand_reset.963628979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.2718672473 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4136490916 ps |
| CPU time | 29.75 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:58:24 PM UTC 24 |
| Peak memory | 207356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2718672473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.aon_timer_stress_all_with_rand_reset.2718672473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.1641422789 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 464935385 ps |
| CPU time | 2.42 seconds |
| Started | Sep 18 09:01:41 PM UTC 24 |
| Finished | Sep 18 09:01:44 PM UTC 24 |
| Peak memory | 203316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641422789 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1641422789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.3840331823 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 410795384 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 08:57:57 PM UTC 24 |
| Finished | Sep 18 08:57:59 PM UTC 24 |
| Peak memory | 205840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840331823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3840331823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.599930939 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 120995871179 ps |
| CPU time | 45.11 seconds |
| Started | Sep 18 08:58:54 PM UTC 24 |
| Finished | Sep 18 08:59:41 PM UTC 24 |
| Peak memory | 207312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599930939 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.599930939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.938926787 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3867848730 ps |
| CPU time | 2.17 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:57:56 PM UTC 24 |
| Peak memory | 234300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938926787 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.938926787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.710632407 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 45807971046 ps |
| CPU time | 42.47 seconds |
| Started | Sep 18 08:59:40 PM UTC 24 |
| Finished | Sep 18 09:00:23 PM UTC 24 |
| Peak memory | 207436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=710632407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 26.aon_timer_stress_all_with_rand_reset.710632407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.1528187176 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 76078947357 ps |
| CPU time | 65.85 seconds |
| Started | Sep 18 09:01:11 PM UTC 24 |
| Finished | Sep 18 09:02:19 PM UTC 24 |
| Peak memory | 223588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1528187176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 45.aon_timer_stress_all_with_rand_reset.1528187176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.1702141933 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 164392852052 ps |
| CPU time | 42.36 seconds |
| Started | Sep 18 08:58:22 PM UTC 24 |
| Finished | Sep 18 08:59:06 PM UTC 24 |
| Peak memory | 207208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702141933 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.1702141933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.261278171 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 17574292431 ps |
| CPU time | 48.24 seconds |
| Started | Sep 18 08:58:52 PM UTC 24 |
| Finished | Sep 18 08:59:42 PM UTC 24 |
| Peak memory | 207436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=261278171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 19.aon_timer_stress_all_with_rand_reset.261278171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.294237704 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 15987948627 ps |
| CPU time | 29.67 seconds |
| Started | Sep 18 09:01:05 PM UTC 24 |
| Finished | Sep 18 09:01:36 PM UTC 24 |
| Peak memory | 207388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=294237704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 44.aon_timer_stress_all_with_rand_reset.294237704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.1147180822 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 9180964938 ps |
| CPU time | 49.88 seconds |
| Started | Sep 18 09:01:28 PM UTC 24 |
| Finished | Sep 18 09:02:19 PM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1147180822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 48.aon_timer_stress_all_with_rand_reset.1147180822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.1876187910 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 139156838967 ps |
| CPU time | 81.3 seconds |
| Started | Sep 18 09:00:42 PM UTC 24 |
| Finished | Sep 18 09:02:06 PM UTC 24 |
| Peak memory | 207312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876187910 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.1876187910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/38.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.2270203503 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 418813959455 ps |
| CPU time | 763.73 seconds |
| Started | Sep 18 09:00:13 PM UTC 24 |
| Finished | Sep 18 09:13:06 PM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270203503 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.2270203503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/33.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.3800856584 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 9484228555 ps |
| CPU time | 15.75 seconds |
| Started | Sep 18 08:58:25 PM UTC 24 |
| Finished | Sep 18 08:58:42 PM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3800856584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 12.aon_timer_stress_all_with_rand_reset.3800856584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.666109829 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 8158172822 ps |
| CPU time | 21.77 seconds |
| Started | Sep 18 08:59:32 PM UTC 24 |
| Finished | Sep 18 08:59:55 PM UTC 24 |
| Peak memory | 207184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666109829 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.666109829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/25.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.3222257597 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 21742602051 ps |
| CPU time | 4.57 seconds |
| Started | Sep 18 09:01:18 PM UTC 24 |
| Finished | Sep 18 09:01:24 PM UTC 24 |
| Peak memory | 207180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222257597 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.3222257597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/46.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.1140006088 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 245784384643 ps |
| CPU time | 64.65 seconds |
| Started | Sep 18 08:59:46 PM UTC 24 |
| Finished | Sep 18 09:00:52 PM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140006088 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.1140006088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/27.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.723621141 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 85560579474 ps |
| CPU time | 122.37 seconds |
| Started | Sep 18 08:58:39 PM UTC 24 |
| Finished | Sep 18 09:00:44 PM UTC 24 |
| Peak memory | 207184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723621141 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.723621141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.3816584523 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 6054546920 ps |
| CPU time | 31.08 seconds |
| Started | Sep 18 09:00:12 PM UTC 24 |
| Finished | Sep 18 09:00:45 PM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3816584523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 33.aon_timer_stress_all_with_rand_reset.3816584523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.736945146 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4533348409 ps |
| CPU time | 2.38 seconds |
| Started | Sep 18 09:01:37 PM UTC 24 |
| Finished | Sep 18 09:01:40 PM UTC 24 |
| Peak memory | 205800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736945146 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.736945146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.3203521018 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 18111241629 ps |
| CPU time | 51.28 seconds |
| Started | Sep 18 08:59:45 PM UTC 24 |
| Finished | Sep 18 09:00:38 PM UTC 24 |
| Peak memory | 216384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3203521018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 27.aon_timer_stress_all_with_rand_reset.3203521018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.643432561 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 125260938078 ps |
| CPU time | 57.63 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:58:52 PM UTC 24 |
| Peak memory | 207116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643432561 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.643432561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.3639310712 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 252883555875 ps |
| CPU time | 96.8 seconds |
| Started | Sep 18 08:58:59 PM UTC 24 |
| Finished | Sep 18 09:00:37 PM UTC 24 |
| Peak memory | 207280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639310712 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.3639310712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/20.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.1210855379 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 26544926980 ps |
| CPU time | 61.03 seconds |
| Started | Sep 18 09:00:58 PM UTC 24 |
| Finished | Sep 18 09:02:01 PM UTC 24 |
| Peak memory | 223760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1210855379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 42.aon_timer_stress_all_with_rand_reset.1210855379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.3503984337 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 162838210935 ps |
| CPU time | 92.87 seconds |
| Started | Sep 18 08:58:04 PM UTC 24 |
| Finished | Sep 18 08:59:39 PM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503984337 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.3503984337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.3464459550 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 142974068981 ps |
| CPU time | 95.33 seconds |
| Started | Sep 18 09:00:24 PM UTC 24 |
| Finished | Sep 18 09:02:02 PM UTC 24 |
| Peak memory | 207284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464459550 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.3464459550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/35.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.2336780745 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 37748375515 ps |
| CPU time | 35.85 seconds |
| Started | Sep 18 09:00:40 PM UTC 24 |
| Finished | Sep 18 09:01:18 PM UTC 24 |
| Peak memory | 222396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2336780745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 38.aon_timer_stress_all_with_rand_reset.2336780745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.241792547 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 72631758293 ps |
| CPU time | 117.94 seconds |
| Started | Sep 18 08:57:58 PM UTC 24 |
| Finished | Sep 18 08:59:58 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241792547 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.241792547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.3499578926 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 287361135221 ps |
| CPU time | 144.61 seconds |
| Started | Sep 18 08:59:49 PM UTC 24 |
| Finished | Sep 18 09:02:16 PM UTC 24 |
| Peak memory | 207248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499578926 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.3499578926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/28.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.259223816 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 152389259285 ps |
| CPU time | 112.46 seconds |
| Started | Sep 18 09:00:55 PM UTC 24 |
| Finished | Sep 18 09:02:50 PM UTC 24 |
| Peak memory | 207184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259223816 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.259223816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/41.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.686711367 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 53195296292 ps |
| CPU time | 54.02 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:58:49 PM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686711367 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.686711367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.1978413083 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 122010034003 ps |
| CPU time | 38.55 seconds |
| Started | Sep 18 08:58:09 PM UTC 24 |
| Finished | Sep 18 08:58:48 PM UTC 24 |
| Peak memory | 207184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978413083 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.1978413083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.4243013630 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 136952562455 ps |
| CPU time | 249.97 seconds |
| Started | Sep 18 08:58:31 PM UTC 24 |
| Finished | Sep 18 09:02:46 PM UTC 24 |
| Peak memory | 207184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243013630 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.4243013630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.2192039381 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7273935829 ps |
| CPU time | 25.38 seconds |
| Started | Sep 18 08:57:54 PM UTC 24 |
| Finished | Sep 18 08:58:21 PM UTC 24 |
| Peak memory | 207400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2192039381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 3.aon_timer_stress_all_with_rand_reset.2192039381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.2563099787 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 100438824441 ps |
| CPU time | 105.55 seconds |
| Started | Sep 18 08:58:00 PM UTC 24 |
| Finished | Sep 18 08:59:48 PM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563099787 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.2563099787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.835819688 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2982123442 ps |
| CPU time | 26.24 seconds |
| Started | Sep 18 08:58:03 PM UTC 24 |
| Finished | Sep 18 08:58:30 PM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=835819688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 6.aon_timer_stress_all_with_rand_reset.835819688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.2041846696 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 504869739 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 08:57:51 PM UTC 24 |
| Finished | Sep 18 08:57:54 PM UTC 24 |
| Peak memory | 205124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041846696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2041846696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.1888235011 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 109326361000 ps |
| CPU time | 108.71 seconds |
| Started | Sep 18 08:59:03 PM UTC 24 |
| Finished | Sep 18 09:00:54 PM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888235011 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.1888235011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/21.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.3935864701 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 13796699769 ps |
| CPU time | 21.13 seconds |
| Started | Sep 18 08:59:57 PM UTC 24 |
| Finished | Sep 18 09:00:19 PM UTC 24 |
| Peak memory | 216244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3935864701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 30.aon_timer_stress_all_with_rand_reset.3935864701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.424922992 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 140136242609 ps |
| CPU time | 24.8 seconds |
| Started | Sep 18 09:00:36 PM UTC 24 |
| Finished | Sep 18 09:01:02 PM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424922992 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.424922992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/37.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.536511933 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1339565703 ps |
| CPU time | 11.14 seconds |
| Started | Sep 18 09:00:45 PM UTC 24 |
| Finished | Sep 18 09:00:58 PM UTC 24 |
| Peak memory | 216156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=536511933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.aon_timer_stress_all_with_rand_reset.536511933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.3466753061 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 112944638900 ps |
| CPU time | 174.7 seconds |
| Started | Sep 18 08:58:36 PM UTC 24 |
| Finished | Sep 18 09:01:33 PM UTC 24 |
| Peak memory | 207244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466753061 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.3466753061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.1893183157 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 43081417392 ps |
| CPU time | 91.24 seconds |
| Started | Sep 18 08:59:27 PM UTC 24 |
| Finished | Sep 18 09:01:00 PM UTC 24 |
| Peak memory | 207248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893183157 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.1893183157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/24.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.3274238441 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4569480415 ps |
| CPU time | 48.45 seconds |
| Started | Sep 18 09:00:28 PM UTC 24 |
| Finished | Sep 18 09:01:19 PM UTC 24 |
| Peak memory | 207436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3274238441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 36.aon_timer_stress_all_with_rand_reset.3274238441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.2802429627 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 12561427010 ps |
| CPU time | 24.47 seconds |
| Started | Sep 18 09:00:35 PM UTC 24 |
| Finished | Sep 18 09:01:00 PM UTC 24 |
| Peak memory | 222984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2802429627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 37.aon_timer_stress_all_with_rand_reset.2802429627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.1191888542 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1957838705 ps |
| CPU time | 13.04 seconds |
| Started | Sep 18 08:57:58 PM UTC 24 |
| Finished | Sep 18 08:58:12 PM UTC 24 |
| Peak memory | 223012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1191888542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 4.aon_timer_stress_all_with_rand_reset.1191888542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.2107412440 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 35549090905 ps |
| CPU time | 70.48 seconds |
| Started | Sep 18 09:01:25 PM UTC 24 |
| Finished | Sep 18 09:02:37 PM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107412440 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.2107412440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/47.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.2375864349 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 12888125433 ps |
| CPU time | 36.18 seconds |
| Started | Sep 18 08:58:50 PM UTC 24 |
| Finished | Sep 18 08:59:28 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2375864349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 18.aon_timer_stress_all_with_rand_reset.2375864349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.2462611882 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 17161595530 ps |
| CPU time | 32.45 seconds |
| Started | Sep 18 09:00:08 PM UTC 24 |
| Finished | Sep 18 09:00:42 PM UTC 24 |
| Peak memory | 207088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462611882 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.2462611882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/31.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.1023128956 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 849672859771 ps |
| CPU time | 1423.39 seconds |
| Started | Sep 18 09:01:30 PM UTC 24 |
| Finished | Sep 18 09:25:28 PM UTC 24 |
| Peak memory | 207116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023128956 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.1023128956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/48.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.3313439479 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 231767375125 ps |
| CPU time | 31.51 seconds |
| Started | Sep 18 08:58:06 PM UTC 24 |
| Finished | Sep 18 08:58:39 PM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313439479 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.3313439479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.3963151884 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2763550240 ps |
| CPU time | 17.11 seconds |
| Started | Sep 18 09:01:17 PM UTC 24 |
| Finished | Sep 18 09:01:36 PM UTC 24 |
| Peak memory | 207400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3963151884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 46.aon_timer_stress_all_with_rand_reset.3963151884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.2729541005 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 326311966650 ps |
| CPU time | 545.68 seconds |
| Started | Sep 18 08:58:13 PM UTC 24 |
| Finished | Sep 18 09:07:25 PM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729541005 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.2729541005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3862079071 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2289867547 ps |
| CPU time | 5.79 seconds |
| Started | Sep 18 09:01:42 PM UTC 24 |
| Finished | Sep 18 09:01:49 PM UTC 24 |
| Peak memory | 205552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862079071 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.3862079071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.1173968800 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 46200347660 ps |
| CPU time | 72.64 seconds |
| Started | Sep 18 09:01:01 PM UTC 24 |
| Finished | Sep 18 09:02:16 PM UTC 24 |
| Peak memory | 207176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173968800 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.1173968800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/43.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.310154344 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 92516047194 ps |
| CPU time | 126.98 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 09:00:02 PM UTC 24 |
| Peak memory | 207136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310154344 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.310154344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.826940532 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 343829773521 ps |
| CPU time | 524.92 seconds |
| Started | Sep 18 08:58:46 PM UTC 24 |
| Finished | Sep 18 09:07:37 PM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826940532 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.826940532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.525671206 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9378119221 ps |
| CPU time | 36.21 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:58:31 PM UTC 24 |
| Peak memory | 222904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=525671206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.aon_timer_stress_all_with_rand_reset.525671206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.1946719901 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 82952788929 ps |
| CPU time | 47.16 seconds |
| Started | Sep 18 08:59:58 PM UTC 24 |
| Finished | Sep 18 09:00:47 PM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946719901 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.1946719901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/30.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.1525005688 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 261396891619 ps |
| CPU time | 206.86 seconds |
| Started | Sep 18 09:00:30 PM UTC 24 |
| Finished | Sep 18 09:04:00 PM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525005688 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.1525005688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/36.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.3295569504 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 339165320584 ps |
| CPU time | 589.02 seconds |
| Started | Sep 18 09:00:51 PM UTC 24 |
| Finished | Sep 18 09:10:46 PM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295569504 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.3295569504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/40.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.3265065034 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2066555310 ps |
| CPU time | 12.63 seconds |
| Started | Sep 18 08:58:11 PM UTC 24 |
| Finished | Sep 18 08:58:24 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3265065034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.aon_timer_stress_all_with_rand_reset.3265065034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.1796144502 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 337739031872 ps |
| CPU time | 82.65 seconds |
| Started | Sep 18 08:58:25 PM UTC 24 |
| Finished | Sep 18 08:59:50 PM UTC 24 |
| Peak memory | 207252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796144502 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.1796144502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.753737068 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 478242463 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 08:58:41 PM UTC 24 |
| Finished | Sep 18 08:58:44 PM UTC 24 |
| Peak memory | 205780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753737068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.753737068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.631356748 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 60898696145 ps |
| CPU time | 99.09 seconds |
| Started | Sep 18 08:58:50 PM UTC 24 |
| Finished | Sep 18 09:00:31 PM UTC 24 |
| Peak memory | 207312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631356748 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.631356748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.3887188547 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 11888778991 ps |
| CPU time | 23.22 seconds |
| Started | Sep 18 09:00:49 PM UTC 24 |
| Finished | Sep 18 09:01:14 PM UTC 24 |
| Peak memory | 223352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3887188547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 40.aon_timer_stress_all_with_rand_reset.3887188547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.4044203644 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 611360609 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 09:01:01 PM UTC 24 |
| Finished | Sep 18 09:01:04 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044203644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4044203644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/43.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.3731915866 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 540877573 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 09:01:32 PM UTC 24 |
| Finished | Sep 18 09:01:36 PM UTC 24 |
| Peak memory | 205308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731915866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3731915866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/49.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.1016592709 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 493498568 ps |
| CPU time | 0.96 seconds |
| Started | Sep 18 08:57:59 PM UTC 24 |
| Finished | Sep 18 08:58:01 PM UTC 24 |
| Peak memory | 205368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016592709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1016592709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.920167077 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 196503808262 ps |
| CPU time | 296.26 seconds |
| Started | Sep 18 08:58:42 PM UTC 24 |
| Finished | Sep 18 09:03:43 PM UTC 24 |
| Peak memory | 207184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920167077 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.920167077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.274993288 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 3273174305 ps |
| CPU time | 42.17 seconds |
| Started | Sep 18 08:58:41 PM UTC 24 |
| Finished | Sep 18 08:59:25 PM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=274993288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.aon_timer_stress_all_with_rand_reset.274993288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.445147589 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 500833747 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 08:58:49 PM UTC 24 |
| Finished | Sep 18 08:58:51 PM UTC 24 |
| Peak memory | 205364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445147589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.445147589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.1474499704 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 490693987 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 08:58:52 PM UTC 24 |
| Finished | Sep 18 08:58:55 PM UTC 24 |
| Peak memory | 205780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474499704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1474499704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.899843493 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2828237371 ps |
| CPU time | 2.93 seconds |
| Started | Sep 18 08:59:55 PM UTC 24 |
| Finished | Sep 18 08:59:59 PM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899843493 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.899843493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/29.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.1281447089 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 424836354 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 09:00:40 PM UTC 24 |
| Finished | Sep 18 09:00:43 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281447089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1281447089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/38.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.894605888 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3055608965 ps |
| CPU time | 20.73 seconds |
| Started | Sep 18 08:58:31 PM UTC 24 |
| Finished | Sep 18 08:58:54 PM UTC 24 |
| Peak memory | 207456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=894605888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.aon_timer_stress_all_with_rand_reset.894605888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.1021147644 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5918739376 ps |
| CPU time | 31.74 seconds |
| Started | Sep 18 08:58:45 PM UTC 24 |
| Finished | Sep 18 08:59:18 PM UTC 24 |
| Peak memory | 222968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1021147644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 17.aon_timer_stress_all_with_rand_reset.1021147644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.2297058397 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2844600622 ps |
| CPU time | 18.29 seconds |
| Started | Sep 18 08:59:31 PM UTC 24 |
| Finished | Sep 18 08:59:51 PM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2297058397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 25.aon_timer_stress_all_with_rand_reset.2297058397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.3811358307 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 404284456 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 09:00:23 PM UTC 24 |
| Finished | Sep 18 09:00:26 PM UTC 24 |
| Peak memory | 205780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811358307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3811358307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/35.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.656880764 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 359010218 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 09:00:32 PM UTC 24 |
| Finished | Sep 18 09:00:35 PM UTC 24 |
| Peak memory | 205780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656880764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.656880764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/37.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.1817013120 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 491973952 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 09:01:10 PM UTC 24 |
| Finished | Sep 18 09:01:12 PM UTC 24 |
| Peak memory | 205364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817013120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1817013120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/45.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.3012356202 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 154559871061 ps |
| CPU time | 56.41 seconds |
| Started | Sep 18 09:01:12 PM UTC 24 |
| Finished | Sep 18 09:02:10 PM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012356202 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.3012356202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/45.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.269245215 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 510184776 ps |
| CPU time | 2.5 seconds |
| Started | Sep 18 08:58:14 PM UTC 24 |
| Finished | Sep 18 08:58:18 PM UTC 24 |
| Peak memory | 205452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269245215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.269245215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.1729684611 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3368222579 ps |
| CPU time | 19.02 seconds |
| Started | Sep 18 08:58:15 PM UTC 24 |
| Finished | Sep 18 08:58:35 PM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1729684611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 10.aon_timer_stress_all_with_rand_reset.1729684611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.2292980453 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 544200253 ps |
| CPU time | 1.73 seconds |
| Started | Sep 18 08:58:29 PM UTC 24 |
| Finished | Sep 18 08:58:32 PM UTC 24 |
| Peak memory | 205364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292980453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2292980453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.1114411257 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 432807447 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 08:59:44 PM UTC 24 |
| Finished | Sep 18 08:59:46 PM UTC 24 |
| Peak memory | 205780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114411257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1114411257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/27.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.2889882425 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 274437957972 ps |
| CPU time | 63.87 seconds |
| Started | Sep 18 08:57:55 PM UTC 24 |
| Finished | Sep 18 08:59:01 PM UTC 24 |
| Peak memory | 207312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889882425 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.2889882425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.979589189 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4578770264 ps |
| CPU time | 9.05 seconds |
| Started | Sep 18 09:00:08 PM UTC 24 |
| Finished | Sep 18 09:00:19 PM UTC 24 |
| Peak memory | 207248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979589189 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.979589189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/32.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.419088735 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 602157533774 ps |
| CPU time | 1131.67 seconds |
| Started | Sep 18 09:00:46 PM UTC 24 |
| Finished | Sep 18 09:19:51 PM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419088735 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.419088735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/39.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.3287744941 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 360155588 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 08:58:10 PM UTC 24 |
| Finished | Sep 18 08:58:12 PM UTC 24 |
| Peak memory | 205840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287744941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3287744941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.1066127173 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 172857610726 ps |
| CPU time | 264.44 seconds |
| Started | Sep 18 08:59:10 PM UTC 24 |
| Finished | Sep 18 09:03:39 PM UTC 24 |
| Peak memory | 207116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066127173 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.1066127173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/22.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.1395935626 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 368264231 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 08:59:57 PM UTC 24 |
| Finished | Sep 18 08:59:59 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395935626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1395935626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/30.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.4261989112 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 52428297455 ps |
| CPU time | 20.92 seconds |
| Started | Sep 18 08:58:16 PM UTC 24 |
| Finished | Sep 18 08:58:38 PM UTC 24 |
| Peak memory | 207252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261989112 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.4261989112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.2245033695 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 379617003176 ps |
| CPU time | 100.29 seconds |
| Started | Sep 18 09:00:21 PM UTC 24 |
| Finished | Sep 18 09:02:04 PM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245033695 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.2245033695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/34.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.4265456682 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1137575571 ps |
| CPU time | 7.05 seconds |
| Started | Sep 18 09:00:21 PM UTC 24 |
| Finished | Sep 18 09:00:29 PM UTC 24 |
| Peak memory | 216296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4265456682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 34.aon_timer_stress_all_with_rand_reset.4265456682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.2218952837 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 142549349312 ps |
| CPU time | 36.63 seconds |
| Started | Sep 18 09:00:59 PM UTC 24 |
| Finished | Sep 18 09:01:37 PM UTC 24 |
| Peak memory | 207116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218952837 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.2218952837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/42.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.2977053837 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3742934972 ps |
| CPU time | 24 seconds |
| Started | Sep 18 09:01:33 PM UTC 24 |
| Finished | Sep 18 09:01:59 PM UTC 24 |
| Peak memory | 207588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2977053837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 49.aon_timer_stress_all_with_rand_reset.2977053837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.1001902827 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 506308260 ps |
| CPU time | 1.85 seconds |
| Started | Sep 18 08:58:03 PM UTC 24 |
| Finished | Sep 18 08:58:05 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001902827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1001902827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.2733139431 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 12974640956 ps |
| CPU time | 35.69 seconds |
| Started | Sep 18 08:58:06 PM UTC 24 |
| Finished | Sep 18 08:58:43 PM UTC 24 |
| Peak memory | 216252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2733139431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 7.aon_timer_stress_all_with_rand_reset.2733139431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.464583178 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 422748042 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 08:58:07 PM UTC 24 |
| Finished | Sep 18 08:58:10 PM UTC 24 |
| Peak memory | 205780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464583178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.464583178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.1139763956 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 566651714 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:57:55 PM UTC 24 |
| Peak memory | 205836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139763956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1139763956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.3031050360 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 574525877 ps |
| CPU time | 2.46 seconds |
| Started | Sep 18 08:59:06 PM UTC 24 |
| Finished | Sep 18 08:59:10 PM UTC 24 |
| Peak memory | 205316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031050360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3031050360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/22.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.3055218293 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 599850168888 ps |
| CPU time | 1160.2 seconds |
| Started | Sep 18 08:59:24 PM UTC 24 |
| Finished | Sep 18 09:18:56 PM UTC 24 |
| Peak memory | 207308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055218293 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.3055218293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/23.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.2422618534 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 444618633 ps |
| CPU time | 1.62 seconds |
| Started | Sep 18 08:59:29 PM UTC 24 |
| Finished | Sep 18 08:59:32 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422618534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2422618534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/25.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.1759821221 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 505985064 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 08:59:47 PM UTC 24 |
| Finished | Sep 18 08:59:49 PM UTC 24 |
| Peak memory | 205364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759821221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1759821221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/28.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.199038075 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 550155505 ps |
| CPU time | 1.66 seconds |
| Started | Sep 18 08:59:52 PM UTC 24 |
| Finished | Sep 18 08:59:54 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199038075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.199038075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/29.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.641025600 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 573267828 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 09:00:28 PM UTC 24 |
| Finished | Sep 18 09:00:31 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641025600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.641025600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/36.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.3204700349 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 602557931 ps |
| CPU time | 1.72 seconds |
| Started | Sep 18 09:00:44 PM UTC 24 |
| Finished | Sep 18 09:00:47 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204700349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3204700349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/39.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.4170981042 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 532095324 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 09:00:57 PM UTC 24 |
| Finished | Sep 18 09:01:00 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170981042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.4170981042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/42.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.2988405889 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 207836381774 ps |
| CPU time | 30.97 seconds |
| Started | Sep 18 09:01:06 PM UTC 24 |
| Finished | Sep 18 09:01:38 PM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988405889 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.2988405889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/44.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.880545844 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 407080640 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 09:01:16 PM UTC 24 |
| Finished | Sep 18 09:01:18 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880545844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.880545844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/46.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3540260461 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 8661585142 ps |
| CPU time | 5.7 seconds |
| Started | Sep 18 09:02:03 PM UTC 24 |
| Finished | Sep 18 09:02:09 PM UTC 24 |
| Peak memory | 207132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540260461 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.3540260461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.978309871 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 555555414 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 08:58:18 PM UTC 24 |
| Finished | Sep 18 08:58:21 PM UTC 24 |
| Peak memory | 203828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978309871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.978309871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.634723233 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2636207481 ps |
| CPU time | 21.15 seconds |
| Started | Sep 18 08:58:39 PM UTC 24 |
| Finished | Sep 18 08:59:02 PM UTC 24 |
| Peak memory | 207460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=634723233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.aon_timer_stress_all_with_rand_reset.634723233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.3795074529 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 635127411 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 08:58:57 PM UTC 24 |
| Finished | Sep 18 08:58:59 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795074529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3795074529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/20.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.3053806136 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 593716003 ps |
| CPU time | 1.71 seconds |
| Started | Sep 18 08:59:02 PM UTC 24 |
| Finished | Sep 18 08:59:05 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053806136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3053806136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/21.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.3376207751 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 513043777 ps |
| CPU time | 2.7 seconds |
| Started | Sep 18 08:59:23 PM UTC 24 |
| Finished | Sep 18 08:59:26 PM UTC 24 |
| Peak memory | 205372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376207751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3376207751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/23.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.3201837967 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 532220639 ps |
| CPU time | 0.94 seconds |
| Started | Sep 18 08:59:36 PM UTC 24 |
| Finished | Sep 18 08:59:38 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201837967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3201837967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/26.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.1972374965 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2240716412 ps |
| CPU time | 6.87 seconds |
| Started | Sep 18 08:59:49 PM UTC 24 |
| Finished | Sep 18 08:59:57 PM UTC 24 |
| Peak memory | 223164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1972374965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 28.aon_timer_stress_all_with_rand_reset.1972374965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.1156846686 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 510322283 ps |
| CPU time | 1 seconds |
| Started | Sep 18 09:00:00 PM UTC 24 |
| Finished | Sep 18 09:00:07 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156846686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1156846686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/31.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.1911314982 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2528749350 ps |
| CPU time | 31.25 seconds |
| Started | Sep 18 09:00:08 PM UTC 24 |
| Finished | Sep 18 09:00:41 PM UTC 24 |
| Peak memory | 223380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1911314982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 32.aon_timer_stress_all_with_rand_reset.1911314982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.3196758674 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 395296551 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 09:00:12 PM UTC 24 |
| Finished | Sep 18 09:00:15 PM UTC 24 |
| Peak memory | 205484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196758674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3196758674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/33.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.471239714 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 638426346 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 09:00:54 PM UTC 24 |
| Finished | Sep 18 09:00:56 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471239714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.471239714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/41.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.3623310087 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 3027099934 ps |
| CPU time | 28.63 seconds |
| Started | Sep 18 09:01:01 PM UTC 24 |
| Finished | Sep 18 09:01:31 PM UTC 24 |
| Peak memory | 207300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3623310087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 43.aon_timer_stress_all_with_rand_reset.3623310087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.1224967779 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 498948590 ps |
| CPU time | 2.46 seconds |
| Started | Sep 18 09:01:23 PM UTC 24 |
| Finished | Sep 18 09:01:26 PM UTC 24 |
| Peak memory | 205500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224967779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1224967779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/47.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.930559000 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3319758901 ps |
| CPU time | 15.56 seconds |
| Started | Sep 18 08:58:00 PM UTC 24 |
| Finished | Sep 18 08:58:17 PM UTC 24 |
| Peak memory | 222956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=930559000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.aon_timer_stress_all_with_rand_reset.930559000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.3109493889 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 344927616 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 08:58:06 PM UTC 24 |
| Finished | Sep 18 08:58:08 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109493889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3109493889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1519366500 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 8585202699 ps |
| CPU time | 18.57 seconds |
| Started | Sep 18 09:02:20 PM UTC 24 |
| Finished | Sep 18 09:02:40 PM UTC 24 |
| Peak memory | 207048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519366500 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.1519366500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.3703626947 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 461518791 ps |
| CPU time | 0.92 seconds |
| Started | Sep 18 08:58:34 PM UTC 24 |
| Finished | Sep 18 08:58:36 PM UTC 24 |
| Peak memory | 205308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703626947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3703626947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.2398802690 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 502181737 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 08:58:45 PM UTC 24 |
| Finished | Sep 18 08:58:47 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398802690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2398802690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.1081985605 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 421640748 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:57:55 PM UTC 24 |
| Peak memory | 205840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081985605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1081985605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.453260060 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 549321237 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 08:59:26 PM UTC 24 |
| Finished | Sep 18 08:59:28 PM UTC 24 |
| Peak memory | 205484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453260060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.453260060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/24.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.128195691 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 624269470 ps |
| CPU time | 1.79 seconds |
| Started | Sep 18 08:57:54 PM UTC 24 |
| Finished | Sep 18 08:57:57 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128195691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.128195691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.966891949 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 537472804 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 09:00:08 PM UTC 24 |
| Finished | Sep 18 09:00:11 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966891949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.966891949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/32.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.820678396 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 484634100 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 09:00:19 PM UTC 24 |
| Finished | Sep 18 09:00:23 PM UTC 24 |
| Peak memory | 205364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820678396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.820678396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/34.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.4046002326 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 11513769417 ps |
| CPU time | 38.23 seconds |
| Started | Sep 18 09:00:24 PM UTC 24 |
| Finished | Sep 18 09:01:04 PM UTC 24 |
| Peak memory | 207492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4046002326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 35.aon_timer_stress_all_with_rand_reset.4046002326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.938278871 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 517259419 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 09:00:48 PM UTC 24 |
| Finished | Sep 18 09:00:51 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938278871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.938278871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/40.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.2678620745 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 618174457 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 09:01:05 PM UTC 24 |
| Finished | Sep 18 09:01:07 PM UTC 24 |
| Peak memory | 205364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678620745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2678620745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/44.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.884133303 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 228667081020 ps |
| CPU time | 69.91 seconds |
| Started | Sep 18 09:01:34 PM UTC 24 |
| Finished | Sep 18 09:02:46 PM UTC 24 |
| Peak memory | 207184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884133303 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.884133303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/49.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1773821879 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 577445126 ps |
| CPU time | 2.8 seconds |
| Started | Sep 18 09:01:42 PM UTC 24 |
| Finished | Sep 18 09:01:46 PM UTC 24 |
| Peak memory | 203256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773821879 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.1773821879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4198088985 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 5216508905 ps |
| CPU time | 25.09 seconds |
| Started | Sep 18 09:01:41 PM UTC 24 |
| Finished | Sep 18 09:02:07 PM UTC 24 |
| Peak memory | 205648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198088985 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.4198088985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.508750294 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 837652629 ps |
| CPU time | 1.66 seconds |
| Started | Sep 18 09:01:40 PM UTC 24 |
| Finished | Sep 18 09:01:43 PM UTC 24 |
| Peak memory | 199904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508750294 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.508750294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1034747876 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 458312852 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 09:01:42 PM UTC 24 |
| Finished | Sep 18 09:01:45 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1034747876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim er_csr_mem_rw_with_rand_reset.1034747876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.4015019123 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 370844521 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 09:01:37 PM UTC 24 |
| Finished | Sep 18 09:01:39 PM UTC 24 |
| Peak memory | 202656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015019123 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4015019123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2718189480 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 317996551 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 09:01:39 PM UTC 24 |
| Finished | Sep 18 09:01:41 PM UTC 24 |
| Peak memory | 199912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718189480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.2718189480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.2075071691 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 495103147 ps |
| CPU time | 1.61 seconds |
| Started | Sep 18 09:01:38 PM UTC 24 |
| Finished | Sep 18 09:01:40 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075071691 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.2075071691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.2516276176 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 437312199 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 09:01:37 PM UTC 24 |
| Finished | Sep 18 09:01:41 PM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516276176 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2516276176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2559558208 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 440747896 ps |
| CPU time | 2.41 seconds |
| Started | Sep 18 09:01:52 PM UTC 24 |
| Finished | Sep 18 09:01:55 PM UTC 24 |
| Peak memory | 203188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559558208 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.2559558208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1716551187 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1214770022 ps |
| CPU time | 7.17 seconds |
| Started | Sep 18 09:01:50 PM UTC 24 |
| Finished | Sep 18 09:01:58 PM UTC 24 |
| Peak memory | 205588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716551187 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.1716551187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2839033605 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1390413831 ps |
| CPU time | 3.16 seconds |
| Started | Sep 18 09:01:49 PM UTC 24 |
| Finished | Sep 18 09:01:53 PM UTC 24 |
| Peak memory | 203248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839033605 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.2839033605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3747332179 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 353640689 ps |
| CPU time | 2.1 seconds |
| Started | Sep 18 09:01:53 PM UTC 24 |
| Finished | Sep 18 09:01:56 PM UTC 24 |
| Peak memory | 205556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3747332179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim er_csr_mem_rw_with_rand_reset.3747332179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.1760967848 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 464838224 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 09:01:50 PM UTC 24 |
| Finished | Sep 18 09:01:52 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760967848 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1760967848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.587499834 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 554508588 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 09:01:45 PM UTC 24 |
| Finished | Sep 18 09:01:47 PM UTC 24 |
| Peak memory | 199492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587499834 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.587499834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2186052981 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 427321429 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 09:01:48 PM UTC 24 |
| Finished | Sep 18 09:01:51 PM UTC 24 |
| Peak memory | 199912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186052981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.2186052981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3104979738 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 320460439 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 09:01:46 PM UTC 24 |
| Finished | Sep 18 09:01:49 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104979738 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.3104979738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2195517578 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3242529672 ps |
| CPU time | 8.08 seconds |
| Started | Sep 18 09:01:52 PM UTC 24 |
| Finished | Sep 18 09:02:01 PM UTC 24 |
| Peak memory | 205488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195517578 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.2195517578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.4065379442 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 675819517 ps |
| CPU time | 3.02 seconds |
| Started | Sep 18 09:01:43 PM UTC 24 |
| Finished | Sep 18 09:01:47 PM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065379442 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.4065379442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3133001436 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4203308156 ps |
| CPU time | 4.88 seconds |
| Started | Sep 18 09:01:45 PM UTC 24 |
| Finished | Sep 18 09:01:51 PM UTC 24 |
| Peak memory | 205264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133001436 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.3133001436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.729650678 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 381856546 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 09:02:19 PM UTC 24 |
| Finished | Sep 18 09:02:21 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=729650678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_tim er_csr_mem_rw_with_rand_reset.729650678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.559454537 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 394822318 ps |
| CPU time | 0.96 seconds |
| Started | Sep 18 09:02:19 PM UTC 24 |
| Finished | Sep 18 09:02:21 PM UTC 24 |
| Peak memory | 201892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559454537 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.559454537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.3499597032 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 410844965 ps |
| CPU time | 1.62 seconds |
| Started | Sep 18 09:02:19 PM UTC 24 |
| Finished | Sep 18 09:02:22 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499597032 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3499597032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.903867173 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1604111322 ps |
| CPU time | 3.55 seconds |
| Started | Sep 18 09:02:19 PM UTC 24 |
| Finished | Sep 18 09:02:24 PM UTC 24 |
| Peak memory | 203568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903867173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.903867173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.3172213979 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 424394807 ps |
| CPU time | 2.77 seconds |
| Started | Sep 18 09:02:19 PM UTC 24 |
| Finished | Sep 18 09:02:23 PM UTC 24 |
| Peak memory | 207196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172213979 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3172213979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2025781181 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 8092584045 ps |
| CPU time | 13.3 seconds |
| Started | Sep 18 09:02:19 PM UTC 24 |
| Finished | Sep 18 09:02:33 PM UTC 24 |
| Peak memory | 206992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025781181 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.2025781181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3916712391 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 525534024 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 09:02:20 PM UTC 24 |
| Finished | Sep 18 09:02:23 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3916712391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_ti mer_csr_mem_rw_with_rand_reset.3916712391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.361691525 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 368765360 ps |
| CPU time | 1.88 seconds |
| Started | Sep 18 09:02:20 PM UTC 24 |
| Finished | Sep 18 09:02:23 PM UTC 24 |
| Peak memory | 201832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361691525 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.361691525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.898398894 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 410307449 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 09:02:20 PM UTC 24 |
| Finished | Sep 18 09:02:22 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898398894 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.898398894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2030009030 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1493058318 ps |
| CPU time | 2.66 seconds |
| Started | Sep 18 09:02:20 PM UTC 24 |
| Finished | Sep 18 09:02:24 PM UTC 24 |
| Peak memory | 203572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030009030 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.2030009030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.3483617431 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 330692543 ps |
| CPU time | 2.28 seconds |
| Started | Sep 18 09:02:20 PM UTC 24 |
| Finished | Sep 18 09:02:23 PM UTC 24 |
| Peak memory | 207128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483617431 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3483617431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.446323080 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 435710802 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 09:02:22 PM UTC 24 |
| Finished | Sep 18 09:02:24 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=446323080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_tim er_csr_mem_rw_with_rand_reset.446323080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.250787519 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 514535830 ps |
| CPU time | 0.94 seconds |
| Started | Sep 18 09:02:22 PM UTC 24 |
| Finished | Sep 18 09:02:24 PM UTC 24 |
| Peak memory | 201832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250787519 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.250787519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.2132818750 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 510551938 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 09:02:22 PM UTC 24 |
| Finished | Sep 18 09:02:24 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132818750 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2132818750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2328288480 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1630459583 ps |
| CPU time | 5.58 seconds |
| Started | Sep 18 09:02:22 PM UTC 24 |
| Finished | Sep 18 09:02:28 PM UTC 24 |
| Peak memory | 203240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328288480 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.2328288480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3470157727 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 741491533 ps |
| CPU time | 2.7 seconds |
| Started | Sep 18 09:02:20 PM UTC 24 |
| Finished | Sep 18 09:02:24 PM UTC 24 |
| Peak memory | 207280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470157727 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3470157727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2580448145 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 9368316261 ps |
| CPU time | 3.58 seconds |
| Started | Sep 18 09:02:20 PM UTC 24 |
| Finished | Sep 18 09:02:25 PM UTC 24 |
| Peak memory | 207100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580448145 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.2580448145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1951957501 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 312468576 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 09:02:24 PM UTC 24 |
| Finished | Sep 18 09:02:27 PM UTC 24 |
| Peak memory | 205084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1951957501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti mer_csr_mem_rw_with_rand_reset.1951957501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.3980606037 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 500208058 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 09:02:23 PM UTC 24 |
| Finished | Sep 18 09:02:25 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980606037 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3980606037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.187759701 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 497142765 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 09:02:23 PM UTC 24 |
| Finished | Sep 18 09:02:25 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187759701 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.187759701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2351535969 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1325717606 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 09:02:24 PM UTC 24 |
| Finished | Sep 18 09:02:27 PM UTC 24 |
| Peak memory | 202020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351535969 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.2351535969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3633471762 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 553275908 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 09:02:22 PM UTC 24 |
| Finished | Sep 18 09:02:24 PM UTC 24 |
| Peak memory | 206936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633471762 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3633471762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3180150735 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 8592175373 ps |
| CPU time | 17.1 seconds |
| Started | Sep 18 09:02:23 PM UTC 24 |
| Finished | Sep 18 09:02:41 PM UTC 24 |
| Peak memory | 207028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180150735 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.3180150735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.156037040 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 481153999 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 09:02:25 PM UTC 24 |
| Finished | Sep 18 09:02:28 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=156037040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_tim er_csr_mem_rw_with_rand_reset.156037040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.2300156390 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 496135400 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 09:02:24 PM UTC 24 |
| Finished | Sep 18 09:02:27 PM UTC 24 |
| Peak memory | 201832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300156390 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2300156390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.2235585476 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 431903997 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 09:02:24 PM UTC 24 |
| Finished | Sep 18 09:02:26 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235585476 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2235585476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3967679608 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1428352028 ps |
| CPU time | 2.65 seconds |
| Started | Sep 18 09:02:25 PM UTC 24 |
| Finished | Sep 18 09:02:29 PM UTC 24 |
| Peak memory | 203380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967679608 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.3967679608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.3657389946 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1642394613 ps |
| CPU time | 1.89 seconds |
| Started | Sep 18 09:02:24 PM UTC 24 |
| Finished | Sep 18 09:02:27 PM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657389946 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3657389946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3567329384 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 8833442664 ps |
| CPU time | 1.74 seconds |
| Started | Sep 18 09:02:24 PM UTC 24 |
| Finished | Sep 18 09:02:27 PM UTC 24 |
| Peak memory | 206516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567329384 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.3567329384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3355243705 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 496605359 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 09:02:27 PM UTC 24 |
| Finished | Sep 18 09:02:29 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3355243705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti mer_csr_mem_rw_with_rand_reset.3355243705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.2993263737 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 518712548 ps |
| CPU time | 1.48 seconds |
| Started | Sep 18 09:02:26 PM UTC 24 |
| Finished | Sep 18 09:02:28 PM UTC 24 |
| Peak memory | 201832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993263737 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2993263737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.3815166094 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 429947368 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 09:02:26 PM UTC 24 |
| Finished | Sep 18 09:02:28 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815166094 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3815166094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.418186873 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 1565593282 ps |
| CPU time | 2.36 seconds |
| Started | Sep 18 09:02:27 PM UTC 24 |
| Finished | Sep 18 09:02:30 PM UTC 24 |
| Peak memory | 203304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418186873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.418186873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.3092643847 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 289285641 ps |
| CPU time | 1.65 seconds |
| Started | Sep 18 09:02:25 PM UTC 24 |
| Finished | Sep 18 09:02:28 PM UTC 24 |
| Peak memory | 207120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092643847 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3092643847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2913771145 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 8107921703 ps |
| CPU time | 6.7 seconds |
| Started | Sep 18 09:02:26 PM UTC 24 |
| Finished | Sep 18 09:02:33 PM UTC 24 |
| Peak memory | 207256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913771145 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.2913771145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2285763233 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 413640782 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 09:02:28 PM UTC 24 |
| Finished | Sep 18 09:02:30 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2285763233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti mer_csr_mem_rw_with_rand_reset.2285763233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.682712041 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 312380929 ps |
| CPU time | 1.56 seconds |
| Started | Sep 18 09:02:27 PM UTC 24 |
| Finished | Sep 18 09:02:30 PM UTC 24 |
| Peak memory | 201892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682712041 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.682712041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.612051004 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 508796103 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 09:02:27 PM UTC 24 |
| Finished | Sep 18 09:02:29 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612051004 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.612051004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4175991665 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1279118708 ps |
| CPU time | 3.62 seconds |
| Started | Sep 18 09:02:28 PM UTC 24 |
| Finished | Sep 18 09:02:33 PM UTC 24 |
| Peak memory | 203380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175991665 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.4175991665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.1860465948 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 568741426 ps |
| CPU time | 3.38 seconds |
| Started | Sep 18 09:02:27 PM UTC 24 |
| Finished | Sep 18 09:02:31 PM UTC 24 |
| Peak memory | 207064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860465948 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1860465948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3203132647 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 4446695091 ps |
| CPU time | 4.28 seconds |
| Started | Sep 18 09:02:27 PM UTC 24 |
| Finished | Sep 18 09:02:32 PM UTC 24 |
| Peak memory | 206280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203132647 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.3203132647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1787099615 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 395329109 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 09:02:29 PM UTC 24 |
| Finished | Sep 18 09:02:32 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1787099615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti mer_csr_mem_rw_with_rand_reset.1787099615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.1155286709 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 358241679 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 09:02:28 PM UTC 24 |
| Finished | Sep 18 09:02:31 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155286709 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1155286709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.771596944 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 503282116 ps |
| CPU time | 1.52 seconds |
| Started | Sep 18 09:02:28 PM UTC 24 |
| Finished | Sep 18 09:02:31 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771596944 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.771596944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3669386330 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1522170478 ps |
| CPU time | 3.22 seconds |
| Started | Sep 18 09:02:29 PM UTC 24 |
| Finished | Sep 18 09:02:34 PM UTC 24 |
| Peak memory | 203572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669386330 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.3669386330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.3772492868 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 545516980 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 09:02:28 PM UTC 24 |
| Finished | Sep 18 09:02:32 PM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772492868 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3772492868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.712913675 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 8341030087 ps |
| CPU time | 4.85 seconds |
| Started | Sep 18 09:02:28 PM UTC 24 |
| Finished | Sep 18 09:02:34 PM UTC 24 |
| Peak memory | 207332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712913675 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.712913675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3361424955 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 470639084 ps |
| CPU time | 1.98 seconds |
| Started | Sep 18 09:02:31 PM UTC 24 |
| Finished | Sep 18 09:02:34 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3361424955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_ti mer_csr_mem_rw_with_rand_reset.3361424955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.1146437388 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 469062039 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 09:02:30 PM UTC 24 |
| Finished | Sep 18 09:02:32 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146437388 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1146437388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.1190906675 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 458940878 ps |
| CPU time | 2.26 seconds |
| Started | Sep 18 09:02:30 PM UTC 24 |
| Finished | Sep 18 09:02:33 PM UTC 24 |
| Peak memory | 201120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190906675 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1190906675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1690119588 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2748351395 ps |
| CPU time | 4.52 seconds |
| Started | Sep 18 09:02:30 PM UTC 24 |
| Finished | Sep 18 09:02:35 PM UTC 24 |
| Peak memory | 205684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690119588 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.1690119588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.1684197948 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1188273262 ps |
| CPU time | 2.81 seconds |
| Started | Sep 18 09:02:29 PM UTC 24 |
| Finished | Sep 18 09:02:33 PM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684197948 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1684197948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4123554588 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 8357735101 ps |
| CPU time | 15.36 seconds |
| Started | Sep 18 09:02:30 PM UTC 24 |
| Finished | Sep 18 09:02:46 PM UTC 24 |
| Peak memory | 206896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123554588 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.4123554588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3317337163 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 483718353 ps |
| CPU time | 0.89 seconds |
| Started | Sep 18 09:02:32 PM UTC 24 |
| Finished | Sep 18 09:02:34 PM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3317337163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti mer_csr_mem_rw_with_rand_reset.3317337163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.3420096230 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 278423143 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 09:02:32 PM UTC 24 |
| Finished | Sep 18 09:02:34 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420096230 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3420096230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.3896762564 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 413580151 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 09:02:31 PM UTC 24 |
| Finished | Sep 18 09:02:33 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896762564 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3896762564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1650528694 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1194123033 ps |
| CPU time | 1.47 seconds |
| Started | Sep 18 09:02:32 PM UTC 24 |
| Finished | Sep 18 09:02:35 PM UTC 24 |
| Peak memory | 202020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650528694 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.1650528694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.3692512043 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 791291617 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 09:02:31 PM UTC 24 |
| Finished | Sep 18 09:02:36 PM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692512043 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3692512043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4025186002 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4252079178 ps |
| CPU time | 3.95 seconds |
| Started | Sep 18 09:02:31 PM UTC 24 |
| Finished | Sep 18 09:02:36 PM UTC 24 |
| Peak memory | 205700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025186002 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.4025186002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2680761077 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 484782070 ps |
| CPU time | 2.52 seconds |
| Started | Sep 18 09:02:01 PM UTC 24 |
| Finished | Sep 18 09:02:05 PM UTC 24 |
| Peak memory | 203244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680761077 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.2680761077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1376702821 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 12479186181 ps |
| CPU time | 8.08 seconds |
| Started | Sep 18 09:02:00 PM UTC 24 |
| Finished | Sep 18 09:02:10 PM UTC 24 |
| Peak memory | 205712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376702821 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.1376702821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1844440957 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1066339752 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 09:01:59 PM UTC 24 |
| Finished | Sep 18 09:02:03 PM UTC 24 |
| Peak memory | 203320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844440957 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.1844440957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3041084019 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 586904107 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 09:02:02 PM UTC 24 |
| Finished | Sep 18 09:02:04 PM UTC 24 |
| Peak memory | 204968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3041084019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_tim er_csr_mem_rw_with_rand_reset.3041084019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.1334626392 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 344821242 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 09:01:59 PM UTC 24 |
| Finished | Sep 18 09:02:01 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334626392 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1334626392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.4268445027 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 375172097 ps |
| CPU time | 2 seconds |
| Started | Sep 18 09:01:56 PM UTC 24 |
| Finished | Sep 18 09:01:59 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268445027 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.4268445027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3095109629 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 442056866 ps |
| CPU time | 0.95 seconds |
| Started | Sep 18 09:01:58 PM UTC 24 |
| Finished | Sep 18 09:02:00 PM UTC 24 |
| Peak memory | 199912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095109629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.3095109629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.3213046753 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 451076264 ps |
| CPU time | 2.11 seconds |
| Started | Sep 18 09:01:57 PM UTC 24 |
| Finished | Sep 18 09:02:00 PM UTC 24 |
| Peak memory | 201324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213046753 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.3213046753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1092901988 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1157550490 ps |
| CPU time | 2.34 seconds |
| Started | Sep 18 09:02:01 PM UTC 24 |
| Finished | Sep 18 09:02:05 PM UTC 24 |
| Peak memory | 203376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092901988 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.1092901988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2948448321 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 654615688 ps |
| CPU time | 2.38 seconds |
| Started | Sep 18 09:01:54 PM UTC 24 |
| Finished | Sep 18 09:01:57 PM UTC 24 |
| Peak memory | 206992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948448321 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2948448321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2950374673 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 8335169489 ps |
| CPU time | 8.84 seconds |
| Started | Sep 18 09:01:55 PM UTC 24 |
| Finished | Sep 18 09:02:05 PM UTC 24 |
| Peak memory | 207096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950374673 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.2950374673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2362363946 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 449676717 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 09:02:32 PM UTC 24 |
| Finished | Sep 18 09:02:35 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362363946 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2362363946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/20.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.3555441747 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 488926850 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 09:02:32 PM UTC 24 |
| Finished | Sep 18 09:02:36 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555441747 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3555441747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/21.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3267747648 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 387592596 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 09:02:32 PM UTC 24 |
| Finished | Sep 18 09:02:35 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267747648 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3267747648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/22.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.3694085388 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 367123096 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 09:02:32 PM UTC 24 |
| Finished | Sep 18 09:02:35 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694085388 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3694085388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/23.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.830115035 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 448514339 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 09:02:34 PM UTC 24 |
| Finished | Sep 18 09:02:36 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830115035 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.830115035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/24.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.4250542524 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 435508811 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 09:02:34 PM UTC 24 |
| Finished | Sep 18 09:02:37 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250542524 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.4250542524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/25.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.1445453941 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 435035743 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 09:02:34 PM UTC 24 |
| Finished | Sep 18 09:02:36 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445453941 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1445453941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/26.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1283050549 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 351690260 ps |
| CPU time | 0.71 seconds |
| Started | Sep 18 09:02:34 PM UTC 24 |
| Finished | Sep 18 09:02:36 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283050549 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1283050549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/27.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2995642001 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 463978393 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 09:02:35 PM UTC 24 |
| Finished | Sep 18 09:02:37 PM UTC 24 |
| Peak memory | 201892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995642001 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2995642001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/28.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.3267296193 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 353094310 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 09:02:35 PM UTC 24 |
| Finished | Sep 18 09:02:37 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267296193 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3267296193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/29.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2014517059 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 544512175 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 09:02:06 PM UTC 24 |
| Finished | Sep 18 09:02:08 PM UTC 24 |
| Peak memory | 201772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014517059 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.2014517059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2026662621 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 11115836079 ps |
| CPU time | 6.17 seconds |
| Started | Sep 18 09:02:06 PM UTC 24 |
| Finished | Sep 18 09:02:13 PM UTC 24 |
| Peak memory | 205576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026662621 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.2026662621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3491727835 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 879478451 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 09:02:05 PM UTC 24 |
| Finished | Sep 18 09:02:08 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491727835 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.3491727835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2483659790 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 433977864 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 09:02:06 PM UTC 24 |
| Finished | Sep 18 09:02:08 PM UTC 24 |
| Peak memory | 205728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2483659790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim er_csr_mem_rw_with_rand_reset.2483659790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.2354897640 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 504494882 ps |
| CPU time | 0.96 seconds |
| Started | Sep 18 09:02:06 PM UTC 24 |
| Finished | Sep 18 09:02:08 PM UTC 24 |
| Peak memory | 201572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354897640 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2354897640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.805863323 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 288546562 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 09:02:03 PM UTC 24 |
| Finished | Sep 18 09:02:05 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805863323 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.805863323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3109595614 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 382624061 ps |
| CPU time | 0.93 seconds |
| Started | Sep 18 09:02:05 PM UTC 24 |
| Finished | Sep 18 09:02:07 PM UTC 24 |
| Peak memory | 199912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109595614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.3109595614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.1928498612 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 488118137 ps |
| CPU time | 1.74 seconds |
| Started | Sep 18 09:02:04 PM UTC 24 |
| Finished | Sep 18 09:02:06 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928498612 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.1928498612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1069982868 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2627155000 ps |
| CPU time | 10.83 seconds |
| Started | Sep 18 09:02:06 PM UTC 24 |
| Finished | Sep 18 09:02:18 PM UTC 24 |
| Peak memory | 205680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069982868 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.1069982868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2254052470 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 687640501 ps |
| CPU time | 2.88 seconds |
| Started | Sep 18 09:02:02 PM UTC 24 |
| Finished | Sep 18 09:02:05 PM UTC 24 |
| Peak memory | 207032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254052470 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2254052470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.4017565603 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 531836223 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 09:02:35 PM UTC 24 |
| Finished | Sep 18 09:02:37 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017565603 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.4017565603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/30.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.3236237371 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 309612065 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 09:02:35 PM UTC 24 |
| Finished | Sep 18 09:02:37 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236237371 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3236237371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/31.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.4284740856 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 370915912 ps |
| CPU time | 2.05 seconds |
| Started | Sep 18 09:02:35 PM UTC 24 |
| Finished | Sep 18 09:02:38 PM UTC 24 |
| Peak memory | 201196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284740856 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.4284740856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/32.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.924643648 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 405297308 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 09:02:35 PM UTC 24 |
| Finished | Sep 18 09:02:37 PM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924643648 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.924643648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/33.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.4222778917 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 302437523 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 09:02:35 PM UTC 24 |
| Finished | Sep 18 09:02:37 PM UTC 24 |
| Peak memory | 201892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222778917 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4222778917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/34.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.1685341342 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 543347808 ps |
| CPU time | 1.04 seconds |
| Started | Sep 18 09:02:35 PM UTC 24 |
| Finished | Sep 18 09:02:37 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685341342 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1685341342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/35.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3318798021 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 516637342 ps |
| CPU time | 0.91 seconds |
| Started | Sep 18 09:02:36 PM UTC 24 |
| Finished | Sep 18 09:02:38 PM UTC 24 |
| Peak memory | 198744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318798021 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3318798021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/36.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.2852914058 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 331521195 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 09:02:36 PM UTC 24 |
| Finished | Sep 18 09:02:39 PM UTC 24 |
| Peak memory | 200648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852914058 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2852914058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/37.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.3386097599 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 512247478 ps |
| CPU time | 1.65 seconds |
| Started | Sep 18 09:02:36 PM UTC 24 |
| Finished | Sep 18 09:02:39 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386097599 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3386097599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/38.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.3884860357 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 329419621 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 09:02:36 PM UTC 24 |
| Finished | Sep 18 09:02:38 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884860357 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3884860357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/39.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.929958642 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 729372395 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 09:02:10 PM UTC 24 |
| Finished | Sep 18 09:02:12 PM UTC 24 |
| Peak memory | 201952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929958642 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.929958642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.794145386 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 5107934846 ps |
| CPU time | 5.15 seconds |
| Started | Sep 18 09:02:09 PM UTC 24 |
| Finished | Sep 18 09:02:15 PM UTC 24 |
| Peak memory | 205628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794145386 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.794145386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1711236807 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1210621602 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 09:02:09 PM UTC 24 |
| Finished | Sep 18 09:02:11 PM UTC 24 |
| Peak memory | 201772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711236807 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.1711236807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1556278952 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 342843344 ps |
| CPU time | 1.04 seconds |
| Started | Sep 18 09:02:10 PM UTC 24 |
| Finished | Sep 18 09:02:12 PM UTC 24 |
| Peak memory | 205056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1556278952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim er_csr_mem_rw_with_rand_reset.1556278952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.4105085137 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 378782232 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 09:02:09 PM UTC 24 |
| Finished | Sep 18 09:02:12 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105085137 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4105085137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.44428067 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 632842555 ps |
| CPU time | 0.9 seconds |
| Started | Sep 18 09:02:07 PM UTC 24 |
| Finished | Sep 18 09:02:09 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44428067 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.44428067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.696167426 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 471891513 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 09:02:09 PM UTC 24 |
| Finished | Sep 18 09:02:12 PM UTC 24 |
| Peak memory | 199968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696167426 -assert nopostproc + UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.696167426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.429709457 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 458682902 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 09:02:08 PM UTC 24 |
| Finished | Sep 18 09:02:10 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429709457 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.429709457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2651174726 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1503127983 ps |
| CPU time | 3.31 seconds |
| Started | Sep 18 09:02:10 PM UTC 24 |
| Finished | Sep 18 09:02:14 PM UTC 24 |
| Peak memory | 203240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651174726 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.2651174726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.3179090534 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 426370975 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 09:02:06 PM UTC 24 |
| Finished | Sep 18 09:02:09 PM UTC 24 |
| Peak memory | 206880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179090534 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3179090534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1830698409 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 8798207338 ps |
| CPU time | 8.52 seconds |
| Started | Sep 18 09:02:07 PM UTC 24 |
| Finished | Sep 18 09:02:17 PM UTC 24 |
| Peak memory | 207272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830698409 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.1830698409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.847140595 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 515204602 ps |
| CPU time | 0.71 seconds |
| Started | Sep 18 09:02:36 PM UTC 24 |
| Finished | Sep 18 09:02:38 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847140595 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.847140595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/40.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.1159151111 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 283074360 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 09:02:36 PM UTC 24 |
| Finished | Sep 18 09:02:39 PM UTC 24 |
| Peak memory | 198964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159151111 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1159151111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/41.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.141630528 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 359622306 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 09:02:36 PM UTC 24 |
| Finished | Sep 18 09:02:39 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141630528 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.141630528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/42.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.3360568924 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 315287413 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 09:02:37 PM UTC 24 |
| Finished | Sep 18 09:02:39 PM UTC 24 |
| Peak memory | 201284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360568924 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3360568924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/43.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.3147790667 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 501538428 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 09:02:37 PM UTC 24 |
| Finished | Sep 18 09:02:39 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147790667 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3147790667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/44.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.1391907991 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 337666117 ps |
| CPU time | 0.74 seconds |
| Started | Sep 18 09:02:38 PM UTC 24 |
| Finished | Sep 18 09:02:40 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391907991 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1391907991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/45.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.239200548 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 354099144 ps |
| CPU time | 0.85 seconds |
| Started | Sep 18 09:02:38 PM UTC 24 |
| Finished | Sep 18 09:02:40 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239200548 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.239200548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/46.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.3673623964 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 438393690 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 09:02:38 PM UTC 24 |
| Finished | Sep 18 09:02:41 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673623964 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3673623964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/47.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.2549217178 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 276205631 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 09:02:38 PM UTC 24 |
| Finished | Sep 18 09:02:40 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549217178 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2549217178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/48.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.490672032 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 488421531 ps |
| CPU time | 0.8 seconds |
| Started | Sep 18 09:02:38 PM UTC 24 |
| Finished | Sep 18 09:02:40 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490672032 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.490672032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/49.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.181564702 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 435805294 ps |
| CPU time | 1.12 seconds |
| Started | Sep 18 09:02:11 PM UTC 24 |
| Finished | Sep 18 09:02:13 PM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=181564702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_time r_csr_mem_rw_with_rand_reset.181564702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.290577828 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 473090183 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 09:02:11 PM UTC 24 |
| Finished | Sep 18 09:02:13 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290577828 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.290577828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.776471389 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 292677196 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 09:02:11 PM UTC 24 |
| Finished | Sep 18 09:02:13 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776471389 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.776471389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3067016031 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2310116135 ps |
| CPU time | 2.59 seconds |
| Started | Sep 18 09:02:11 PM UTC 24 |
| Finished | Sep 18 09:02:15 PM UTC 24 |
| Peak memory | 205680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067016031 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.3067016031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.4121967769 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 454360956 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 09:02:10 PM UTC 24 |
| Finished | Sep 18 09:02:14 PM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121967769 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.4121967769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2352608962 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 8983335261 ps |
| CPU time | 6.12 seconds |
| Started | Sep 18 09:02:10 PM UTC 24 |
| Finished | Sep 18 09:02:18 PM UTC 24 |
| Peak memory | 206868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352608962 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.2352608962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2584889257 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 419959727 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 09:02:14 PM UTC 24 |
| Finished | Sep 18 09:02:16 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2584889257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_tim er_csr_mem_rw_with_rand_reset.2584889257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.3885135925 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 453930008 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 09:02:13 PM UTC 24 |
| Finished | Sep 18 09:02:15 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885135925 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3885135925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.62194172 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 449753790 ps |
| CPU time | 1.52 seconds |
| Started | Sep 18 09:02:12 PM UTC 24 |
| Finished | Sep 18 09:02:15 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62194172 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.62194172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.698662398 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1061940779 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 09:02:13 PM UTC 24 |
| Finished | Sep 18 09:02:15 PM UTC 24 |
| Peak memory | 201960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698662398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.698662398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3399447089 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 471514443 ps |
| CPU time | 2.58 seconds |
| Started | Sep 18 09:02:12 PM UTC 24 |
| Finished | Sep 18 09:02:16 PM UTC 24 |
| Peak memory | 206836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399447089 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3399447089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1017647512 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 8797728438 ps |
| CPU time | 5.77 seconds |
| Started | Sep 18 09:02:12 PM UTC 24 |
| Finished | Sep 18 09:02:19 PM UTC 24 |
| Peak memory | 206740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017647512 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.1017647512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3375405116 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 419700873 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 09:02:15 PM UTC 24 |
| Finished | Sep 18 09:02:17 PM UTC 24 |
| Peak memory | 206556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3375405116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim er_csr_mem_rw_with_rand_reset.3375405116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.2664993485 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 465025373 ps |
| CPU time | 0.88 seconds |
| Started | Sep 18 09:02:15 PM UTC 24 |
| Finished | Sep 18 09:02:17 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664993485 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2664993485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.2733165099 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 333241762 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 09:02:15 PM UTC 24 |
| Finished | Sep 18 09:02:18 PM UTC 24 |
| Peak memory | 199768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733165099 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2733165099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3726087096 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2354879444 ps |
| CPU time | 8.87 seconds |
| Started | Sep 18 09:02:15 PM UTC 24 |
| Finished | Sep 18 09:02:25 PM UTC 24 |
| Peak memory | 205236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726087096 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.3726087096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.4119379709 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 568922901 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 09:02:14 PM UTC 24 |
| Finished | Sep 18 09:02:17 PM UTC 24 |
| Peak memory | 206940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119379709 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.4119379709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2776222052 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3962681920 ps |
| CPU time | 3.89 seconds |
| Started | Sep 18 09:02:15 PM UTC 24 |
| Finished | Sep 18 09:02:20 PM UTC 24 |
| Peak memory | 206548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776222052 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.2776222052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1677721670 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 389495449 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 09:02:16 PM UTC 24 |
| Finished | Sep 18 09:02:19 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1677721670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim er_csr_mem_rw_with_rand_reset.1677721670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.1385374182 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 479393207 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 09:02:16 PM UTC 24 |
| Finished | Sep 18 09:02:18 PM UTC 24 |
| Peak memory | 201768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385374182 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1385374182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.3647289671 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 512265130 ps |
| CPU time | 1.04 seconds |
| Started | Sep 18 09:02:16 PM UTC 24 |
| Finished | Sep 18 09:02:18 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647289671 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3647289671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.834403272 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1261607200 ps |
| CPU time | 1.93 seconds |
| Started | Sep 18 09:02:16 PM UTC 24 |
| Finished | Sep 18 09:02:19 PM UTC 24 |
| Peak memory | 201960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834403272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.834403272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.3199012796 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 357687692 ps |
| CPU time | 2.37 seconds |
| Started | Sep 18 09:02:16 PM UTC 24 |
| Finished | Sep 18 09:02:20 PM UTC 24 |
| Peak memory | 207096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199012796 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3199012796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3565232574 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 8630336284 ps |
| CPU time | 8.69 seconds |
| Started | Sep 18 09:02:16 PM UTC 24 |
| Finished | Sep 18 09:02:26 PM UTC 24 |
| Peak memory | 206932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565232574 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.3565232574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1834319733 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 470845974 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 09:02:18 PM UTC 24 |
| Finished | Sep 18 09:02:20 PM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1834319733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_tim er_csr_mem_rw_with_rand_reset.1834319733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.2843188589 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 467435343 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 09:02:18 PM UTC 24 |
| Finished | Sep 18 09:02:21 PM UTC 24 |
| Peak memory | 203380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843188589 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2843188589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.2737989000 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 453976173 ps |
| CPU time | 1.59 seconds |
| Started | Sep 18 09:02:18 PM UTC 24 |
| Finished | Sep 18 09:02:20 PM UTC 24 |
| Peak memory | 201832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737989000 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2737989000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3110406993 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1337865142 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 09:02:18 PM UTC 24 |
| Finished | Sep 18 09:02:20 PM UTC 24 |
| Peak memory | 201956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110406993 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.3110406993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1067026138 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 410676567 ps |
| CPU time | 2.65 seconds |
| Started | Sep 18 09:02:17 PM UTC 24 |
| Finished | Sep 18 09:02:21 PM UTC 24 |
| Peak memory | 207328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067026138 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1067026138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2470696836 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 8701377966 ps |
| CPU time | 19.08 seconds |
| Started | Sep 18 09:02:18 PM UTC 24 |
| Finished | Sep 18 09:02:38 PM UTC 24 |
| Peak memory | 207056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470696836 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_17/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.2470696836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.437809081 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 10870252595 ps |
| CPU time | 22.85 seconds |
| Started | Sep 18 08:57:51 PM UTC 24 |
| Finished | Sep 18 08:58:16 PM UTC 24 |
| Peak memory | 206128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437809081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.437809081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.3675270745 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 390410605 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 08:57:51 PM UTC 24 |
| Finished | Sep 18 08:57:54 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675270745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3675270745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/0.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.4220766839 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 31544884734 ps |
| CPU time | 12.47 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:58:06 PM UTC 24 |
| Peak memory | 205908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220766839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4220766839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.2116506265 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8330898834 ps |
| CPU time | 3.35 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:57:57 PM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116506265 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2116506265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.3070911239 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 446638036 ps |
| CPU time | 1.72 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:57:55 PM UTC 24 |
| Peak memory | 203824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070911239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3070911239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/1.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.491599061 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 52784765905 ps |
| CPU time | 19.94 seconds |
| Started | Sep 18 08:58:14 PM UTC 24 |
| Finished | Sep 18 08:58:35 PM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491599061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.491599061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.65332546 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 419029483 ps |
| CPU time | 0.98 seconds |
| Started | Sep 18 08:58:13 PM UTC 24 |
| Finished | Sep 18 08:58:15 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65332546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.65332546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/10.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.2655992747 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 26025751002 ps |
| CPU time | 62.17 seconds |
| Started | Sep 18 08:58:18 PM UTC 24 |
| Finished | Sep 18 08:59:22 PM UTC 24 |
| Peak memory | 205712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655992747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2655992747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.2324084677 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 484299942 ps |
| CPU time | 1.02 seconds |
| Started | Sep 18 08:58:18 PM UTC 24 |
| Finished | Sep 18 08:58:21 PM UTC 24 |
| Peak memory | 203644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324084677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2324084677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.3430182675 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 36992428032 ps |
| CPU time | 33.71 seconds |
| Started | Sep 18 08:58:20 PM UTC 24 |
| Finished | Sep 18 08:58:55 PM UTC 24 |
| Peak memory | 216248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3430182675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 11.aon_timer_stress_all_with_rand_reset.3430182675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.1101770411 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 429138756 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 08:58:22 PM UTC 24 |
| Finished | Sep 18 08:58:24 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101770411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1101770411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.3444795161 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 19743769493 ps |
| CPU time | 7.5 seconds |
| Started | Sep 18 08:58:22 PM UTC 24 |
| Finished | Sep 18 08:58:31 PM UTC 24 |
| Peak memory | 205936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444795161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3444795161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.2043995934 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 550458275 ps |
| CPU time | 2.42 seconds |
| Started | Sep 18 08:58:22 PM UTC 24 |
| Finished | Sep 18 08:58:25 PM UTC 24 |
| Peak memory | 205692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043995934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2043995934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/12.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.4020983666 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 61056022954 ps |
| CPU time | 109.21 seconds |
| Started | Sep 18 08:58:26 PM UTC 24 |
| Finished | Sep 18 09:00:18 PM UTC 24 |
| Peak memory | 205948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020983666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4020983666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.2806676328 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 487995184 ps |
| CPU time | 2.28 seconds |
| Started | Sep 18 08:58:25 PM UTC 24 |
| Finished | Sep 18 08:58:29 PM UTC 24 |
| Peak memory | 205732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806676328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2806676328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/13.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.3837730702 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 33689633654 ps |
| CPU time | 8.59 seconds |
| Started | Sep 18 08:58:32 PM UTC 24 |
| Finished | Sep 18 08:58:43 PM UTC 24 |
| Peak memory | 206060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837730702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3837730702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.2811676076 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 500114156 ps |
| CPU time | 2.32 seconds |
| Started | Sep 18 08:58:31 PM UTC 24 |
| Finished | Sep 18 08:58:35 PM UTC 24 |
| Peak memory | 205796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811676076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2811676076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/14.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.2970368913 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 409127469 ps |
| CPU time | 1.99 seconds |
| Started | Sep 18 08:58:37 PM UTC 24 |
| Finished | Sep 18 08:58:40 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970368913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2970368913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.554506665 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 34704165654 ps |
| CPU time | 27.06 seconds |
| Started | Sep 18 08:58:37 PM UTC 24 |
| Finished | Sep 18 08:59:05 PM UTC 24 |
| Peak memory | 206000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554506665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.554506665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.1590302405 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 526103414 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 08:58:36 PM UTC 24 |
| Finished | Sep 18 08:58:39 PM UTC 24 |
| Peak memory | 205784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590302405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1590302405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/15.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.3305952861 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 31166983779 ps |
| CPU time | 50.46 seconds |
| Started | Sep 18 08:58:40 PM UTC 24 |
| Finished | Sep 18 08:59:32 PM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305952861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3305952861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.3712905666 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 594303634 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 08:58:40 PM UTC 24 |
| Finished | Sep 18 08:58:43 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712905666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3712905666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/16.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.4154290781 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 6768696323 ps |
| CPU time | 12.47 seconds |
| Started | Sep 18 08:58:44 PM UTC 24 |
| Finished | Sep 18 08:58:57 PM UTC 24 |
| Peak memory | 205948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154290781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.4154290781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.2219502204 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 593249004 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 08:58:44 PM UTC 24 |
| Finished | Sep 18 08:58:46 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219502204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2219502204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/17.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.4240452371 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 33331469637 ps |
| CPU time | 55.47 seconds |
| Started | Sep 18 08:58:48 PM UTC 24 |
| Finished | Sep 18 08:59:45 PM UTC 24 |
| Peak memory | 205996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240452371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4240452371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.190574813 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 594451613 ps |
| CPU time | 2.8 seconds |
| Started | Sep 18 08:58:47 PM UTC 24 |
| Finished | Sep 18 08:58:51 PM UTC 24 |
| Peak memory | 205656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190574813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.190574813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/18.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.591714741 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 10402721073 ps |
| CPU time | 7.44 seconds |
| Started | Sep 18 08:58:52 PM UTC 24 |
| Finished | Sep 18 08:59:01 PM UTC 24 |
| Peak memory | 205788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591714741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.591714741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.3699086571 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 525478579 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 08:58:52 PM UTC 24 |
| Finished | Sep 18 08:58:55 PM UTC 24 |
| Peak memory | 205220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699086571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3699086571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/19.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.3715293381 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 20049821268 ps |
| CPU time | 45.86 seconds |
| Started | Sep 18 08:57:53 PM UTC 24 |
| Finished | Sep 18 08:58:40 PM UTC 24 |
| Peak memory | 205916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715293381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3715293381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.2226254866 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4472482923 ps |
| CPU time | 7.22 seconds |
| Started | Sep 18 08:57:54 PM UTC 24 |
| Finished | Sep 18 08:58:03 PM UTC 24 |
| Peak memory | 234488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226254866 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2226254866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.2720363998 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 52609501401 ps |
| CPU time | 117.76 seconds |
| Started | Sep 18 08:58:56 PM UTC 24 |
| Finished | Sep 18 09:00:55 PM UTC 24 |
| Peak memory | 206056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720363998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2720363998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/20.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.3504090365 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 500864397 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 08:58:55 PM UTC 24 |
| Finished | Sep 18 08:58:58 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504090365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3504090365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/20.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.3354238078 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 6610557756 ps |
| CPU time | 20.42 seconds |
| Started | Sep 18 08:58:58 PM UTC 24 |
| Finished | Sep 18 08:59:19 PM UTC 24 |
| Peak memory | 223104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3354238078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 20.aon_timer_stress_all_with_rand_reset.3354238078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.3086078887 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 43873086497 ps |
| CPU time | 18.9 seconds |
| Started | Sep 18 08:59:02 PM UTC 24 |
| Finished | Sep 18 08:59:22 PM UTC 24 |
| Peak memory | 205992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086078887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3086078887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/21.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.3501951699 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 512694878 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 08:59:00 PM UTC 24 |
| Finished | Sep 18 08:59:02 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501951699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3501951699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/21.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.3048823743 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 19650083027 ps |
| CPU time | 57 seconds |
| Started | Sep 18 08:59:06 PM UTC 24 |
| Finished | Sep 18 09:00:05 PM UTC 24 |
| Peak memory | 206140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048823743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3048823743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/22.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.2460566366 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 568161143 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 08:59:05 PM UTC 24 |
| Finished | Sep 18 08:59:07 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460566366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2460566366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/22.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.1273068415 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1403513453 ps |
| CPU time | 1.59 seconds |
| Started | Sep 18 08:59:20 PM UTC 24 |
| Finished | Sep 18 08:59:23 PM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273068415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1273068415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/23.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.2815871523 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 430243071 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 08:59:18 PM UTC 24 |
| Finished | Sep 18 08:59:21 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815871523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2815871523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/23.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.4166052243 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1393541932 ps |
| CPU time | 8.74 seconds |
| Started | Sep 18 08:59:23 PM UTC 24 |
| Finished | Sep 18 08:59:32 PM UTC 24 |
| Peak memory | 222780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4166052243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 23.aon_timer_stress_all_with_rand_reset.4166052243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.1122942454 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 34448706887 ps |
| CPU time | 18.01 seconds |
| Started | Sep 18 08:59:24 PM UTC 24 |
| Finished | Sep 18 08:59:43 PM UTC 24 |
| Peak memory | 205920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122942454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1122942454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/24.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.2408094871 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 588880277 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 08:59:24 PM UTC 24 |
| Finished | Sep 18 08:59:26 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408094871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2408094871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/24.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.3142114973 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3521409782 ps |
| CPU time | 36.69 seconds |
| Started | Sep 18 08:59:27 PM UTC 24 |
| Finished | Sep 18 09:00:05 PM UTC 24 |
| Peak memory | 216360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3142114973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 24.aon_timer_stress_all_with_rand_reset.3142114973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.4194771375 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 17704860802 ps |
| CPU time | 49.2 seconds |
| Started | Sep 18 08:59:29 PM UTC 24 |
| Finished | Sep 18 09:00:20 PM UTC 24 |
| Peak memory | 205988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194771375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4194771375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/25.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.861880945 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 498442861 ps |
| CPU time | 1.45 seconds |
| Started | Sep 18 08:59:28 PM UTC 24 |
| Finished | Sep 18 08:59:30 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861880945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.861880945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/25.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.1181038118 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 46746618810 ps |
| CPU time | 18.57 seconds |
| Started | Sep 18 08:59:33 PM UTC 24 |
| Finished | Sep 18 08:59:53 PM UTC 24 |
| Peak memory | 206012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181038118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1181038118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/26.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.4040508820 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 546679410 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 08:59:33 PM UTC 24 |
| Finished | Sep 18 08:59:36 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040508820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4040508820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/26.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.1530390651 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 23652562608 ps |
| CPU time | 54.79 seconds |
| Started | Sep 18 08:59:43 PM UTC 24 |
| Finished | Sep 18 09:00:39 PM UTC 24 |
| Peak memory | 206076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530390651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1530390651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/27.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.966381003 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 381094097 ps |
| CPU time | 1.4 seconds |
| Started | Sep 18 08:59:42 PM UTC 24 |
| Finished | Sep 18 08:59:44 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966381003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.966381003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/27.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.1967878251 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 24677036784 ps |
| CPU time | 63.6 seconds |
| Started | Sep 18 08:59:47 PM UTC 24 |
| Finished | Sep 18 09:00:52 PM UTC 24 |
| Peak memory | 205928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967878251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1967878251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/28.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.2135657368 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 369783743 ps |
| CPU time | 1.45 seconds |
| Started | Sep 18 08:59:46 PM UTC 24 |
| Finished | Sep 18 08:59:48 PM UTC 24 |
| Peak memory | 205604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135657368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2135657368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/28.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.2100598603 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 20464121405 ps |
| CPU time | 14.14 seconds |
| Started | Sep 18 08:59:50 PM UTC 24 |
| Finished | Sep 18 09:00:06 PM UTC 24 |
| Peak memory | 205920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100598603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2100598603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/29.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.4212067991 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 565879986 ps |
| CPU time | 2.74 seconds |
| Started | Sep 18 08:59:50 PM UTC 24 |
| Finished | Sep 18 08:59:54 PM UTC 24 |
| Peak memory | 205936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212067991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4212067991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/29.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.3388991636 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 27031224264 ps |
| CPU time | 10.3 seconds |
| Started | Sep 18 08:57:54 PM UTC 24 |
| Finished | Sep 18 08:58:06 PM UTC 24 |
| Peak memory | 205924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388991636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3388991636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.3353033594 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8157496355 ps |
| CPU time | 20.69 seconds |
| Started | Sep 18 08:57:57 PM UTC 24 |
| Finished | Sep 18 08:58:18 PM UTC 24 |
| Peak memory | 234544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353033594 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3353033594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.1707921998 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 416726346 ps |
| CPU time | 2 seconds |
| Started | Sep 18 08:57:54 PM UTC 24 |
| Finished | Sep 18 08:57:57 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707921998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1707921998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/3.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.3476283753 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 21820428520 ps |
| CPU time | 9.03 seconds |
| Started | Sep 18 08:59:56 PM UTC 24 |
| Finished | Sep 18 09:00:06 PM UTC 24 |
| Peak memory | 206148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476283753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3476283753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/30.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.195535694 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 343110944 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 08:59:55 PM UTC 24 |
| Finished | Sep 18 08:59:57 PM UTC 24 |
| Peak memory | 205724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195535694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.195535694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/30.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.1119815545 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 38884809630 ps |
| CPU time | 67.85 seconds |
| Started | Sep 18 08:59:59 PM UTC 24 |
| Finished | Sep 18 09:01:09 PM UTC 24 |
| Peak memory | 206068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119815545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1119815545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/31.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.2108303409 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 474356571 ps |
| CPU time | 1.48 seconds |
| Started | Sep 18 08:59:59 PM UTC 24 |
| Finished | Sep 18 09:00:02 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108303409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2108303409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/31.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.113251138 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 8669358059 ps |
| CPU time | 18.38 seconds |
| Started | Sep 18 09:00:08 PM UTC 24 |
| Finished | Sep 18 09:00:28 PM UTC 24 |
| Peak memory | 223108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=113251138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.aon_timer_stress_all_with_rand_reset.113251138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.3008075955 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 20710690738 ps |
| CPU time | 46.39 seconds |
| Started | Sep 18 09:00:08 PM UTC 24 |
| Finished | Sep 18 09:00:56 PM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008075955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3008075955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/32.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.2499574880 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 539955858 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 09:00:08 PM UTC 24 |
| Finished | Sep 18 09:00:11 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499574880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2499574880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/32.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.988130714 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 7793535246 ps |
| CPU time | 6.34 seconds |
| Started | Sep 18 09:00:12 PM UTC 24 |
| Finished | Sep 18 09:00:20 PM UTC 24 |
| Peak memory | 206144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988130714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.988130714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/33.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.3952191955 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 407423315 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 09:00:09 PM UTC 24 |
| Finished | Sep 18 09:00:11 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952191955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3952191955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/33.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.1850826323 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 14936877719 ps |
| CPU time | 19.19 seconds |
| Started | Sep 18 09:00:18 PM UTC 24 |
| Finished | Sep 18 09:00:39 PM UTC 24 |
| Peak memory | 206076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850826323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1850826323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/34.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.3987009017 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 474647991 ps |
| CPU time | 2.55 seconds |
| Started | Sep 18 09:00:16 PM UTC 24 |
| Finished | Sep 18 09:00:20 PM UTC 24 |
| Peak memory | 205628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987009017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3987009017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/34.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.1744532061 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 43873438719 ps |
| CPU time | 25.83 seconds |
| Started | Sep 18 09:00:22 PM UTC 24 |
| Finished | Sep 18 09:00:50 PM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744532061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1744532061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/35.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.307918134 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 420695809 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 09:00:21 PM UTC 24 |
| Finished | Sep 18 09:00:23 PM UTC 24 |
| Peak memory | 205784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307918134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.307918134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/35.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.1383079215 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3761206850 ps |
| CPU time | 3.58 seconds |
| Started | Sep 18 09:00:27 PM UTC 24 |
| Finished | Sep 18 09:00:32 PM UTC 24 |
| Peak memory | 205728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383079215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1383079215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/36.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.2325907848 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 619415702 ps |
| CPU time | 1.83 seconds |
| Started | Sep 18 09:00:24 PM UTC 24 |
| Finished | Sep 18 09:00:27 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325907848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2325907848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/36.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.2215187482 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 36693592709 ps |
| CPU time | 26.85 seconds |
| Started | Sep 18 09:00:32 PM UTC 24 |
| Finished | Sep 18 09:01:01 PM UTC 24 |
| Peak memory | 205924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215187482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2215187482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/37.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.1088282616 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 362264746 ps |
| CPU time | 1.09 seconds |
| Started | Sep 18 09:00:31 PM UTC 24 |
| Finished | Sep 18 09:00:33 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088282616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1088282616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/37.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.2232223992 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 49606294737 ps |
| CPU time | 73.79 seconds |
| Started | Sep 18 09:00:39 PM UTC 24 |
| Finished | Sep 18 09:01:55 PM UTC 24 |
| Peak memory | 206012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232223992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2232223992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/38.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.2218039254 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 520028875 ps |
| CPU time | 1.87 seconds |
| Started | Sep 18 09:00:39 PM UTC 24 |
| Finished | Sep 18 09:00:42 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218039254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2218039254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/38.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.1273876390 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 40231210248 ps |
| CPU time | 41.53 seconds |
| Started | Sep 18 09:00:43 PM UTC 24 |
| Finished | Sep 18 09:01:26 PM UTC 24 |
| Peak memory | 206148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273876390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1273876390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/39.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.1185578595 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 371663315 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 09:00:43 PM UTC 24 |
| Finished | Sep 18 09:00:46 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185578595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1185578595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/39.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.520785353 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 31265024377 ps |
| CPU time | 11.34 seconds |
| Started | Sep 18 08:57:57 PM UTC 24 |
| Finished | Sep 18 08:58:09 PM UTC 24 |
| Peak memory | 205936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520785353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.520785353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.4060386538 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4279249993 ps |
| CPU time | 2.13 seconds |
| Started | Sep 18 08:57:58 PM UTC 24 |
| Finished | Sep 18 08:58:01 PM UTC 24 |
| Peak memory | 234244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060386538 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.4060386538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.3484897966 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 557580631 ps |
| CPU time | 1.77 seconds |
| Started | Sep 18 08:57:57 PM UTC 24 |
| Finished | Sep 18 08:57:59 PM UTC 24 |
| Peak memory | 205896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484897966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3484897966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/4.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.2781062953 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 48353124458 ps |
| CPU time | 22.16 seconds |
| Started | Sep 18 09:00:47 PM UTC 24 |
| Finished | Sep 18 09:01:11 PM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781062953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2781062953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/40.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.3086073635 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 439590267 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 09:00:46 PM UTC 24 |
| Finished | Sep 18 09:00:49 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086073635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3086073635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/40.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.1654203495 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 55574319943 ps |
| CPU time | 22.1 seconds |
| Started | Sep 18 09:00:53 PM UTC 24 |
| Finished | Sep 18 09:01:16 PM UTC 24 |
| Peak memory | 206076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654203495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1654203495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/41.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.2903142435 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 471053300 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 09:00:52 PM UTC 24 |
| Finished | Sep 18 09:00:54 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903142435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2903142435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/41.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.2612558403 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4094523474 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 09:00:57 PM UTC 24 |
| Finished | Sep 18 09:01:00 PM UTC 24 |
| Peak memory | 205728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612558403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2612558403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/42.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.4270474546 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 497557656 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 09:00:56 PM UTC 24 |
| Finished | Sep 18 09:00:58 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270474546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.4270474546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/42.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.724480604 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 11349452803 ps |
| CPU time | 19.38 seconds |
| Started | Sep 18 09:01:01 PM UTC 24 |
| Finished | Sep 18 09:01:22 PM UTC 24 |
| Peak memory | 205804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724480604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.724480604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/43.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.1646995534 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 512290113 ps |
| CPU time | 1.73 seconds |
| Started | Sep 18 09:01:00 PM UTC 24 |
| Finished | Sep 18 09:01:03 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646995534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1646995534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/43.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.1368540122 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 32173756120 ps |
| CPU time | 64.45 seconds |
| Started | Sep 18 09:01:04 PM UTC 24 |
| Finished | Sep 18 09:02:10 PM UTC 24 |
| Peak memory | 206092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368540122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1368540122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/44.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.2371140775 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 429326066 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 09:01:03 PM UTC 24 |
| Finished | Sep 18 09:01:05 PM UTC 24 |
| Peak memory | 205784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371140775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2371140775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/44.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.2023658083 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 23499908089 ps |
| CPU time | 57 seconds |
| Started | Sep 18 09:01:10 PM UTC 24 |
| Finished | Sep 18 09:02:09 PM UTC 24 |
| Peak memory | 205928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023658083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2023658083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/45.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.1607084492 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 410628985 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 09:01:08 PM UTC 24 |
| Finished | Sep 18 09:01:10 PM UTC 24 |
| Peak memory | 205724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607084492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1607084492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/45.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.2920908354 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 6447663230 ps |
| CPU time | 11.83 seconds |
| Started | Sep 18 09:01:14 PM UTC 24 |
| Finished | Sep 18 09:01:27 PM UTC 24 |
| Peak memory | 206068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920908354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2920908354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/46.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.3054348541 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 581088223 ps |
| CPU time | 1.72 seconds |
| Started | Sep 18 09:01:13 PM UTC 24 |
| Finished | Sep 18 09:01:16 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054348541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3054348541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/46.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.450706348 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 46174255477 ps |
| CPU time | 20.49 seconds |
| Started | Sep 18 09:01:20 PM UTC 24 |
| Finished | Sep 18 09:01:41 PM UTC 24 |
| Peak memory | 205800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450706348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.450706348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/47.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.3782196268 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 490094555 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 09:01:20 PM UTC 24 |
| Finished | Sep 18 09:01:22 PM UTC 24 |
| Peak memory | 203540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782196268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3782196268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/47.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.3857564765 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 560147783 ps |
| CPU time | 2.35 seconds |
| Started | Sep 18 09:01:23 PM UTC 24 |
| Finished | Sep 18 09:01:26 PM UTC 24 |
| Peak memory | 207252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3857564765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 47.aon_timer_stress_all_with_rand_reset.3857564765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.2167742857 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 408355896 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 09:01:27 PM UTC 24 |
| Finished | Sep 18 09:01:29 PM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167742857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2167742857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/48.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.3430683367 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 9070572088 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 09:01:27 PM UTC 24 |
| Finished | Sep 18 09:01:31 PM UTC 24 |
| Peak memory | 206068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430683367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3430683367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/48.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.53499564 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 616262461 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 09:01:27 PM UTC 24 |
| Finished | Sep 18 09:01:29 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53499564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.53499564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/48.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.3311431477 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 47604946489 ps |
| CPU time | 38.22 seconds |
| Started | Sep 18 09:01:31 PM UTC 24 |
| Finished | Sep 18 09:02:11 PM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311431477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3311431477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/49.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.3057552253 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 379565833 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 09:01:30 PM UTC 24 |
| Finished | Sep 18 09:01:32 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057552253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3057552253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/49.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.3729482228 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 25576837203 ps |
| CPU time | 12.46 seconds |
| Started | Sep 18 08:57:59 PM UTC 24 |
| Finished | Sep 18 08:58:13 PM UTC 24 |
| Peak memory | 206000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729482228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3729482228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.4136000916 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 414354846 ps |
| CPU time | 2.24 seconds |
| Started | Sep 18 08:57:58 PM UTC 24 |
| Finished | Sep 18 08:58:01 PM UTC 24 |
| Peak memory | 205720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136000916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.4136000916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/5.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.3792815303 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5291062604 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 08:58:01 PM UTC 24 |
| Finished | Sep 18 08:58:06 PM UTC 24 |
| Peak memory | 206064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792815303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3792815303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.675271555 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 383828190 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 08:58:00 PM UTC 24 |
| Finished | Sep 18 08:58:03 PM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675271555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.675271555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/6.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.306631843 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 20315413454 ps |
| CPU time | 38.07 seconds |
| Started | Sep 18 08:58:05 PM UTC 24 |
| Finished | Sep 18 08:58:44 PM UTC 24 |
| Peak memory | 206084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306631843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.306631843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.1504905306 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 556819342 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 08:58:04 PM UTC 24 |
| Finished | Sep 18 08:58:07 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504905306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1504905306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/7.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.3424104177 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 25961071398 ps |
| CPU time | 40.35 seconds |
| Started | Sep 18 08:58:07 PM UTC 24 |
| Finished | Sep 18 08:58:49 PM UTC 24 |
| Peak memory | 205928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424104177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3424104177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.1874648797 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 371959751 ps |
| CPU time | 1.05 seconds |
| Started | Sep 18 08:58:07 PM UTC 24 |
| Finished | Sep 18 08:58:09 PM UTC 24 |
| Peak memory | 203868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874648797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1874648797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/8.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.3274672926 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 34934553525 ps |
| CPU time | 39.85 seconds |
| Started | Sep 18 08:58:10 PM UTC 24 |
| Finished | Sep 18 08:58:51 PM UTC 24 |
| Peak memory | 205904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274672926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3274672926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.1843117273 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 357673552 ps |
| CPU time | 2.1 seconds |
| Started | Sep 18 08:58:10 PM UTC 24 |
| Finished | Sep 18 08:58:13 PM UTC 24 |
| Peak memory | 205592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843117273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1843117273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/aon_timer-sim-vcs/9.aon_timer_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |