Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 18741 1 T1 11 T3 11 T5 12
bark[1] 295 1 T9 14 T21 63 T96 41
bark[2] 327 1 T21 42 T110 14 T84 14
bark[3] 195 1 T108 21 T78 5 T97 21
bark[4] 431 1 T96 21 T94 14 T134 91
bark[5] 194 1 T39 21 T136 30 T73 89
bark[6] 194 1 T22 21 T126 21 T97 21
bark[7] 172 1 T70 74 T167 14 T149 7
bark[8] 286 1 T42 57 T178 14 T156 21
bark[9] 340 1 T16 14 T118 21 T78 21
bark[10] 261 1 T28 21 T47 14 T103 74
bark[11] 308 1 T10 21 T15 7 T18 14
bark[12] 325 1 T40 26 T187 5 T136 26
bark[13] 359 1 T2 14 T41 21 T103 35
bark[14] 417 1 T27 14 T41 7 T108 19
bark[15] 289 1 T22 61 T78 14 T120 30
bark[16] 212 1 T10 30 T78 5 T119 30
bark[17] 718 1 T43 5 T126 45 T119 56
bark[18] 634 1 T168 14 T150 14 T134 197
bark[19] 467 1 T43 35 T70 5 T131 14
bark[20] 622 1 T42 127 T96 26 T127 14
bark[21] 304 1 T28 38 T97 40 T132 14
bark[22] 386 1 T96 95 T71 26 T126 21
bark[23] 141 1 T8 14 T160 14 T97 69
bark[24] 210 1 T39 21 T118 14 T138 14
bark[25] 300 1 T18 101 T46 14 T21 23
bark[26] 210 1 T39 7 T42 21 T103 21
bark[27] 487 1 T10 7 T29 14 T24 14
bark[28] 403 1 T4 14 T109 42 T73 154
bark[29] 486 1 T151 14 T28 21 T40 48
bark[30] 271 1 T41 26 T106 14 T22 21
bark[31] 420 1 T18 5 T156 38 T72 68
bark_0 4637 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 18338 1 T1 10 T3 10 T5 11
bite[1] 387 1 T8 13 T24 30 T96 21
bite[2] 238 1 T41 21 T42 46 T132 13
bite[3] 530 1 T10 21 T96 95 T71 51
bite[4] 400 1 T48 13 T22 30 T70 4
bite[5] 449 1 T27 13 T136 280 T97 21
bite[6] 437 1 T42 56 T43 4 T101 13
bite[7] 273 1 T10 30 T96 26 T134 46
bite[8] 275 1 T28 21 T42 79 T106 13
bite[9] 655 1 T21 63 T110 13 T84 13
bite[10] 366 1 T16 13 T46 13 T72 21
bite[11] 434 1 T70 73 T150 13 T156 47
bite[12] 229 1 T18 100 T178 13 T149 6
bite[13] 204 1 T47 13 T160 13 T22 21
bite[14] 313 1 T21 22 T118 21 T146 13
bite[15] 434 1 T40 47 T42 21 T96 40
bite[16] 511 1 T10 6 T40 26 T120 51
bite[17] 352 1 T9 13 T139 13 T172 13
bite[18] 136 1 T24 13 T21 42 T125 30
bite[19] 202 1 T39 21 T22 21 T78 4
bite[20] 401 1 T2 13 T15 6 T24 21
bite[21] 343 1 T39 6 T41 25 T131 13
bite[22] 243 1 T41 21 T119 30 T86 21
bite[23] 612 1 T45 13 T156 38 T119 26
bite[24] 282 1 T187 4 T78 4 T120 30
bite[25] 175 1 T18 4 T103 21 T109 30
bite[26] 351 1 T28 21 T22 21 T96 21
bite[27] 276 1 T151 13 T123 21 T181 13
bite[28] 117 1 T29 13 T39 21 T41 6
bite[29] 330 1 T4 13 T28 37 T43 34
bite[30] 307 1 T138 13 T136 25 T125 21
bite[31] 309 1 T18 13 T154 13 T167 13
bite_0 5133 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29036 1 T1 11 T2 21 T3 11
auto[1] 5006 1 T1 7 T3 7 T7 7


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 397 1 T18 19 T188 9 T97 24
prescale[1] 339 1 T15 2 T41 37 T42 2
prescale[2] 379 1 T44 9 T39 92 T189 9
prescale[3] 230 1 T40 2 T41 2 T22 44
prescale[4] 566 1 T190 9 T49 9 T42 2
prescale[5] 599 1 T18 2 T28 213 T23 54
prescale[6] 276 1 T191 9 T149 56 T126 19
prescale[7] 275 1 T10 126 T18 2 T192 9
prescale[8] 249 1 T24 9 T193 9 T71 4
prescale[9] 350 1 T18 2 T28 19 T40 2
prescale[10] 379 1 T39 2 T71 2 T187 2
prescale[11] 238 1 T28 9 T40 2 T118 37
prescale[12] 544 1 T5 9 T17 9 T18 2
prescale[13] 482 1 T18 2 T24 28 T194 9
prescale[14] 434 1 T18 2 T24 19 T40 2
prescale[15] 604 1 T18 2 T39 2 T148 77
prescale[16] 467 1 T24 2 T70 2 T187 4
prescale[17] 435 1 T50 9 T71 2 T148 2
prescale[18] 637 1 T14 9 T40 2 T42 2
prescale[19] 583 1 T28 2 T41 2 T187 2
prescale[20] 379 1 T103 33 T136 2 T120 2
prescale[21] 541 1 T15 2 T18 117 T21 24
prescale[22] 327 1 T10 47 T24 79 T70 2
prescale[23] 382 1 T10 2 T28 19 T40 19
prescale[24] 399 1 T24 2 T42 61 T91 2
prescale[25] 469 1 T15 2 T28 2 T39 99
prescale[26] 199 1 T15 2 T42 2 T195 9
prescale[27] 210 1 T41 2 T71 2 T187 2
prescale[28] 456 1 T10 2 T118 24 T71 2
prescale[29] 331 1 T40 2 T41 2 T78 2
prescale[30] 551 1 T10 2 T28 49 T40 2
prescale[31] 273 1 T196 9 T22 24 T70 2
prescale_0 21062 1 T1 18 T2 21 T3 18


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23136 1 T1 9 T2 21 T3 9
auto[1] 10906 1 T1 9 T3 9 T4 12


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 34042 1 T1 18 T2 21 T3 18


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 18772 1 T1 13 T2 1 T3 13
wkup[1] 138 1 T42 36 T70 21 T109 30
wkup[2] 159 1 T84 15 T108 30 T148 30
wkup[3] 179 1 T42 21 T71 21 T126 21
wkup[4] 194 1 T120 21 T73 26 T134 27
wkup[5] 124 1 T28 21 T21 21 T43 6
wkup[6] 129 1 T39 21 T178 15 T85 42
wkup[7] 246 1 T39 24 T96 31 T138 15
wkup[8] 218 1 T108 21 T120 30 T146 15
wkup[9] 190 1 T39 21 T48 15 T156 21
wkup[10] 183 1 T28 21 T41 21 T71 21
wkup[11] 163 1 T96 21 T78 8 T121 21
wkup[12] 180 1 T154 15 T43 15 T120 21
wkup[13] 114 1 T16 15 T22 21 T110 15
wkup[14] 221 1 T24 21 T136 30 T97 21
wkup[15] 180 1 T47 15 T42 21 T73 26
wkup[16] 78 1 T42 21 T22 21 T94 15
wkup[17] 178 1 T24 21 T43 21 T118 15
wkup[18] 117 1 T24 15 T72 21 T109 60
wkup[19] 228 1 T126 21 T78 6 T136 30
wkup[20] 144 1 T2 15 T21 21 T131 15
wkup[21] 251 1 T9 15 T18 21 T97 21
wkup[22] 232 1 T127 15 T86 8 T81 21
wkup[23] 290 1 T10 8 T18 6 T43 15
wkup[24] 99 1 T10 21 T21 21 T136 30
wkup[25] 78 1 T150 15 T85 21 T102 6
wkup[26] 149 1 T28 30 T71 21 T187 6
wkup[27] 87 1 T29 15 T28 21 T41 15
wkup[28] 192 1 T103 21 T72 21 T143 21
wkup[29] 292 1 T39 21 T40 26 T91 42
wkup[30] 219 1 T42 21 T96 21 T97 21
wkup[31] 295 1 T45 15 T39 8 T21 21
wkup[32] 187 1 T151 15 T28 42 T39 31
wkup[33] 372 1 T8 15 T103 21 T119 30
wkup[34] 215 1 T149 21 T119 26 T85 21
wkup[35] 202 1 T170 15 T73 21 T86 26
wkup[36] 168 1 T86 21 T85 30 T123 24
wkup[37] 264 1 T21 24 T167 15 T149 15
wkup[38] 144 1 T46 15 T126 21 T119 30
wkup[39] 134 1 T136 15 T152 15 T73 6
wkup[40] 157 1 T40 26 T118 21 T136 21
wkup[41] 207 1 T10 73 T22 30 T149 21
wkup[42] 239 1 T168 15 T78 21 T119 26
wkup[43] 213 1 T106 15 T148 21 T136 21
wkup[44] 198 1 T24 30 T126 21 T156 21
wkup[45] 98 1 T10 15 T160 15 T23 21
wkup[46] 238 1 T103 21 T156 47 T136 30
wkup[47] 178 1 T42 21 T78 26 T72 21
wkup[48] 220 1 T97 56 T85 30 T134 51
wkup[49] 162 1 T22 21 T162 21 T85 15
wkup[50] 335 1 T10 21 T27 15 T18 30
wkup[51] 109 1 T78 15 T125 21 T79 56
wkup[52] 171 1 T39 21 T149 21 T103 15
wkup[53] 93 1 T10 30 T97 21 T161 21
wkup[54] 44 1 T41 21 T114 15 T149 8
wkup[55] 234 1 T41 21 T96 21 T108 21
wkup[56] 291 1 T21 21 T149 21 T148 41
wkup[57] 182 1 T28 21 T22 21 T71 21
wkup[58] 185 1 T18 21 T71 26 T148 21
wkup[59] 92 1 T15 8 T24 21 T134 21
wkup[60] 257 1 T28 26 T39 26 T21 21
wkup[61] 141 1 T128 21 T129 47 T104 21
wkup[62] 194 1 T96 21 T149 30 T73 30
wkup[63] 185 1 T4 15 T28 21 T39 21
wkup_0 3614 1 T1 5 T2 5 T3 5

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