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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.31 99.32 95.61 100.00 98.38 99.51 43.07


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T30 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3641793976 Sep 24 09:34:49 PM UTC 24 Sep 24 09:35:01 PM UTC 24 4401865309 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.888993002 Sep 24 09:34:58 PM UTC 24 Sep 24 09:35:01 PM UTC 24 335895835 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2150120469 Sep 24 09:35:02 PM UTC 24 Sep 24 09:35:04 PM UTC 24 627645149 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3489539246 Sep 24 09:34:59 PM UTC 24 Sep 24 09:35:04 PM UTC 24 645411732 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2570402315 Sep 24 09:35:02 PM UTC 24 Sep 24 09:35:04 PM UTC 24 1304173645 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3971620193 Sep 24 09:35:04 PM UTC 24 Sep 24 09:35:06 PM UTC 24 300750075 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.2397979164 Sep 24 09:35:03 PM UTC 24 Sep 24 09:35:06 PM UTC 24 510753216 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2499500412 Sep 24 09:35:03 PM UTC 24 Sep 24 09:35:07 PM UTC 24 1060822865 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3530282099 Sep 24 09:35:05 PM UTC 24 Sep 24 09:35:08 PM UTC 24 743148359 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2131453563 Sep 24 09:35:05 PM UTC 24 Sep 24 09:35:08 PM UTC 24 383396847 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.3983444496 Sep 24 09:35:05 PM UTC 24 Sep 24 09:35:09 PM UTC 24 519046028 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.541103977 Sep 24 09:35:06 PM UTC 24 Sep 24 09:35:09 PM UTC 24 523216766 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1366895355 Sep 24 09:35:03 PM UTC 24 Sep 24 09:35:10 PM UTC 24 8115786352 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2138546702 Sep 24 09:35:07 PM UTC 24 Sep 24 09:35:10 PM UTC 24 461630113 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2568083207 Sep 24 09:35:07 PM UTC 24 Sep 24 09:35:11 PM UTC 24 1493915975 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.1288245728 Sep 24 09:35:09 PM UTC 24 Sep 24 09:35:11 PM UTC 24 305438740 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.478422044 Sep 24 09:35:05 PM UTC 24 Sep 24 09:35:13 PM UTC 24 5838587814 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.948608093 Sep 24 09:35:11 PM UTC 24 Sep 24 09:35:13 PM UTC 24 550332637 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1039425567 Sep 24 09:35:11 PM UTC 24 Sep 24 09:35:13 PM UTC 24 468551394 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.2800433476 Sep 24 09:35:10 PM UTC 24 Sep 24 09:35:13 PM UTC 24 493776757 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2601587432 Sep 24 09:34:59 PM UTC 24 Sep 24 09:35:13 PM UTC 24 13062478138 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.281250457 Sep 24 09:35:08 PM UTC 24 Sep 24 09:35:13 PM UTC 24 387338505 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3878374332 Sep 24 09:35:12 PM UTC 24 Sep 24 09:35:14 PM UTC 24 425185233 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3351873123 Sep 24 09:35:13 PM UTC 24 Sep 24 09:35:16 PM UTC 24 467667864 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.788610919 Sep 24 09:35:11 PM UTC 24 Sep 24 09:35:16 PM UTC 24 1085832058 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.1924552638 Sep 24 09:35:14 PM UTC 24 Sep 24 09:35:16 PM UTC 24 433453699 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.421483047 Sep 24 09:35:14 PM UTC 24 Sep 24 09:35:16 PM UTC 24 318720412 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.919463297 Sep 24 09:35:12 PM UTC 24 Sep 24 09:35:17 PM UTC 24 7036366039 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.966406056 Sep 24 09:35:14 PM UTC 24 Sep 24 09:35:18 PM UTC 24 432601464 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.473252671 Sep 24 09:35:15 PM UTC 24 Sep 24 09:35:18 PM UTC 24 449397731 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.3232289721 Sep 24 09:35:14 PM UTC 24 Sep 24 09:35:18 PM UTC 24 333034644 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1630152681 Sep 24 09:35:15 PM UTC 24 Sep 24 09:35:19 PM UTC 24 989013807 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1782206819 Sep 24 09:35:08 PM UTC 24 Sep 24 09:35:19 PM UTC 24 4338731700 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2519362860 Sep 24 09:35:17 PM UTC 24 Sep 24 09:35:19 PM UTC 24 493017340 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4048325907 Sep 24 09:35:17 PM UTC 24 Sep 24 09:35:20 PM UTC 24 1398764608 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2098531625 Sep 24 09:35:18 PM UTC 24 Sep 24 09:35:21 PM UTC 24 439336289 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2356966008 Sep 24 09:35:19 PM UTC 24 Sep 24 09:35:22 PM UTC 24 466669014 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3414570803 Sep 24 09:35:19 PM UTC 24 Sep 24 09:35:22 PM UTC 24 336617263 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.2631181333 Sep 24 09:35:19 PM UTC 24 Sep 24 09:35:22 PM UTC 24 513390356 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.267167652 Sep 24 09:35:20 PM UTC 24 Sep 24 09:35:23 PM UTC 24 522964351 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.4090037299 Sep 24 09:35:18 PM UTC 24 Sep 24 09:35:23 PM UTC 24 415327717 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.223974813 Sep 24 09:35:20 PM UTC 24 Sep 24 09:35:23 PM UTC 24 420578435 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2966622492 Sep 24 09:35:20 PM UTC 24 Sep 24 09:35:24 PM UTC 24 954530459 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.172348165 Sep 24 09:35:22 PM UTC 24 Sep 24 09:35:24 PM UTC 24 469328612 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.4263791373 Sep 24 09:35:22 PM UTC 24 Sep 24 09:35:24 PM UTC 24 429189359 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.4263627094 Sep 24 09:35:23 PM UTC 24 Sep 24 09:35:25 PM UTC 24 300330318 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3928197680 Sep 24 09:35:12 PM UTC 24 Sep 24 09:35:25 PM UTC 24 2877433984 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.4266333814 Sep 24 09:35:23 PM UTC 24 Sep 24 09:35:25 PM UTC 24 524965425 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2929325267 Sep 24 09:35:24 PM UTC 24 Sep 24 09:35:26 PM UTC 24 501154574 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1722107169 Sep 24 09:35:21 PM UTC 24 Sep 24 09:35:26 PM UTC 24 1364846293 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.4191599229 Sep 24 09:35:24 PM UTC 24 Sep 24 09:35:26 PM UTC 24 321499542 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.1119958668 Sep 24 09:35:24 PM UTC 24 Sep 24 09:35:27 PM UTC 24 422923367 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1109502699 Sep 24 09:35:23 PM UTC 24 Sep 24 09:35:27 PM UTC 24 4619992052 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.514694500 Sep 24 09:35:24 PM UTC 24 Sep 24 09:35:27 PM UTC 24 1387101928 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.2026078657 Sep 24 09:35:25 PM UTC 24 Sep 24 09:35:27 PM UTC 24 531902664 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3856104749 Sep 24 09:35:25 PM UTC 24 Sep 24 09:35:28 PM UTC 24 432061207 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3004008825 Sep 24 09:35:24 PM UTC 24 Sep 24 09:35:28 PM UTC 24 532282173 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.4005529321 Sep 24 09:35:25 PM UTC 24 Sep 24 09:35:29 PM UTC 24 445356006 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.2458120331 Sep 24 09:35:25 PM UTC 24 Sep 24 09:35:29 PM UTC 24 332837896 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.3703073782 Sep 24 09:35:27 PM UTC 24 Sep 24 09:35:30 PM UTC 24 714912032 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2264697089 Sep 24 09:35:27 PM UTC 24 Sep 24 09:35:30 PM UTC 24 376611507 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.254773591 Sep 24 09:35:28 PM UTC 24 Sep 24 09:35:30 PM UTC 24 425026255 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3768418482 Sep 24 09:35:28 PM UTC 24 Sep 24 09:35:31 PM UTC 24 1250784320 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2037435379 Sep 24 09:35:24 PM UTC 24 Sep 24 09:35:31 PM UTC 24 8718909806 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2723879196 Sep 24 09:35:27 PM UTC 24 Sep 24 09:35:31 PM UTC 24 2272150492 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2062552542 Sep 24 09:35:29 PM UTC 24 Sep 24 09:35:31 PM UTC 24 417761731 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.3267025145 Sep 24 09:35:28 PM UTC 24 Sep 24 09:35:31 PM UTC 24 456714917 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.3448702297 Sep 24 09:35:29 PM UTC 24 Sep 24 09:35:31 PM UTC 24 535644704 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.1404999885 Sep 24 09:35:29 PM UTC 24 Sep 24 09:35:32 PM UTC 24 527626060 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1663482571 Sep 24 09:35:29 PM UTC 24 Sep 24 09:35:33 PM UTC 24 397386821 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3214587001 Sep 24 09:35:30 PM UTC 24 Sep 24 09:35:33 PM UTC 24 493201584 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.2429195166 Sep 24 09:35:31 PM UTC 24 Sep 24 09:35:33 PM UTC 24 348894218 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.2337262186 Sep 24 09:35:31 PM UTC 24 Sep 24 09:35:34 PM UTC 24 478348157 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3436756523 Sep 24 09:35:20 PM UTC 24 Sep 24 09:35:34 PM UTC 24 7175300712 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.2008443704 Sep 24 09:35:50 PM UTC 24 Sep 24 09:35:51 PM UTC 24 303861668 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3752006143 Sep 24 09:35:24 PM UTC 24 Sep 24 09:35:34 PM UTC 24 2461344081 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3293991212 Sep 24 09:35:27 PM UTC 24 Sep 24 09:35:35 PM UTC 24 3915703538 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1041270101 Sep 24 09:35:31 PM UTC 24 Sep 24 09:35:35 PM UTC 24 5186913801 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1660914477 Sep 24 09:35:29 PM UTC 24 Sep 24 09:35:35 PM UTC 24 4078152552 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.2468402650 Sep 24 09:35:30 PM UTC 24 Sep 24 09:35:35 PM UTC 24 1091276790 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4137888087 Sep 24 09:35:14 PM UTC 24 Sep 24 09:35:35 PM UTC 24 7534224147 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.3396949660 Sep 24 09:35:33 PM UTC 24 Sep 24 09:35:35 PM UTC 24 517969224 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1930485721 Sep 24 09:35:33 PM UTC 24 Sep 24 09:35:36 PM UTC 24 472833339 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1639877605 Sep 24 09:35:34 PM UTC 24 Sep 24 09:35:36 PM UTC 24 2490869132 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3221951021 Sep 24 09:35:33 PM UTC 24 Sep 24 09:35:36 PM UTC 24 1242248496 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2630118670 Sep 24 09:35:30 PM UTC 24 Sep 24 09:35:36 PM UTC 24 1374279243 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.3835653023 Sep 24 09:35:34 PM UTC 24 Sep 24 09:35:36 PM UTC 24 327148115 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4101205620 Sep 24 09:35:34 PM UTC 24 Sep 24 09:35:37 PM UTC 24 462257732 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2717548242 Sep 24 09:35:35 PM UTC 24 Sep 24 09:35:37 PM UTC 24 445968759 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.212761966 Sep 24 09:35:19 PM UTC 24 Sep 24 09:35:37 PM UTC 24 7900796458 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.222573088 Sep 24 09:35:35 PM UTC 24 Sep 24 09:35:37 PM UTC 24 578758945 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.1681921145 Sep 24 09:35:33 PM UTC 24 Sep 24 09:35:37 PM UTC 24 354671344 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4284529243 Sep 24 09:35:35 PM UTC 24 Sep 24 09:35:38 PM UTC 24 1785461902 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.1086412513 Sep 24 09:35:35 PM UTC 24 Sep 24 09:35:38 PM UTC 24 338334343 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1386464694 Sep 24 09:35:44 PM UTC 24 Sep 24 09:35:51 PM UTC 24 8563290038 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.3552409144 Sep 24 09:35:49 PM UTC 24 Sep 24 09:35:51 PM UTC 24 460316981 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1860106092 Sep 24 09:35:25 PM UTC 24 Sep 24 09:35:38 PM UTC 24 4154342300 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.2269271380 Sep 24 09:35:35 PM UTC 24 Sep 24 09:35:39 PM UTC 24 734912547 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3752652254 Sep 24 09:35:36 PM UTC 24 Sep 24 09:35:39 PM UTC 24 341245987 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.81346075 Sep 24 09:35:36 PM UTC 24 Sep 24 09:35:39 PM UTC 24 279840010 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.3159518639 Sep 24 09:35:36 PM UTC 24 Sep 24 09:35:39 PM UTC 24 430897238 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3262180676 Sep 24 09:35:45 PM UTC 24 Sep 24 09:35:51 PM UTC 24 2111613126 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1154920705 Sep 24 09:35:36 PM UTC 24 Sep 24 09:35:39 PM UTC 24 1641330046 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.4176649237 Sep 24 09:35:38 PM UTC 24 Sep 24 09:35:40 PM UTC 24 366415299 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1047854056 Sep 24 09:35:38 PM UTC 24 Sep 24 09:35:40 PM UTC 24 414660769 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.1436288276 Sep 24 09:35:38 PM UTC 24 Sep 24 09:35:40 PM UTC 24 359261374 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.3610794680 Sep 24 09:35:39 PM UTC 24 Sep 24 09:35:41 PM UTC 24 280987189 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1362557664 Sep 24 09:35:39 PM UTC 24 Sep 24 09:35:41 PM UTC 24 540490761 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.324293650 Sep 24 09:35:39 PM UTC 24 Sep 24 09:35:42 PM UTC 24 526017044 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.106489594 Sep 24 09:35:38 PM UTC 24 Sep 24 09:35:42 PM UTC 24 1654328492 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2591821191 Sep 24 09:35:38 PM UTC 24 Sep 24 09:35:42 PM UTC 24 2242001047 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.532879458 Sep 24 09:35:40 PM UTC 24 Sep 24 09:35:43 PM UTC 24 416650263 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.885375914 Sep 24 09:35:40 PM UTC 24 Sep 24 09:35:43 PM UTC 24 506160873 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3270376917 Sep 24 09:35:40 PM UTC 24 Sep 24 09:35:43 PM UTC 24 438156257 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3294740654 Sep 24 09:35:33 PM UTC 24 Sep 24 09:35:43 PM UTC 24 4234567754 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.251013829 Sep 24 09:35:40 PM UTC 24 Sep 24 09:35:43 PM UTC 24 3391879840 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.1001284548 Sep 24 09:35:40 PM UTC 24 Sep 24 09:35:43 PM UTC 24 318257754 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2591114021 Sep 24 09:35:39 PM UTC 24 Sep 24 09:35:43 PM UTC 24 4058626866 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1070650351 Sep 24 09:35:41 PM UTC 24 Sep 24 09:35:44 PM UTC 24 384949302 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3996945616 Sep 24 09:35:36 PM UTC 24 Sep 24 09:35:44 PM UTC 24 4408681305 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3238056267 Sep 24 09:35:40 PM UTC 24 Sep 24 09:35:44 PM UTC 24 4416800538 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.2093728822 Sep 24 09:35:39 PM UTC 24 Sep 24 09:35:45 PM UTC 24 571832541 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.1626947324 Sep 24 09:35:41 PM UTC 24 Sep 24 09:35:45 PM UTC 24 427927140 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.342794091 Sep 24 09:35:43 PM UTC 24 Sep 24 09:35:45 PM UTC 24 299719184 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.3072716283 Sep 24 09:35:43 PM UTC 24 Sep 24 09:35:46 PM UTC 24 453437560 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1135550669 Sep 24 09:35:44 PM UTC 24 Sep 24 09:35:46 PM UTC 24 427044732 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1066326061 Sep 24 09:35:41 PM UTC 24 Sep 24 09:35:46 PM UTC 24 1316702353 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.1537114828 Sep 24 09:35:44 PM UTC 24 Sep 24 09:35:46 PM UTC 24 290997907 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1374075066 Sep 24 09:35:44 PM UTC 24 Sep 24 09:35:47 PM UTC 24 1352450374 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3975495017 Sep 24 09:35:44 PM UTC 24 Sep 24 09:35:47 PM UTC 24 577816161 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.1694757189 Sep 24 09:35:44 PM UTC 24 Sep 24 09:35:47 PM UTC 24 279129525 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.2715305964 Sep 24 09:35:44 PM UTC 24 Sep 24 09:35:48 PM UTC 24 358300627 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.3624572160 Sep 24 09:35:45 PM UTC 24 Sep 24 09:35:48 PM UTC 24 374837388 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1987658578 Sep 24 09:35:17 PM UTC 24 Sep 24 09:35:48 PM UTC 24 13022301558 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.334099096 Sep 24 09:35:46 PM UTC 24 Sep 24 09:35:48 PM UTC 24 359179065 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2475055294 Sep 24 09:35:46 PM UTC 24 Sep 24 09:35:49 PM UTC 24 313886630 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.1244664907 Sep 24 09:35:47 PM UTC 24 Sep 24 09:35:49 PM UTC 24 369956999 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.481457782 Sep 24 09:35:47 PM UTC 24 Sep 24 09:35:49 PM UTC 24 432720674 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.2940860199 Sep 24 09:35:45 PM UTC 24 Sep 24 09:35:49 PM UTC 24 483325489 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2328709358 Sep 24 09:35:35 PM UTC 24 Sep 24 09:35:49 PM UTC 24 4392339674 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.2913841931 Sep 24 09:35:47 PM UTC 24 Sep 24 09:35:49 PM UTC 24 326024091 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.3959299523 Sep 24 09:35:45 PM UTC 24 Sep 24 09:35:49 PM UTC 24 498657891 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3792071900 Sep 24 09:35:45 PM UTC 24 Sep 24 09:35:50 PM UTC 24 4106338695 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.2718452302 Sep 24 09:35:48 PM UTC 24 Sep 24 09:35:50 PM UTC 24 476613288 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.2745763352 Sep 24 09:35:48 PM UTC 24 Sep 24 09:35:50 PM UTC 24 397824647 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.4066013436 Sep 24 09:35:48 PM UTC 24 Sep 24 09:35:50 PM UTC 24 475448308 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.3268869192 Sep 24 09:35:48 PM UTC 24 Sep 24 09:35:50 PM UTC 24 330634753 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.2918825965 Sep 24 09:35:48 PM UTC 24 Sep 24 09:35:51 PM UTC 24 364358746 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3107862057 Sep 24 09:35:43 PM UTC 24 Sep 24 09:35:51 PM UTC 24 2714113136 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.529947285 Sep 24 09:35:49 PM UTC 24 Sep 24 09:35:51 PM UTC 24 470623487 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3552669776 Sep 24 09:35:49 PM UTC 24 Sep 24 09:35:51 PM UTC 24 534350227 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.12676993 Sep 24 09:35:49 PM UTC 24 Sep 24 09:35:51 PM UTC 24 404512897 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3252195356 Sep 24 09:35:49 PM UTC 24 Sep 24 09:35:52 PM UTC 24 528220656 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1895145441 Sep 24 09:35:43 PM UTC 24 Sep 24 09:35:52 PM UTC 24 4020318400 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.4280000162 Sep 24 09:35:49 PM UTC 24 Sep 24 09:35:52 PM UTC 24 471155639 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.900759945 Sep 24 09:35:49 PM UTC 24 Sep 24 09:35:52 PM UTC 24 300178360 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.2007758295 Sep 24 09:35:49 PM UTC 24 Sep 24 09:35:52 PM UTC 24 373549176 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.4119304298 Sep 24 09:35:51 PM UTC 24 Sep 24 09:35:53 PM UTC 24 425432146 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.3882808579 Sep 24 09:35:51 PM UTC 24 Sep 24 09:35:53 PM UTC 24 419616378 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.4016086269 Sep 24 09:35:51 PM UTC 24 Sep 24 09:35:53 PM UTC 24 488110575 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.1816653326 Sep 24 09:35:51 PM UTC 24 Sep 24 09:35:53 PM UTC 24 299727932 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1259384314 Sep 24 09:35:51 PM UTC 24 Sep 24 09:35:53 PM UTC 24 450979564 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.1652208960 Sep 24 09:35:51 PM UTC 24 Sep 24 09:35:53 PM UTC 24 498628348 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.3111250795 Sep 24 09:35:51 PM UTC 24 Sep 24 09:35:53 PM UTC 24 512476803 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.4263425851 Sep 24 09:35:52 PM UTC 24 Sep 24 09:35:54 PM UTC 24 456724462 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.4286032853 Sep 24 09:35:52 PM UTC 24 Sep 24 09:35:54 PM UTC 24 373864235 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.618234320 Sep 24 09:35:52 PM UTC 24 Sep 24 09:35:54 PM UTC 24 539477050 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.1828712656 Sep 24 09:35:52 PM UTC 24 Sep 24 09:35:54 PM UTC 24 503477611 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.2808652510 Sep 24 09:35:52 PM UTC 24 Sep 24 09:35:55 PM UTC 24 287899269 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.147550696 Sep 24 09:35:38 PM UTC 24 Sep 24 09:35:56 PM UTC 24 8057224949 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.3837431087
Short name T2
Test name
Test status
Simulation time 578495654 ps
CPU time 2.32 seconds
Started Sep 24 09:29:37 PM UTC 24
Finished Sep 24 09:29:40 PM UTC 24
Peak memory 205756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837431087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3837431087
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.3354310787
Short name T10
Test name
Test status
Simulation time 20688060179 ps
CPU time 26.38 seconds
Started Sep 24 09:29:40 PM UTC 24
Finished Sep 24 09:30:08 PM UTC 24
Peak memory 216360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3354310787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.aon_timer_stress_all_with_rand_reset.3354310787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.2620053141
Short name T22
Test name
Test status
Simulation time 69618730354 ps
CPU time 17.36 seconds
Started Sep 24 09:31:06 PM UTC 24
Finished Sep 24 09:31:25 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620053141 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.2620053141
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3641793976
Short name T30
Test name
Test status
Simulation time 4401865309 ps
CPU time 11.25 seconds
Started Sep 24 09:34:49 PM UTC 24
Finished Sep 24 09:35:01 PM UTC 24
Peak memory 205764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641793976 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.3641793976
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.697862529
Short name T73
Test name
Test status
Simulation time 22412185591 ps
CPU time 39.5 seconds
Started Sep 24 09:32:39 PM UTC 24
Finished Sep 24 09:33:20 PM UTC 24
Peak memory 207284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=697862529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 27.aon_timer_stress_all_with_rand_reset.697862529
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.1475487776
Short name T24
Test name
Test status
Simulation time 10042745216 ps
CPU time 14.46 seconds
Started Sep 24 09:30:32 PM UTC 24
Finished Sep 24 09:30:48 PM UTC 24
Peak memory 223268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1475487776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 6.aon_timer_stress_all_with_rand_reset.1475487776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2601587432
Short name T54
Test name
Test status
Simulation time 13062478138 ps
CPU time 12.61 seconds
Started Sep 24 09:34:59 PM UTC 24
Finished Sep 24 09:35:13 PM UTC 24
Peak memory 205968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601587432 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.2601587432
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.1504253719
Short name T96
Test name
Test status
Simulation time 49543979355 ps
CPU time 41.79 seconds
Started Sep 24 09:31:11 PM UTC 24
Finished Sep 24 09:31:54 PM UTC 24
Peak memory 207220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504253719 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.1504253719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.3345019181
Short name T79
Test name
Test status
Simulation time 71583462519 ps
CPU time 108.25 seconds
Started Sep 24 09:32:06 PM UTC 24
Finished Sep 24 09:33:56 PM UTC 24
Peak memory 207164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345019181 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.3345019181
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/21.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.3369920873
Short name T85
Test name
Test status
Simulation time 65424360127 ps
CPU time 30.64 seconds
Started Sep 24 09:33:03 PM UTC 24
Finished Sep 24 09:33:35 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369920873 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.3369920873
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/32.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.606540675
Short name T77
Test name
Test status
Simulation time 77325921786 ps
CPU time 150.02 seconds
Started Sep 24 09:34:14 PM UTC 24
Finished Sep 24 09:36:47 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606540675 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.606540675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/44.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.208787044
Short name T11
Test name
Test status
Simulation time 7761796409 ps
CPU time 13.57 seconds
Started Sep 24 09:29:42 PM UTC 24
Finished Sep 24 09:29:57 PM UTC 24
Peak memory 234604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208787044 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.208787044
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.1362765073
Short name T112
Test name
Test status
Simulation time 27592217130 ps
CPU time 42.7 seconds
Started Sep 24 09:34:35 PM UTC 24
Finished Sep 24 09:35:19 PM UTC 24
Peak memory 216488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1362765073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 48.aon_timer_stress_all_with_rand_reset.1362765073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.3834917793
Short name T130
Test name
Test status
Simulation time 165620690278 ps
CPU time 300.86 seconds
Started Sep 24 09:31:38 PM UTC 24
Finished Sep 24 09:36:43 PM UTC 24
Peak memory 207188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834917793 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.3834917793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.3553960256
Short name T111
Test name
Test status
Simulation time 65738811792 ps
CPU time 60.87 seconds
Started Sep 24 09:34:21 PM UTC 24
Finished Sep 24 09:35:23 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553960256 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.3553960256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/46.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.2009938085
Short name T109
Test name
Test status
Simulation time 178486601359 ps
CPU time 105.71 seconds
Started Sep 24 09:31:32 PM UTC 24
Finished Sep 24 09:33:20 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009938085 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.2009938085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.2879979650
Short name T122
Test name
Test status
Simulation time 188552723428 ps
CPU time 55.97 seconds
Started Sep 24 09:33:31 PM UTC 24
Finished Sep 24 09:34:29 PM UTC 24
Peak memory 207188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879979650 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.2879979650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/36.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.239552799
Short name T95
Test name
Test status
Simulation time 75864047606 ps
CPU time 55.89 seconds
Started Sep 24 09:34:07 PM UTC 24
Finished Sep 24 09:35:05 PM UTC 24
Peak memory 207240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239552799 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.239552799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/42.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.3833950253
Short name T129
Test name
Test status
Simulation time 16817637008 ps
CPU time 44.58 seconds
Started Sep 24 09:34:11 PM UTC 24
Finished Sep 24 09:34:57 PM UTC 24
Peak memory 223520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3833950253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 43.aon_timer_stress_all_with_rand_reset.3833950253
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.2728118914
Short name T104
Test name
Test status
Simulation time 169944840299 ps
CPU time 332.64 seconds
Started Sep 24 09:30:17 PM UTC 24
Finished Sep 24 09:35:54 PM UTC 24
Peak memory 207060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728118914 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.2728118914
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.3008536753
Short name T134
Test name
Test status
Simulation time 6822265908 ps
CPU time 50.47 seconds
Started Sep 24 09:32:49 PM UTC 24
Finished Sep 24 09:33:41 PM UTC 24
Peak memory 222880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3008536753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.aon_timer_stress_all_with_rand_reset.3008536753
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.1235461718
Short name T41
Test name
Test status
Simulation time 8085617010 ps
CPU time 41.48 seconds
Started Sep 24 09:30:34 PM UTC 24
Finished Sep 24 09:31:17 PM UTC 24
Peak memory 207480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1235461718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 7.aon_timer_stress_all_with_rand_reset.1235461718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.1445108502
Short name T137
Test name
Test status
Simulation time 7961377357 ps
CPU time 42.93 seconds
Started Sep 24 09:34:17 PM UTC 24
Finished Sep 24 09:35:02 PM UTC 24
Peak memory 222984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1445108502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 45.aon_timer_stress_all_with_rand_reset.1445108502
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.3537652266
Short name T97
Test name
Test status
Simulation time 11667994294 ps
CPU time 37.67 seconds
Started Sep 24 09:32:10 PM UTC 24
Finished Sep 24 09:32:49 PM UTC 24
Peak memory 207380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3537652266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 22.aon_timer_stress_all_with_rand_reset.3537652266
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.270900372
Short name T119
Test name
Test status
Simulation time 4317568661 ps
CPU time 10.62 seconds
Started Sep 24 09:32:33 PM UTC 24
Finished Sep 24 09:32:45 PM UTC 24
Peak memory 207088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270900372 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.270900372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/26.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.945440135
Short name T72
Test name
Test status
Simulation time 8558041214 ps
CPU time 20.01 seconds
Started Sep 24 09:32:24 PM UTC 24
Finished Sep 24 09:32:45 PM UTC 24
Peak memory 207464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=945440135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 25.aon_timer_stress_all_with_rand_reset.945440135
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.2485057868
Short name T86
Test name
Test status
Simulation time 5179833733 ps
CPU time 52.43 seconds
Started Sep 24 09:32:31 PM UTC 24
Finished Sep 24 09:33:25 PM UTC 24
Peak memory 216332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2485057868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 26.aon_timer_stress_all_with_rand_reset.2485057868
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.533635003
Short name T93
Test name
Test status
Simulation time 9059869150 ps
CPU time 21.08 seconds
Started Sep 24 09:34:01 PM UTC 24
Finished Sep 24 09:34:23 PM UTC 24
Peak memory 223068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=533635003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 41.aon_timer_stress_all_with_rand_reset.533635003
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.3515128693
Short name T120
Test name
Test status
Simulation time 9481026589 ps
CPU time 32.59 seconds
Started Sep 24 09:32:20 PM UTC 24
Finished Sep 24 09:32:54 PM UTC 24
Peak memory 216320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3515128693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 24.aon_timer_stress_all_with_rand_reset.3515128693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.1442792312
Short name T76
Test name
Test status
Simulation time 136031370434 ps
CPU time 270.84 seconds
Started Sep 24 09:32:50 PM UTC 24
Finished Sep 24 09:37:25 PM UTC 24
Peak memory 207088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442792312 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.1442792312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/29.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.2669042833
Short name T121
Test name
Test status
Simulation time 12382464710 ps
CPU time 22.6 seconds
Started Sep 24 09:33:43 PM UTC 24
Finished Sep 24 09:34:07 PM UTC 24
Peak memory 216272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2669042833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 39.aon_timer_stress_all_with_rand_reset.2669042833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.2530374107
Short name T107
Test name
Test status
Simulation time 112025654383 ps
CPU time 162.71 seconds
Started Sep 24 09:34:37 PM UTC 24
Finished Sep 24 09:37:23 PM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530374107 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.2530374107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/48.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.2368777069
Short name T46
Test name
Test status
Simulation time 663830695 ps
CPU time 1 seconds
Started Sep 24 09:30:49 PM UTC 24
Finished Sep 24 09:30:51 PM UTC 24
Peak memory 205312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368777069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2368777069
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.384715997
Short name T102
Test name
Test status
Simulation time 4225778309 ps
CPU time 27.66 seconds
Started Sep 24 09:34:14 PM UTC 24
Finished Sep 24 09:34:43 PM UTC 24
Peak memory 222824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=384715997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 44.aon_timer_stress_all_with_rand_reset.384715997
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.944513964
Short name T126
Test name
Test status
Simulation time 231165237521 ps
CPU time 103.6 seconds
Started Sep 24 09:30:27 PM UTC 24
Finished Sep 24 09:32:12 PM UTC 24
Peak memory 207108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944513964 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.944513964
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.3053353547
Short name T39
Test name
Test status
Simulation time 6710124455 ps
CPU time 24.47 seconds
Started Sep 24 09:30:41 PM UTC 24
Finished Sep 24 09:31:07 PM UTC 24
Peak memory 223184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3053353547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 8.aon_timer_stress_all_with_rand_reset.3053353547
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.1517614640
Short name T88
Test name
Test status
Simulation time 181243935872 ps
CPU time 69.11 seconds
Started Sep 24 09:34:12 PM UTC 24
Finished Sep 24 09:35:23 PM UTC 24
Peak memory 207096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517614640 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.1517614640
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/43.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.3782514319
Short name T136
Test name
Test status
Simulation time 26689354309 ps
CPU time 84.88 seconds
Started Sep 24 09:31:19 PM UTC 24
Finished Sep 24 09:32:46 PM UTC 24
Peak memory 222780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3782514319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 13.aon_timer_stress_all_with_rand_reset.3782514319
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.3109218536
Short name T21
Test name
Test status
Simulation time 44831104806 ps
CPU time 70.88 seconds
Started Sep 24 09:30:01 PM UTC 24
Finished Sep 24 09:31:14 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109218536 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.3109218536
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.2331402829
Short name T100
Test name
Test status
Simulation time 380457608307 ps
CPU time 599.63 seconds
Started Sep 24 09:33:36 PM UTC 24
Finished Sep 24 09:43:42 PM UTC 24
Peak memory 207100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331402829 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.2331402829
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/37.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.3594424004
Short name T105
Test name
Test status
Simulation time 58421852673 ps
CPU time 111.83 seconds
Started Sep 24 09:33:54 PM UTC 24
Finished Sep 24 09:35:48 PM UTC 24
Peak memory 207224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594424004 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.3594424004
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/40.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.2539408312
Short name T103
Test name
Test status
Simulation time 238650484882 ps
CPU time 104.01 seconds
Started Sep 24 09:30:32 PM UTC 24
Finished Sep 24 09:32:18 PM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539408312 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.2539408312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.3087380954
Short name T117
Test name
Test status
Simulation time 129223545468 ps
CPU time 55.28 seconds
Started Sep 24 09:33:11 PM UTC 24
Finished Sep 24 09:34:08 PM UTC 24
Peak memory 207164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087380954 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.3087380954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/33.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.195522531
Short name T128
Test name
Test status
Simulation time 97527276909 ps
CPU time 79.66 seconds
Started Sep 24 09:33:19 PM UTC 24
Finished Sep 24 09:34:41 PM UTC 24
Peak memory 207244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195522531 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.195522531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/34.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.882287801
Short name T161
Test name
Test status
Simulation time 13856905148 ps
CPU time 34.07 seconds
Started Sep 24 09:34:25 PM UTC 24
Finished Sep 24 09:35:01 PM UTC 24
Peak memory 216420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=882287801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 47.aon_timer_stress_all_with_rand_reset.882287801
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.1610253842
Short name T98
Test name
Test status
Simulation time 162158644688 ps
CPU time 309.64 seconds
Started Sep 24 09:29:50 PM UTC 24
Finished Sep 24 09:35:04 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610253842 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.1610253842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.2617746295
Short name T125
Test name
Test status
Simulation time 50687458859 ps
CPU time 82.44 seconds
Started Sep 24 09:31:23 PM UTC 24
Finished Sep 24 09:32:47 PM UTC 24
Peak memory 207188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617746295 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.2617746295
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.334036839
Short name T80
Test name
Test status
Simulation time 108081878456 ps
CPU time 248.13 seconds
Started Sep 24 09:31:58 PM UTC 24
Finished Sep 24 09:36:10 PM UTC 24
Peak memory 207220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334036839 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.334036839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/20.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.517290092
Short name T90
Test name
Test status
Simulation time 246747342098 ps
CPU time 445.86 seconds
Started Sep 24 09:32:55 PM UTC 24
Finished Sep 24 09:40:27 PM UTC 24
Peak memory 207088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517290092 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.517290092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/31.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.4180447785
Short name T81
Test name
Test status
Simulation time 9383614323 ps
CPU time 23.75 seconds
Started Sep 24 09:33:38 PM UTC 24
Finished Sep 24 09:34:03 PM UTC 24
Peak memory 223260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4180447785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 38.aon_timer_stress_all_with_rand_reset.4180447785
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.2613934718
Short name T115
Test name
Test status
Simulation time 131611399871 ps
CPU time 216.94 seconds
Started Sep 24 09:33:44 PM UTC 24
Finished Sep 24 09:37:25 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613934718 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.2613934718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/39.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.3545377729
Short name T140
Test name
Test status
Simulation time 124303104507 ps
CPU time 221.51 seconds
Started Sep 24 09:34:25 PM UTC 24
Finished Sep 24 09:38:10 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545377729 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.3545377729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/47.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.5884154
Short name T123
Test name
Test status
Simulation time 97050846273 ps
CPU time 178 seconds
Started Sep 24 09:30:52 PM UTC 24
Finished Sep 24 09:33:53 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5884154 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.5884154
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2570402315
Short name T32
Test name
Test status
Simulation time 1304173645 ps
CPU time 1.73 seconds
Started Sep 24 09:35:02 PM UTC 24
Finished Sep 24 09:35:04 PM UTC 24
Peak memory 201892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570402315 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.2570402315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.218760101
Short name T143
Test name
Test status
Simulation time 3465512885 ps
CPU time 32.28 seconds
Started Sep 24 09:33:10 PM UTC 24
Finished Sep 24 09:33:44 PM UTC 24
Peak memory 223724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=218760101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.aon_timer_stress_all_with_rand_reset.218760101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.3538419959
Short name T144
Test name
Test status
Simulation time 3021793583 ps
CPU time 31.07 seconds
Started Sep 24 09:34:44 PM UTC 24
Finished Sep 24 09:35:16 PM UTC 24
Peak memory 223852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3538419959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 49.aon_timer_stress_all_with_rand_reset.3538419959
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.2739854401
Short name T118
Test name
Test status
Simulation time 141235278116 ps
CPU time 32.09 seconds
Started Sep 24 09:31:20 PM UTC 24
Finished Sep 24 09:31:53 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739854401 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.2739854401
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.1250102314
Short name T74
Test name
Test status
Simulation time 2885384904 ps
CPU time 26.75 seconds
Started Sep 24 09:32:55 PM UTC 24
Finished Sep 24 09:33:23 PM UTC 24
Peak memory 223420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1250102314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 31.aon_timer_stress_all_with_rand_reset.1250102314
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.3876973103
Short name T42
Test name
Test status
Simulation time 14257447747 ps
CPU time 30.15 seconds
Started Sep 24 09:30:50 PM UTC 24
Finished Sep 24 09:31:22 PM UTC 24
Peak memory 207576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3876973103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 9.aon_timer_stress_all_with_rand_reset.3876973103
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.1805380777
Short name T114
Test name
Test status
Simulation time 376250872 ps
CPU time 1.17 seconds
Started Sep 24 09:31:31 PM UTC 24
Finished Sep 24 09:31:33 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805380777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1805380777
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.3603374083
Short name T108
Test name
Test status
Simulation time 4122279419 ps
CPU time 39.32 seconds
Started Sep 24 09:31:32 PM UTC 24
Finished Sep 24 09:32:13 PM UTC 24
Peak memory 223768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3603374083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 16.aon_timer_stress_all_with_rand_reset.3603374083
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.1821724874
Short name T94
Test name
Test status
Simulation time 516005728 ps
CPU time 1.65 seconds
Started Sep 24 09:32:45 PM UTC 24
Finished Sep 24 09:32:48 PM UTC 24
Peak memory 205792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821724874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1821724874
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/28.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.1887095234
Short name T23
Test name
Test status
Simulation time 83712313828 ps
CPU time 64.71 seconds
Started Sep 24 09:30:43 PM UTC 24
Finished Sep 24 09:31:50 PM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887095234 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.1887095234
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.675652309
Short name T110
Test name
Test status
Simulation time 426676756 ps
CPU time 1.98 seconds
Started Sep 24 09:31:25 PM UTC 24
Finished Sep 24 09:31:28 PM UTC 24
Peak memory 205792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675652309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.675652309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.2941072417
Short name T149
Test name
Test status
Simulation time 10048666906 ps
CPU time 24.79 seconds
Started Sep 24 09:31:45 PM UTC 24
Finished Sep 24 09:32:12 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2941072417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 18.aon_timer_stress_all_with_rand_reset.2941072417
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.3026754523
Short name T142
Test name
Test status
Simulation time 160352250362 ps
CPU time 290.44 seconds
Started Sep 24 09:32:21 PM UTC 24
Finished Sep 24 09:37:16 PM UTC 24
Peak memory 207232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026754523 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.3026754523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/24.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.3350328696
Short name T156
Test name
Test status
Simulation time 94124666269 ps
CPU time 15.26 seconds
Started Sep 24 09:32:25 PM UTC 24
Finished Sep 24 09:32:42 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350328696 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.3350328696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/25.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.3360557979
Short name T113
Test name
Test status
Simulation time 51079366142 ps
CPU time 106.81 seconds
Started Sep 24 09:33:39 PM UTC 24
Finished Sep 24 09:35:28 PM UTC 24
Peak memory 207248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360557979 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.3360557979
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/38.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.523565118
Short name T40
Test name
Test status
Simulation time 6893578834 ps
CPU time 51.55 seconds
Started Sep 24 09:30:15 PM UTC 24
Finished Sep 24 09:31:08 PM UTC 24
Peak memory 207464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=523565118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 4.aon_timer_stress_all_with_rand_reset.523565118
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.2242370482
Short name T83
Test name
Test status
Simulation time 480437353 ps
CPU time 1.16 seconds
Started Sep 24 09:33:52 PM UTC 24
Finished Sep 24 09:33:55 PM UTC 24
Peak memory 205792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242370482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2242370482
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/40.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.2847309602
Short name T75
Test name
Test status
Simulation time 3967151678 ps
CPU time 19.16 seconds
Started Sep 24 09:33:54 PM UTC 24
Finished Sep 24 09:34:14 PM UTC 24
Peak memory 223740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2847309602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 40.aon_timer_stress_all_with_rand_reset.2847309602
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.822580878
Short name T155
Test name
Test status
Simulation time 225147438620 ps
CPU time 400.72 seconds
Started Sep 24 09:29:41 PM UTC 24
Finished Sep 24 09:36:27 PM UTC 24
Peak memory 207108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822580878 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.822580878
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.3163751040
Short name T4
Test name
Test status
Simulation time 575140981 ps
CPU time 2.66 seconds
Started Sep 24 09:29:46 PM UTC 24
Finished Sep 24 09:29:49 PM UTC 24
Peak memory 205908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163751040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3163751040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.3348350101
Short name T159
Test name
Test status
Simulation time 374606517723 ps
CPU time 142.83 seconds
Started Sep 24 09:31:53 PM UTC 24
Finished Sep 24 09:34:18 PM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348350101 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.3348350101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/19.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.2174176101
Short name T78
Test name
Test status
Simulation time 2031891141 ps
CPU time 23.03 seconds
Started Sep 24 09:32:06 PM UTC 24
Finished Sep 24 09:32:30 PM UTC 24
Peak memory 207336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2174176101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 21.aon_timer_stress_all_with_rand_reset.2174176101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.2793929917
Short name T138
Test name
Test status
Simulation time 388866477 ps
CPU time 1.87 seconds
Started Sep 24 09:32:13 PM UTC 24
Finished Sep 24 09:32:16 PM UTC 24
Peak memory 205376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793929917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2793929917
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/23.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.1032427619
Short name T132
Test name
Test status
Simulation time 545453733 ps
CPU time 1.06 seconds
Started Sep 24 09:33:00 PM UTC 24
Finished Sep 24 09:33:02 PM UTC 24
Peak memory 205844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032427619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1032427619
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/32.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.857627129
Short name T91
Test name
Test status
Simulation time 15016822849 ps
CPU time 18.01 seconds
Started Sep 24 09:33:18 PM UTC 24
Finished Sep 24 09:33:38 PM UTC 24
Peak memory 223032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=857627129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 34.aon_timer_stress_all_with_rand_reset.857627129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.1033472871
Short name T116
Test name
Test status
Simulation time 494927248 ps
CPU time 1.11 seconds
Started Sep 24 09:34:19 PM UTC 24
Finished Sep 24 09:34:22 PM UTC 24
Peak memory 205792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033472871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1033472871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/46.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.4294696276
Short name T28
Test name
Test status
Simulation time 4589742321 ps
CPU time 23.71 seconds
Started Sep 24 09:30:25 PM UTC 24
Finished Sep 24 09:30:50 PM UTC 24
Peak memory 216248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4294696276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 5.aon_timer_stress_all_with_rand_reset.4294696276
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.3341462605
Short name T29
Test name
Test status
Simulation time 543424145 ps
CPU time 2.51 seconds
Started Sep 24 09:30:29 PM UTC 24
Finished Sep 24 09:30:32 PM UTC 24
Peak memory 205844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341462605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3341462605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.582789694
Short name T45
Test name
Test status
Simulation time 473234531 ps
CPU time 2.46 seconds
Started Sep 24 09:30:39 PM UTC 24
Finished Sep 24 09:30:42 PM UTC 24
Peak memory 205904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582789694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.582789694
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.1250451652
Short name T82
Test name
Test status
Simulation time 624092583958 ps
CPU time 1144.97 seconds
Started Sep 24 09:32:42 PM UTC 24
Finished Sep 24 09:52:00 PM UTC 24
Peak memory 207076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250451652 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.1250451652
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/27.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.3962835574
Short name T99
Test name
Test status
Simulation time 413142600 ps
CPU time 1.28 seconds
Started Sep 24 09:33:38 PM UTC 24
Finished Sep 24 09:33:40 PM UTC 24
Peak memory 205788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962835574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3962835574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/38.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.1686818792
Short name T89
Test name
Test status
Simulation time 467220552 ps
CPU time 1.05 seconds
Started Sep 24 09:34:10 PM UTC 24
Finished Sep 24 09:34:13 PM UTC 24
Peak memory 205792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686818792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1686818792
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/43.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.3430714592
Short name T70
Test name
Test status
Simulation time 7455370521 ps
CPU time 18.64 seconds
Started Sep 24 09:31:25 PM UTC 24
Finished Sep 24 09:31:45 PM UTC 24
Peak memory 216272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3430714592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 15.aon_timer_stress_all_with_rand_reset.3430714592
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.342942054
Short name T135
Test name
Test status
Simulation time 502866501 ps
CPU time 2.32 seconds
Started Sep 24 09:32:03 PM UTC 24
Finished Sep 24 09:32:06 PM UTC 24
Peak memory 205708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342942054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.342942054
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/21.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.253055615
Short name T127
Test name
Test status
Simulation time 458978672 ps
CPU time 1.21 seconds
Started Sep 24 09:32:49 PM UTC 24
Finished Sep 24 09:32:51 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253055615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.253055615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/29.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.3911925563
Short name T124
Test name
Test status
Simulation time 495991810 ps
CPU time 1.07 seconds
Started Sep 24 09:34:14 PM UTC 24
Finished Sep 24 09:34:16 PM UTC 24
Peak memory 205316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911925563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3911925563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/44.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.2905964059
Short name T133
Test name
Test status
Simulation time 193391323654 ps
CPU time 269.23 seconds
Started Sep 24 09:30:37 PM UTC 24
Finished Sep 24 09:35:11 PM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905964059 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.2905964059
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.958424421
Short name T106
Test name
Test status
Simulation time 400326477 ps
CPU time 0.99 seconds
Started Sep 24 09:31:22 PM UTC 24
Finished Sep 24 09:31:24 PM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958424421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.958424421
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.2915267165
Short name T71
Test name
Test status
Simulation time 15253610007 ps
CPU time 33.71 seconds
Started Sep 24 09:31:23 PM UTC 24
Finished Sep 24 09:31:58 PM UTC 24
Peak memory 222944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2915267165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 14.aon_timer_stress_all_with_rand_reset.2915267165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.3229449461
Short name T179
Test name
Test status
Simulation time 181994385279 ps
CPU time 322.82 seconds
Started Sep 24 09:31:26 PM UTC 24
Finished Sep 24 09:36:54 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229449461 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.3229449461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.1281769807
Short name T84
Test name
Test status
Simulation time 513365714 ps
CPU time 2.32 seconds
Started Sep 24 09:31:35 PM UTC 24
Finished Sep 24 09:31:38 PM UTC 24
Peak memory 205720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281769807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1281769807
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.3067797554
Short name T131
Test name
Test status
Simulation time 609658438 ps
CPU time 0.96 seconds
Started Sep 24 09:31:50 PM UTC 24
Finished Sep 24 09:31:52 PM UTC 24
Peak memory 205372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067797554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3067797554
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/19.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.1049794307
Short name T148
Test name
Test status
Simulation time 3200069582 ps
CPU time 21.26 seconds
Started Sep 24 09:31:56 PM UTC 24
Finished Sep 24 09:32:19 PM UTC 24
Peak memory 207388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1049794307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 20.aon_timer_stress_all_with_rand_reset.1049794307
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.2146996698
Short name T139
Test name
Test status
Simulation time 419154241 ps
CPU time 1.53 seconds
Started Sep 24 09:32:39 PM UTC 24
Finished Sep 24 09:32:41 PM UTC 24
Peak memory 205192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146996698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2146996698
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/27.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.4125608897
Short name T87
Test name
Test status
Simulation time 392807237 ps
CPU time 1.51 seconds
Started Sep 24 09:33:30 PM UTC 24
Finished Sep 24 09:33:33 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125608897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.4125608897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/36.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.212402025
Short name T147
Test name
Test status
Simulation time 30939773571 ps
CPU time 78.09 seconds
Started Sep 24 09:34:02 PM UTC 24
Finished Sep 24 09:35:22 PM UTC 24
Peak memory 207108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212402025 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.212402025
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/41.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.1388741800
Short name T43
Test name
Test status
Simulation time 2659424953 ps
CPU time 18.52 seconds
Started Sep 24 09:31:06 PM UTC 24
Finished Sep 24 09:31:26 PM UTC 24
Peak memory 216192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1388741800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.aon_timer_stress_all_with_rand_reset.1388741800
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.2090831157
Short name T160
Test name
Test status
Simulation time 491843409 ps
CPU time 1.64 seconds
Started Sep 24 09:31:15 PM UTC 24
Finished Sep 24 09:31:18 PM UTC 24
Peak memory 203864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090831157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2090831157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/12.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.3050382537
Short name T101
Test name
Test status
Simulation time 411711827 ps
CPU time 1.16 seconds
Started Sep 24 09:31:42 PM UTC 24
Finished Sep 24 09:31:45 PM UTC 24
Peak memory 205792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050382537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3050382537
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.3060975081
Short name T170
Test name
Test status
Simulation time 667218261 ps
CPU time 1.06 seconds
Started Sep 24 09:32:20 PM UTC 24
Finished Sep 24 09:32:22 PM UTC 24
Peak memory 205316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060975081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3060975081
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/24.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.2987003458
Short name T180
Test name
Test status
Simulation time 361303036666 ps
CPU time 182.66 seconds
Started Sep 24 09:32:53 PM UTC 24
Finished Sep 24 09:35:59 PM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987003458 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.2987003458
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/30.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.1283928684
Short name T163
Test name
Test status
Simulation time 9622328375 ps
CPU time 33.39 seconds
Started Sep 24 09:32:52 PM UTC 24
Finished Sep 24 09:33:27 PM UTC 24
Peak memory 216260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1283928684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.aon_timer_stress_all_with_rand_reset.1283928684
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.3017993979
Short name T164
Test name
Test status
Simulation time 5029733005 ps
CPU time 27.58 seconds
Started Sep 24 09:33:31 PM UTC 24
Finished Sep 24 09:34:00 PM UTC 24
Peak memory 216336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3017993979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 36.aon_timer_stress_all_with_rand_reset.3017993979
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.2369356620
Short name T173
Test name
Test status
Simulation time 608464184 ps
CPU time 1.47 seconds
Started Sep 24 09:33:34 PM UTC 24
Finished Sep 24 09:33:37 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369356620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2369356620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/37.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1109502699
Short name T184
Test name
Test status
Simulation time 4619992052 ps
CPU time 2.92 seconds
Started Sep 24 09:35:23 PM UTC 24
Finished Sep 24 09:35:27 PM UTC 24
Peak memory 206464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109502699 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.1109502699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.3971756590
Short name T167
Test name
Test status
Simulation time 376697776 ps
CPU time 2.31 seconds
Started Sep 24 09:32:07 PM UTC 24
Finished Sep 24 09:32:10 PM UTC 24
Peak memory 205712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971756590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3971756590
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/22.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.2518241086
Short name T183
Test name
Test status
Simulation time 523450423026 ps
CPU time 238.1 seconds
Started Sep 24 09:32:11 PM UTC 24
Finished Sep 24 09:36:13 PM UTC 24
Peak memory 207232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518241086 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.2518241086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/22.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.1503426704
Short name T168
Test name
Test status
Simulation time 546068900 ps
CPU time 1.72 seconds
Started Sep 24 09:32:24 PM UTC 24
Finished Sep 24 09:32:27 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503426704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1503426704
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/25.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.3350275212
Short name T150
Test name
Test status
Simulation time 497648212 ps
CPU time 1.36 seconds
Started Sep 24 09:32:30 PM UTC 24
Finished Sep 24 09:32:33 PM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350275212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3350275212
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/26.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.92597160
Short name T9
Test name
Test status
Simulation time 357640535 ps
CPU time 1.43 seconds
Started Sep 24 09:30:05 PM UTC 24
Finished Sep 24 09:30:07 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92597160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.92597160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.2964662724
Short name T157
Test name
Test status
Simulation time 265840277578 ps
CPU time 456.01 seconds
Started Sep 24 09:30:06 PM UTC 24
Finished Sep 24 09:37:47 PM UTC 24
Peak memory 207108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964662724 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.2964662724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.1346953344
Short name T146
Test name
Test status
Simulation time 419050704 ps
CPU time 1.18 seconds
Started Sep 24 09:33:16 PM UTC 24
Finished Sep 24 09:33:19 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346953344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1346953344
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/34.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.1432565561
Short name T166
Test name
Test status
Simulation time 478895793 ps
CPU time 1.26 seconds
Started Sep 24 09:33:24 PM UTC 24
Finished Sep 24 09:33:26 PM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432565561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1432565561
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/35.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.3476474546
Short name T153
Test name
Test status
Simulation time 508209849116 ps
CPU time 474.1 seconds
Started Sep 24 09:33:26 PM UTC 24
Finished Sep 24 09:41:26 PM UTC 24
Peak memory 207096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476474546 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.3476474546
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/35.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.1686719394
Short name T27
Test name
Test status
Simulation time 512605374 ps
CPU time 1.14 seconds
Started Sep 24 09:30:12 PM UTC 24
Finished Sep 24 09:30:14 PM UTC 24
Peak memory 205844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686719394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1686719394
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.3391583579
Short name T169
Test name
Test status
Simulation time 591803199 ps
CPU time 2.93 seconds
Started Sep 24 09:34:15 PM UTC 24
Finished Sep 24 09:34:19 PM UTC 24
Peak memory 205328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391583579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3391583579
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/45.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.1297498201
Short name T174
Test name
Test status
Simulation time 7165172921 ps
CPU time 52.44 seconds
Started Sep 24 09:34:21 PM UTC 24
Finished Sep 24 09:35:15 PM UTC 24
Peak memory 207464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1297498201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 46.aon_timer_stress_all_with_rand_reset.1297498201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.1454695399
Short name T176
Test name
Test status
Simulation time 483670071 ps
CPU time 1.51 seconds
Started Sep 24 09:34:24 PM UTC 24
Finished Sep 24 09:34:27 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454695399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1454695399
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/47.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.2437561847
Short name T177
Test name
Test status
Simulation time 483314515 ps
CPU time 1.31 seconds
Started Sep 24 09:34:32 PM UTC 24
Finished Sep 24 09:34:35 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437561847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2437561847
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/48.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.2593262631
Short name T16
Test name
Test status
Simulation time 612063390 ps
CPU time 1.15 seconds
Started Sep 24 09:30:25 PM UTC 24
Finished Sep 24 09:30:27 PM UTC 24
Peak memory 205428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593262631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2593262631
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.3719755872
Short name T18
Test name
Test status
Simulation time 15845301988 ps
CPU time 44.04 seconds
Started Sep 24 09:29:46 PM UTC 24
Finished Sep 24 09:30:31 PM UTC 24
Peak memory 216276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3719755872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 1.aon_timer_stress_all_with_rand_reset.3719755872
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.2851839846
Short name T47
Test name
Test status
Simulation time 497035108 ps
CPU time 1.34 seconds
Started Sep 24 09:31:02 PM UTC 24
Finished Sep 24 09:31:05 PM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851839846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2851839846
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.4191197630
Short name T48
Test name
Test status
Simulation time 605136632 ps
CPU time 1.29 seconds
Started Sep 24 09:31:09 PM UTC 24
Finished Sep 24 09:31:11 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191197630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4191197630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.2450607674
Short name T154
Test name
Test status
Simulation time 415295942 ps
CPU time 2.25 seconds
Started Sep 24 09:31:19 PM UTC 24
Finished Sep 24 09:31:22 PM UTC 24
Peak memory 205784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450607674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2450607674
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.2110798499
Short name T178
Test name
Test status
Simulation time 454344724 ps
CPU time 1.16 seconds
Started Sep 24 09:31:56 PM UTC 24
Finished Sep 24 09:31:58 PM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110798499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2110798499
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/20.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.2819939334
Short name T162
Test name
Test status
Simulation time 3834907688 ps
CPU time 4.08 seconds
Started Sep 24 09:32:46 PM UTC 24
Finished Sep 24 09:32:52 PM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819939334 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.2819939334
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/28.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.3626862064
Short name T145
Test name
Test status
Simulation time 528425677 ps
CPU time 1.33 seconds
Started Sep 24 09:32:52 PM UTC 24
Finished Sep 24 09:32:54 PM UTC 24
Peak memory 205432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626862064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3626862064
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/30.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.3597174219
Short name T182
Test name
Test status
Simulation time 378795726 ps
CPU time 2.16 seconds
Started Sep 24 09:32:54 PM UTC 24
Finished Sep 24 09:32:57 PM UTC 24
Peak memory 205712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597174219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3597174219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/31.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.2051499145
Short name T152
Test name
Test status
Simulation time 484635680 ps
CPU time 1.28 seconds
Started Sep 24 09:33:08 PM UTC 24
Finished Sep 24 09:33:10 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051499145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2051499145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/33.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.1552383472
Short name T171
Test name
Test status
Simulation time 10736304579 ps
CPU time 16.93 seconds
Started Sep 24 09:33:34 PM UTC 24
Finished Sep 24 09:33:53 PM UTC 24
Peak memory 222744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1552383472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 37.aon_timer_stress_all_with_rand_reset.1552383472
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.2661988148
Short name T92
Test name
Test status
Simulation time 561921944 ps
CPU time 1.25 seconds
Started Sep 24 09:33:42 PM UTC 24
Finished Sep 24 09:33:44 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661988148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2661988148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/39.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.2008784318
Short name T181
Test name
Test status
Simulation time 467960796 ps
CPU time 1.62 seconds
Started Sep 24 09:34:00 PM UTC 24
Finished Sep 24 09:34:03 PM UTC 24
Peak memory 205848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008784318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2008784318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/41.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.296898507
Short name T165
Test name
Test status
Simulation time 5668401275 ps
CPU time 14.85 seconds
Started Sep 24 09:34:07 PM UTC 24
Finished Sep 24 09:34:24 PM UTC 24
Peak memory 207056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=296898507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 42.aon_timer_stress_all_with_rand_reset.296898507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.4154234502
Short name T151
Test name
Test status
Simulation time 596925985 ps
CPU time 2.81 seconds
Started Sep 24 09:30:34 PM UTC 24
Finished Sep 24 09:30:38 PM UTC 24
Peak memory 205900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154234502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.4154234502
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3489539246
Short name T38
Test name
Test status
Simulation time 645411732 ps
CPU time 3.8 seconds
Started Sep 24 09:34:59 PM UTC 24
Finished Sep 24 09:35:04 PM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489539246 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.3489539246
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2616385787
Short name T36
Test name
Test status
Simulation time 870204265 ps
CPU time 2.17 seconds
Started Sep 24 09:34:57 PM UTC 24
Finished Sep 24 09:35:00 PM UTC 24
Peak memory 201144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616385787 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.2616385787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2150120469
Short name T37
Test name
Test status
Simulation time 627645149 ps
CPU time 1.4 seconds
Started Sep 24 09:35:02 PM UTC 24
Finished Sep 24 09:35:04 PM UTC 24
Peak memory 206940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2150120469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_csr_mem_rw_with_rand_reset.2150120469
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.888993002
Short name T31
Test name
Test status
Simulation time 335895835 ps
CPU time 2.11 seconds
Started Sep 24 09:34:58 PM UTC 24
Finished Sep 24 09:35:01 PM UTC 24
Peak memory 201200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888993002 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.888993002
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.3393505734
Short name T278
Test name
Test status
Simulation time 512402127 ps
CPU time 1.34 seconds
Started Sep 24 09:34:52 PM UTC 24
Finished Sep 24 09:34:54 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393505734 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3393505734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3953799030
Short name T279
Test name
Test status
Simulation time 407778973 ps
CPU time 1.41 seconds
Started Sep 24 09:34:55 PM UTC 24
Finished Sep 24 09:34:58 PM UTC 24
Peak memory 199844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953799030 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.3953799030
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.4074603114
Short name T280
Test name
Test status
Simulation time 457330409 ps
CPU time 2.65 seconds
Started Sep 24 09:34:55 PM UTC 24
Finished Sep 24 09:34:59 PM UTC 24
Peak memory 201316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074603114 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.4074603114
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.274784027
Short name T277
Test name
Test status
Simulation time 515251896 ps
CPU time 3.75 seconds
Started Sep 24 09:34:47 PM UTC 24
Finished Sep 24 09:34:52 PM UTC 24
Peak memory 207160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274784027 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.274784027
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.541103977
Short name T52
Test name
Test status
Simulation time 523216766 ps
CPU time 2.19 seconds
Started Sep 24 09:35:06 PM UTC 24
Finished Sep 24 09:35:09 PM UTC 24
Peak memory 205284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541103977 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.541103977
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.478422044
Short name T53
Test name
Test status
Simulation time 5838587814 ps
CPU time 6.33 seconds
Started Sep 24 09:35:05 PM UTC 24
Finished Sep 24 09:35:13 PM UTC 24
Peak memory 206024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478422044 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.478422044
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3530282099
Short name T69
Test name
Test status
Simulation time 743148359 ps
CPU time 1.53 seconds
Started Sep 24 09:35:05 PM UTC 24
Finished Sep 24 09:35:08 PM UTC 24
Peak memory 199724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530282099 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.3530282099
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2138546702
Short name T197
Test name
Test status
Simulation time 461630113 ps
CPU time 1.9 seconds
Started Sep 24 09:35:07 PM UTC 24
Finished Sep 24 09:35:10 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2138546702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_csr_mem_rw_with_rand_reset.2138546702
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.3983444496
Short name T51
Test name
Test status
Simulation time 519046028 ps
CPU time 2.64 seconds
Started Sep 24 09:35:05 PM UTC 24
Finished Sep 24 09:35:09 PM UTC 24
Peak memory 203304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983444496 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3983444496
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.2397979164
Short name T282
Test name
Test status
Simulation time 510753216 ps
CPU time 2.63 seconds
Started Sep 24 09:35:03 PM UTC 24
Finished Sep 24 09:35:06 PM UTC 24
Peak memory 201448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397979164 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2397979164
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2131453563
Short name T284
Test name
Test status
Simulation time 383396847 ps
CPU time 1.75 seconds
Started Sep 24 09:35:05 PM UTC 24
Finished Sep 24 09:35:08 PM UTC 24
Peak memory 199844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131453563 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.2131453563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3971620193
Short name T281
Test name
Test status
Simulation time 300750075 ps
CPU time 1.08 seconds
Started Sep 24 09:35:04 PM UTC 24
Finished Sep 24 09:35:06 PM UTC 24
Peak memory 199712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971620193 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.3971620193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2568083207
Short name T63
Test name
Test status
Simulation time 1493915975 ps
CPU time 2.29 seconds
Started Sep 24 09:35:07 PM UTC 24
Finished Sep 24 09:35:11 PM UTC 24
Peak memory 203372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568083207 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.2568083207
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.2499500412
Short name T283
Test name
Test status
Simulation time 1060822865 ps
CPU time 3.63 seconds
Started Sep 24 09:35:03 PM UTC 24
Finished Sep 24 09:35:07 PM UTC 24
Peak memory 207060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499500412 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2499500412
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1366895355
Short name T34
Test name
Test status
Simulation time 8115786352 ps
CPU time 5.94 seconds
Started Sep 24 09:35:03 PM UTC 24
Finished Sep 24 09:35:10 PM UTC 24
Peak memory 207316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366895355 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.1366895355
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1930485721
Short name T336
Test name
Test status
Simulation time 472833339 ps
CPU time 1.92 seconds
Started Sep 24 09:35:33 PM UTC 24
Finished Sep 24 09:35:36 PM UTC 24
Peak memory 205052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1930485721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_ti
mer_csr_mem_rw_with_rand_reset.1930485721
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.2337262186
Short name T327
Test name
Test status
Simulation time 478348157 ps
CPU time 1.13 seconds
Started Sep 24 09:35:31 PM UTC 24
Finished Sep 24 09:35:34 PM UTC 24
Peak memory 199692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337262186 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2337262186
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.2429195166
Short name T326
Test name
Test status
Simulation time 348894218 ps
CPU time 1.02 seconds
Started Sep 24 09:35:31 PM UTC 24
Finished Sep 24 09:35:33 PM UTC 24
Peak memory 199732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429195166 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2429195166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3221951021
Short name T338
Test name
Test status
Simulation time 1242248496 ps
CPU time 2.61 seconds
Started Sep 24 09:35:33 PM UTC 24
Finished Sep 24 09:35:36 PM UTC 24
Peak memory 203372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221951021 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.3221951021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.2468402650
Short name T333
Test name
Test status
Simulation time 1091276790 ps
CPU time 3.5 seconds
Started Sep 24 09:35:30 PM UTC 24
Finished Sep 24 09:35:35 PM UTC 24
Peak memory 207084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468402650 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2468402650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1041270101
Short name T331
Test name
Test status
Simulation time 5186913801 ps
CPU time 2.18 seconds
Started Sep 24 09:35:31 PM UTC 24
Finished Sep 24 09:35:35 PM UTC 24
Peak memory 205436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041270101 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.1041270101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4101205620
Short name T341
Test name
Test status
Simulation time 462257732 ps
CPU time 1.63 seconds
Started Sep 24 09:35:34 PM UTC 24
Finished Sep 24 09:35:37 PM UTC 24
Peak memory 203824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4101205620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_ti
mer_csr_mem_rw_with_rand_reset.4101205620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.3835653023
Short name T340
Test name
Test status
Simulation time 327148115 ps
CPU time 1.48 seconds
Started Sep 24 09:35:34 PM UTC 24
Finished Sep 24 09:35:36 PM UTC 24
Peak memory 201764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835653023 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3835653023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.3396949660
Short name T335
Test name
Test status
Simulation time 517969224 ps
CPU time 1.6 seconds
Started Sep 24 09:35:33 PM UTC 24
Finished Sep 24 09:35:35 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396949660 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3396949660
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1639877605
Short name T337
Test name
Test status
Simulation time 2490869132 ps
CPU time 1.12 seconds
Started Sep 24 09:35:34 PM UTC 24
Finished Sep 24 09:35:36 PM UTC 24
Peak memory 203908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639877605 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.1639877605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.1681921145
Short name T345
Test name
Test status
Simulation time 354671344 ps
CPU time 3.8 seconds
Started Sep 24 09:35:33 PM UTC 24
Finished Sep 24 09:35:37 PM UTC 24
Peak memory 207056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681921145 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1681921145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3294740654
Short name T368
Test name
Test status
Simulation time 4234567754 ps
CPU time 9.2 seconds
Started Sep 24 09:35:33 PM UTC 24
Finished Sep 24 09:35:43 PM UTC 24
Peak memory 206652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294740654 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.3294740654
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.222573088
Short name T344
Test name
Test status
Simulation time 578758945 ps
CPU time 1.23 seconds
Started Sep 24 09:35:35 PM UTC 24
Finished Sep 24 09:35:37 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=222573088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_tim
er_csr_mem_rw_with_rand_reset.222573088
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2717548242
Short name T342
Test name
Test status
Simulation time 445968759 ps
CPU time 0.83 seconds
Started Sep 24 09:35:35 PM UTC 24
Finished Sep 24 09:35:37 PM UTC 24
Peak memory 201764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717548242 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2717548242
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.1086412513
Short name T347
Test name
Test status
Simulation time 338334343 ps
CPU time 1.78 seconds
Started Sep 24 09:35:35 PM UTC 24
Finished Sep 24 09:35:38 PM UTC 24
Peak memory 201756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086412513 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1086412513
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/12.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4284529243
Short name T346
Test name
Test status
Simulation time 1785461902 ps
CPU time 1.34 seconds
Started Sep 24 09:35:35 PM UTC 24
Finished Sep 24 09:35:38 PM UTC 24
Peak memory 201952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284529243 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.4284529243
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.2269271380
Short name T351
Test name
Test status
Simulation time 734912547 ps
CPU time 2.6 seconds
Started Sep 24 09:35:35 PM UTC 24
Finished Sep 24 09:35:39 PM UTC 24
Peak memory 207276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269271380 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2269271380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2328709358
Short name T391
Test name
Test status
Simulation time 4392339674 ps
CPU time 12.64 seconds
Started Sep 24 09:35:35 PM UTC 24
Finished Sep 24 09:35:49 PM UTC 24
Peak memory 205944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328709358 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.2328709358
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1047854056
Short name T358
Test name
Test status
Simulation time 414660769 ps
CPU time 1.48 seconds
Started Sep 24 09:35:38 PM UTC 24
Finished Sep 24 09:35:40 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1047854056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti
mer_csr_mem_rw_with_rand_reset.1047854056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.81346075
Short name T353
Test name
Test status
Simulation time 279840010 ps
CPU time 1.31 seconds
Started Sep 24 09:35:36 PM UTC 24
Finished Sep 24 09:35:39 PM UTC 24
Peak memory 201824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81346075 -assert nopostproc +UVM_TESTNAME=aon_
timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.81346075
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.3159518639
Short name T354
Test name
Test status
Simulation time 430897238 ps
CPU time 1.48 seconds
Started Sep 24 09:35:36 PM UTC 24
Finished Sep 24 09:35:39 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159518639 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3159518639
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1154920705
Short name T356
Test name
Test status
Simulation time 1641330046 ps
CPU time 1.59 seconds
Started Sep 24 09:35:36 PM UTC 24
Finished Sep 24 09:35:39 PM UTC 24
Peak memory 201952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154920705 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.1154920705
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3752652254
Short name T352
Test name
Test status
Simulation time 341245987 ps
CPU time 1.36 seconds
Started Sep 24 09:35:36 PM UTC 24
Finished Sep 24 09:35:39 PM UTC 24
Peak memory 206924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752652254 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3752652254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3996945616
Short name T373
Test name
Test status
Simulation time 4408681305 ps
CPU time 6.71 seconds
Started Sep 24 09:35:36 PM UTC 24
Finished Sep 24 09:35:44 PM UTC 24
Peak memory 205440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996945616 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.3996945616
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1362557664
Short name T361
Test name
Test status
Simulation time 540490761 ps
CPU time 1.57 seconds
Started Sep 24 09:35:39 PM UTC 24
Finished Sep 24 09:35:41 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1362557664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_ti
mer_csr_mem_rw_with_rand_reset.1362557664
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.4176649237
Short name T357
Test name
Test status
Simulation time 366415299 ps
CPU time 0.99 seconds
Started Sep 24 09:35:38 PM UTC 24
Finished Sep 24 09:35:40 PM UTC 24
Peak memory 199716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176649237 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.4176649237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.1436288276
Short name T359
Test name
Test status
Simulation time 359261374 ps
CPU time 1.35 seconds
Started Sep 24 09:35:38 PM UTC 24
Finished Sep 24 09:35:40 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436288276 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1436288276
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2591821191
Short name T364
Test name
Test status
Simulation time 2242001047 ps
CPU time 2.94 seconds
Started Sep 24 09:35:38 PM UTC 24
Finished Sep 24 09:35:42 PM UTC 24
Peak memory 205412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591821191 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.2591821191
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.106489594
Short name T363
Test name
Test status
Simulation time 1654328492 ps
CPU time 3.18 seconds
Started Sep 24 09:35:38 PM UTC 24
Finished Sep 24 09:35:42 PM UTC 24
Peak memory 207152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106489594 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.106489594
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.147550696
Short name T420
Test name
Test status
Simulation time 8057224949 ps
CPU time 17.2 seconds
Started Sep 24 09:35:38 PM UTC 24
Finished Sep 24 09:35:56 PM UTC 24
Peak memory 207056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147550696 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.147550696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3270376917
Short name T367
Test name
Test status
Simulation time 438156257 ps
CPU time 1.74 seconds
Started Sep 24 09:35:40 PM UTC 24
Finished Sep 24 09:35:43 PM UTC 24
Peak memory 203936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3270376917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti
mer_csr_mem_rw_with_rand_reset.3270376917
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.324293650
Short name T362
Test name
Test status
Simulation time 526017044 ps
CPU time 1.56 seconds
Started Sep 24 09:35:39 PM UTC 24
Finished Sep 24 09:35:42 PM UTC 24
Peak memory 201824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324293650 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.324293650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.3610794680
Short name T360
Test name
Test status
Simulation time 280987189 ps
CPU time 0.95 seconds
Started Sep 24 09:35:39 PM UTC 24
Finished Sep 24 09:35:41 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610794680 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3610794680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.251013829
Short name T369
Test name
Test status
Simulation time 3391879840 ps
CPU time 1.92 seconds
Started Sep 24 09:35:40 PM UTC 24
Finished Sep 24 09:35:43 PM UTC 24
Peak memory 204004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251013829 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.251013829
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.2093728822
Short name T375
Test name
Test status
Simulation time 571832541 ps
CPU time 4.67 seconds
Started Sep 24 09:35:39 PM UTC 24
Finished Sep 24 09:35:45 PM UTC 24
Peak memory 207120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093728822 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2093728822
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2591114021
Short name T371
Test name
Test status
Simulation time 4058626866 ps
CPU time 3.45 seconds
Started Sep 24 09:35:39 PM UTC 24
Finished Sep 24 09:35:43 PM UTC 24
Peak memory 206484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591114021 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.2591114021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1070650351
Short name T372
Test name
Test status
Simulation time 384949302 ps
CPU time 1.36 seconds
Started Sep 24 09:35:41 PM UTC 24
Finished Sep 24 09:35:44 PM UTC 24
Peak memory 205584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1070650351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti
mer_csr_mem_rw_with_rand_reset.1070650351
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.532879458
Short name T365
Test name
Test status
Simulation time 416650263 ps
CPU time 1.28 seconds
Started Sep 24 09:35:40 PM UTC 24
Finished Sep 24 09:35:43 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532879458 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.532879458
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.1001284548
Short name T370
Test name
Test status
Simulation time 318257754 ps
CPU time 2 seconds
Started Sep 24 09:35:40 PM UTC 24
Finished Sep 24 09:35:43 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001284548 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1001284548
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1066326061
Short name T379
Test name
Test status
Simulation time 1316702353 ps
CPU time 3.8 seconds
Started Sep 24 09:35:41 PM UTC 24
Finished Sep 24 09:35:46 PM UTC 24
Peak memory 203308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066326061 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.1066326061
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.885375914
Short name T366
Test name
Test status
Simulation time 506160873 ps
CPU time 1.6 seconds
Started Sep 24 09:35:40 PM UTC 24
Finished Sep 24 09:35:43 PM UTC 24
Peak memory 205284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885375914 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.885375914
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3238056267
Short name T374
Test name
Test status
Simulation time 4416800538 ps
CPU time 3.26 seconds
Started Sep 24 09:35:40 PM UTC 24
Finished Sep 24 09:35:44 PM UTC 24
Peak memory 206228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238056267 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.3238056267
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1135550669
Short name T378
Test name
Test status
Simulation time 427044732 ps
CPU time 1.22 seconds
Started Sep 24 09:35:44 PM UTC 24
Finished Sep 24 09:35:46 PM UTC 24
Peak memory 203936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1135550669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti
mer_csr_mem_rw_with_rand_reset.1135550669
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.3072716283
Short name T62
Test name
Test status
Simulation time 453437560 ps
CPU time 2.18 seconds
Started Sep 24 09:35:43 PM UTC 24
Finished Sep 24 09:35:46 PM UTC 24
Peak memory 201124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072716283 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3072716283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.342794091
Short name T377
Test name
Test status
Simulation time 299719184 ps
CPU time 1.39 seconds
Started Sep 24 09:35:43 PM UTC 24
Finished Sep 24 09:35:45 PM UTC 24
Peak memory 199716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342794091 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.342794091
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3107862057
Short name T400
Test name
Test status
Simulation time 2714113136 ps
CPU time 6.83 seconds
Started Sep 24 09:35:43 PM UTC 24
Finished Sep 24 09:35:51 PM UTC 24
Peak memory 205484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107862057 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.3107862057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.1626947324
Short name T376
Test name
Test status
Simulation time 427927140 ps
CPU time 2.4 seconds
Started Sep 24 09:35:41 PM UTC 24
Finished Sep 24 09:35:45 PM UTC 24
Peak memory 207012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626947324 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1626947324
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1895145441
Short name T186
Test name
Test status
Simulation time 4020318400 ps
CPU time 7.81 seconds
Started Sep 24 09:35:43 PM UTC 24
Finished Sep 24 09:35:52 PM UTC 24
Peak memory 206732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895145441 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.1895145441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3975495017
Short name T382
Test name
Test status
Simulation time 577816161 ps
CPU time 1.68 seconds
Started Sep 24 09:35:44 PM UTC 24
Finished Sep 24 09:35:47 PM UTC 24
Peak memory 205316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3975495017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_ti
mer_csr_mem_rw_with_rand_reset.3975495017
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.1537114828
Short name T380
Test name
Test status
Simulation time 290997907 ps
CPU time 1.37 seconds
Started Sep 24 09:35:44 PM UTC 24
Finished Sep 24 09:35:46 PM UTC 24
Peak memory 199716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537114828 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1537114828
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.1694757189
Short name T383
Test name
Test status
Simulation time 279129525 ps
CPU time 1.82 seconds
Started Sep 24 09:35:44 PM UTC 24
Finished Sep 24 09:35:47 PM UTC 24
Peak memory 201756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694757189 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1694757189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1374075066
Short name T381
Test name
Test status
Simulation time 1352450374 ps
CPU time 1.58 seconds
Started Sep 24 09:35:44 PM UTC 24
Finished Sep 24 09:35:47 PM UTC 24
Peak memory 201892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374075066 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.1374075066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.2715305964
Short name T384
Test name
Test status
Simulation time 358300627 ps
CPU time 2.65 seconds
Started Sep 24 09:35:44 PM UTC 24
Finished Sep 24 09:35:48 PM UTC 24
Peak memory 207184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715305964 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2715305964
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1386464694
Short name T348
Test name
Test status
Simulation time 8563290038 ps
CPU time 6.03 seconds
Started Sep 24 09:35:44 PM UTC 24
Finished Sep 24 09:35:51 PM UTC 24
Peak memory 207000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386464694 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.1386464694
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.334099096
Short name T386
Test name
Test status
Simulation time 359179065 ps
CPU time 1.71 seconds
Started Sep 24 09:35:46 PM UTC 24
Finished Sep 24 09:35:48 PM UTC 24
Peak memory 206940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=334099096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_tim
er_csr_mem_rw_with_rand_reset.334099096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.3624572160
Short name T61
Test name
Test status
Simulation time 374837388 ps
CPU time 1.45 seconds
Started Sep 24 09:35:45 PM UTC 24
Finished Sep 24 09:35:48 PM UTC 24
Peak memory 201764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624572160 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3624572160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.2940860199
Short name T390
Test name
Test status
Simulation time 483325489 ps
CPU time 2.44 seconds
Started Sep 24 09:35:45 PM UTC 24
Finished Sep 24 09:35:49 PM UTC 24
Peak memory 201116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940860199 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2940860199
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/19.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3262180676
Short name T355
Test name
Test status
Simulation time 2111613126 ps
CPU time 4.57 seconds
Started Sep 24 09:35:45 PM UTC 24
Finished Sep 24 09:35:51 PM UTC 24
Peak memory 205344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262180676 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.3262180676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.3959299523
Short name T393
Test name
Test status
Simulation time 498657891 ps
CPU time 2.92 seconds
Started Sep 24 09:35:45 PM UTC 24
Finished Sep 24 09:35:49 PM UTC 24
Peak memory 206788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959299523 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3959299523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3792071900
Short name T394
Test name
Test status
Simulation time 4106338695 ps
CPU time 3.23 seconds
Started Sep 24 09:35:45 PM UTC 24
Finished Sep 24 09:35:50 PM UTC 24
Peak memory 206456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792071900 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.3792071900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3878374332
Short name T289
Test name
Test status
Simulation time 425185233 ps
CPU time 1.5 seconds
Started Sep 24 09:35:12 PM UTC 24
Finished Sep 24 09:35:14 PM UTC 24
Peak memory 201772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878374332 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.3878374332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.919463297
Short name T294
Test name
Test status
Simulation time 7036366039 ps
CPU time 4.58 seconds
Started Sep 24 09:35:12 PM UTC 24
Finished Sep 24 09:35:17 PM UTC 24
Peak memory 205632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919463297 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.919463297
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.788610919
Short name T291
Test name
Test status
Simulation time 1085832058 ps
CPU time 4.16 seconds
Started Sep 24 09:35:11 PM UTC 24
Finished Sep 24 09:35:16 PM UTC 24
Peak memory 203564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788610919 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.788610919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3351873123
Short name T290
Test name
Test status
Simulation time 467667864 ps
CPU time 1.77 seconds
Started Sep 24 09:35:13 PM UTC 24
Finished Sep 24 09:35:16 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3351873123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_tim
er_csr_mem_rw_with_rand_reset.3351873123
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.948608093
Short name T64
Test name
Test status
Simulation time 550332637 ps
CPU time 1.16 seconds
Started Sep 24 09:35:11 PM UTC 24
Finished Sep 24 09:35:13 PM UTC 24
Peak memory 199716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948608093 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.948608093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.1288245728
Short name T285
Test name
Test status
Simulation time 305438740 ps
CPU time 1.25 seconds
Started Sep 24 09:35:09 PM UTC 24
Finished Sep 24 09:35:11 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288245728 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1288245728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1039425567
Short name T286
Test name
Test status
Simulation time 468551394 ps
CPU time 1.25 seconds
Started Sep 24 09:35:11 PM UTC 24
Finished Sep 24 09:35:13 PM UTC 24
Peak memory 199844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039425567 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.1039425567
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.2800433476
Short name T287
Test name
Test status
Simulation time 493776757 ps
CPU time 2.42 seconds
Started Sep 24 09:35:10 PM UTC 24
Finished Sep 24 09:35:13 PM UTC 24
Peak memory 201316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800433476 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.2800433476
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3928197680
Short name T66
Test name
Test status
Simulation time 2877433984 ps
CPU time 11.77 seconds
Started Sep 24 09:35:12 PM UTC 24
Finished Sep 24 09:35:25 PM UTC 24
Peak memory 205412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928197680 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.3928197680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.281250457
Short name T288
Test name
Test status
Simulation time 387338505 ps
CPU time 3.74 seconds
Started Sep 24 09:35:08 PM UTC 24
Finished Sep 24 09:35:13 PM UTC 24
Peak memory 206988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281250457 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.281250457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1782206819
Short name T35
Test name
Test status
Simulation time 4338731700 ps
CPU time 9.61 seconds
Started Sep 24 09:35:08 PM UTC 24
Finished Sep 24 09:35:19 PM UTC 24
Peak memory 206652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782206819 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.1782206819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2475055294
Short name T387
Test name
Test status
Simulation time 313886630 ps
CPU time 1.94 seconds
Started Sep 24 09:35:46 PM UTC 24
Finished Sep 24 09:35:49 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475055294 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2475055294
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/20.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.1244664907
Short name T388
Test name
Test status
Simulation time 369956999 ps
CPU time 1 seconds
Started Sep 24 09:35:47 PM UTC 24
Finished Sep 24 09:35:49 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244664907 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1244664907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/21.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.2913841931
Short name T392
Test name
Test status
Simulation time 326024091 ps
CPU time 1.38 seconds
Started Sep 24 09:35:47 PM UTC 24
Finished Sep 24 09:35:49 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913841931 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2913841931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/22.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.481457782
Short name T389
Test name
Test status
Simulation time 432720674 ps
CPU time 0.9 seconds
Started Sep 24 09:35:47 PM UTC 24
Finished Sep 24 09:35:49 PM UTC 24
Peak memory 199716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481457782 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.481457782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/23.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.2718452302
Short name T395
Test name
Test status
Simulation time 476613288 ps
CPU time 0.86 seconds
Started Sep 24 09:35:48 PM UTC 24
Finished Sep 24 09:35:50 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718452302 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2718452302
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/24.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.3268869192
Short name T398
Test name
Test status
Simulation time 330634753 ps
CPU time 1.44 seconds
Started Sep 24 09:35:48 PM UTC 24
Finished Sep 24 09:35:50 PM UTC 24
Peak memory 201756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268869192 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3268869192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/25.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.2745763352
Short name T396
Test name
Test status
Simulation time 397824647 ps
CPU time 1.3 seconds
Started Sep 24 09:35:48 PM UTC 24
Finished Sep 24 09:35:50 PM UTC 24
Peak memory 199704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745763352 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2745763352
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/26.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.2918825965
Short name T399
Test name
Test status
Simulation time 364358746 ps
CPU time 1.54 seconds
Started Sep 24 09:35:48 PM UTC 24
Finished Sep 24 09:35:51 PM UTC 24
Peak memory 201756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918825965 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2918825965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/27.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.4066013436
Short name T397
Test name
Test status
Simulation time 475448308 ps
CPU time 1.26 seconds
Started Sep 24 09:35:48 PM UTC 24
Finished Sep 24 09:35:50 PM UTC 24
Peak memory 199704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066013436 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4066013436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/28.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.529947285
Short name T401
Test name
Test status
Simulation time 470623487 ps
CPU time 0.87 seconds
Started Sep 24 09:35:49 PM UTC 24
Finished Sep 24 09:35:51 PM UTC 24
Peak memory 201764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529947285 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.529947285
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/29.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2519362860
Short name T56
Test name
Test status
Simulation time 493017340 ps
CPU time 1.56 seconds
Started Sep 24 09:35:17 PM UTC 24
Finished Sep 24 09:35:19 PM UTC 24
Peak memory 201772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519362860 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.2519362860
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1987658578
Short name T385
Test name
Test status
Simulation time 13022301558 ps
CPU time 30.23 seconds
Started Sep 24 09:35:17 PM UTC 24
Finished Sep 24 09:35:48 PM UTC 24
Peak memory 205908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987658578 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.1987658578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1630152681
Short name T297
Test name
Test status
Simulation time 989013807 ps
CPU time 2.44 seconds
Started Sep 24 09:35:15 PM UTC 24
Finished Sep 24 09:35:19 PM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630152681 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.1630152681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2098531625
Short name T298
Test name
Test status
Simulation time 439336289 ps
CPU time 2.12 seconds
Started Sep 24 09:35:18 PM UTC 24
Finished Sep 24 09:35:21 PM UTC 24
Peak memory 205352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2098531625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_csr_mem_rw_with_rand_reset.2098531625
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.473252671
Short name T55
Test name
Test status
Simulation time 449397731 ps
CPU time 1.27 seconds
Started Sep 24 09:35:15 PM UTC 24
Finished Sep 24 09:35:18 PM UTC 24
Peak memory 201764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473252671 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.473252671
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.966406056
Short name T295
Test name
Test status
Simulation time 432601464 ps
CPU time 2.32 seconds
Started Sep 24 09:35:14 PM UTC 24
Finished Sep 24 09:35:18 PM UTC 24
Peak memory 203440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966406056 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.966406056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.421483047
Short name T293
Test name
Test status
Simulation time 318720412 ps
CPU time 1.08 seconds
Started Sep 24 09:35:14 PM UTC 24
Finished Sep 24 09:35:16 PM UTC 24
Peak memory 199844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421483047 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.421483047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.1924552638
Short name T292
Test name
Test status
Simulation time 433453699 ps
CPU time 1.13 seconds
Started Sep 24 09:35:14 PM UTC 24
Finished Sep 24 09:35:16 PM UTC 24
Peak memory 199712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924552638 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.1924552638
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4048325907
Short name T65
Test name
Test status
Simulation time 1398764608 ps
CPU time 2.45 seconds
Started Sep 24 09:35:17 PM UTC 24
Finished Sep 24 09:35:20 PM UTC 24
Peak memory 203372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048325907 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.4048325907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.3232289721
Short name T296
Test name
Test status
Simulation time 333034644 ps
CPU time 2.81 seconds
Started Sep 24 09:35:14 PM UTC 24
Finished Sep 24 09:35:18 PM UTC 24
Peak memory 206808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232289721 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3232289721
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4137888087
Short name T334
Test name
Test status
Simulation time 7534224147 ps
CPU time 19.97 seconds
Started Sep 24 09:35:14 PM UTC 24
Finished Sep 24 09:35:35 PM UTC 24
Peak memory 206996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137888087 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.4137888087
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.3552409144
Short name T349
Test name
Test status
Simulation time 460316981 ps
CPU time 1.2 seconds
Started Sep 24 09:35:49 PM UTC 24
Finished Sep 24 09:35:51 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552409144 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3552409144
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/30.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.2007758295
Short name T407
Test name
Test status
Simulation time 373549176 ps
CPU time 1.5 seconds
Started Sep 24 09:35:49 PM UTC 24
Finished Sep 24 09:35:52 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007758295 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2007758295
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/31.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3552669776
Short name T402
Test name
Test status
Simulation time 534350227 ps
CPU time 0.82 seconds
Started Sep 24 09:35:49 PM UTC 24
Finished Sep 24 09:35:51 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552669776 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3552669776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/32.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.900759945
Short name T406
Test name
Test status
Simulation time 300178360 ps
CPU time 1.24 seconds
Started Sep 24 09:35:49 PM UTC 24
Finished Sep 24 09:35:52 PM UTC 24
Peak memory 201764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900759945 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.900759945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/33.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.4280000162
Short name T405
Test name
Test status
Simulation time 471155639 ps
CPU time 1.16 seconds
Started Sep 24 09:35:49 PM UTC 24
Finished Sep 24 09:35:52 PM UTC 24
Peak memory 201824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280000162 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4280000162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/34.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.12676993
Short name T403
Test name
Test status
Simulation time 404512897 ps
CPU time 1.05 seconds
Started Sep 24 09:35:49 PM UTC 24
Finished Sep 24 09:35:51 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12676993 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.12676993
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/35.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3252195356
Short name T404
Test name
Test status
Simulation time 528220656 ps
CPU time 1.01 seconds
Started Sep 24 09:35:49 PM UTC 24
Finished Sep 24 09:35:52 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252195356 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3252195356
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/36.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.2008443704
Short name T328
Test name
Test status
Simulation time 303861668 ps
CPU time 0.87 seconds
Started Sep 24 09:35:50 PM UTC 24
Finished Sep 24 09:35:51 PM UTC 24
Peak memory 201756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008443704 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2008443704
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/37.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.3882808579
Short name T409
Test name
Test status
Simulation time 419616378 ps
CPU time 1.11 seconds
Started Sep 24 09:35:51 PM UTC 24
Finished Sep 24 09:35:53 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882808579 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3882808579
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/38.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.1816653326
Short name T411
Test name
Test status
Simulation time 299727932 ps
CPU time 1.05 seconds
Started Sep 24 09:35:51 PM UTC 24
Finished Sep 24 09:35:53 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816653326 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1816653326
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/39.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.267167652
Short name T57
Test name
Test status
Simulation time 522964351 ps
CPU time 1.49 seconds
Started Sep 24 09:35:20 PM UTC 24
Finished Sep 24 09:35:23 PM UTC 24
Peak memory 201824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267167652 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.267167652
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3436756523
Short name T60
Test name
Test status
Simulation time 7175300712 ps
CPU time 12.43 seconds
Started Sep 24 09:35:20 PM UTC 24
Finished Sep 24 09:35:34 PM UTC 24
Peak memory 205580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436756523 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.3436756523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2966622492
Short name T304
Test name
Test status
Simulation time 954530459 ps
CPU time 2.57 seconds
Started Sep 24 09:35:20 PM UTC 24
Finished Sep 24 09:35:24 PM UTC 24
Peak memory 203320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966622492 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.2966622492
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.172348165
Short name T305
Test name
Test status
Simulation time 469328612 ps
CPU time 1.43 seconds
Started Sep 24 09:35:22 PM UTC 24
Finished Sep 24 09:35:24 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=172348165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_time
r_csr_mem_rw_with_rand_reset.172348165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.223974813
Short name T303
Test name
Test status
Simulation time 420578435 ps
CPU time 2.17 seconds
Started Sep 24 09:35:20 PM UTC 24
Finished Sep 24 09:35:23 PM UTC 24
Peak memory 201264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223974813 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.223974813
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.2631181333
Short name T301
Test name
Test status
Simulation time 513390356 ps
CPU time 2.12 seconds
Started Sep 24 09:35:19 PM UTC 24
Finished Sep 24 09:35:22 PM UTC 24
Peak memory 201120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631181333 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2631181333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3414570803
Short name T300
Test name
Test status
Simulation time 336617263 ps
CPU time 1.9 seconds
Started Sep 24 09:35:19 PM UTC 24
Finished Sep 24 09:35:22 PM UTC 24
Peak memory 199844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414570803 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.3414570803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2356966008
Short name T299
Test name
Test status
Simulation time 466669014 ps
CPU time 1.53 seconds
Started Sep 24 09:35:19 PM UTC 24
Finished Sep 24 09:35:22 PM UTC 24
Peak memory 199712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356966008 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.2356966008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1722107169
Short name T67
Test name
Test status
Simulation time 1364846293 ps
CPU time 3.57 seconds
Started Sep 24 09:35:21 PM UTC 24
Finished Sep 24 09:35:26 PM UTC 24
Peak memory 203304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722107169 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.1722107169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.4090037299
Short name T302
Test name
Test status
Simulation time 415327717 ps
CPU time 4.11 seconds
Started Sep 24 09:35:18 PM UTC 24
Finished Sep 24 09:35:23 PM UTC 24
Peak memory 207028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090037299 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4090037299
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.212761966
Short name T343
Test name
Test status
Simulation time 7900796458 ps
CPU time 17.01 seconds
Started Sep 24 09:35:19 PM UTC 24
Finished Sep 24 09:35:37 PM UTC 24
Peak memory 206988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212761966 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.212761966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.3111250795
Short name T414
Test name
Test status
Simulation time 512476803 ps
CPU time 1.6 seconds
Started Sep 24 09:35:51 PM UTC 24
Finished Sep 24 09:35:53 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111250795 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3111250795
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/40.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.4016086269
Short name T410
Test name
Test status
Simulation time 488110575 ps
CPU time 1.02 seconds
Started Sep 24 09:35:51 PM UTC 24
Finished Sep 24 09:35:53 PM UTC 24
Peak memory 201756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016086269 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.4016086269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/41.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.1652208960
Short name T413
Test name
Test status
Simulation time 498628348 ps
CPU time 1.31 seconds
Started Sep 24 09:35:51 PM UTC 24
Finished Sep 24 09:35:53 PM UTC 24
Peak memory 199688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652208960 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1652208960
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/42.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.4119304298
Short name T408
Test name
Test status
Simulation time 425432146 ps
CPU time 0.79 seconds
Started Sep 24 09:35:51 PM UTC 24
Finished Sep 24 09:35:53 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119304298 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.4119304298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/43.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1259384314
Short name T412
Test name
Test status
Simulation time 450979564 ps
CPU time 1.05 seconds
Started Sep 24 09:35:51 PM UTC 24
Finished Sep 24 09:35:53 PM UTC 24
Peak memory 199684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259384314 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1259384314
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/44.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.4263425851
Short name T415
Test name
Test status
Simulation time 456724462 ps
CPU time 0.73 seconds
Started Sep 24 09:35:52 PM UTC 24
Finished Sep 24 09:35:54 PM UTC 24
Peak memory 199700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263425851 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.4263425851
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/45.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.618234320
Short name T417
Test name
Test status
Simulation time 539477050 ps
CPU time 0.87 seconds
Started Sep 24 09:35:52 PM UTC 24
Finished Sep 24 09:35:54 PM UTC 24
Peak memory 199712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618234320 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.618234320
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/46.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.4286032853
Short name T416
Test name
Test status
Simulation time 373864235 ps
CPU time 0.73 seconds
Started Sep 24 09:35:52 PM UTC 24
Finished Sep 24 09:35:54 PM UTC 24
Peak memory 201756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286032853 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.4286032853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/47.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.1828712656
Short name T418
Test name
Test status
Simulation time 503477611 ps
CPU time 0.84 seconds
Started Sep 24 09:35:52 PM UTC 24
Finished Sep 24 09:35:54 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828712656 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1828712656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/48.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.2808652510
Short name T419
Test name
Test status
Simulation time 287899269 ps
CPU time 1.43 seconds
Started Sep 24 09:35:52 PM UTC 24
Finished Sep 24 09:35:55 PM UTC 24
Peak memory 199708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808652510 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2808652510
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/49.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2929325267
Short name T309
Test name
Test status
Simulation time 501154574 ps
CPU time 0.98 seconds
Started Sep 24 09:35:24 PM UTC 24
Finished Sep 24 09:35:26 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2929325267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_tim
er_csr_mem_rw_with_rand_reset.2929325267
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.4266333814
Short name T308
Test name
Test status
Simulation time 524965425 ps
CPU time 1.52 seconds
Started Sep 24 09:35:23 PM UTC 24
Finished Sep 24 09:35:25 PM UTC 24
Peak memory 201764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266333814 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.4266333814
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.4263627094
Short name T307
Test name
Test status
Simulation time 300330318 ps
CPU time 1 seconds
Started Sep 24 09:35:23 PM UTC 24
Finished Sep 24 09:35:25 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263627094 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.4263627094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3752006143
Short name T329
Test name
Test status
Simulation time 2461344081 ps
CPU time 9.25 seconds
Started Sep 24 09:35:24 PM UTC 24
Finished Sep 24 09:35:34 PM UTC 24
Peak memory 205412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752006143 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.3752006143
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.4263791373
Short name T306
Test name
Test status
Simulation time 429189359 ps
CPU time 1.7 seconds
Started Sep 24 09:35:22 PM UTC 24
Finished Sep 24 09:35:24 PM UTC 24
Peak memory 206992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263791373 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.4263791373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3856104749
Short name T312
Test name
Test status
Simulation time 432061207 ps
CPU time 1.41 seconds
Started Sep 24 09:35:25 PM UTC 24
Finished Sep 24 09:35:28 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3856104749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_tim
er_csr_mem_rw_with_rand_reset.3856104749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.4191599229
Short name T58
Test name
Test status
Simulation time 321499542 ps
CPU time 1.02 seconds
Started Sep 24 09:35:24 PM UTC 24
Finished Sep 24 09:35:26 PM UTC 24
Peak memory 201824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191599229 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.4191599229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.1119958668
Short name T310
Test name
Test status
Simulation time 422923367 ps
CPU time 1.47 seconds
Started Sep 24 09:35:24 PM UTC 24
Finished Sep 24 09:35:27 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119958668 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1119958668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.514694500
Short name T68
Test name
Test status
Simulation time 1387101928 ps
CPU time 2.12 seconds
Started Sep 24 09:35:24 PM UTC 24
Finished Sep 24 09:35:27 PM UTC 24
Peak memory 203496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514694500 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.514694500
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3004008825
Short name T313
Test name
Test status
Simulation time 532282173 ps
CPU time 3.44 seconds
Started Sep 24 09:35:24 PM UTC 24
Finished Sep 24 09:35:28 PM UTC 24
Peak memory 207060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004008825 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3004008825
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2037435379
Short name T185
Test name
Test status
Simulation time 8718909806 ps
CPU time 5.74 seconds
Started Sep 24 09:35:24 PM UTC 24
Finished Sep 24 09:35:31 PM UTC 24
Peak memory 206808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037435379 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.2037435379
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2264697089
Short name T317
Test name
Test status
Simulation time 376611507 ps
CPU time 2.25 seconds
Started Sep 24 09:35:27 PM UTC 24
Finished Sep 24 09:35:30 PM UTC 24
Peak memory 205748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2264697089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim
er_csr_mem_rw_with_rand_reset.2264697089
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.4005529321
Short name T314
Test name
Test status
Simulation time 445356006 ps
CPU time 2.14 seconds
Started Sep 24 09:35:25 PM UTC 24
Finished Sep 24 09:35:29 PM UTC 24
Peak memory 201192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005529321 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.4005529321
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.2026078657
Short name T311
Test name
Test status
Simulation time 531902664 ps
CPU time 0.98 seconds
Started Sep 24 09:35:25 PM UTC 24
Finished Sep 24 09:35:27 PM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026078657 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2026078657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2723879196
Short name T320
Test name
Test status
Simulation time 2272150492 ps
CPU time 3.5 seconds
Started Sep 24 09:35:27 PM UTC 24
Finished Sep 24 09:35:31 PM UTC 24
Peak memory 205484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723879196 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.2723879196
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.2458120331
Short name T315
Test name
Test status
Simulation time 332837896 ps
CPU time 2.85 seconds
Started Sep 24 09:35:25 PM UTC 24
Finished Sep 24 09:35:29 PM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458120331 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2458120331
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1860106092
Short name T350
Test name
Test status
Simulation time 4154342300 ps
CPU time 11.53 seconds
Started Sep 24 09:35:25 PM UTC 24
Finished Sep 24 09:35:38 PM UTC 24
Peak memory 205416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860106092 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.1860106092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2062552542
Short name T321
Test name
Test status
Simulation time 417761731 ps
CPU time 1.21 seconds
Started Sep 24 09:35:29 PM UTC 24
Finished Sep 24 09:35:31 PM UTC 24
Peak memory 206940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2062552542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim
er_csr_mem_rw_with_rand_reset.2062552542
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.254773591
Short name T318
Test name
Test status
Simulation time 425026255 ps
CPU time 1.1 seconds
Started Sep 24 09:35:28 PM UTC 24
Finished Sep 24 09:35:30 PM UTC 24
Peak memory 199716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254773591 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.254773591
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.3267025145
Short name T322
Test name
Test status
Simulation time 456714917 ps
CPU time 2.56 seconds
Started Sep 24 09:35:28 PM UTC 24
Finished Sep 24 09:35:31 PM UTC 24
Peak memory 201448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267025145 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3267025145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3768418482
Short name T319
Test name
Test status
Simulation time 1250784320 ps
CPU time 1.72 seconds
Started Sep 24 09:35:28 PM UTC 24
Finished Sep 24 09:35:31 PM UTC 24
Peak memory 201892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768418482 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.3768418482
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.3703073782
Short name T316
Test name
Test status
Simulation time 714912032 ps
CPU time 2.05 seconds
Started Sep 24 09:35:27 PM UTC 24
Finished Sep 24 09:35:30 PM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703073782 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3703073782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3293991212
Short name T330
Test name
Test status
Simulation time 3915703538 ps
CPU time 6.72 seconds
Started Sep 24 09:35:27 PM UTC 24
Finished Sep 24 09:35:35 PM UTC 24
Peak memory 205432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293991212 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.3293991212
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3214587001
Short name T325
Test name
Test status
Simulation time 493201584 ps
CPU time 1.3 seconds
Started Sep 24 09:35:30 PM UTC 24
Finished Sep 24 09:35:33 PM UTC 24
Peak memory 203940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3214587001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_tim
er_csr_mem_rw_with_rand_reset.3214587001
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.1404999885
Short name T59
Test name
Test status
Simulation time 527626060 ps
CPU time 1.48 seconds
Started Sep 24 09:35:29 PM UTC 24
Finished Sep 24 09:35:32 PM UTC 24
Peak memory 199776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404999885 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1404999885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.3448702297
Short name T323
Test name
Test status
Simulation time 535644704 ps
CPU time 1.33 seconds
Started Sep 24 09:35:29 PM UTC 24
Finished Sep 24 09:35:31 PM UTC 24
Peak memory 199780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448702297 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3448702297
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2630118670
Short name T339
Test name
Test status
Simulation time 1374279243 ps
CPU time 4.99 seconds
Started Sep 24 09:35:30 PM UTC 24
Finished Sep 24 09:35:36 PM UTC 24
Peak memory 203300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630118670 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.2630118670
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.1663482571
Short name T324
Test name
Test status
Simulation time 397386821 ps
CPU time 2.48 seconds
Started Sep 24 09:35:29 PM UTC 24
Finished Sep 24 09:35:33 PM UTC 24
Peak memory 207088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663482571 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1663482571
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1660914477
Short name T332
Test name
Test status
Simulation time 4078152552 ps
CPU time 4.54 seconds
Started Sep 24 09:35:29 PM UTC 24
Finished Sep 24 09:35:35 PM UTC 24
Peak memory 206696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660914477 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.1660914477
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.3668722673
Short name T5
Test name
Test status
Simulation time 16028882977 ps
CPU time 22.58 seconds
Started Sep 24 09:29:36 PM UTC 24
Finished Sep 24 09:30:00 PM UTC 24
Peak memory 206084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668722673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3668722673
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1450806454
Short name T1
Test name
Test status
Simulation time 695849569 ps
CPU time 1.04 seconds
Started Sep 24 09:29:33 PM UTC 24
Finished Sep 24 09:29:35 PM UTC 24
Peak memory 205068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450806454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1450806454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/0.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.2407562209
Short name T199
Test name
Test status
Simulation time 24465846386 ps
CPU time 46.87 seconds
Started Sep 24 09:29:44 PM UTC 24
Finished Sep 24 09:30:32 PM UTC 24
Peak memory 206068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407562209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2407562209
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.1582452073
Short name T12
Test name
Test status
Simulation time 8159302591 ps
CPU time 4.56 seconds
Started Sep 24 09:29:54 PM UTC 24
Finished Sep 24 09:29:59 PM UTC 24
Peak memory 234492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582452073 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1582452073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.2898915115
Short name T3
Test name
Test status
Simulation time 549023952 ps
CPU time 1.55 seconds
Started Sep 24 09:29:42 PM UTC 24
Finished Sep 24 09:29:45 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898915115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2898915115
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/1.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.2381737791
Short name T192
Test name
Test status
Simulation time 15552030337 ps
CPU time 34.28 seconds
Started Sep 24 09:31:01 PM UTC 24
Finished Sep 24 09:31:37 PM UTC 24
Peak memory 206080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381737791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2381737791
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.533127133
Short name T202
Test name
Test status
Simulation time 495418318 ps
CPU time 2.32 seconds
Started Sep 24 09:30:57 PM UTC 24
Finished Sep 24 09:31:01 PM UTC 24
Peak memory 205728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533127133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.533127133
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/10.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.1057907218
Short name T49
Test name
Test status
Simulation time 5662869370 ps
CPU time 5.39 seconds
Started Sep 24 09:31:08 PM UTC 24
Finished Sep 24 09:31:14 PM UTC 24
Peak memory 206000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057907218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1057907218
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.2677058662
Short name T203
Test name
Test status
Simulation time 549286800 ps
CPU time 2.56 seconds
Started Sep 24 09:31:06 PM UTC 24
Finished Sep 24 09:31:10 PM UTC 24
Peak memory 205584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677058662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2677058662
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/11.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.2820334428
Short name T193
Test name
Test status
Simulation time 16728328832 ps
CPU time 3.47 seconds
Started Sep 24 09:31:14 PM UTC 24
Finished Sep 24 09:31:19 PM UTC 24
Peak memory 206072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820334428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2820334428
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/12.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.1211252803
Short name T204
Test name
Test status
Simulation time 380076006 ps
CPU time 1.2 seconds
Started Sep 24 09:31:12 PM UTC 24
Finished Sep 24 09:31:14 PM UTC 24
Peak memory 205724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211252803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1211252803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/12.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.2088881084
Short name T221
Test name
Test status
Simulation time 48858878215 ps
CPU time 62.43 seconds
Started Sep 24 09:31:19 PM UTC 24
Finished Sep 24 09:32:23 PM UTC 24
Peak memory 206008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088881084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2088881084
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.2564425031
Short name T141
Test name
Test status
Simulation time 404059498 ps
CPU time 1.41 seconds
Started Sep 24 09:31:19 PM UTC 24
Finished Sep 24 09:31:21 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564425031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2564425031
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/13.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.1973357284
Short name T189
Test name
Test status
Simulation time 5753266693 ps
CPU time 1.76 seconds
Started Sep 24 09:31:21 PM UTC 24
Finished Sep 24 09:31:24 PM UTC 24
Peak memory 205016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973357284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1973357284
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.3877537590
Short name T206
Test name
Test status
Simulation time 469438804 ps
CPU time 2.38 seconds
Started Sep 24 09:31:20 PM UTC 24
Finished Sep 24 09:31:23 PM UTC 24
Peak memory 205720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877537590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3877537590
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/14.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.2671080657
Short name T191
Test name
Test status
Simulation time 12464492850 ps
CPU time 38.8 seconds
Started Sep 24 09:31:24 PM UTC 24
Finished Sep 24 09:32:04 PM UTC 24
Peak memory 206144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671080657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2671080657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.604318457
Short name T207
Test name
Test status
Simulation time 654284627 ps
CPU time 1.13 seconds
Started Sep 24 09:31:24 PM UTC 24
Finished Sep 24 09:31:26 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604318457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.604318457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/15.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.2000120785
Short name T211
Test name
Test status
Simulation time 10860580609 ps
CPU time 24.04 seconds
Started Sep 24 09:31:30 PM UTC 24
Finished Sep 24 09:31:55 PM UTC 24
Peak memory 205936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000120785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2000120785
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.1211837733
Short name T208
Test name
Test status
Simulation time 496434903 ps
CPU time 1.8 seconds
Started Sep 24 09:31:28 PM UTC 24
Finished Sep 24 09:31:31 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211837733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1211837733
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/16.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.4145033638
Short name T218
Test name
Test status
Simulation time 24161850330 ps
CPU time 41.63 seconds
Started Sep 24 09:31:34 PM UTC 24
Finished Sep 24 09:32:17 PM UTC 24
Peak memory 205952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145033638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.4145033638
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.3161970810
Short name T209
Test name
Test status
Simulation time 629228875 ps
CPU time 1.48 seconds
Started Sep 24 09:31:32 PM UTC 24
Finished Sep 24 09:31:34 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161970810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3161970810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.413477288
Short name T187
Test name
Test status
Simulation time 3270002702 ps
CPU time 34.81 seconds
Started Sep 24 09:31:35 PM UTC 24
Finished Sep 24 09:32:11 PM UTC 24
Peak memory 216364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=413477288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 17.aon_timer_stress_all_with_rand_reset.413477288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.1981837145
Short name T188
Test name
Test status
Simulation time 1635290226 ps
CPU time 2.21 seconds
Started Sep 24 09:31:42 PM UTC 24
Finished Sep 24 09:31:46 PM UTC 24
Peak memory 205656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981837145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1981837145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.1478346086
Short name T210
Test name
Test status
Simulation time 390541482 ps
CPU time 1.16 seconds
Started Sep 24 09:31:39 PM UTC 24
Finished Sep 24 09:31:41 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478346086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1478346086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.3193216317
Short name T276
Test name
Test status
Simulation time 180215732793 ps
CPU time 336.45 seconds
Started Sep 24 09:31:47 PM UTC 24
Finished Sep 24 09:37:27 PM UTC 24
Peak memory 207092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193216317 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.3193216317
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/18.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.2199199067
Short name T215
Test name
Test status
Simulation time 28787938961 ps
CPU time 17.17 seconds
Started Sep 24 09:31:47 PM UTC 24
Finished Sep 24 09:32:05 PM UTC 24
Peak memory 206096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199199067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2199199067
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/19.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.2958783311
Short name T205
Test name
Test status
Simulation time 380054254 ps
CPU time 1.08 seconds
Started Sep 24 09:31:47 PM UTC 24
Finished Sep 24 09:31:49 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958783311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2958783311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/19.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.1958713042
Short name T8
Test name
Test status
Simulation time 498870579 ps
CPU time 2.63 seconds
Started Sep 24 09:30:00 PM UTC 24
Finished Sep 24 09:30:04 PM UTC 24
Peak memory 205316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958713042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1958713042
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.1922338954
Short name T14
Test name
Test status
Simulation time 36362692734 ps
CPU time 16.5 seconds
Started Sep 24 09:29:59 PM UTC 24
Finished Sep 24 09:30:17 PM UTC 24
Peak memory 206076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922338954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1922338954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.2320385452
Short name T20
Test name
Test status
Simulation time 4194594871 ps
CPU time 2.46 seconds
Started Sep 24 09:30:01 PM UTC 24
Finished Sep 24 09:30:05 PM UTC 24
Peak memory 234248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320385452 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2320385452
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.684449171
Short name T6
Test name
Test status
Simulation time 609538153 ps
CPU time 1.34 seconds
Started Sep 24 09:29:58 PM UTC 24
Finished Sep 24 09:30:00 PM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684449171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.684449171
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/2.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.1702971973
Short name T222
Test name
Test status
Simulation time 58557860216 ps
CPU time 26.84 seconds
Started Sep 24 09:31:55 PM UTC 24
Finished Sep 24 09:32:23 PM UTC 24
Peak memory 206080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702971973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1702971973
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/20.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.1599685557
Short name T212
Test name
Test status
Simulation time 496970219 ps
CPU time 2.24 seconds
Started Sep 24 09:31:54 PM UTC 24
Finished Sep 24 09:31:57 PM UTC 24
Peak memory 205764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599685557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1599685557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/20.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.1265440945
Short name T214
Test name
Test status
Simulation time 10721237741 ps
CPU time 4.27 seconds
Started Sep 24 09:31:59 PM UTC 24
Finished Sep 24 09:32:05 PM UTC 24
Peak memory 205880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265440945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1265440945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/21.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.3236133283
Short name T213
Test name
Test status
Simulation time 612305723 ps
CPU time 1.43 seconds
Started Sep 24 09:31:59 PM UTC 24
Finished Sep 24 09:32:02 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236133283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3236133283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/21.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.1056194936
Short name T229
Test name
Test status
Simulation time 53822674207 ps
CPU time 41.25 seconds
Started Sep 24 09:32:07 PM UTC 24
Finished Sep 24 09:32:49 PM UTC 24
Peak memory 205936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056194936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1056194936
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/22.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.2404156474
Short name T216
Test name
Test status
Simulation time 374266090 ps
CPU time 2.25 seconds
Started Sep 24 09:32:06 PM UTC 24
Finished Sep 24 09:32:09 PM UTC 24
Peak memory 205724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404156474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2404156474
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/22.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.3694436948
Short name T232
Test name
Test status
Simulation time 61608019284 ps
CPU time 41.04 seconds
Started Sep 24 09:32:12 PM UTC 24
Finished Sep 24 09:32:55 PM UTC 24
Peak memory 206008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694436948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3694436948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/23.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.1430199037
Short name T217
Test name
Test status
Simulation time 463863540 ps
CPU time 1.94 seconds
Started Sep 24 09:32:12 PM UTC 24
Finished Sep 24 09:32:15 PM UTC 24
Peak memory 205604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430199037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1430199037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/23.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.1504284106
Short name T219
Test name
Test status
Simulation time 1597505551 ps
CPU time 5.11 seconds
Started Sep 24 09:32:13 PM UTC 24
Finished Sep 24 09:32:20 PM UTC 24
Peak memory 218316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1504284106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 23.aon_timer_stress_all_with_rand_reset.1504284106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.3860451296
Short name T225
Test name
Test status
Simulation time 31840167939 ps
CPU time 13.7 seconds
Started Sep 24 09:32:18 PM UTC 24
Finished Sep 24 09:32:33 PM UTC 24
Peak memory 206080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860451296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3860451296
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/24.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.4190812004
Short name T220
Test name
Test status
Simulation time 356721742 ps
CPU time 1.4 seconds
Started Sep 24 09:32:17 PM UTC 24
Finished Sep 24 09:32:20 PM UTC 24
Peak memory 205604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190812004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4190812004
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/24.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.3566919604
Short name T243
Test name
Test status
Simulation time 28771208862 ps
CPU time 65.77 seconds
Started Sep 24 09:32:23 PM UTC 24
Finished Sep 24 09:33:30 PM UTC 24
Peak memory 205936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566919604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3566919604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/25.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.463033093
Short name T223
Test name
Test status
Simulation time 457094424 ps
CPU time 2.25 seconds
Started Sep 24 09:32:21 PM UTC 24
Finished Sep 24 09:32:24 PM UTC 24
Peak memory 205724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463033093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.463033093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/25.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.2233059468
Short name T238
Test name
Test status
Simulation time 27285487879 ps
CPU time 38.49 seconds
Started Sep 24 09:32:27 PM UTC 24
Finished Sep 24 09:33:07 PM UTC 24
Peak memory 206000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233059468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2233059468
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/26.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.2793261308
Short name T224
Test name
Test status
Simulation time 546029040 ps
CPU time 1.32 seconds
Started Sep 24 09:32:27 PM UTC 24
Finished Sep 24 09:32:30 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793261308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2793261308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/26.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.4239804491
Short name T237
Test name
Test status
Simulation time 11161398074 ps
CPU time 26.78 seconds
Started Sep 24 09:32:39 PM UTC 24
Finished Sep 24 09:33:07 PM UTC 24
Peak memory 206160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239804491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.4239804491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/27.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.4162886086
Short name T226
Test name
Test status
Simulation time 432858926 ps
CPU time 2.01 seconds
Started Sep 24 09:32:34 PM UTC 24
Finished Sep 24 09:32:37 PM UTC 24
Peak memory 205784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162886086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.4162886086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/27.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.1629172922
Short name T231
Test name
Test status
Simulation time 11114325875 ps
CPU time 9.51 seconds
Started Sep 24 09:32:43 PM UTC 24
Finished Sep 24 09:32:54 PM UTC 24
Peak memory 205936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629172922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1629172922
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/28.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.1976712483
Short name T227
Test name
Test status
Simulation time 529334047 ps
CPU time 1.33 seconds
Started Sep 24 09:32:43 PM UTC 24
Finished Sep 24 09:32:46 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976712483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1976712483
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/28.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.3281572341
Short name T236
Test name
Test status
Simulation time 10471820897 ps
CPU time 18.44 seconds
Started Sep 24 09:32:46 PM UTC 24
Finished Sep 24 09:33:06 PM UTC 24
Peak memory 206000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281572341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3281572341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/29.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.3432915456
Short name T228
Test name
Test status
Simulation time 526556182 ps
CPU time 1.39 seconds
Started Sep 24 09:32:46 PM UTC 24
Finished Sep 24 09:32:49 PM UTC 24
Peak memory 203816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432915456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3432915456
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/29.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.1172173736
Short name T195
Test name
Test status
Simulation time 34153740396 ps
CPU time 84.37 seconds
Started Sep 24 09:30:05 PM UTC 24
Finished Sep 24 09:31:31 PM UTC 24
Peak memory 206148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172173736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1172173736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.461168451
Short name T25
Test name
Test status
Simulation time 4009020358 ps
CPU time 12.48 seconds
Started Sep 24 09:30:08 PM UTC 24
Finished Sep 24 09:30:21 PM UTC 24
Peak memory 234224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461168451 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.461168451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.3700145157
Short name T7
Test name
Test status
Simulation time 488054054 ps
CPU time 1.29 seconds
Started Sep 24 09:30:01 PM UTC 24
Finished Sep 24 09:30:04 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700145157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3700145157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.3008490962
Short name T15
Test name
Test status
Simulation time 2191857075 ps
CPU time 19.17 seconds
Started Sep 24 09:30:06 PM UTC 24
Finished Sep 24 09:30:26 PM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3008490962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 3.aon_timer_stress_all_with_rand_reset.3008490962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.394731634
Short name T240
Test name
Test status
Simulation time 11265332484 ps
CPU time 22.43 seconds
Started Sep 24 09:32:51 PM UTC 24
Finished Sep 24 09:33:15 PM UTC 24
Peak memory 205956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394731634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.394731634
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/30.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.4048188644
Short name T230
Test name
Test status
Simulation time 528549069 ps
CPU time 2.34 seconds
Started Sep 24 09:32:50 PM UTC 24
Finished Sep 24 09:32:53 PM UTC 24
Peak memory 205648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048188644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.4048188644
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/30.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.2405605386
Short name T234
Test name
Test status
Simulation time 3560342347 ps
CPU time 3.65 seconds
Started Sep 24 09:32:54 PM UTC 24
Finished Sep 24 09:32:59 PM UTC 24
Peak memory 205788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405605386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2405605386
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/31.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.1197313782
Short name T233
Test name
Test status
Simulation time 458078800 ps
CPU time 2.41 seconds
Started Sep 24 09:32:54 PM UTC 24
Finished Sep 24 09:32:58 PM UTC 24
Peak memory 205652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197313782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1197313782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/31.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.713176790
Short name T273
Test name
Test status
Simulation time 55659923616 ps
CPU time 141.29 seconds
Started Sep 24 09:32:59 PM UTC 24
Finished Sep 24 09:35:23 PM UTC 24
Peak memory 206020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713176790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.713176790
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/32.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.1846369462
Short name T235
Test name
Test status
Simulation time 462045110 ps
CPU time 2.67 seconds
Started Sep 24 09:32:59 PM UTC 24
Finished Sep 24 09:33:02 PM UTC 24
Peak memory 205908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846369462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1846369462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/32.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.2157754130
Short name T175
Test name
Test status
Simulation time 1605706344 ps
CPU time 9.29 seconds
Started Sep 24 09:33:03 PM UTC 24
Finished Sep 24 09:33:13 PM UTC 24
Peak memory 216128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2157754130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 32.aon_timer_stress_all_with_rand_reset.2157754130
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.1919994150
Short name T253
Test name
Test status
Simulation time 33036836826 ps
CPU time 55.67 seconds
Started Sep 24 09:33:08 PM UTC 24
Finished Sep 24 09:34:05 PM UTC 24
Peak memory 206008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919994150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1919994150
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/33.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.2049653628
Short name T239
Test name
Test status
Simulation time 640123301 ps
CPU time 1.12 seconds
Started Sep 24 09:33:07 PM UTC 24
Finished Sep 24 09:33:09 PM UTC 24
Peak memory 205604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049653628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2049653628
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/33.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.1057520734
Short name T255
Test name
Test status
Simulation time 47095154316 ps
CPU time 49.94 seconds
Started Sep 24 09:33:15 PM UTC 24
Finished Sep 24 09:34:07 PM UTC 24
Peak memory 206008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057520734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1057520734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/34.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.3769747367
Short name T241
Test name
Test status
Simulation time 568954396 ps
CPU time 2.63 seconds
Started Sep 24 09:33:14 PM UTC 24
Finished Sep 24 09:33:18 PM UTC 24
Peak memory 205916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769747367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3769747367
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/34.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.2612134229
Short name T246
Test name
Test status
Simulation time 8008145369 ps
CPU time 13.6 seconds
Started Sep 24 09:33:21 PM UTC 24
Finished Sep 24 09:33:35 PM UTC 24
Peak memory 206024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612134229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2612134229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/35.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.807098706
Short name T242
Test name
Test status
Simulation time 509347946 ps
CPU time 1.77 seconds
Started Sep 24 09:33:21 PM UTC 24
Finished Sep 24 09:33:23 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807098706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.807098706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/35.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.4132805732
Short name T245
Test name
Test status
Simulation time 2077319512 ps
CPU time 4.16 seconds
Started Sep 24 09:33:28 PM UTC 24
Finished Sep 24 09:33:33 PM UTC 24
Peak memory 205652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132805732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.4132805732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/36.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.578035121
Short name T244
Test name
Test status
Simulation time 469637923 ps
CPU time 2.49 seconds
Started Sep 24 09:33:27 PM UTC 24
Finished Sep 24 09:33:30 PM UTC 24
Peak memory 205652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578035121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.578035121
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/36.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.2094889842
Short name T260
Test name
Test status
Simulation time 50685655272 ps
CPU time 39.59 seconds
Started Sep 24 09:33:33 PM UTC 24
Finished Sep 24 09:34:14 PM UTC 24
Peak memory 206088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094889842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2094889842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/37.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.2264560783
Short name T247
Test name
Test status
Simulation time 383039941 ps
CPU time 1.52 seconds
Started Sep 24 09:33:33 PM UTC 24
Finished Sep 24 09:33:36 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264560783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2264560783
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/37.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.2957163003
Short name T263
Test name
Test status
Simulation time 37761946694 ps
CPU time 40.04 seconds
Started Sep 24 09:33:37 PM UTC 24
Finished Sep 24 09:34:18 PM UTC 24
Peak memory 206096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957163003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2957163003
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/38.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.182855814
Short name T248
Test name
Test status
Simulation time 427567715 ps
CPU time 1.3 seconds
Started Sep 24 09:33:37 PM UTC 24
Finished Sep 24 09:33:39 PM UTC 24
Peak memory 205780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182855814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.182855814
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/38.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.3947048138
Short name T251
Test name
Test status
Simulation time 7163838045 ps
CPU time 9.65 seconds
Started Sep 24 09:33:41 PM UTC 24
Finished Sep 24 09:33:52 PM UTC 24
Peak memory 205944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947048138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3947048138
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/39.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.659214264
Short name T249
Test name
Test status
Simulation time 522342401 ps
CPU time 1.63 seconds
Started Sep 24 09:33:40 PM UTC 24
Finished Sep 24 09:33:43 PM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659214264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.659214264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/39.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.977633168
Short name T17
Test name
Test status
Simulation time 16645964058 ps
CPU time 15.6 seconds
Started Sep 24 09:30:11 PM UTC 24
Finished Sep 24 09:30:28 PM UTC 24
Peak memory 205932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977633168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.977633168
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.2435084042
Short name T26
Test name
Test status
Simulation time 4102062302 ps
CPU time 4.22 seconds
Started Sep 24 09:30:18 PM UTC 24
Finished Sep 24 09:30:24 PM UTC 24
Peak memory 234236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435084042 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2435084042
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.2855547837
Short name T13
Test name
Test status
Simulation time 525326921 ps
CPU time 1.32 seconds
Started Sep 24 09:30:09 PM UTC 24
Finished Sep 24 09:30:11 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855547837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2855547837
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/4.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.445626600
Short name T259
Test name
Test status
Simulation time 15809698508 ps
CPU time 23.47 seconds
Started Sep 24 09:33:48 PM UTC 24
Finished Sep 24 09:34:13 PM UTC 24
Peak memory 205932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445626600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.445626600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/40.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.2193797807
Short name T250
Test name
Test status
Simulation time 426494919 ps
CPU time 1.73 seconds
Started Sep 24 09:33:45 PM UTC 24
Finished Sep 24 09:33:48 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193797807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2193797807
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/40.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.914109919
Short name T271
Test name
Test status
Simulation time 33345912914 ps
CPU time 56.04 seconds
Started Sep 24 09:33:57 PM UTC 24
Finished Sep 24 09:34:54 PM UTC 24
Peak memory 206012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914109919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.914109919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/41.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.819616331
Short name T252
Test name
Test status
Simulation time 378088347 ps
CPU time 1.99 seconds
Started Sep 24 09:33:56 PM UTC 24
Finished Sep 24 09:33:59 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819616331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.819616331
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/41.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.727035572
Short name T172
Test name
Test status
Simulation time 411091792 ps
CPU time 1.13 seconds
Started Sep 24 09:34:06 PM UTC 24
Finished Sep 24 09:34:09 PM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727035572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.727035572
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/42.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.4146397861
Short name T256
Test name
Test status
Simulation time 21014924243 ps
CPU time 7.32 seconds
Started Sep 24 09:34:04 PM UTC 24
Finished Sep 24 09:34:13 PM UTC 24
Peak memory 205928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146397861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4146397861
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/42.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.1067158418
Short name T254
Test name
Test status
Simulation time 455290257 ps
CPU time 1.57 seconds
Started Sep 24 09:34:04 PM UTC 24
Finished Sep 24 09:34:07 PM UTC 24
Peak memory 205724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067158418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1067158418
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/42.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.3633594546
Short name T257
Test name
Test status
Simulation time 17365328219 ps
CPU time 2.07 seconds
Started Sep 24 09:34:09 PM UTC 24
Finished Sep 24 09:34:13 PM UTC 24
Peak memory 206072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633594546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3633594546
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/43.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.1315634383
Short name T258
Test name
Test status
Simulation time 575878959 ps
CPU time 2.87 seconds
Started Sep 24 09:34:08 PM UTC 24
Finished Sep 24 09:34:13 PM UTC 24
Peak memory 205648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315634383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1315634383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/43.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.3789900262
Short name T272
Test name
Test status
Simulation time 17301944256 ps
CPU time 48.05 seconds
Started Sep 24 09:34:14 PM UTC 24
Finished Sep 24 09:35:04 PM UTC 24
Peak memory 206000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789900262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3789900262
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/44.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.48095079
Short name T262
Test name
Test status
Simulation time 372461190 ps
CPU time 1.45 seconds
Started Sep 24 09:34:14 PM UTC 24
Finished Sep 24 09:34:16 PM UTC 24
Peak memory 203876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48095079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.48095079
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/44.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.2067061117
Short name T268
Test name
Test status
Simulation time 26778859572 ps
CPU time 21.99 seconds
Started Sep 24 09:34:15 PM UTC 24
Finished Sep 24 09:34:38 PM UTC 24
Peak memory 205936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067061117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2067061117
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/45.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.155523048
Short name T261
Test name
Test status
Simulation time 419178542 ps
CPU time 1.06 seconds
Started Sep 24 09:34:14 PM UTC 24
Finished Sep 24 09:34:16 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155523048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.155523048
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/45.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.2945528528
Short name T274
Test name
Test status
Simulation time 49921928726 ps
CPU time 87.67 seconds
Started Sep 24 09:34:18 PM UTC 24
Finished Sep 24 09:35:48 PM UTC 24
Peak memory 205952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945528528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2945528528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/46.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.476075624
Short name T264
Test name
Test status
Simulation time 537183377 ps
CPU time 1.2 seconds
Started Sep 24 09:34:17 PM UTC 24
Finished Sep 24 09:34:20 PM UTC 24
Peak memory 203872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476075624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.476075624
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/46.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.3570932902
Short name T269
Test name
Test status
Simulation time 11452850673 ps
CPU time 18.72 seconds
Started Sep 24 09:34:23 PM UTC 24
Finished Sep 24 09:34:43 PM UTC 24
Peak memory 205936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570932902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3570932902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/47.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.61800449
Short name T265
Test name
Test status
Simulation time 377251223 ps
CPU time 1.52 seconds
Started Sep 24 09:34:22 PM UTC 24
Finished Sep 24 09:34:24 PM UTC 24
Peak memory 205728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61800449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.61800449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/47.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.2960271293
Short name T267
Test name
Test status
Simulation time 1371181601 ps
CPU time 4.61 seconds
Started Sep 24 09:34:30 PM UTC 24
Finished Sep 24 09:34:36 PM UTC 24
Peak memory 205852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960271293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2960271293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/48.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.1219387650
Short name T266
Test name
Test status
Simulation time 420506762 ps
CPU time 2.4 seconds
Started Sep 24 09:34:27 PM UTC 24
Finished Sep 24 09:34:31 PM UTC 24
Peak memory 205652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219387650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1219387650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/48.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.3599199345
Short name T158
Test name
Test status
Simulation time 566421276 ps
CPU time 1.32 seconds
Started Sep 24 09:34:44 PM UTC 24
Finished Sep 24 09:34:46 PM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599199345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3599199345
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/49.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.3450376595
Short name T275
Test name
Test status
Simulation time 61335454542 ps
CPU time 107.76 seconds
Started Sep 24 09:34:41 PM UTC 24
Finished Sep 24 09:36:31 PM UTC 24
Peak memory 205928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450376595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3450376595
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/49.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.1231758203
Short name T270
Test name
Test status
Simulation time 551237035 ps
CPU time 2.6 seconds
Started Sep 24 09:34:39 PM UTC 24
Finished Sep 24 09:34:43 PM UTC 24
Peak memory 205584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231758203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1231758203
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/49.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.775546548
Short name T44
Test name
Test status
Simulation time 5010004515 ps
CPU time 18.05 seconds
Started Sep 24 09:30:22 PM UTC 24
Finished Sep 24 09:30:42 PM UTC 24
Peak memory 206056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775546548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.775546548
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.2409496344
Short name T33
Test name
Test status
Simulation time 565679489 ps
CPU time 2.6 seconds
Started Sep 24 09:30:20 PM UTC 24
Finished Sep 24 09:30:24 PM UTC 24
Peak memory 205308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409496344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2409496344
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/5.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.293046451
Short name T194
Test name
Test status
Simulation time 25406534923 ps
CPU time 60.68 seconds
Started Sep 24 09:30:29 PM UTC 24
Finished Sep 24 09:31:31 PM UTC 24
Peak memory 205928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293046451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.293046451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.1753482012
Short name T19
Test name
Test status
Simulation time 511754174 ps
CPU time 2.53 seconds
Started Sep 24 09:30:28 PM UTC 24
Finished Sep 24 09:30:31 PM UTC 24
Peak memory 205520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753482012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1753482012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/6.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.2811086650
Short name T196
Test name
Test status
Simulation time 40931991492 ps
CPU time 35.85 seconds
Started Sep 24 09:30:33 PM UTC 24
Finished Sep 24 09:31:10 PM UTC 24
Peak memory 206100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811086650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2811086650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.3435569559
Short name T200
Test name
Test status
Simulation time 525651039 ps
CPU time 2.72 seconds
Started Sep 24 09:30:33 PM UTC 24
Finished Sep 24 09:30:37 PM UTC 24
Peak memory 205896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435569559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3435569559
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/7.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.546815152
Short name T50
Test name
Test status
Simulation time 33571970993 ps
CPU time 39.3 seconds
Started Sep 24 09:30:38 PM UTC 24
Finished Sep 24 09:31:18 PM UTC 24
Peak memory 206152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546815152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.546815152
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.2263723905
Short name T198
Test name
Test status
Simulation time 481855771 ps
CPU time 1.33 seconds
Started Sep 24 09:30:38 PM UTC 24
Finished Sep 24 09:30:40 PM UTC 24
Peak memory 205840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263723905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2263723905
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/8.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.2780559560
Short name T190
Test name
Test status
Simulation time 6730790038 ps
CPU time 6.75 seconds
Started Sep 24 09:30:48 PM UTC 24
Finished Sep 24 09:30:56 PM UTC 24
Peak memory 205940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780559560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2780559560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.2633707669
Short name T201
Test name
Test status
Simulation time 497311322 ps
CPU time 2.7 seconds
Started Sep 24 09:30:43 PM UTC 24
Finished Sep 24 09:30:47 PM UTC 24
Peak memory 205456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633707669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2633707669
Directory /workspaces/repo/scratch/os_regression_2024_09_23/aon_timer-sim-vcs/9.aon_timer_smoke/latest
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