Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	17475	1			T1	10		T3	10		T4	14
bark[1]	581	1			T83	14		T95	91		T112	258
bark[2]	745	1			T12	171		T45	158		T112	183
bark[3]	132	1			T49	14		T150	50		T176	14
bark[4]	499	1			T18	14		T26	21		T27	59
bark[5]	549	1			T44	5		T25	62		T46	35
bark[6]	435	1			T17	14		T39	21		T134	14
bark[7]	791	1			T12	7		T35	178		T101	21
bark[8]	57	1			T17	5		T88	14		T78	5
bark[9]	143	1			T72	35		T107	21		T109	7
bark[10]	340	1			T114	14		T112	39		T116	35
bark[11]	295	1			T48	119		T73	26		T109	21
bark[12]	205	1			T32	14		T135	7		T116	30
bark[13]	224	1			T135	21		T177	14		T27	30
bark[14]	821	1			T135	223		T112	64		T164	14
bark[15]	463	1			T2	14		T45	26		T39	21
bark[16]	528	1			T20	21		T39	21		T47	7
bark[17]	517	1			T34	14		T35	195		T28	26
bark[18]	329	1			T6	14		T39	52		T182	14
bark[19]	202	1			T75	87		T85	21		T167	7
bark[20]	686	1			T20	39		T35	21		T89	14
bark[21]	218	1			T135	7		T154	14		T96	21
bark[22]	449	1			T20	26		T44	21		T46	26
bark[23]	19	1			T158	5		T173	14		-	-
bark[24]	267	1			T28	21		T95	7		T183	14
bark[25]	315	1			T22	14		T116	7		T110	120
bark[26]	626	1			T72	35		T170	14		T78	21
bark[27]	305	1			T35	192		T152	14		T108	21
bark[28]	218	1			T46	21		T47	7		T27	21
bark[29]	435	1			T17	26		T39	7		T112	158
bark[30]	333	1			T35	35		T71	47		T153	14
bark[31]	689	1			T25	21		T35	5		T27	51
bark_0	4875	1			T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	17278	1			T1	9		T3	9		T5	9
bite[1]	225	1			T46	21		T112	39		T27	59
bite[2]	325	1			T88	13		T47	6		T89	13
bite[3]	716	1			T112	257		T116	30		T179	13
bite[4]	554	1			T39	6		T83	13		T135	6
bite[5]	267	1			T34	13		T35	21		T194	14
bite[6]	278	1			T154	13		T131	13		T102	21
bite[7]	403	1			T109	291		T122	26		T80	26
bite[8]	355	1			T180	178		T109	46		T130	4
bite[9]	550	1			T176	13		T109	21		T110	21
bite[10]	522	1			T45	183		T39	51		T148	84
bite[11]	331	1			T15	13		T35	35		T183	13
bite[12]	379	1			T35	4		T114	13		T26	21
bite[13]	364	1			T44	4		T39	21		T135	6
bite[14]	453	1			T48	118		T135	42		T150	249
bite[15]	270	1			T6	13		T95	6		T71	21
bite[16]	190	1			T161	13		T116	68		T100	26
bite[17]	182	1			T12	6		T25	21		T95	90
bite[18]	324	1			T17	4		T150	6		T128	13
bite[19]	426	1			T18	13		T44	21		T39	21
bite[20]	300	1			T84	21		T150	42		T75	184
bite[21]	204	1			T26	21		T78	17		T147	6
bite[22]	351	1			T39	21		T101	13		T71	67
bite[23]	605	1			T49	13		T35	194		T27	30
bite[24]	828	1			T47	6		T134	13		T135	21
bite[25]	239	1			T8	13		T28	26		T72	34
bite[26]	225	1			T17	13		T20	26		T78	4
bite[27]	331	1			T2	13		T20	39		T32	13
bite[28]	449	1			T12	170		T101	21		T163	13
bite[29]	686	1			T22	13		T17	25		T35	177
bite[30]	220	1			T20	21		T72	6		T96	21
bite[31]	524	1			T4	13		T182	13		T46	76
bite_0	5412	1			T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31743

1

T1

17

T2

21

T3

17

auto[1]

3023

1

T17

132

T44

31

T25

24

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	914	1			T45	191		T35	59		T28	32
prescale[1]	162	1			T44	2		T39	2		T27	9
prescale[2]	836	1			T44	9		T112	9		T71	177
prescale[3]	228	1			T19	9		T180	60		T142	4
prescale[4]	254	1			T17	62		T35	9		T46	2
prescale[5]	258	1			T20	2		T50	9		T45	19
prescale[6]	426	1			T45	19		T46	46		T195	9
prescale[7]	308	1			T12	2		T44	2		T116	23
prescale[8]	475	1			T28	28		T196	9		T95	2
prescale[9]	416	1			T17	35		T44	21		T35	4
prescale[10]	545	1			T44	19		T135	40		T197	9
prescale[11]	332	1			T35	45		T48	2		T71	2
prescale[12]	365	1			T17	9		T46	25		T48	4
prescale[13]	301	1			T9	9		T25	26		T39	23
prescale[14]	194	1			T16	9		T20	19		T44	19
prescale[15]	458	1			T20	37		T35	2		T46	12
prescale[16]	348	1			T46	47		T198	9		T95	2
prescale[17]	363	1			T35	98		T46	75		T199	9
prescale[18]	483	1			T20	2		T21	9		T112	42
prescale[19]	387	1			T45	11		T112	72		T72	2
prescale[20]	491	1			T12	73		T39	2		T35	9
prescale[21]	320	1			T200	9		T101	19		T73	2
prescale[22]	517	1			T13	9		T201	9		T26	24
prescale[23]	673	1			T17	2		T25	24		T46	19
prescale[24]	354	1			T44	2		T73	23		T96	19
prescale[25]	406	1			T135	78		T26	19		T78	2
prescale[26]	367	1			T17	2		T25	19		T202	9
prescale[27]	220	1			T25	19		T203	9		T71	23
prescale[28]	425	1			T35	151		T158	2		T116	130
prescale[29]	502	1			T20	45		T112	40		T116	9
prescale[30]	465	1			T46	2		T71	23		T204	9
prescale[31]	426	1			T44	2		T35	19		T158	2
prescale_0	21547	1			T1	17		T2	21		T3	17

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23358

1

T1

17

T2

21

T3

17

auto[1]

11408

1

T9

10

T10

9

T12

63

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

wkup_cause_cleared

34766

1

T1

17

T2

21

T3

17

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	19314	1			T1	12		T2	1		T3	12
wkup[1]	284	1			T35	35		T112	21		T170	15
wkup[2]	217	1			T83	15		T112	21		T116	21
wkup[3]	132	1			T35	35		T47	8		T112	21
wkup[4]	236	1			T46	21		T123	36		T91	21
wkup[5]	215	1			T35	21		T135	21		T112	21
wkup[6]	233	1			T45	30		T116	6		T84	21
wkup[7]	109	1			T2	15		T112	26		T156	21
wkup[8]	146	1			T12	23		T147	30		T148	21
wkup[9]	202	1			T20	39		T25	21		T135	8
wkup[10]	164	1			T88	15		T184	15		T71	21
wkup[11]	185	1			T20	26		T153	15		T150	72
wkup[12]	149	1			T157	39		T144	21		T100	21
wkup[13]	119	1			T35	30		T180	21		T77	26
wkup[14]	204	1			T96	21		T109	21		T165	35
wkup[15]	212	1			T34	15		T26	21		T112	21
wkup[16]	161	1			T44	21		T95	26		T161	15
wkup[17]	190	1			T12	21		T135	21		T96	21
wkup[18]	146	1			T158	21		T72	8		T96	21
wkup[19]	99	1			T109	21		T119	21		T188	21
wkup[20]	140	1			T22	15		T32	15		T46	26
wkup[21]	265	1			T20	21		T45	26		T150	21
wkup[22]	187	1			T165	21		T110	21		T118	26
wkup[23]	229	1			T39	15		T116	35		T107	21
wkup[24]	182	1			T17	6		T45	26		T46	21
wkup[25]	122	1			T6	15		T15	15		T39	8
wkup[26]	196	1			T20	21		T46	21		T78	21
wkup[27]	203	1			T25	21		T95	8		T71	26
wkup[28]	113	1			T158	8		T180	24		T187	15
wkup[29]	198	1			T71	21		T116	21		T96	42
wkup[30]	281	1			T39	21		T35	21		T95	31
wkup[31]	281	1			T46	15		T26	21		T112	21
wkup[32]	148	1			T28	21		T101	21		T116	30
wkup[33]	188	1			T8	15		T112	30		T154	15
wkup[34]	224	1			T182	15		T112	21		T142	6
wkup[35]	158	1			T114	15		T142	21		T110	35
wkup[36]	74	1			T135	21		T108	24		T167	8
wkup[37]	182	1			T44	21		T46	21		T150	42
wkup[38]	281	1			T95	26		T112	21		T72	15
wkup[39]	273	1			T39	21		T35	26		T112	21
wkup[40]	275	1			T12	21		T17	15		T47	8
wkup[41]	216	1			T27	21		T116	21		T147	8
wkup[42]	156	1			T135	51		T109	42		T110	21
wkup[43]	271	1			T4	15		T35	21		T112	21
wkup[44]	206	1			T35	6		T135	8		T112	69
wkup[45]	203	1			T18	15		T48	42		T116	21
wkup[46]	159	1			T158	27		T116	21		T150	30
wkup[47]	338	1			T12	26		T134	15		T112	21
wkup[48]	172	1			T44	6		T39	21		T148	21
wkup[49]	225	1			T116	21		T84	21		T81	15
wkup[50]	149	1			T135	21		T116	26		T109	21
wkup[51]	114	1			T26	21		T112	21		T169	15
wkup[52]	230	1			T46	15		T158	21		T116	21
wkup[53]	120	1			T27	21		T84	21		T77	21
wkup[54]	113	1			T48	15		T142	21		T91	35
wkup[55]	105	1			T17	21		T44	6		T72	21
wkup[56]	84	1			T131	15		T102	21		T144	21
wkup[57]	221	1			T112	81		T116	21		T180	21
wkup[58]	160	1			T17	21		T116	71		T118	21
wkup[59]	196	1			T48	21		T183	15		T71	29
wkup[60]	192	1			T45	21		T35	21		T28	52
wkup[61]	197	1			T112	21		T164	15		T91	21
wkup[62]	109	1			T49	15		T27	30		T107	8
wkup[63]	78	1			T39	21		T35	21		T89	15
wkup_0	3835	1			T1	5		T2	5		T3	5