| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.79 | 99.32 | 95.61 | 100.00 | 98.38 | 99.51 | 45.90 |
| T283 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.49767801 | Oct 03 11:24:42 AM UTC 24 | Oct 03 11:24:44 AM UTC 24 | 477329609 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.57440525 | Oct 03 11:24:42 AM UTC 24 | Oct 03 11:24:47 AM UTC 24 | 4102147116 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.48817490 | Oct 03 11:24:45 AM UTC 24 | Oct 03 11:24:47 AM UTC 24 | 395486713 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.367114392 | Oct 03 11:24:45 AM UTC 24 | Oct 03 11:24:47 AM UTC 24 | 428736127 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.880187224 | Oct 03 11:24:47 AM UTC 24 | Oct 03 11:24:49 AM UTC 24 | 328003364 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2502062410 | Oct 03 11:24:48 AM UTC 24 | Oct 03 11:24:51 AM UTC 24 | 575671529 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3346906863 | Oct 03 11:24:47 AM UTC 24 | Oct 03 11:24:52 AM UTC 24 | 1006062077 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2491675921 | Oct 03 11:24:51 AM UTC 24 | Oct 03 11:24:54 AM UTC 24 | 409392875 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1390031110 | Oct 03 11:24:48 AM UTC 24 | Oct 03 11:24:56 AM UTC 24 | 6595136755 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.219229397 | Oct 03 11:24:52 AM UTC 24 | Oct 03 11:24:56 AM UTC 24 | 840137051 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1371231817 | Oct 03 11:24:53 AM UTC 24 | Oct 03 11:24:57 AM UTC 24 | 4395767863 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.1425407333 | Oct 03 11:24:55 AM UTC 24 | Oct 03 11:24:57 AM UTC 24 | 471544312 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.2548137687 | Oct 03 11:24:56 AM UTC 24 | Oct 03 11:24:58 AM UTC 24 | 348629717 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.91636228 | Oct 03 11:24:57 AM UTC 24 | Oct 03 11:25:00 AM UTC 24 | 350674744 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.826582404 | Oct 03 11:24:57 AM UTC 24 | Oct 03 11:25:00 AM UTC 24 | 656809258 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1992085375 | Oct 03 11:24:57 AM UTC 24 | Oct 03 11:25:00 AM UTC 24 | 604209607 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3595047499 | Oct 03 11:24:57 AM UTC 24 | Oct 03 11:25:01 AM UTC 24 | 410571324 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.516725467 | Oct 03 11:24:59 AM UTC 24 | Oct 03 11:25:01 AM UTC 24 | 1550588308 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1249371618 | Oct 03 11:24:51 AM UTC 24 | Oct 03 11:25:02 AM UTC 24 | 2150203540 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.296288578 | Oct 03 11:25:01 AM UTC 24 | Oct 03 11:25:03 AM UTC 24 | 361939224 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.1760904064 | Oct 03 11:25:02 AM UTC 24 | Oct 03 11:25:04 AM UTC 24 | 512237372 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2057703761 | Oct 03 11:25:03 AM UTC 24 | Oct 03 11:25:05 AM UTC 24 | 317970585 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.1408632557 | Oct 03 11:25:02 AM UTC 24 | Oct 03 11:25:05 AM UTC 24 | 343058046 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3931824526 | Oct 03 11:24:57 AM UTC 24 | Oct 03 11:25:06 AM UTC 24 | 4431159218 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.1284552590 | Oct 03 11:25:01 AM UTC 24 | Oct 03 11:25:06 AM UTC 24 | 511236372 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3707597161 | Oct 03 11:25:01 AM UTC 24 | Oct 03 11:25:06 AM UTC 24 | 4014399391 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1324406442 | Oct 03 11:25:04 AM UTC 24 | Oct 03 11:25:07 AM UTC 24 | 1177944849 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.893671723 | Oct 03 11:25:05 AM UTC 24 | Oct 03 11:25:07 AM UTC 24 | 291714225 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.2875651527 | Oct 03 11:25:08 AM UTC 24 | Oct 03 11:25:10 AM UTC 24 | 286475566 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3959240305 | Oct 03 11:25:08 AM UTC 24 | Oct 03 11:25:10 AM UTC 24 | 441294092 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.444565920 | Oct 03 11:25:07 AM UTC 24 | Oct 03 11:25:10 AM UTC 24 | 517184302 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1574702799 | Oct 03 11:25:06 AM UTC 24 | Oct 03 11:25:10 AM UTC 24 | 435620217 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.3035125123 | Oct 03 11:25:07 AM UTC 24 | Oct 03 11:25:11 AM UTC 24 | 614813691 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2371357705 | Oct 03 11:25:11 AM UTC 24 | Oct 03 11:25:13 AM UTC 24 | 456491477 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2255096670 | Oct 03 11:25:11 AM UTC 24 | Oct 03 11:25:13 AM UTC 24 | 717670508 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1388290738 | Oct 03 11:25:11 AM UTC 24 | Oct 03 11:25:13 AM UTC 24 | 528918908 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1455204774 | Oct 03 11:25:08 AM UTC 24 | Oct 03 11:25:13 AM UTC 24 | 4689760296 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.1435039047 | Oct 03 11:25:11 AM UTC 24 | Oct 03 11:25:14 AM UTC 24 | 433711916 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1511702907 | Oct 03 11:25:12 AM UTC 24 | Oct 03 11:25:15 AM UTC 24 | 1110278263 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1935548124 | Oct 03 11:25:06 AM UTC 24 | Oct 03 11:25:15 AM UTC 24 | 2563316459 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.3573496051 | Oct 03 11:25:14 AM UTC 24 | Oct 03 11:25:17 AM UTC 24 | 634894787 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2706646853 | Oct 03 11:25:14 AM UTC 24 | Oct 03 11:25:17 AM UTC 24 | 323963268 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.533583432 | Oct 03 11:25:14 AM UTC 24 | Oct 03 11:25:17 AM UTC 24 | 456685089 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2842711567 | Oct 03 11:25:15 AM UTC 24 | Oct 03 11:25:18 AM UTC 24 | 358815569 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.176812001 | Oct 03 11:25:15 AM UTC 24 | Oct 03 11:25:18 AM UTC 24 | 452444073 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.139006597 | Oct 03 11:25:16 AM UTC 24 | Oct 03 11:25:19 AM UTC 24 | 1134283915 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.1947022659 | Oct 03 11:25:18 AM UTC 24 | Oct 03 11:25:20 AM UTC 24 | 545792647 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1576899610 | Oct 03 11:25:19 AM UTC 24 | Oct 03 11:25:21 AM UTC 24 | 563657240 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1986908043 | Oct 03 11:25:19 AM UTC 24 | Oct 03 11:25:22 AM UTC 24 | 428180327 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1152226298 | Oct 03 11:25:19 AM UTC 24 | Oct 03 11:25:22 AM UTC 24 | 2151747551 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2227596665 | Oct 03 11:25:14 AM UTC 24 | Oct 03 11:25:23 AM UTC 24 | 4282956082 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.3325140496 | Oct 03 11:25:20 AM UTC 24 | Oct 03 11:25:24 AM UTC 24 | 567131696 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.3919378140 | Oct 03 11:25:22 AM UTC 24 | Oct 03 11:25:25 AM UTC 24 | 447172326 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3749338625 | Oct 03 11:25:11 AM UTC 24 | Oct 03 11:25:25 AM UTC 24 | 13801585283 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3569511597 | Oct 03 11:25:21 AM UTC 24 | Oct 03 11:25:25 AM UTC 24 | 4032342151 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.3302925961 | Oct 03 11:25:23 AM UTC 24 | Oct 03 11:25:25 AM UTC 24 | 546466658 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2836646311 | Oct 03 11:25:24 AM UTC 24 | Oct 03 11:25:27 AM UTC 24 | 406550842 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.3319449268 | Oct 03 11:25:36 AM UTC 24 | Oct 03 11:25:40 AM UTC 24 | 484076006 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2951857535 | Oct 03 11:25:25 AM UTC 24 | Oct 03 11:25:27 AM UTC 24 | 417947462 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4286975950 | Oct 03 11:25:23 AM UTC 24 | Oct 03 11:25:28 AM UTC 24 | 1603157766 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.3890303150 | Oct 03 11:25:26 AM UTC 24 | Oct 03 11:25:28 AM UTC 24 | 328034029 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.2897628131 | Oct 03 11:25:24 AM UTC 24 | Oct 03 11:25:29 AM UTC 24 | 515961737 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.886261466 | Oct 03 11:25:27 AM UTC 24 | Oct 03 11:25:31 AM UTC 24 | 2150272657 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2206399274 | Oct 03 11:25:28 AM UTC 24 | Oct 03 11:25:31 AM UTC 24 | 371005610 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.1260199937 | Oct 03 11:25:29 AM UTC 24 | Oct 03 11:25:32 AM UTC 24 | 526792170 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2714790963 | Oct 03 11:25:18 AM UTC 24 | Oct 03 11:25:32 AM UTC 24 | 10727778464 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3027004014 | Oct 03 11:25:31 AM UTC 24 | Oct 03 11:25:33 AM UTC 24 | 367965963 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.3932297196 | Oct 03 11:25:30 AM UTC 24 | Oct 03 11:25:34 AM UTC 24 | 536441188 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.1364817010 | Oct 03 11:25:29 AM UTC 24 | Oct 03 11:25:35 AM UTC 24 | 584086390 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1199858460 | Oct 03 11:25:06 AM UTC 24 | Oct 03 11:25:35 AM UTC 24 | 13881294742 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.2428979227 | Oct 03 11:25:32 AM UTC 24 | Oct 03 11:25:35 AM UTC 24 | 377859242 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1330259337 | Oct 03 11:25:31 AM UTC 24 | Oct 03 11:25:36 AM UTC 24 | 892003351 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.867178758 | Oct 03 11:25:32 AM UTC 24 | Oct 03 11:25:36 AM UTC 24 | 845956725 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.3717202391 | Oct 03 11:25:34 AM UTC 24 | Oct 03 11:25:37 AM UTC 24 | 390218623 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.937450213 | Oct 03 11:25:25 AM UTC 24 | Oct 03 11:25:37 AM UTC 24 | 4489352486 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1671888862 | Oct 03 11:25:36 AM UTC 24 | Oct 03 11:25:39 AM UTC 24 | 327452872 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.760860076 | Oct 03 11:25:37 AM UTC 24 | Oct 03 11:25:39 AM UTC 24 | 346362777 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.279863342 | Oct 03 11:25:37 AM UTC 24 | Oct 03 11:25:40 AM UTC 24 | 498309633 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4171509099 | Oct 03 11:25:38 AM UTC 24 | Oct 03 11:25:41 AM UTC 24 | 617248259 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.479327771 | Oct 03 11:25:38 AM UTC 24 | Oct 03 11:25:41 AM UTC 24 | 1593787113 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3207560965 | Oct 03 11:25:35 AM UTC 24 | Oct 03 11:25:41 AM UTC 24 | 1464782190 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.617624269 | Oct 03 11:25:39 AM UTC 24 | Oct 03 11:25:42 AM UTC 24 | 299507998 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.382301120 | Oct 03 11:25:40 AM UTC 24 | Oct 03 11:25:43 AM UTC 24 | 299166189 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.3280317995 | Oct 03 11:25:40 AM UTC 24 | Oct 03 11:25:44 AM UTC 24 | 387776924 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2097906791 | Oct 03 11:25:32 AM UTC 24 | Oct 03 11:25:44 AM UTC 24 | 8191846756 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3222885217 | Oct 03 11:25:41 AM UTC 24 | Oct 03 11:25:44 AM UTC 24 | 342571135 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2338901086 | Oct 03 11:25:39 AM UTC 24 | Oct 03 11:25:44 AM UTC 24 | 4589030461 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3761886858 | Oct 03 11:25:41 AM UTC 24 | Oct 03 11:25:45 AM UTC 24 | 1540298096 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.2657603729 | Oct 03 11:25:43 AM UTC 24 | Oct 03 11:25:45 AM UTC 24 | 464259113 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.4200161139 | Oct 03 11:25:44 AM UTC 24 | Oct 03 11:25:46 AM UTC 24 | 311802607 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.1828359722 | Oct 03 11:25:42 AM UTC 24 | Oct 03 11:25:46 AM UTC 24 | 411222360 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.679966753 | Oct 03 11:25:45 AM UTC 24 | Oct 03 11:25:48 AM UTC 24 | 492229743 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.111157352 | Oct 03 11:25:45 AM UTC 24 | Oct 03 11:25:48 AM UTC 24 | 526526581 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.227098731 | Oct 03 11:25:45 AM UTC 24 | Oct 03 11:25:48 AM UTC 24 | 483179751 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.78901775 | Oct 03 11:25:46 AM UTC 24 | Oct 03 11:25:49 AM UTC 24 | 570286950 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2367049761 | Oct 03 11:25:37 AM UTC 24 | Oct 03 11:25:49 AM UTC 24 | 8845172154 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3456089299 | Oct 03 11:25:45 AM UTC 24 | Oct 03 11:25:49 AM UTC 24 | 774074320 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2386164164 | Oct 03 11:25:46 AM UTC 24 | Oct 03 11:25:49 AM UTC 24 | 2474425897 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1297589294 | Oct 03 11:25:47 AM UTC 24 | Oct 03 11:25:50 AM UTC 24 | 4242299447 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3335451531 | Oct 03 11:25:46 AM UTC 24 | Oct 03 11:25:50 AM UTC 24 | 475953355 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1663520414 | Oct 03 11:25:49 AM UTC 24 | Oct 03 11:25:51 AM UTC 24 | 267401269 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2555338702 | Oct 03 11:25:49 AM UTC 24 | Oct 03 11:25:51 AM UTC 24 | 292238633 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.236816146 | Oct 03 11:25:45 AM UTC 24 | Oct 03 11:25:52 AM UTC 24 | 2602405331 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2283464142 | Oct 03 11:25:50 AM UTC 24 | Oct 03 11:25:52 AM UTC 24 | 371950117 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3207239059 | Oct 03 11:25:29 AM UTC 24 | Oct 03 11:25:53 AM UTC 24 | 7560450512 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.1871448984 | Oct 03 11:25:51 AM UTC 24 | Oct 03 11:25:53 AM UTC 24 | 383049021 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.1327591901 | Oct 03 11:25:50 AM UTC 24 | Oct 03 11:25:53 AM UTC 24 | 463439482 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4133170566 | Oct 03 11:25:50 AM UTC 24 | Oct 03 11:25:55 AM UTC 24 | 2077904245 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.2093481380 | Oct 03 11:25:50 AM UTC 24 | Oct 03 11:25:55 AM UTC 24 | 486833314 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1923194252 | Oct 03 11:25:51 AM UTC 24 | Oct 03 11:25:55 AM UTC 24 | 1531116228 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.33226609 | Oct 03 11:25:52 AM UTC 24 | Oct 03 11:25:56 AM UTC 24 | 446557225 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.1218288755 | Oct 03 11:25:53 AM UTC 24 | Oct 03 11:25:56 AM UTC 24 | 519081867 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.528597944 | Oct 03 11:25:54 AM UTC 24 | Oct 03 11:25:56 AM UTC 24 | 513344707 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.1099996860 | Oct 03 11:25:52 AM UTC 24 | Oct 03 11:25:57 AM UTC 24 | 566702248 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.207451009 | Oct 03 11:25:55 AM UTC 24 | Oct 03 11:25:57 AM UTC 24 | 608689813 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2491463081 | Oct 03 11:25:54 AM UTC 24 | Oct 03 11:25:57 AM UTC 24 | 1072452852 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1031571678 | Oct 03 11:25:42 AM UTC 24 | Oct 03 11:25:59 AM UTC 24 | 7936433443 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.3595381119 | Oct 03 11:25:57 AM UTC 24 | Oct 03 11:25:59 AM UTC 24 | 503108486 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.3524142132 | Oct 03 11:25:57 AM UTC 24 | Oct 03 11:26:00 AM UTC 24 | 309457027 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.3194022681 | Oct 03 11:26:12 AM UTC 24 | Oct 03 11:26:16 AM UTC 24 | 436521431 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.408011690 | Oct 03 11:25:56 AM UTC 24 | Oct 03 11:26:00 AM UTC 24 | 535765808 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1160248524 | Oct 03 11:25:57 AM UTC 24 | Oct 03 11:26:00 AM UTC 24 | 352039305 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.3498302530 | Oct 03 11:25:58 AM UTC 24 | Oct 03 11:26:01 AM UTC 24 | 314429046 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.449390614 | Oct 03 11:25:58 AM UTC 24 | Oct 03 11:26:01 AM UTC 24 | 685513581 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.135865485 | Oct 03 11:26:00 AM UTC 24 | Oct 03 11:26:02 AM UTC 24 | 369427803 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4248836344 | Oct 03 11:26:00 AM UTC 24 | Oct 03 11:26:04 AM UTC 24 | 355670255 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.481422960 | Oct 03 11:26:00 AM UTC 24 | Oct 03 11:26:04 AM UTC 24 | 358723801 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.991165470 | Oct 03 11:26:02 AM UTC 24 | Oct 03 11:26:04 AM UTC 24 | 271315347 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.500593148 | Oct 03 11:26:02 AM UTC 24 | Oct 03 11:26:04 AM UTC 24 | 2906147969 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1418973639 | Oct 03 11:25:57 AM UTC 24 | Oct 03 11:26:05 AM UTC 24 | 2307154943 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.3370419909 | Oct 03 11:26:02 AM UTC 24 | Oct 03 11:26:05 AM UTC 24 | 528413230 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4263050278 | Oct 03 11:26:00 AM UTC 24 | Oct 03 11:26:06 AM UTC 24 | 4362108563 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.497129032 | Oct 03 11:25:45 AM UTC 24 | Oct 03 11:26:07 AM UTC 24 | 8617599541 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2041432192 | Oct 03 11:26:00 AM UTC 24 | Oct 03 11:26:07 AM UTC 24 | 2708916507 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1913438357 | Oct 03 11:26:04 AM UTC 24 | Oct 03 11:26:07 AM UTC 24 | 544476121 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.1176956279 | Oct 03 11:26:12 AM UTC 24 | Oct 03 11:26:15 AM UTC 24 | 455037565 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.3654869007 | Oct 03 11:26:05 AM UTC 24 | Oct 03 11:26:08 AM UTC 24 | 471557288 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.4213927556 | Oct 03 11:26:05 AM UTC 24 | Oct 03 11:26:08 AM UTC 24 | 379949233 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2020958314 | Oct 03 11:26:05 AM UTC 24 | Oct 03 11:26:08 AM UTC 24 | 4703335804 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.3020161172 | Oct 03 11:26:06 AM UTC 24 | Oct 03 11:26:09 AM UTC 24 | 429592790 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.958940382 | Oct 03 11:26:06 AM UTC 24 | Oct 03 11:26:09 AM UTC 24 | 481117369 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.513767736 | Oct 03 11:26:05 AM UTC 24 | Oct 03 11:26:09 AM UTC 24 | 706618241 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3507917352 | Oct 03 11:25:53 AM UTC 24 | Oct 03 11:26:10 AM UTC 24 | 8423517809 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.3316132524 | Oct 03 11:26:08 AM UTC 24 | Oct 03 11:26:11 AM UTC 24 | 433659617 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3206786496 | Oct 03 11:25:58 AM UTC 24 | Oct 03 11:26:12 AM UTC 24 | 7960495376 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.3263902645 | Oct 03 11:26:08 AM UTC 24 | Oct 03 11:26:12 AM UTC 24 | 265674525 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.548604840 | Oct 03 11:26:10 AM UTC 24 | Oct 03 11:26:12 AM UTC 24 | 470415420 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3913003551 | Oct 03 11:26:08 AM UTC 24 | Oct 03 11:26:12 AM UTC 24 | 380786805 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2125930053 | Oct 03 11:25:56 AM UTC 24 | Oct 03 11:26:12 AM UTC 24 | 8258744536 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.1412876023 | Oct 03 11:26:08 AM UTC 24 | Oct 03 11:26:12 AM UTC 24 | 485243226 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.690601848 | Oct 03 11:26:08 AM UTC 24 | Oct 03 11:26:12 AM UTC 24 | 510317401 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.3965319642 | Oct 03 11:26:10 AM UTC 24 | Oct 03 11:26:12 AM UTC 24 | 485304459 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.4279772307 | Oct 03 11:26:11 AM UTC 24 | Oct 03 11:26:13 AM UTC 24 | 457391436 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.1660183651 | Oct 03 11:26:11 AM UTC 24 | Oct 03 11:26:14 AM UTC 24 | 456650689 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3502597369 | Oct 03 11:26:12 AM UTC 24 | Oct 03 11:26:14 AM UTC 24 | 309449979 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3266016906 | Oct 03 11:26:13 AM UTC 24 | Oct 03 11:26:16 AM UTC 24 | 480911497 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2105484689 | Oct 03 11:26:13 AM UTC 24 | Oct 03 11:26:16 AM UTC 24 | 502080585 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.372543898 | Oct 03 11:26:13 AM UTC 24 | Oct 03 11:26:16 AM UTC 24 | 329658862 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.2851033269 | Oct 03 11:26:13 AM UTC 24 | Oct 03 11:26:16 AM UTC 24 | 476524762 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.160562670 | Oct 03 11:26:06 AM UTC 24 | Oct 03 11:26:17 AM UTC 24 | 2169151324 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.3943584322 | Oct 03 11:26:13 AM UTC 24 | Oct 03 11:26:17 AM UTC 24 | 268934356 ps | ||
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| T413 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.4078424896 | Oct 03 11:26:13 AM UTC 24 | Oct 03 11:26:17 AM UTC 24 | 494280560 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2567188820 | Oct 03 11:26:13 AM UTC 24 | Oct 03 11:26:17 AM UTC 24 | 445087231 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.3830200776 | Oct 03 11:26:14 AM UTC 24 | Oct 03 11:26:17 AM UTC 24 | 426256968 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2964885600 | Oct 03 11:25:50 AM UTC 24 | Oct 03 11:26:18 AM UTC 24 | 8181188163 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.1492326648 | Oct 03 11:26:16 AM UTC 24 | Oct 03 11:26:18 AM UTC 24 | 473510892 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2395832405 | Oct 03 11:26:16 AM UTC 24 | Oct 03 11:26:18 AM UTC 24 | 287533863 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.1009451604 | Oct 03 11:26:17 AM UTC 24 | Oct 03 11:26:19 AM UTC 24 | 434552964 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.3262159594 | Oct 03 11:26:17 AM UTC 24 | Oct 03 11:26:19 AM UTC 24 | 482050780 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.333007874 | Oct 03 11:26:17 AM UTC 24 | Oct 03 11:26:20 AM UTC 24 | 463291990 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.1944072372 | Oct 03 11:26:18 AM UTC 24 | Oct 03 11:26:20 AM UTC 24 | 352505061 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.399727064 | Oct 03 11:26:18 AM UTC 24 | Oct 03 11:26:21 AM UTC 24 | 436429016 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.1401480938 | Oct 03 11:26:18 AM UTC 24 | Oct 03 11:26:21 AM UTC 24 | 381951560 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.2591667291 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 439118181 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 11:26:22 AM UTC 24 |
| Finished | Oct 03 11:26:25 AM UTC 24 |
| Peak memory | 205428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591667291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2591667291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.1845238424 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3569669205 ps |
| CPU time | 21.89 seconds |
| Started | Oct 03 11:26:27 AM UTC 24 |
| Finished | Oct 03 11:26:50 AM UTC 24 |
| Peak memory | 222880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1845238424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 3.aon_timer_stress_all_with_rand_reset.1845238424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.1463585394 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11200373519 ps |
| CPU time | 48.93 seconds |
| Started | Oct 03 11:26:22 AM UTC 24 |
| Finished | Oct 03 11:27:13 AM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1463585394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.aon_timer_stress_all_with_rand_reset.1463585394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.57440525 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4102147116 ps |
| CPU time | 3.57 seconds |
| Started | Oct 03 11:24:42 AM UTC 24 |
| Finished | Oct 03 11:24:47 AM UTC 24 |
| Peak memory | 206692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57440525 -assert nopostproc +UVM_TEST NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.57440525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.953654538 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 57409161114 ps |
| CPU time | 73.96 seconds |
| Started | Oct 03 11:28:47 AM UTC 24 |
| Finished | Oct 03 11:30:02 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=953654538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.aon_timer_stress_all_with_rand_reset.953654538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.43499263 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 59772510572 ps |
| CPU time | 111.91 seconds |
| Started | Oct 03 11:26:22 AM UTC 24 |
| Finished | Oct 03 11:28:16 AM UTC 24 |
| Peak memory | 207244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43499263 -assert nopostproc +UVM_TESTNAME =aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.43499263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.2638786248 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2108466977 ps |
| CPU time | 18.21 seconds |
| Started | Oct 03 11:26:18 AM UTC 24 |
| Finished | Oct 03 11:26:38 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2638786248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.aon_timer_stress_all_with_rand_reset.2638786248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1390031110 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 6595136755 ps |
| CPU time | 6.14 seconds |
| Started | Oct 03 11:24:48 AM UTC 24 |
| Finished | Oct 03 11:24:56 AM UTC 24 |
| Peak memory | 205580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390031110 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.1390031110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.4157895846 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 15157164151 ps |
| CPU time | 61.28 seconds |
| Started | Oct 03 11:27:07 AM UTC 24 |
| Finished | Oct 03 11:28:10 AM UTC 24 |
| Peak memory | 207524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4157895846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.aon_timer_stress_all_with_rand_reset.4157895846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.3444336771 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 15126515294 ps |
| CPU time | 45.64 seconds |
| Started | Oct 03 11:31:35 AM UTC 24 |
| Finished | Oct 03 11:32:22 AM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3444336771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 44.aon_timer_stress_all_with_rand_reset.3444336771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.335058179 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 5855724479 ps |
| CPU time | 46.07 seconds |
| Started | Oct 03 11:27:53 AM UTC 24 |
| Finished | Oct 03 11:28:40 AM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=335058179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.aon_timer_stress_all_with_rand_reset.335058179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.1673867823 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 92191246348 ps |
| CPU time | 143.58 seconds |
| Started | Oct 03 11:31:23 AM UTC 24 |
| Finished | Oct 03 11:33:49 AM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673867823 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.1673867823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/42.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.1777744849 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4412161999 ps |
| CPU time | 13.39 seconds |
| Started | Oct 03 11:26:19 AM UTC 24 |
| Finished | Oct 03 11:26:34 AM UTC 24 |
| Peak memory | 234572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777744849 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1777744849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.528739692 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 23616696198 ps |
| CPU time | 18.82 seconds |
| Started | Oct 03 11:30:52 AM UTC 24 |
| Finished | Oct 03 11:31:12 AM UTC 24 |
| Peak memory | 207180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528739692 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.528739692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/36.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.2973446222 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 134556958426 ps |
| CPU time | 273.52 seconds |
| Started | Oct 03 11:28:52 AM UTC 24 |
| Finished | Oct 03 11:33:30 AM UTC 24 |
| Peak memory | 207336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973446222 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.2973446222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/24.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.1082337610 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 5774442087 ps |
| CPU time | 38.73 seconds |
| Started | Oct 03 11:32:07 AM UTC 24 |
| Finished | Oct 03 11:32:48 AM UTC 24 |
| Peak memory | 222796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1082337610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 48.aon_timer_stress_all_with_rand_reset.1082337610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.2518731481 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2440540562 ps |
| CPU time | 20.05 seconds |
| Started | Oct 03 11:31:10 AM UTC 24 |
| Finished | Oct 03 11:31:31 AM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2518731481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 39.aon_timer_stress_all_with_rand_reset.2518731481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.764699842 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 120059915461 ps |
| CPU time | 173.69 seconds |
| Started | Oct 03 11:26:18 AM UTC 24 |
| Finished | Oct 03 11:29:15 AM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764699842 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.764699842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.2840373041 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 87329447130 ps |
| CPU time | 170.38 seconds |
| Started | Oct 03 11:28:16 AM UTC 24 |
| Finished | Oct 03 11:31:09 AM UTC 24 |
| Peak memory | 207116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840373041 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.2840373041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.1811097823 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 59364114007 ps |
| CPU time | 18.69 seconds |
| Started | Oct 03 11:29:31 AM UTC 24 |
| Finished | Oct 03 11:29:50 AM UTC 24 |
| Peak memory | 207252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811097823 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.1811097823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/28.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.1508630469 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 222869172732 ps |
| CPU time | 195.74 seconds |
| Started | Oct 03 11:31:53 AM UTC 24 |
| Finished | Oct 03 11:35:12 AM UTC 24 |
| Peak memory | 207252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508630469 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.1508630469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/46.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.617308710 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 50923138735 ps |
| CPU time | 24.43 seconds |
| Started | Oct 03 11:30:25 AM UTC 24 |
| Finished | Oct 03 11:30:51 AM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617308710 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.617308710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/34.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.620360006 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 306152235734 ps |
| CPU time | 555.72 seconds |
| Started | Oct 03 11:27:07 AM UTC 24 |
| Finished | Oct 03 11:36:30 AM UTC 24 |
| Peak memory | 207244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620360006 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.620360006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.1490762257 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 125087627755 ps |
| CPU time | 232.56 seconds |
| Started | Oct 03 11:27:38 AM UTC 24 |
| Finished | Oct 03 11:31:34 AM UTC 24 |
| Peak memory | 207180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490762257 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.1490762257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.2800757174 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 9024266466 ps |
| CPU time | 42.85 seconds |
| Started | Oct 03 11:29:19 AM UTC 24 |
| Finished | Oct 03 11:30:04 AM UTC 24 |
| Peak memory | 207352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2800757174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 27.aon_timer_stress_all_with_rand_reset.2800757174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.2116562854 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2674628189 ps |
| CPU time | 19.17 seconds |
| Started | Oct 03 11:26:50 AM UTC 24 |
| Finished | Oct 03 11:27:10 AM UTC 24 |
| Peak memory | 207316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2116562854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 6.aon_timer_stress_all_with_rand_reset.2116562854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.254883075 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 95940555180 ps |
| CPU time | 123.6 seconds |
| Started | Oct 03 11:26:59 AM UTC 24 |
| Finished | Oct 03 11:29:04 AM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254883075 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.254883075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.3276215156 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 506462695979 ps |
| CPU time | 97.77 seconds |
| Started | Oct 03 11:30:59 AM UTC 24 |
| Finished | Oct 03 11:32:39 AM UTC 24 |
| Peak memory | 207096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276215156 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.3276215156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/37.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.930486311 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 122928160203 ps |
| CPU time | 178.67 seconds |
| Started | Oct 03 11:28:23 AM UTC 24 |
| Finished | Oct 03 11:31:25 AM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930486311 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.930486311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.1018932201 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 153218759748 ps |
| CPU time | 57.62 seconds |
| Started | Oct 03 11:28:39 AM UTC 24 |
| Finished | Oct 03 11:29:39 AM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018932201 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.1018932201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/22.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.3559334397 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 10848038662 ps |
| CPU time | 23.93 seconds |
| Started | Oct 03 11:29:54 AM UTC 24 |
| Finished | Oct 03 11:30:19 AM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3559334397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 31.aon_timer_stress_all_with_rand_reset.3559334397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.3470915631 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 317914021595 ps |
| CPU time | 239.77 seconds |
| Started | Oct 03 11:31:43 AM UTC 24 |
| Finished | Oct 03 11:35:46 AM UTC 24 |
| Peak memory | 207096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470915631 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.3470915631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/45.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.2211294609 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1986981736 ps |
| CPU time | 14.11 seconds |
| Started | Oct 03 11:26:42 AM UTC 24 |
| Finished | Oct 03 11:26:57 AM UTC 24 |
| Peak memory | 207260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2211294609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 5.aon_timer_stress_all_with_rand_reset.2211294609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.1867160464 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5021124096 ps |
| CPU time | 16.62 seconds |
| Started | Oct 03 11:26:57 AM UTC 24 |
| Finished | Oct 03 11:27:15 AM UTC 24 |
| Peak memory | 207372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1867160464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 7.aon_timer_stress_all_with_rand_reset.1867160464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.734644634 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 847798434932 ps |
| CPU time | 880.07 seconds |
| Started | Oct 03 11:28:31 AM UTC 24 |
| Finished | Oct 03 11:43:21 AM UTC 24 |
| Peak memory | 207344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734644634 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.734644634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/21.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.2694235293 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3686588254 ps |
| CPU time | 32.28 seconds |
| Started | Oct 03 11:28:30 AM UTC 24 |
| Finished | Oct 03 11:29:04 AM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2694235293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 21.aon_timer_stress_all_with_rand_reset.2694235293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.2075404064 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 9291575725 ps |
| CPU time | 48.7 seconds |
| Started | Oct 03 11:31:04 AM UTC 24 |
| Finished | Oct 03 11:31:55 AM UTC 24 |
| Peak memory | 207388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2075404064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 38.aon_timer_stress_all_with_rand_reset.2075404064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.3291294492 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 13490981629 ps |
| CPU time | 52.89 seconds |
| Started | Oct 03 11:29:48 AM UTC 24 |
| Finished | Oct 03 11:30:43 AM UTC 24 |
| Peak memory | 223060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3291294492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 30.aon_timer_stress_all_with_rand_reset.3291294492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.777537559 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 232206241795 ps |
| CPU time | 283.03 seconds |
| Started | Oct 03 11:29:55 AM UTC 24 |
| Finished | Oct 03 11:34:41 AM UTC 24 |
| Peak memory | 207148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777537559 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.777537559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/31.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.1704396162 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3810674732 ps |
| CPU time | 49.07 seconds |
| Started | Oct 03 11:30:24 AM UTC 24 |
| Finished | Oct 03 11:31:15 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1704396162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 34.aon_timer_stress_all_with_rand_reset.1704396162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.4170797476 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 4338031863 ps |
| CPU time | 21.19 seconds |
| Started | Oct 03 11:31:19 AM UTC 24 |
| Finished | Oct 03 11:31:41 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4170797476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 41.aon_timer_stress_all_with_rand_reset.4170797476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.2940977275 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 12861940660 ps |
| CPU time | 35.42 seconds |
| Started | Oct 03 11:27:10 AM UTC 24 |
| Finished | Oct 03 11:27:47 AM UTC 24 |
| Peak memory | 216336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2940977275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 10.aon_timer_stress_all_with_rand_reset.2940977275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.3271747988 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 78310515758 ps |
| CPU time | 127.3 seconds |
| Started | Oct 03 11:28:47 AM UTC 24 |
| Finished | Oct 03 11:30:56 AM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271747988 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.3271747988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/23.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.3763301810 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 240592209748 ps |
| CPU time | 111.61 seconds |
| Started | Oct 03 11:30:04 AM UTC 24 |
| Finished | Oct 03 11:31:58 AM UTC 24 |
| Peak memory | 207316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763301810 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.3763301810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/32.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.4063522439 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 10469574313 ps |
| CPU time | 35.79 seconds |
| Started | Oct 03 11:30:08 AM UTC 24 |
| Finished | Oct 03 11:30:46 AM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4063522439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 33.aon_timer_stress_all_with_rand_reset.4063522439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.961483931 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 6190349683 ps |
| CPU time | 25.77 seconds |
| Started | Oct 03 11:28:05 AM UTC 24 |
| Finished | Oct 03 11:28:32 AM UTC 24 |
| Peak memory | 222680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=961483931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.aon_timer_stress_all_with_rand_reset.961483931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.1110830620 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 297663673610 ps |
| CPU time | 54.32 seconds |
| Started | Oct 03 11:30:11 AM UTC 24 |
| Finished | Oct 03 11:31:06 AM UTC 24 |
| Peak memory | 207096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110830620 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.1110830620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/33.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.1379148400 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 38509394086 ps |
| CPU time | 50.98 seconds |
| Started | Oct 03 11:26:21 AM UTC 24 |
| Finished | Oct 03 11:27:13 AM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379148400 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.1379148400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.2667774260 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 55408269280 ps |
| CPU time | 33.06 seconds |
| Started | Oct 03 11:27:47 AM UTC 24 |
| Finished | Oct 03 11:28:22 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667774260 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.2667774260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.4051168420 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 13663946984 ps |
| CPU time | 51 seconds |
| Started | Oct 03 11:28:36 AM UTC 24 |
| Finished | Oct 03 11:29:29 AM UTC 24 |
| Peak memory | 216424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4051168420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 22.aon_timer_stress_all_with_rand_reset.4051168420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.880187224 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 328003364 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 11:24:47 AM UTC 24 |
| Finished | Oct 03 11:24:49 AM UTC 24 |
| Peak memory | 201764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880187224 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.880187224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.1946067362 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4187483947 ps |
| CPU time | 45.23 seconds |
| Started | Oct 03 11:26:21 AM UTC 24 |
| Finished | Oct 03 11:27:08 AM UTC 24 |
| Peak memory | 216192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1946067362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.aon_timer_stress_all_with_rand_reset.1946067362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.3189720127 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3976430259 ps |
| CPU time | 32.64 seconds |
| Started | Oct 03 11:28:11 AM UTC 24 |
| Finished | Oct 03 11:28:45 AM UTC 24 |
| Peak memory | 222772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3189720127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 17.aon_timer_stress_all_with_rand_reset.3189720127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.1220142418 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6001445825 ps |
| CPU time | 32.33 seconds |
| Started | Oct 03 11:31:42 AM UTC 24 |
| Finished | Oct 03 11:32:16 AM UTC 24 |
| Peak memory | 216424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1220142418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 45.aon_timer_stress_all_with_rand_reset.1220142418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.1850745248 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 506046279145 ps |
| CPU time | 1030.54 seconds |
| Started | Oct 03 11:26:28 AM UTC 24 |
| Finished | Oct 03 11:43:50 AM UTC 24 |
| Peak memory | 207172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850745248 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.1850745248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.1276095997 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 240511816979 ps |
| CPU time | 368.11 seconds |
| Started | Oct 03 11:29:50 AM UTC 24 |
| Finished | Oct 03 11:36:03 AM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276095997 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.1276095997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/30.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.1817915729 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 62033016790 ps |
| CPU time | 60.76 seconds |
| Started | Oct 03 11:31:28 AM UTC 24 |
| Finished | Oct 03 11:32:31 AM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817915729 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.1817915729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/43.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.643898969 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 392588546 ps |
| CPU time | 0.85 seconds |
| Started | Oct 03 11:27:45 AM UTC 24 |
| Finished | Oct 03 11:27:47 AM UTC 24 |
| Peak memory | 205372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643898969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.643898969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.1533114808 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 284664557872 ps |
| CPU time | 446.27 seconds |
| Started | Oct 03 11:29:05 AM UTC 24 |
| Finished | Oct 03 11:36:38 AM UTC 24 |
| Peak memory | 207204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533114808 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.1533114808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/25.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.4123367026 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 422813622 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 11:29:48 AM UTC 24 |
| Finished | Oct 03 11:29:51 AM UTC 24 |
| Peak memory | 205732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123367026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4123367026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/30.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.3552991510 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 568422239 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 11:30:47 AM UTC 24 |
| Finished | Oct 03 11:30:50 AM UTC 24 |
| Peak memory | 205792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552991510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3552991510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/36.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.1054130880 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 366375290 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 11:31:10 AM UTC 24 |
| Finished | Oct 03 11:31:12 AM UTC 24 |
| Peak memory | 205196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054130880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1054130880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/39.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.923492299 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 126795127974 ps |
| CPU time | 271.52 seconds |
| Started | Oct 03 11:31:10 AM UTC 24 |
| Finished | Oct 03 11:35:45 AM UTC 24 |
| Peak memory | 207308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923492299 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.923492299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/39.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.480742714 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 157812680554 ps |
| CPU time | 81.78 seconds |
| Started | Oct 03 11:26:37 AM UTC 24 |
| Finished | Oct 03 11:28:01 AM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480742714 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.480742714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.495549444 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 116435619377 ps |
| CPU time | 225.03 seconds |
| Started | Oct 03 11:31:15 AM UTC 24 |
| Finished | Oct 03 11:35:04 AM UTC 24 |
| Peak memory | 207252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495549444 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.495549444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/40.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.683942912 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2089443559 ps |
| CPU time | 9.23 seconds |
| Started | Oct 03 11:31:13 AM UTC 24 |
| Finished | Oct 03 11:31:24 AM UTC 24 |
| Peak memory | 223368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=683942912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 40.aon_timer_stress_all_with_rand_reset.683942912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.713482434 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 129343266172 ps |
| CPU time | 223.48 seconds |
| Started | Oct 03 11:32:17 AM UTC 24 |
| Finished | Oct 03 11:36:03 AM UTC 24 |
| Peak memory | 207108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713482434 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.713482434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/49.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.3256458414 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 190769824126 ps |
| CPU time | 68.25 seconds |
| Started | Oct 03 11:27:02 AM UTC 24 |
| Finished | Oct 03 11:28:12 AM UTC 24 |
| Peak memory | 207092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256458414 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.3256458414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.4012698959 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 531193830 ps |
| CPU time | 2.7 seconds |
| Started | Oct 03 11:27:14 AM UTC 24 |
| Finished | Oct 03 11:27:18 AM UTC 24 |
| Peak memory | 205896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012698959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4012698959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.3783947315 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 8060243594 ps |
| CPU time | 24.45 seconds |
| Started | Oct 03 11:27:19 AM UTC 24 |
| Finished | Oct 03 11:27:45 AM UTC 24 |
| Peak memory | 207500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3783947315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 12.aon_timer_stress_all_with_rand_reset.3783947315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.1534641490 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 141260696158 ps |
| CPU time | 261.16 seconds |
| Started | Oct 03 11:28:08 AM UTC 24 |
| Finished | Oct 03 11:32:33 AM UTC 24 |
| Peak memory | 207252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534641490 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.1534641490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.1614736585 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 348427909661 ps |
| CPU time | 596.83 seconds |
| Started | Oct 03 11:28:11 AM UTC 24 |
| Finished | Oct 03 11:38:15 AM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614736585 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.1614736585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.1622039071 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2779827073 ps |
| CPU time | 13.78 seconds |
| Started | Oct 03 11:28:20 AM UTC 24 |
| Finished | Oct 03 11:28:35 AM UTC 24 |
| Peak memory | 222956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1622039071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 19.aon_timer_stress_all_with_rand_reset.1622039071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.1298951822 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 74255807925 ps |
| CPU time | 66.03 seconds |
| Started | Oct 03 11:29:16 AM UTC 24 |
| Finished | Oct 03 11:30:24 AM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298951822 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.1298951822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/26.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.2603683511 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 351790371 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 11:26:35 AM UTC 24 |
| Finished | Oct 03 11:26:38 AM UTC 24 |
| Peak memory | 205312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603683511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2603683511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.291968000 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 410702179 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 11:31:48 AM UTC 24 |
| Finished | Oct 03 11:31:52 AM UTC 24 |
| Peak memory | 205792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291968000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.291968000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/46.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.3660393775 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 955912254455 ps |
| CPU time | 304.43 seconds |
| Started | Oct 03 11:32:08 AM UTC 24 |
| Finished | Oct 03 11:37:17 AM UTC 24 |
| Peak memory | 207084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660393775 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.3660393775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/48.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.1243272923 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 382192407 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 11:32:14 AM UTC 24 |
| Finished | Oct 03 11:32:17 AM UTC 24 |
| Peak memory | 205196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243272923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1243272923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/49.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.3148371760 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 488806787 ps |
| CPU time | 2.22 seconds |
| Started | Oct 03 11:28:10 AM UTC 24 |
| Finished | Oct 03 11:28:14 AM UTC 24 |
| Peak memory | 205784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148371760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3148371760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.2334710493 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 15737569299 ps |
| CPU time | 59.6 seconds |
| Started | Oct 03 11:28:16 AM UTC 24 |
| Finished | Oct 03 11:29:17 AM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2334710493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 18.aon_timer_stress_all_with_rand_reset.2334710493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.2666737616 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2781039261 ps |
| CPU time | 9.75 seconds |
| Started | Oct 03 11:29:04 AM UTC 24 |
| Finished | Oct 03 11:29:15 AM UTC 24 |
| Peak memory | 216360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2666737616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 25.aon_timer_stress_all_with_rand_reset.2666737616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.1663877158 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 6756068618 ps |
| CPU time | 29.53 seconds |
| Started | Oct 03 11:29:12 AM UTC 24 |
| Finished | Oct 03 11:29:43 AM UTC 24 |
| Peak memory | 223280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1663877158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 26.aon_timer_stress_all_with_rand_reset.1663877158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.923403556 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2534099420 ps |
| CPU time | 16.87 seconds |
| Started | Oct 03 11:29:29 AM UTC 24 |
| Finished | Oct 03 11:29:47 AM UTC 24 |
| Peak memory | 223904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=923403556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.aon_timer_stress_all_with_rand_reset.923403556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.2349201381 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1442430636 ps |
| CPU time | 7.89 seconds |
| Started | Oct 03 11:29:39 AM UTC 24 |
| Finished | Oct 03 11:29:48 AM UTC 24 |
| Peak memory | 207336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2349201381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 29.aon_timer_stress_all_with_rand_reset.2349201381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.3236866412 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 443193484 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 11:31:16 AM UTC 24 |
| Finished | Oct 03 11:31:18 AM UTC 24 |
| Peak memory | 205848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236866412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3236866412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/41.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.2633435838 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 471419854 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 11:31:23 AM UTC 24 |
| Finished | Oct 03 11:31:25 AM UTC 24 |
| Peak memory | 205848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633435838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2633435838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/42.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.1804871644 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 591740922 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 11:26:41 AM UTC 24 |
| Finished | Oct 03 11:26:44 AM UTC 24 |
| Peak memory | 205372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804871644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1804871644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.962131558 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 477938204 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 11:26:57 AM UTC 24 |
| Finished | Oct 03 11:26:59 AM UTC 24 |
| Peak memory | 205780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962131558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.962131558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.177622994 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 392106578 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 11:27:01 AM UTC 24 |
| Finished | Oct 03 11:27:03 AM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177622994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.177622994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.2725313500 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 89163856961 ps |
| CPU time | 163.53 seconds |
| Started | Oct 03 11:29:20 AM UTC 24 |
| Finished | Oct 03 11:32:07 AM UTC 24 |
| Peak memory | 207204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725313500 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.2725313500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/27.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.1498607160 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 575185017 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 11:30:07 AM UTC 24 |
| Finished | Oct 03 11:30:10 AM UTC 24 |
| Peak memory | 205848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498607160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1498607160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/33.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.1039577204 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 25203043444 ps |
| CPU time | 31.1 seconds |
| Started | Oct 03 11:26:36 AM UTC 24 |
| Finished | Oct 03 11:27:09 AM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1039577204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 4.aon_timer_stress_all_with_rand_reset.1039577204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.3123166232 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1521498043 ps |
| CPU time | 14.7 seconds |
| Started | Oct 03 11:31:23 AM UTC 24 |
| Finished | Oct 03 11:31:39 AM UTC 24 |
| Peak memory | 223680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3123166232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 42.aon_timer_stress_all_with_rand_reset.3123166232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.1284878934 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 63323656800 ps |
| CPU time | 136.82 seconds |
| Started | Oct 03 11:31:37 AM UTC 24 |
| Finished | Oct 03 11:33:56 AM UTC 24 |
| Peak memory | 207252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284878934 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.1284878934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/44.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.2430268288 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 465087211 ps |
| CPU time | 2.27 seconds |
| Started | Oct 03 11:31:42 AM UTC 24 |
| Finished | Oct 03 11:31:45 AM UTC 24 |
| Peak memory | 205704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430268288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2430268288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/45.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.2443478062 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 649838092970 ps |
| CPU time | 956.54 seconds |
| Started | Oct 03 11:27:11 AM UTC 24 |
| Finished | Oct 03 11:43:18 AM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443478062 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.2443478062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.237512650 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 500098629 ps |
| CPU time | 2.66 seconds |
| Started | Oct 03 11:27:18 AM UTC 24 |
| Finished | Oct 03 11:27:22 AM UTC 24 |
| Peak memory | 205848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237512650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.237512650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.4171322644 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 430817418 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 11:27:35 AM UTC 24 |
| Finished | Oct 03 11:27:37 AM UTC 24 |
| Peak memory | 205844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171322644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.4171322644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.4223512567 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 409999429 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 11:31:26 AM UTC 24 |
| Finished | Oct 03 11:31:29 AM UTC 24 |
| Peak memory | 203880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223512567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4223512567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/43.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.457072265 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 120833472105 ps |
| CPU time | 115.15 seconds |
| Started | Oct 03 11:26:51 AM UTC 24 |
| Finished | Oct 03 11:28:48 AM UTC 24 |
| Peak memory | 207244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457072265 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.457072265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.2392378257 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1735198732 ps |
| CPU time | 20.01 seconds |
| Started | Oct 03 11:27:46 AM UTC 24 |
| Finished | Oct 03 11:28:07 AM UTC 24 |
| Peak memory | 222968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2392378257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 14.aon_timer_stress_all_with_rand_reset.2392378257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.1030092823 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 536756149 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 11:28:29 AM UTC 24 |
| Finished | Oct 03 11:28:31 AM UTC 24 |
| Peak memory | 205848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030092823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1030092823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/21.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.2802536939 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 567083503 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 11:30:01 AM UTC 24 |
| Finished | Oct 03 11:30:03 AM UTC 24 |
| Peak memory | 205316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802536939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2802536939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/32.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.487837410 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 6498065656 ps |
| CPU time | 20.05 seconds |
| Started | Oct 03 11:30:42 AM UTC 24 |
| Finished | Oct 03 11:31:04 AM UTC 24 |
| Peak memory | 222912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=487837410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.aon_timer_stress_all_with_rand_reset.487837410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.1962934797 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 6001998557 ps |
| CPU time | 15.69 seconds |
| Started | Oct 03 11:31:27 AM UTC 24 |
| Finished | Oct 03 11:31:44 AM UTC 24 |
| Peak memory | 216364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1962934797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 43.aon_timer_stress_all_with_rand_reset.1962934797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.1788230338 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 15163221646 ps |
| CPU time | 18.42 seconds |
| Started | Oct 03 11:31:52 AM UTC 24 |
| Finished | Oct 03 11:32:13 AM UTC 24 |
| Peak memory | 222908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1788230338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 46.aon_timer_stress_all_with_rand_reset.1788230338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.3689081958 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 536426309 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 11:31:56 AM UTC 24 |
| Finished | Oct 03 11:32:00 AM UTC 24 |
| Peak memory | 205856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689081958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3689081958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/47.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.2424607342 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 368295107 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 11:26:49 AM UTC 24 |
| Finished | Oct 03 11:26:51 AM UTC 24 |
| Peak memory | 205792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424607342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2424607342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.1063752620 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 430650628 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 11:26:20 AM UTC 24 |
| Finished | Oct 03 11:26:22 AM UTC 24 |
| Peak memory | 205844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063752620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1063752620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.3233207940 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 314567774728 ps |
| CPU time | 178.59 seconds |
| Started | Oct 03 11:27:57 AM UTC 24 |
| Finished | Oct 03 11:30:58 AM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233207940 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.3233207940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.3403666535 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 470031592 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 11:28:05 AM UTC 24 |
| Finished | Oct 03 11:28:08 AM UTC 24 |
| Peak memory | 205432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403666535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3403666535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.1459837814 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 426042729 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 11:28:20 AM UTC 24 |
| Finished | Oct 03 11:28:22 AM UTC 24 |
| Peak memory | 203880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459837814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1459837814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.4265620206 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 185877955830 ps |
| CPU time | 90.43 seconds |
| Started | Oct 03 11:28:27 AM UTC 24 |
| Finished | Oct 03 11:29:59 AM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265620206 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.4265620206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/20.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.909649583 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 585134759 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 11:28:44 AM UTC 24 |
| Finished | Oct 03 11:28:46 AM UTC 24 |
| Peak memory | 205492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909649583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.909649583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/23.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.1643571092 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 547944615 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 11:29:04 AM UTC 24 |
| Finished | Oct 03 11:29:07 AM UTC 24 |
| Peak memory | 203880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643571092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1643571092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/25.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.3226950404 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 375468541 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 11:29:09 AM UTC 24 |
| Finished | Oct 03 11:29:11 AM UTC 24 |
| Peak memory | 205848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226950404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3226950404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/26.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.1949713614 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 462110939 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 11:29:18 AM UTC 24 |
| Finished | Oct 03 11:29:21 AM UTC 24 |
| Peak memory | 205752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949713614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1949713614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/27.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.3168356997 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 160740271078 ps |
| CPU time | 121.91 seconds |
| Started | Oct 03 11:30:43 AM UTC 24 |
| Finished | Oct 03 11:32:48 AM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168356997 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.3168356997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/35.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.476736539 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4127698927 ps |
| CPU time | 29.51 seconds |
| Started | Oct 03 11:30:51 AM UTC 24 |
| Finished | Oct 03 11:31:21 AM UTC 24 |
| Peak memory | 216284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=476736539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.aon_timer_stress_all_with_rand_reset.476736539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.1097535668 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 429845222 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 11:30:57 AM UTC 24 |
| Finished | Oct 03 11:30:59 AM UTC 24 |
| Peak memory | 205432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097535668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1097535668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/37.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.712915213 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 520487458 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 11:27:04 AM UTC 24 |
| Finished | Oct 03 11:27:07 AM UTC 24 |
| Peak memory | 205780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712915213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.712915213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3207239059 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 7560450512 ps |
| CPU time | 22.99 seconds |
| Started | Oct 03 11:25:29 AM UTC 24 |
| Finished | Oct 03 11:25:53 AM UTC 24 |
| Peak memory | 206900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207239059 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.3207239059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.3516560975 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 486770438 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 11:26:18 AM UTC 24 |
| Finished | Oct 03 11:26:21 AM UTC 24 |
| Peak memory | 203828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516560975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3516560975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.448854810 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 559203618 ps |
| CPU time | 2.44 seconds |
| Started | Oct 03 11:27:53 AM UTC 24 |
| Finished | Oct 03 11:27:56 AM UTC 24 |
| Peak memory | 205904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448854810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.448854810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.460753779 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 611853264 ps |
| CPU time | 2.84 seconds |
| Started | Oct 03 11:28:15 AM UTC 24 |
| Finished | Oct 03 11:28:18 AM UTC 24 |
| Peak memory | 205832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460753779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.460753779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.4229087399 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 50542136884 ps |
| CPU time | 35.64 seconds |
| Started | Oct 03 11:29:40 AM UTC 24 |
| Finished | Oct 03 11:30:17 AM UTC 24 |
| Peak memory | 207252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229087399 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.4229087399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/29.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.538341930 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 646540857 ps |
| CPU time | 1 seconds |
| Started | Oct 03 11:30:21 AM UTC 24 |
| Finished | Oct 03 11:30:23 AM UTC 24 |
| Peak memory | 203880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538341930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.538341930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/34.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.112221938 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 499691404 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 11:31:02 AM UTC 24 |
| Finished | Oct 03 11:31:05 AM UTC 24 |
| Peak memory | 205372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112221938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.112221938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/38.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.79433968 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 353597912 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 11:31:12 AM UTC 24 |
| Finished | Oct 03 11:31:15 AM UTC 24 |
| Peak memory | 205488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79433968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.79433968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/40.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.2229309395 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9780444083 ps |
| CPU time | 30.49 seconds |
| Started | Oct 03 11:27:02 AM UTC 24 |
| Finished | Oct 03 11:27:34 AM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2229309395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 8.aon_timer_stress_all_with_rand_reset.2229309395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3206786496 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 7960495376 ps |
| CPU time | 12.41 seconds |
| Started | Oct 03 11:25:58 AM UTC 24 |
| Finished | Oct 03 11:26:12 AM UTC 24 |
| Peak memory | 206768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206786496 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.3206786496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.758486261 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 460847771 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 11:27:10 AM UTC 24 |
| Finished | Oct 03 11:27:12 AM UTC 24 |
| Peak memory | 205372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758486261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.758486261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.3434009679 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 137888083723 ps |
| CPU time | 212.9 seconds |
| Started | Oct 03 11:27:16 AM UTC 24 |
| Finished | Oct 03 11:30:52 AM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434009679 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.3434009679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.311556197 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 507530090 ps |
| CPU time | 2.55 seconds |
| Started | Oct 03 11:28:25 AM UTC 24 |
| Finished | Oct 03 11:28:29 AM UTC 24 |
| Peak memory | 205576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311556197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.311556197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/20.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.148392735 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 469805048 ps |
| CPU time | 2.21 seconds |
| Started | Oct 03 11:29:53 AM UTC 24 |
| Finished | Oct 03 11:29:56 AM UTC 24 |
| Peak memory | 205760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148392735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.148392735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/31.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.3496719718 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 541045554 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 11:30:40 AM UTC 24 |
| Finished | Oct 03 11:30:42 AM UTC 24 |
| Peak memory | 203880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496719718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3496719718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/35.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.2533189344 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 386381637 ps |
| CPU time | 2.35 seconds |
| Started | Oct 03 11:32:04 AM UTC 24 |
| Finished | Oct 03 11:32:08 AM UTC 24 |
| Peak memory | 205712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533189344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2533189344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/48.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.4002652931 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1644915423 ps |
| CPU time | 14.75 seconds |
| Started | Oct 03 11:32:15 AM UTC 24 |
| Finished | Oct 03 11:32:31 AM UTC 24 |
| Peak memory | 207372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4002652931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 49.aon_timer_stress_all_with_rand_reset.4002652931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2502062410 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 575671529 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 11:24:48 AM UTC 24 |
| Finished | Oct 03 11:24:51 AM UTC 24 |
| Peak memory | 201772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502062410 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.2502062410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3346906863 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1006062077 ps |
| CPU time | 3.89 seconds |
| Started | Oct 03 11:24:47 AM UTC 24 |
| Finished | Oct 03 11:24:52 AM UTC 24 |
| Peak memory | 203320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346906863 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.3346906863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2491675921 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 409392875 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 11:24:51 AM UTC 24 |
| Finished | Oct 03 11:24:54 AM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2491675921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim er_csr_mem_rw_with_rand_reset.2491675921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.49767801 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 477329609 ps |
| CPU time | 1.14 seconds |
| Started | Oct 03 11:24:42 AM UTC 24 |
| Finished | Oct 03 11:24:44 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49767801 -assert nopostproc +UVM_TESTNAME=aon_tim er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.49767801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.367114392 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 428736127 ps |
| CPU time | 1.1 seconds |
| Started | Oct 03 11:24:45 AM UTC 24 |
| Finished | Oct 03 11:24:47 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367114392 -assert nopostproc + UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.367114392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.48817490 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 395486713 ps |
| CPU time | 0.98 seconds |
| Started | Oct 03 11:24:45 AM UTC 24 |
| Finished | Oct 03 11:24:47 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48817490 -assert nopostproc +UVM_TESTNAM E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.48817490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1249371618 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2150203540 ps |
| CPU time | 10.22 seconds |
| Started | Oct 03 11:24:51 AM UTC 24 |
| Finished | Oct 03 11:25:02 AM UTC 24 |
| Peak memory | 205412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249371618 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.1249371618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.134671416 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 528480910 ps |
| CPU time | 2.38 seconds |
| Started | Oct 03 11:24:41 AM UTC 24 |
| Finished | Oct 03 11:24:44 AM UTC 24 |
| Peak memory | 207164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134671416 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.134671416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1992085375 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 604209607 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 11:24:57 AM UTC 24 |
| Finished | Oct 03 11:25:00 AM UTC 24 |
| Peak memory | 201772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992085375 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.1992085375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3931824526 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 4431159218 ps |
| CPU time | 7.52 seconds |
| Started | Oct 03 11:24:57 AM UTC 24 |
| Finished | Oct 03 11:25:06 AM UTC 24 |
| Peak memory | 205584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931824526 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.3931824526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.826582404 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 656809258 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 11:24:57 AM UTC 24 |
| Finished | Oct 03 11:25:00 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826582404 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.826582404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.296288578 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 361939224 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 11:25:01 AM UTC 24 |
| Finished | Oct 03 11:25:03 AM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=296288578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_time r_csr_mem_rw_with_rand_reset.296288578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.91636228 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 350674744 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 11:24:57 AM UTC 24 |
| Finished | Oct 03 11:25:00 AM UTC 24 |
| Peak memory | 201760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91636228 -assert nopostproc +UVM_TESTNAME=aon_ timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.91636228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.1425407333 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 471544312 ps |
| CPU time | 0.91 seconds |
| Started | Oct 03 11:24:55 AM UTC 24 |
| Finished | Oct 03 11:24:57 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425407333 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1425407333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3595047499 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 410571324 ps |
| CPU time | 2.24 seconds |
| Started | Oct 03 11:24:57 AM UTC 24 |
| Finished | Oct 03 11:25:01 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595047499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.3595047499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.2548137687 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 348629717 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 11:24:56 AM UTC 24 |
| Finished | Oct 03 11:24:58 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548137687 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.2548137687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.516725467 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1550588308 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 11:24:59 AM UTC 24 |
| Finished | Oct 03 11:25:01 AM UTC 24 |
| Peak memory | 201952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516725467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.516725467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.219229397 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 840137051 ps |
| CPU time | 2.97 seconds |
| Started | Oct 03 11:24:52 AM UTC 24 |
| Finished | Oct 03 11:24:56 AM UTC 24 |
| Peak memory | 207096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219229397 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.219229397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1371231817 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4395767863 ps |
| CPU time | 2.74 seconds |
| Started | Oct 03 11:24:53 AM UTC 24 |
| Finished | Oct 03 11:24:57 AM UTC 24 |
| Peak memory | 205420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371231817 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.1371231817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3222885217 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 342571135 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 11:25:41 AM UTC 24 |
| Finished | Oct 03 11:25:44 AM UTC 24 |
| Peak memory | 203936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3222885217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_ti mer_csr_mem_rw_with_rand_reset.3222885217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.3280317995 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 387776924 ps |
| CPU time | 2.36 seconds |
| Started | Oct 03 11:25:40 AM UTC 24 |
| Finished | Oct 03 11:25:44 AM UTC 24 |
| Peak memory | 203500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280317995 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3280317995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.382301120 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 299166189 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 11:25:40 AM UTC 24 |
| Finished | Oct 03 11:25:43 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382301120 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.382301120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3761886858 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1540298096 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 11:25:41 AM UTC 24 |
| Finished | Oct 03 11:25:45 AM UTC 24 |
| Peak memory | 203564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761886858 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.3761886858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.617624269 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 299507998 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 11:25:39 AM UTC 24 |
| Finished | Oct 03 11:25:42 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617624269 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.617624269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2338901086 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4589030461 ps |
| CPU time | 4.13 seconds |
| Started | Oct 03 11:25:39 AM UTC 24 |
| Finished | Oct 03 11:25:44 AM UTC 24 |
| Peak memory | 206704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338901086 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.2338901086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.111157352 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 526526581 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 11:25:45 AM UTC 24 |
| Finished | Oct 03 11:25:48 AM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=111157352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_tim er_csr_mem_rw_with_rand_reset.111157352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.4200161139 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 311802607 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 11:25:44 AM UTC 24 |
| Finished | Oct 03 11:25:46 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200161139 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4200161139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.2657603729 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 464259113 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 11:25:43 AM UTC 24 |
| Finished | Oct 03 11:25:45 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657603729 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2657603729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.236816146 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2602405331 ps |
| CPU time | 6.16 seconds |
| Started | Oct 03 11:25:45 AM UTC 24 |
| Finished | Oct 03 11:25:52 AM UTC 24 |
| Peak memory | 205416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236816146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.236816146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.1828359722 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 411222360 ps |
| CPU time | 3.23 seconds |
| Started | Oct 03 11:25:42 AM UTC 24 |
| Finished | Oct 03 11:25:46 AM UTC 24 |
| Peak memory | 207148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828359722 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1828359722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1031571678 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 7936433443 ps |
| CPU time | 16.21 seconds |
| Started | Oct 03 11:25:42 AM UTC 24 |
| Finished | Oct 03 11:25:59 AM UTC 24 |
| Peak memory | 206972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031571678 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.1031571678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.78901775 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 570286950 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 11:25:46 AM UTC 24 |
| Finished | Oct 03 11:25:49 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=78901775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_time r_csr_mem_rw_with_rand_reset.78901775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.679966753 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 492229743 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 11:25:45 AM UTC 24 |
| Finished | Oct 03 11:25:48 AM UTC 24 |
| Peak memory | 201824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679966753 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.679966753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.227098731 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 483179751 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 11:25:45 AM UTC 24 |
| Finished | Oct 03 11:25:48 AM UTC 24 |
| Peak memory | 203168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227098731 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.227098731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2386164164 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2474425897 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 11:25:46 AM UTC 24 |
| Finished | Oct 03 11:25:49 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386164164 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.2386164164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.3456089299 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 774074320 ps |
| CPU time | 3 seconds |
| Started | Oct 03 11:25:45 AM UTC 24 |
| Finished | Oct 03 11:25:49 AM UTC 24 |
| Peak memory | 207084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456089299 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3456089299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.497129032 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 8617599541 ps |
| CPU time | 20.6 seconds |
| Started | Oct 03 11:25:45 AM UTC 24 |
| Finished | Oct 03 11:26:07 AM UTC 24 |
| Peak memory | 206988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497129032 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.497129032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2283464142 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 371950117 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 11:25:50 AM UTC 24 |
| Finished | Oct 03 11:25:52 AM UTC 24 |
| Peak memory | 203936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2283464142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti mer_csr_mem_rw_with_rand_reset.2283464142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2555338702 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 292238633 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 11:25:49 AM UTC 24 |
| Finished | Oct 03 11:25:51 AM UTC 24 |
| Peak memory | 201764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555338702 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2555338702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1663520414 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 267401269 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 11:25:49 AM UTC 24 |
| Finished | Oct 03 11:25:51 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663520414 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1663520414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4133170566 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2077904245 ps |
| CPU time | 3.89 seconds |
| Started | Oct 03 11:25:50 AM UTC 24 |
| Finished | Oct 03 11:25:55 AM UTC 24 |
| Peak memory | 203376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133170566 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.4133170566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.3335451531 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 475953355 ps |
| CPU time | 3.07 seconds |
| Started | Oct 03 11:25:46 AM UTC 24 |
| Finished | Oct 03 11:25:50 AM UTC 24 |
| Peak memory | 207312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335451531 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3335451531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1297589294 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4242299447 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 11:25:47 AM UTC 24 |
| Finished | Oct 03 11:25:50 AM UTC 24 |
| Peak memory | 206100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297589294 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.1297589294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.33226609 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 446557225 ps |
| CPU time | 2.36 seconds |
| Started | Oct 03 11:25:52 AM UTC 24 |
| Finished | Oct 03 11:25:56 AM UTC 24 |
| Peak memory | 205616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=33226609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_time r_csr_mem_rw_with_rand_reset.33226609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.1871448984 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 383049021 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 11:25:51 AM UTC 24 |
| Finished | Oct 03 11:25:53 AM UTC 24 |
| Peak memory | 201764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871448984 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1871448984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.1327591901 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 463439482 ps |
| CPU time | 2.46 seconds |
| Started | Oct 03 11:25:50 AM UTC 24 |
| Finished | Oct 03 11:25:53 AM UTC 24 |
| Peak memory | 201112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327591901 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1327591901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1923194252 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1531116228 ps |
| CPU time | 3.41 seconds |
| Started | Oct 03 11:25:51 AM UTC 24 |
| Finished | Oct 03 11:25:55 AM UTC 24 |
| Peak memory | 203372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923194252 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.1923194252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.2093481380 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 486833314 ps |
| CPU time | 4.38 seconds |
| Started | Oct 03 11:25:50 AM UTC 24 |
| Finished | Oct 03 11:25:55 AM UTC 24 |
| Peak memory | 207084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093481380 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2093481380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2964885600 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 8181188163 ps |
| CPU time | 26.95 seconds |
| Started | Oct 03 11:25:50 AM UTC 24 |
| Finished | Oct 03 11:26:18 AM UTC 24 |
| Peak memory | 207064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964885600 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.2964885600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.207451009 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 608689813 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 11:25:55 AM UTC 24 |
| Finished | Oct 03 11:25:57 AM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=207451009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_tim er_csr_mem_rw_with_rand_reset.207451009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.528597944 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 513344707 ps |
| CPU time | 0.93 seconds |
| Started | Oct 03 11:25:54 AM UTC 24 |
| Finished | Oct 03 11:25:56 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528597944 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.528597944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.1218288755 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 519081867 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 11:25:53 AM UTC 24 |
| Finished | Oct 03 11:25:56 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218288755 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1218288755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2491463081 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1072452852 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 11:25:54 AM UTC 24 |
| Finished | Oct 03 11:25:57 AM UTC 24 |
| Peak memory | 201952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491463081 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.2491463081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.1099996860 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 566702248 ps |
| CPU time | 3.46 seconds |
| Started | Oct 03 11:25:52 AM UTC 24 |
| Finished | Oct 03 11:25:57 AM UTC 24 |
| Peak memory | 207172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099996860 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1099996860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3507917352 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 8423517809 ps |
| CPU time | 16.02 seconds |
| Started | Oct 03 11:25:53 AM UTC 24 |
| Finished | Oct 03 11:26:10 AM UTC 24 |
| Peak memory | 207044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507917352 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.3507917352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1160248524 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 352039305 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 11:25:57 AM UTC 24 |
| Finished | Oct 03 11:26:00 AM UTC 24 |
| Peak memory | 205484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1160248524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti mer_csr_mem_rw_with_rand_reset.1160248524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.3595381119 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 503108486 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 11:25:57 AM UTC 24 |
| Finished | Oct 03 11:25:59 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595381119 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3595381119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.3524142132 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 309457027 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 11:25:57 AM UTC 24 |
| Finished | Oct 03 11:26:00 AM UTC 24 |
| Peak memory | 201748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524142132 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3524142132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1418973639 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2307154943 ps |
| CPU time | 6.7 seconds |
| Started | Oct 03 11:25:57 AM UTC 24 |
| Finished | Oct 03 11:26:05 AM UTC 24 |
| Peak memory | 205408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418973639 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.1418973639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.408011690 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 535765808 ps |
| CPU time | 3.11 seconds |
| Started | Oct 03 11:25:56 AM UTC 24 |
| Finished | Oct 03 11:26:00 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408011690 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.408011690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2125930053 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 8258744536 ps |
| CPU time | 15 seconds |
| Started | Oct 03 11:25:56 AM UTC 24 |
| Finished | Oct 03 11:26:12 AM UTC 24 |
| Peak memory | 206784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125930053 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.2125930053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4248836344 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 355670255 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 11:26:00 AM UTC 24 |
| Finished | Oct 03 11:26:04 AM UTC 24 |
| Peak memory | 205348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4248836344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti mer_csr_mem_rw_with_rand_reset.4248836344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.135865485 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 369427803 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 11:26:00 AM UTC 24 |
| Finished | Oct 03 11:26:02 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135865485 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.135865485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.3498302530 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 314429046 ps |
| CPU time | 1.62 seconds |
| Started | Oct 03 11:25:58 AM UTC 24 |
| Finished | Oct 03 11:26:01 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498302530 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3498302530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2041432192 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2708916507 ps |
| CPU time | 5.96 seconds |
| Started | Oct 03 11:26:00 AM UTC 24 |
| Finished | Oct 03 11:26:07 AM UTC 24 |
| Peak memory | 205484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041432192 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.2041432192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.449390614 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 685513581 ps |
| CPU time | 2 seconds |
| Started | Oct 03 11:25:58 AM UTC 24 |
| Finished | Oct 03 11:26:01 AM UTC 24 |
| Peak memory | 206584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449390614 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.449390614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1913438357 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 544476121 ps |
| CPU time | 2.79 seconds |
| Started | Oct 03 11:26:04 AM UTC 24 |
| Finished | Oct 03 11:26:07 AM UTC 24 |
| Peak memory | 205612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1913438357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_ti mer_csr_mem_rw_with_rand_reset.1913438357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.3370419909 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 528413230 ps |
| CPU time | 2.88 seconds |
| Started | Oct 03 11:26:02 AM UTC 24 |
| Finished | Oct 03 11:26:05 AM UTC 24 |
| Peak memory | 203500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370419909 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3370419909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.991165470 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 271315347 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 11:26:02 AM UTC 24 |
| Finished | Oct 03 11:26:04 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991165470 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.991165470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.500593148 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2906147969 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 11:26:02 AM UTC 24 |
| Finished | Oct 03 11:26:04 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500593148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.500593148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.481422960 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 358723801 ps |
| CPU time | 2.39 seconds |
| Started | Oct 03 11:26:00 AM UTC 24 |
| Finished | Oct 03 11:26:04 AM UTC 24 |
| Peak memory | 205772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481422960 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.481422960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4263050278 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4362108563 ps |
| CPU time | 4.15 seconds |
| Started | Oct 03 11:26:00 AM UTC 24 |
| Finished | Oct 03 11:26:06 AM UTC 24 |
| Peak memory | 206600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263050278 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.4263050278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.958940382 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 481117369 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 11:26:06 AM UTC 24 |
| Finished | Oct 03 11:26:09 AM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=958940382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_tim er_csr_mem_rw_with_rand_reset.958940382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.3654869007 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 471557288 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 11:26:05 AM UTC 24 |
| Finished | Oct 03 11:26:08 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654869007 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3654869007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.4213927556 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 379949233 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 11:26:05 AM UTC 24 |
| Finished | Oct 03 11:26:08 AM UTC 24 |
| Peak memory | 201756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213927556 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.4213927556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.160562670 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2169151324 ps |
| CPU time | 9.43 seconds |
| Started | Oct 03 11:26:06 AM UTC 24 |
| Finished | Oct 03 11:26:17 AM UTC 24 |
| Peak memory | 205612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160562670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.160562670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.513767736 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 706618241 ps |
| CPU time | 3.32 seconds |
| Started | Oct 03 11:26:05 AM UTC 24 |
| Finished | Oct 03 11:26:09 AM UTC 24 |
| Peak memory | 207220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513767736 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.513767736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2020958314 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4703335804 ps |
| CPU time | 2.55 seconds |
| Started | Oct 03 11:26:05 AM UTC 24 |
| Finished | Oct 03 11:26:08 AM UTC 24 |
| Peak memory | 206804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020958314 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.2020958314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1574702799 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 435620217 ps |
| CPU time | 2.69 seconds |
| Started | Oct 03 11:25:06 AM UTC 24 |
| Finished | Oct 03 11:25:10 AM UTC 24 |
| Peak memory | 203124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574702799 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.1574702799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1199858460 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 13881294742 ps |
| CPU time | 27.64 seconds |
| Started | Oct 03 11:25:06 AM UTC 24 |
| Finished | Oct 03 11:25:35 AM UTC 24 |
| Peak memory | 205636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199858460 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.1199858460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1324406442 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1177944849 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 11:25:04 AM UTC 24 |
| Finished | Oct 03 11:25:07 AM UTC 24 |
| Peak memory | 201772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324406442 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.1324406442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.444565920 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 517184302 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 11:25:07 AM UTC 24 |
| Finished | Oct 03 11:25:10 AM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=444565920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_time r_csr_mem_rw_with_rand_reset.444565920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.893671723 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 291714225 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 11:25:05 AM UTC 24 |
| Finished | Oct 03 11:25:07 AM UTC 24 |
| Peak memory | 201764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893671723 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.893671723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.1408632557 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 343058046 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 11:25:02 AM UTC 24 |
| Finished | Oct 03 11:25:05 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408632557 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1408632557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2057703761 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 317970585 ps |
| CPU time | 0.95 seconds |
| Started | Oct 03 11:25:03 AM UTC 24 |
| Finished | Oct 03 11:25:05 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057703761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.2057703761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.1760904064 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 512237372 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 11:25:02 AM UTC 24 |
| Finished | Oct 03 11:25:04 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760904064 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.1760904064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1935548124 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2563316459 ps |
| CPU time | 7.64 seconds |
| Started | Oct 03 11:25:06 AM UTC 24 |
| Finished | Oct 03 11:25:15 AM UTC 24 |
| Peak memory | 205416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935548124 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.1935548124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.1284552590 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 511236372 ps |
| CPU time | 4.26 seconds |
| Started | Oct 03 11:25:01 AM UTC 24 |
| Finished | Oct 03 11:25:06 AM UTC 24 |
| Peak memory | 207252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284552590 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1284552590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3707597161 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4014399391 ps |
| CPU time | 4.45 seconds |
| Started | Oct 03 11:25:01 AM UTC 24 |
| Finished | Oct 03 11:25:06 AM UTC 24 |
| Peak memory | 206608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707597161 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.3707597161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.3020161172 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 429592790 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 11:26:06 AM UTC 24 |
| Finished | Oct 03 11:26:09 AM UTC 24 |
| Peak memory | 201756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020161172 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3020161172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/20.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.690601848 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 510317401 ps |
| CPU time | 2.51 seconds |
| Started | Oct 03 11:26:08 AM UTC 24 |
| Finished | Oct 03 11:26:12 AM UTC 24 |
| Peak memory | 203168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690601848 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.690601848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/21.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.3913003551 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 380786805 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 11:26:08 AM UTC 24 |
| Finished | Oct 03 11:26:12 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913003551 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3913003551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/22.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.3263902645 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 265674525 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 11:26:08 AM UTC 24 |
| Finished | Oct 03 11:26:12 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263902645 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3263902645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/23.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.1412876023 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 485243226 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 11:26:08 AM UTC 24 |
| Finished | Oct 03 11:26:12 AM UTC 24 |
| Peak memory | 201508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412876023 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1412876023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/24.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.3316132524 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 433659617 ps |
| CPU time | 1.02 seconds |
| Started | Oct 03 11:26:08 AM UTC 24 |
| Finished | Oct 03 11:26:11 AM UTC 24 |
| Peak memory | 201756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316132524 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3316132524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/25.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.3965319642 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 485304459 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 11:26:10 AM UTC 24 |
| Finished | Oct 03 11:26:12 AM UTC 24 |
| Peak memory | 201756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965319642 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3965319642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/26.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.548604840 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 470415420 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 11:26:10 AM UTC 24 |
| Finished | Oct 03 11:26:12 AM UTC 24 |
| Peak memory | 201764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548604840 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.548604840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/27.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.1660183651 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 456650689 ps |
| CPU time | 2.37 seconds |
| Started | Oct 03 11:26:11 AM UTC 24 |
| Finished | Oct 03 11:26:14 AM UTC 24 |
| Peak memory | 201508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660183651 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1660183651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/28.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.4279772307 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 457391436 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 11:26:11 AM UTC 24 |
| Finished | Oct 03 11:26:13 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279772307 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4279772307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/29.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1388290738 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 528918908 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 11:25:11 AM UTC 24 |
| Finished | Oct 03 11:25:13 AM UTC 24 |
| Peak memory | 201772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388290738 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.1388290738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3749338625 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 13801585283 ps |
| CPU time | 12.63 seconds |
| Started | Oct 03 11:25:11 AM UTC 24 |
| Finished | Oct 03 11:25:25 AM UTC 24 |
| Peak memory | 205640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749338625 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.3749338625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2255096670 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 717670508 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 11:25:11 AM UTC 24 |
| Finished | Oct 03 11:25:13 AM UTC 24 |
| Peak memory | 201772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255096670 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.2255096670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2706646853 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 323963268 ps |
| CPU time | 2.07 seconds |
| Started | Oct 03 11:25:14 AM UTC 24 |
| Finished | Oct 03 11:25:17 AM UTC 24 |
| Peak memory | 205620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2706646853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim er_csr_mem_rw_with_rand_reset.2706646853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.1435039047 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 433711916 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 11:25:11 AM UTC 24 |
| Finished | Oct 03 11:25:14 AM UTC 24 |
| Peak memory | 203240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435039047 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1435039047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3959240305 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 441294092 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 11:25:08 AM UTC 24 |
| Finished | Oct 03 11:25:10 AM UTC 24 |
| Peak memory | 201828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959240305 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3959240305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2371357705 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 456491477 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 11:25:11 AM UTC 24 |
| Finished | Oct 03 11:25:13 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371357705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.2371357705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.2875651527 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 286475566 ps |
| CPU time | 1 seconds |
| Started | Oct 03 11:25:08 AM UTC 24 |
| Finished | Oct 03 11:25:10 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875651527 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.2875651527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1511702907 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1110278263 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 11:25:12 AM UTC 24 |
| Finished | Oct 03 11:25:15 AM UTC 24 |
| Peak memory | 201892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511702907 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.1511702907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.3035125123 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 614813691 ps |
| CPU time | 2.68 seconds |
| Started | Oct 03 11:25:07 AM UTC 24 |
| Finished | Oct 03 11:25:11 AM UTC 24 |
| Peak memory | 207088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035125123 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3035125123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1455204774 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4689760296 ps |
| CPU time | 4.95 seconds |
| Started | Oct 03 11:25:08 AM UTC 24 |
| Finished | Oct 03 11:25:13 AM UTC 24 |
| Peak memory | 206288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455204774 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.1455204774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.3194022681 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 436521431 ps |
| CPU time | 2.29 seconds |
| Started | Oct 03 11:26:12 AM UTC 24 |
| Finished | Oct 03 11:26:16 AM UTC 24 |
| Peak memory | 201384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194022681 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3194022681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/30.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.1176956279 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 455037565 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 11:26:12 AM UTC 24 |
| Finished | Oct 03 11:26:15 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176956279 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1176956279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/31.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3502597369 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 309449979 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 11:26:12 AM UTC 24 |
| Finished | Oct 03 11:26:14 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502597369 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3502597369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/32.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.2567188820 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 445087231 ps |
| CPU time | 2.45 seconds |
| Started | Oct 03 11:26:13 AM UTC 24 |
| Finished | Oct 03 11:26:17 AM UTC 24 |
| Peak memory | 201112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567188820 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2567188820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/33.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.2105484689 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 502080585 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 11:26:13 AM UTC 24 |
| Finished | Oct 03 11:26:16 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105484689 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2105484689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/34.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.2851033269 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 476524762 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 11:26:13 AM UTC 24 |
| Finished | Oct 03 11:26:16 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851033269 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2851033269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/35.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3266016906 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 480911497 ps |
| CPU time | 0.96 seconds |
| Started | Oct 03 11:26:13 AM UTC 24 |
| Finished | Oct 03 11:26:16 AM UTC 24 |
| Peak memory | 201756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266016906 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3266016906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/36.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.4078424896 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 494280560 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 11:26:13 AM UTC 24 |
| Finished | Oct 03 11:26:17 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078424896 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.4078424896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/37.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.372543898 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 329658862 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 11:26:13 AM UTC 24 |
| Finished | Oct 03 11:26:16 AM UTC 24 |
| Peak memory | 201764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372543898 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.372543898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/38.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.3943584322 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 268934356 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 11:26:13 AM UTC 24 |
| Finished | Oct 03 11:26:17 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943584322 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3943584322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/39.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1576899610 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 563657240 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 11:25:19 AM UTC 24 |
| Finished | Oct 03 11:25:21 AM UTC 24 |
| Peak memory | 201772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576899610 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.1576899610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2714790963 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 10727778464 ps |
| CPU time | 13.02 seconds |
| Started | Oct 03 11:25:18 AM UTC 24 |
| Finished | Oct 03 11:25:32 AM UTC 24 |
| Peak memory | 205904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714790963 -assert nopostproc +UVM_TESTN AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.2714790963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.139006597 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1134283915 ps |
| CPU time | 2.36 seconds |
| Started | Oct 03 11:25:16 AM UTC 24 |
| Finished | Oct 03 11:25:19 AM UTC 24 |
| Peak memory | 203248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139006597 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.139006597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1986908043 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 428180327 ps |
| CPU time | 2.39 seconds |
| Started | Oct 03 11:25:19 AM UTC 24 |
| Finished | Oct 03 11:25:22 AM UTC 24 |
| Peak memory | 205684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1986908043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim er_csr_mem_rw_with_rand_reset.1986908043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.1947022659 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 545792647 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 11:25:18 AM UTC 24 |
| Finished | Oct 03 11:25:20 AM UTC 24 |
| Peak memory | 201824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947022659 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1947022659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.533583432 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 456685089 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 11:25:14 AM UTC 24 |
| Finished | Oct 03 11:25:17 AM UTC 24 |
| Peak memory | 201452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533583432 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.533583432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2842711567 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 358815569 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 11:25:15 AM UTC 24 |
| Finished | Oct 03 11:25:18 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842711567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.2842711567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.176812001 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 452444073 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 11:25:15 AM UTC 24 |
| Finished | Oct 03 11:25:18 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176812001 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.176812001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1152226298 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2151747551 ps |
| CPU time | 2.62 seconds |
| Started | Oct 03 11:25:19 AM UTC 24 |
| Finished | Oct 03 11:25:22 AM UTC 24 |
| Peak memory | 205676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152226298 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.1152226298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.3573496051 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 634894787 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 11:25:14 AM UTC 24 |
| Finished | Oct 03 11:25:17 AM UTC 24 |
| Peak memory | 206992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573496051 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3573496051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2227596665 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4282956082 ps |
| CPU time | 7.9 seconds |
| Started | Oct 03 11:25:14 AM UTC 24 |
| Finished | Oct 03 11:25:23 AM UTC 24 |
| Peak memory | 206536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227596665 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.2227596665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.3830200776 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 426256968 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 11:26:14 AM UTC 24 |
| Finished | Oct 03 11:26:17 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830200776 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3830200776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/40.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.2465151059 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 509095049 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 11:26:15 AM UTC 24 |
| Finished | Oct 03 11:26:17 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465151059 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2465151059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/41.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2395832405 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 287533863 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 11:26:16 AM UTC 24 |
| Finished | Oct 03 11:26:18 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395832405 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2395832405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/42.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.1492326648 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 473510892 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 11:26:16 AM UTC 24 |
| Finished | Oct 03 11:26:18 AM UTC 24 |
| Peak memory | 201756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492326648 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1492326648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/43.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.3262159594 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 482050780 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 11:26:17 AM UTC 24 |
| Finished | Oct 03 11:26:19 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262159594 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3262159594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/44.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.333007874 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 463291990 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 11:26:17 AM UTC 24 |
| Finished | Oct 03 11:26:20 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333007874 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.333007874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/45.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.1009451604 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 434552964 ps |
| CPU time | 0.94 seconds |
| Started | Oct 03 11:26:17 AM UTC 24 |
| Finished | Oct 03 11:26:19 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009451604 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1009451604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/46.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.1401480938 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 381951560 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 11:26:18 AM UTC 24 |
| Finished | Oct 03 11:26:21 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401480938 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1401480938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/47.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.399727064 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 436429016 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 11:26:18 AM UTC 24 |
| Finished | Oct 03 11:26:21 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399727064 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.399727064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/48.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.1944072372 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 352505061 ps |
| CPU time | 0.9 seconds |
| Started | Oct 03 11:26:18 AM UTC 24 |
| Finished | Oct 03 11:26:20 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944072372 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1944072372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/49.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2836646311 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 406550842 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 11:25:24 AM UTC 24 |
| Finished | Oct 03 11:25:27 AM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2836646311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_tim er_csr_mem_rw_with_rand_reset.2836646311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.3302925961 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 546466658 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 11:25:23 AM UTC 24 |
| Finished | Oct 03 11:25:25 AM UTC 24 |
| Peak memory | 201356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302925961 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3302925961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.3919378140 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 447172326 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 11:25:22 AM UTC 24 |
| Finished | Oct 03 11:25:25 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919378140 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3919378140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4286975950 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1603157766 ps |
| CPU time | 3.51 seconds |
| Started | Oct 03 11:25:23 AM UTC 24 |
| Finished | Oct 03 11:25:28 AM UTC 24 |
| Peak memory | 202904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286975950 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.4286975950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.3325140496 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 567131696 ps |
| CPU time | 2.72 seconds |
| Started | Oct 03 11:25:20 AM UTC 24 |
| Finished | Oct 03 11:25:24 AM UTC 24 |
| Peak memory | 207256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325140496 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3325140496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3569511597 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4032342151 ps |
| CPU time | 2.97 seconds |
| Started | Oct 03 11:25:21 AM UTC 24 |
| Finished | Oct 03 11:25:25 AM UTC 24 |
| Peak memory | 206772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569511597 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.3569511597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2206399274 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 371005610 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 11:25:28 AM UTC 24 |
| Finished | Oct 03 11:25:31 AM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2206399274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_tim er_csr_mem_rw_with_rand_reset.2206399274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.3890303150 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 328034029 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 11:25:26 AM UTC 24 |
| Finished | Oct 03 11:25:28 AM UTC 24 |
| Peak memory | 201824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890303150 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3890303150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.2951857535 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 417947462 ps |
| CPU time | 0.93 seconds |
| Started | Oct 03 11:25:25 AM UTC 24 |
| Finished | Oct 03 11:25:27 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951857535 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2951857535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.886261466 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2150272657 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 11:25:27 AM UTC 24 |
| Finished | Oct 03 11:25:31 AM UTC 24 |
| Peak memory | 205736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886261466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.886261466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.2897628131 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 515961737 ps |
| CPU time | 3.46 seconds |
| Started | Oct 03 11:25:24 AM UTC 24 |
| Finished | Oct 03 11:25:29 AM UTC 24 |
| Peak memory | 207088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897628131 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2897628131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.937450213 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4489352486 ps |
| CPU time | 10.07 seconds |
| Started | Oct 03 11:25:25 AM UTC 24 |
| Finished | Oct 03 11:25:37 AM UTC 24 |
| Peak memory | 206928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937450213 -assert nopostproc +UVM_TES TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.937450213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3027004014 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 367965963 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 11:25:31 AM UTC 24 |
| Finished | Oct 03 11:25:33 AM UTC 24 |
| Peak memory | 205500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3027004014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim er_csr_mem_rw_with_rand_reset.3027004014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.3932297196 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 536441188 ps |
| CPU time | 2.58 seconds |
| Started | Oct 03 11:25:30 AM UTC 24 |
| Finished | Oct 03 11:25:34 AM UTC 24 |
| Peak memory | 203304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932297196 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3932297196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.1260199937 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 526792170 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 11:25:29 AM UTC 24 |
| Finished | Oct 03 11:25:32 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260199937 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1260199937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1330259337 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 892003351 ps |
| CPU time | 3.82 seconds |
| Started | Oct 03 11:25:31 AM UTC 24 |
| Finished | Oct 03 11:25:36 AM UTC 24 |
| Peak memory | 203564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330259337 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.1330259337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.1364817010 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 584086390 ps |
| CPU time | 4.63 seconds |
| Started | Oct 03 11:25:29 AM UTC 24 |
| Finished | Oct 03 11:25:35 AM UTC 24 |
| Peak memory | 206988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364817010 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1364817010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1671888862 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 327452872 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 11:25:36 AM UTC 24 |
| Finished | Oct 03 11:25:39 AM UTC 24 |
| Peak memory | 205428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1671888862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim er_csr_mem_rw_with_rand_reset.1671888862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.3717202391 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 390218623 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 11:25:34 AM UTC 24 |
| Finished | Oct 03 11:25:37 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717202391 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3717202391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.2428979227 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 377859242 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 11:25:32 AM UTC 24 |
| Finished | Oct 03 11:25:35 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428979227 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2428979227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3207560965 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1464782190 ps |
| CPU time | 5.51 seconds |
| Started | Oct 03 11:25:35 AM UTC 24 |
| Finished | Oct 03 11:25:41 AM UTC 24 |
| Peak memory | 203564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207560965 -assert nopostpro c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.3207560965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.867178758 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 845956725 ps |
| CPU time | 2.71 seconds |
| Started | Oct 03 11:25:32 AM UTC 24 |
| Finished | Oct 03 11:25:36 AM UTC 24 |
| Peak memory | 207096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867178758 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.867178758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2097906791 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 8191846756 ps |
| CPU time | 10.41 seconds |
| Started | Oct 03 11:25:32 AM UTC 24 |
| Finished | Oct 03 11:25:44 AM UTC 24 |
| Peak memory | 206880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097906791 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.2097906791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4171509099 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 617248259 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 11:25:38 AM UTC 24 |
| Finished | Oct 03 11:25:41 AM UTC 24 |
| Peak memory | 205468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4171509099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_tim er_csr_mem_rw_with_rand_reset.4171509099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.760860076 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 346362777 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 11:25:37 AM UTC 24 |
| Finished | Oct 03 11:25:39 AM UTC 24 |
| Peak memory | 201764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760860076 -assert nopostproc +UVM_TESTNAME=aon _timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.760860076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.279863342 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 498309633 ps |
| CPU time | 2.38 seconds |
| Started | Oct 03 11:25:37 AM UTC 24 |
| Finished | Oct 03 11:25:40 AM UTC 24 |
| Peak memory | 201516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279863342 -assert nopostproc +UVM_TESTNAME=aon_ti mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.279863342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.479327771 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1593787113 ps |
| CPU time | 2.05 seconds |
| Started | Oct 03 11:25:38 AM UTC 24 |
| Finished | Oct 03 11:25:41 AM UTC 24 |
| Peak memory | 203232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479327771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.479327771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.3319449268 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 484076006 ps |
| CPU time | 3.01 seconds |
| Started | Oct 03 11:25:36 AM UTC 24 |
| Finished | Oct 03 11:25:40 AM UTC 24 |
| Peak memory | 206736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319449268 -assert nopostproc +UVM_TESTNAME=aon_t imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3319449268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2367049761 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 8845172154 ps |
| CPU time | 11.27 seconds |
| Started | Oct 03 11:25:37 AM UTC 24 |
| Finished | Oct 03 11:25:49 AM UTC 24 |
| Peak memory | 206840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367049761 -assert nopostproc +UVM_TE STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.2367049761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.2414258623 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 18014934337 ps |
| CPU time | 13.71 seconds |
| Started | Oct 03 11:26:18 AM UTC 24 |
| Finished | Oct 03 11:26:33 AM UTC 24 |
| Peak memory | 205948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414258623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2414258623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1375051773 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 547086602 ps |
| CPU time | 1 seconds |
| Started | Oct 03 11:26:18 AM UTC 24 |
| Finished | Oct 03 11:26:20 AM UTC 24 |
| Peak memory | 205052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375051773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1375051773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/0.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.1690617264 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 29264677406 ps |
| CPU time | 19.42 seconds |
| Started | Oct 03 11:26:20 AM UTC 24 |
| Finished | Oct 03 11:26:40 AM UTC 24 |
| Peak memory | 205932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690617264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1690617264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.2912508418 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3451026231 ps |
| CPU time | 9.93 seconds |
| Started | Oct 03 11:26:21 AM UTC 24 |
| Finished | Oct 03 11:26:32 AM UTC 24 |
| Peak memory | 234100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912508418 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2912508418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.921958901 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 434380684 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:26:19 AM UTC 24 |
| Finished | Oct 03 11:26:22 AM UTC 24 |
| Peak memory | 203880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921958901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.921958901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/1.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.841852907 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 16913673793 ps |
| CPU time | 8.26 seconds |
| Started | Oct 03 11:27:09 AM UTC 24 |
| Finished | Oct 03 11:27:18 AM UTC 24 |
| Peak memory | 205924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841852907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.841852907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.2006693312 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 572129100 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 11:27:09 AM UTC 24 |
| Finished | Oct 03 11:27:11 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006693312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2006693312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/10.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.790758572 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 21998458157 ps |
| CPU time | 19.58 seconds |
| Started | Oct 03 11:27:13 AM UTC 24 |
| Finished | Oct 03 11:27:34 AM UTC 24 |
| Peak memory | 205924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790758572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.790758572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.2944579860 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 423985554 ps |
| CPU time | 2.4 seconds |
| Started | Oct 03 11:27:12 AM UTC 24 |
| Finished | Oct 03 11:27:15 AM UTC 24 |
| Peak memory | 205692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944579860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2944579860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.4128335755 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 686182355 ps |
| CPU time | 5.85 seconds |
| Started | Oct 03 11:27:14 AM UTC 24 |
| Finished | Oct 03 11:27:21 AM UTC 24 |
| Peak memory | 207232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4128335755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 11.aon_timer_stress_all_with_rand_reset.4128335755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.1749393900 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 12687775151 ps |
| CPU time | 20.76 seconds |
| Started | Oct 03 11:27:18 AM UTC 24 |
| Finished | Oct 03 11:27:40 AM UTC 24 |
| Peak memory | 206008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749393900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1749393900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.3884710986 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 477103903 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 11:27:16 AM UTC 24 |
| Finished | Oct 03 11:27:18 AM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884710986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3884710986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/12.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.1728036235 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 33558992646 ps |
| CPU time | 42.41 seconds |
| Started | Oct 03 11:27:26 AM UTC 24 |
| Finished | Oct 03 11:28:09 AM UTC 24 |
| Peak memory | 206024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728036235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1728036235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.3413897956 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 577218955 ps |
| CPU time | 1 seconds |
| Started | Oct 03 11:27:23 AM UTC 24 |
| Finished | Oct 03 11:27:25 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413897956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3413897956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/13.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.1848098189 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 20795379192 ps |
| CPU time | 42.61 seconds |
| Started | Oct 03 11:27:43 AM UTC 24 |
| Finished | Oct 03 11:28:28 AM UTC 24 |
| Peak memory | 205960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848098189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1848098189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.4231287154 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 425796778 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 11:27:41 AM UTC 24 |
| Finished | Oct 03 11:27:44 AM UTC 24 |
| Peak memory | 205828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231287154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.4231287154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/14.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.2216806585 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 20999267761 ps |
| CPU time | 11.91 seconds |
| Started | Oct 03 11:27:50 AM UTC 24 |
| Finished | Oct 03 11:28:04 AM UTC 24 |
| Peak memory | 206136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216806585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2216806585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.808322091 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 403148187 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 11:27:48 AM UTC 24 |
| Finished | Oct 03 11:27:52 AM UTC 24 |
| Peak memory | 203880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808322091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.808322091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/15.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.71721049 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 50151621101 ps |
| CPU time | 20.92 seconds |
| Started | Oct 03 11:28:03 AM UTC 24 |
| Finished | Oct 03 11:28:25 AM UTC 24 |
| Peak memory | 205936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71721049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.71721049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.235694924 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 492002377 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 11:28:02 AM UTC 24 |
| Finished | Oct 03 11:28:04 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235694924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.235694924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/16.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.3506534005 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 58793051488 ps |
| CPU time | 79.26 seconds |
| Started | Oct 03 11:28:08 AM UTC 24 |
| Finished | Oct 03 11:29:29 AM UTC 24 |
| Peak memory | 206072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506534005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3506534005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.168830317 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 538269311 ps |
| CPU time | 1.08 seconds |
| Started | Oct 03 11:28:08 AM UTC 24 |
| Finished | Oct 03 11:28:10 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168830317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.168830317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/17.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.608844158 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 20177343677 ps |
| CPU time | 8.55 seconds |
| Started | Oct 03 11:28:14 AM UTC 24 |
| Finished | Oct 03 11:28:23 AM UTC 24 |
| Peak memory | 206092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608844158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.608844158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.908379668 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 593177312 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 11:28:12 AM UTC 24 |
| Finished | Oct 03 11:28:15 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908379668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.908379668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/18.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.3262401702 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 6568533003 ps |
| CPU time | 6.46 seconds |
| Started | Oct 03 11:28:19 AM UTC 24 |
| Finished | Oct 03 11:28:26 AM UTC 24 |
| Peak memory | 206016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262401702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3262401702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.639074793 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 480360997 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 11:28:17 AM UTC 24 |
| Finished | Oct 03 11:28:19 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639074793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.639074793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/19.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.1905173997 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 36059422320 ps |
| CPU time | 39.92 seconds |
| Started | Oct 03 11:26:21 AM UTC 24 |
| Finished | Oct 03 11:27:02 AM UTC 24 |
| Peak memory | 205924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905173997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1905173997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.410097695 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7964510240 ps |
| CPU time | 13.35 seconds |
| Started | Oct 03 11:26:22 AM UTC 24 |
| Finished | Oct 03 11:26:37 AM UTC 24 |
| Peak memory | 234496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410097695 -assert nopostproc +UVM_TESTNAME=ao n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.410097695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.3877697678 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 484432738 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 11:26:21 AM UTC 24 |
| Finished | Oct 03 11:26:24 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877697678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3877697678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/2.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.1582119204 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 55284250403 ps |
| CPU time | 28.86 seconds |
| Started | Oct 03 11:28:24 AM UTC 24 |
| Finished | Oct 03 11:28:54 AM UTC 24 |
| Peak memory | 206096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582119204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1582119204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/20.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.156058112 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 487906094 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 11:28:23 AM UTC 24 |
| Finished | Oct 03 11:28:25 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156058112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.156058112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/20.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.3762731670 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1027532886 ps |
| CPU time | 11.66 seconds |
| Started | Oct 03 11:28:25 AM UTC 24 |
| Finished | Oct 03 11:28:38 AM UTC 24 |
| Peak memory | 222592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3762731670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 20.aon_timer_stress_all_with_rand_reset.3762731670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.4065906414 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 25134221698 ps |
| CPU time | 34.7 seconds |
| Started | Oct 03 11:28:29 AM UTC 24 |
| Finished | Oct 03 11:29:05 AM UTC 24 |
| Peak memory | 205936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065906414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4065906414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/21.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.3834321774 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 389643097 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 11:28:28 AM UTC 24 |
| Finished | Oct 03 11:28:30 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834321774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3834321774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/21.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.2344078270 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 431939419 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 11:28:36 AM UTC 24 |
| Finished | Oct 03 11:28:39 AM UTC 24 |
| Peak memory | 205376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344078270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2344078270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/22.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.4166474155 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 6593994434 ps |
| CPU time | 12.04 seconds |
| Started | Oct 03 11:28:33 AM UTC 24 |
| Finished | Oct 03 11:28:46 AM UTC 24 |
| Peak memory | 205928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166474155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.4166474155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/22.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.1319845829 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 438678886 ps |
| CPU time | 2.56 seconds |
| Started | Oct 03 11:28:32 AM UTC 24 |
| Finished | Oct 03 11:28:36 AM UTC 24 |
| Peak memory | 205648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319845829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1319845829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/22.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.465412837 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 3314263810 ps |
| CPU time | 3.47 seconds |
| Started | Oct 03 11:28:41 AM UTC 24 |
| Finished | Oct 03 11:28:46 AM UTC 24 |
| Peak memory | 205720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465412837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.465412837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/23.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.1112939945 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 512404853 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 11:28:40 AM UTC 24 |
| Finished | Oct 03 11:28:43 AM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112939945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1112939945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/23.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.3696672620 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 488009751 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 11:28:49 AM UTC 24 |
| Finished | Oct 03 11:28:51 AM UTC 24 |
| Peak memory | 203880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696672620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3696672620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/24.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.1438385742 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 28472193827 ps |
| CPU time | 26.71 seconds |
| Started | Oct 03 11:28:47 AM UTC 24 |
| Finished | Oct 03 11:29:15 AM UTC 24 |
| Peak memory | 206096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438385742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1438385742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/24.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.186096421 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 535154840 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 11:28:47 AM UTC 24 |
| Finished | Oct 03 11:28:49 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186096421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.186096421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/24.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.3602098437 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 7760258508 ps |
| CPU time | 34.83 seconds |
| Started | Oct 03 11:28:50 AM UTC 24 |
| Finished | Oct 03 11:29:26 AM UTC 24 |
| Peak memory | 223872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3602098437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 24.aon_timer_stress_all_with_rand_reset.3602098437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.1511875216 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3279941755 ps |
| CPU time | 3.32 seconds |
| Started | Oct 03 11:28:59 AM UTC 24 |
| Finished | Oct 03 11:29:04 AM UTC 24 |
| Peak memory | 205788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511875216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1511875216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/25.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.3967177419 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 531653413 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 11:28:55 AM UTC 24 |
| Finished | Oct 03 11:28:58 AM UTC 24 |
| Peak memory | 205656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967177419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3967177419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/25.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.4160319559 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 43763814891 ps |
| CPU time | 42.99 seconds |
| Started | Oct 03 11:29:08 AM UTC 24 |
| Finished | Oct 03 11:29:53 AM UTC 24 |
| Peak memory | 205928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160319559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.4160319559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/26.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.978922858 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 418782143 ps |
| CPU time | 1.1 seconds |
| Started | Oct 03 11:29:05 AM UTC 24 |
| Finished | Oct 03 11:29:08 AM UTC 24 |
| Peak memory | 205900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978922858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.978922858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/26.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.933781679 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1553283249 ps |
| CPU time | 2.44 seconds |
| Started | Oct 03 11:29:16 AM UTC 24 |
| Finished | Oct 03 11:29:19 AM UTC 24 |
| Peak memory | 205720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933781679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.933781679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/27.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.860523022 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 408865424 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 11:29:16 AM UTC 24 |
| Finished | Oct 03 11:29:18 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860523022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.860523022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/27.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.1501564610 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 455544416 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 11:29:27 AM UTC 24 |
| Finished | Oct 03 11:29:30 AM UTC 24 |
| Peak memory | 205848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501564610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1501564610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/28.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.1144426796 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4123637278 ps |
| CPU time | 7.02 seconds |
| Started | Oct 03 11:29:26 AM UTC 24 |
| Finished | Oct 03 11:29:34 AM UTC 24 |
| Peak memory | 205812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144426796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1144426796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/28.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.2709258313 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 558967836 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 11:29:22 AM UTC 24 |
| Finished | Oct 03 11:29:25 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709258313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2709258313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/28.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.515366042 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 535089120 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 11:29:36 AM UTC 24 |
| Finished | Oct 03 11:29:38 AM UTC 24 |
| Peak memory | 205488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515366042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.515366042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/29.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.680637359 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 34163054695 ps |
| CPU time | 28.19 seconds |
| Started | Oct 03 11:29:34 AM UTC 24 |
| Finished | Oct 03 11:30:03 AM UTC 24 |
| Peak memory | 205940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680637359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.680637359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/29.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.1079495432 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 579494918 ps |
| CPU time | 1 seconds |
| Started | Oct 03 11:29:31 AM UTC 24 |
| Finished | Oct 03 11:29:33 AM UTC 24 |
| Peak memory | 205724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079495432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1079495432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/29.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.573941052 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 536954616 ps |
| CPU time | 2.6 seconds |
| Started | Oct 03 11:26:25 AM UTC 24 |
| Finished | Oct 03 11:26:29 AM UTC 24 |
| Peak memory | 205448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573941052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.573941052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.3407994087 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 43420301981 ps |
| CPU time | 82.83 seconds |
| Started | Oct 03 11:26:24 AM UTC 24 |
| Finished | Oct 03 11:27:49 AM UTC 24 |
| Peak memory | 206012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407994087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3407994087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.2600990220 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4296299528 ps |
| CPU time | 10.38 seconds |
| Started | Oct 03 11:26:30 AM UTC 24 |
| Finished | Oct 03 11:26:41 AM UTC 24 |
| Peak memory | 234428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600990220 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2600990220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.3921177975 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 423274608 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 11:26:23 AM UTC 24 |
| Finished | Oct 03 11:26:27 AM UTC 24 |
| Peak memory | 205660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921177975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3921177975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/3.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.1014402605 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1341746805 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 11:29:47 AM UTC 24 |
| Finished | Oct 03 11:29:49 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014402605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1014402605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/30.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.1824017653 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 621426506 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 11:29:44 AM UTC 24 |
| Finished | Oct 03 11:29:46 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824017653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1824017653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/30.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.1033135099 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 34405912144 ps |
| CPU time | 77.36 seconds |
| Started | Oct 03 11:29:51 AM UTC 24 |
| Finished | Oct 03 11:31:11 AM UTC 24 |
| Peak memory | 206008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033135099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1033135099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/31.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.3449079398 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 597180764 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 11:29:51 AM UTC 24 |
| Finished | Oct 03 11:29:54 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449079398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3449079398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/31.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.532878165 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 24743042669 ps |
| CPU time | 6.73 seconds |
| Started | Oct 03 11:30:00 AM UTC 24 |
| Finished | Oct 03 11:30:08 AM UTC 24 |
| Peak memory | 205924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532878165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.532878165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/32.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.4139623895 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 396328363 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 11:29:57 AM UTC 24 |
| Finished | Oct 03 11:30:00 AM UTC 24 |
| Peak memory | 205720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139623895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.4139623895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/32.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.1186108594 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 6146110180 ps |
| CPU time | 22.09 seconds |
| Started | Oct 03 11:30:03 AM UTC 24 |
| Finished | Oct 03 11:30:26 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1186108594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 32.aon_timer_stress_all_with_rand_reset.1186108594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.4072287240 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 20821109049 ps |
| CPU time | 35.7 seconds |
| Started | Oct 03 11:30:04 AM UTC 24 |
| Finished | Oct 03 11:30:41 AM UTC 24 |
| Peak memory | 205928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072287240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.4072287240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/33.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.1437329326 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 551288138 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:30:04 AM UTC 24 |
| Finished | Oct 03 11:30:06 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437329326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1437329326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/33.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.2481666091 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 19673535563 ps |
| CPU time | 33.84 seconds |
| Started | Oct 03 11:30:20 AM UTC 24 |
| Finished | Oct 03 11:30:55 AM UTC 24 |
| Peak memory | 205936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481666091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2481666091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/34.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.1760594240 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 447972897 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 11:30:18 AM UTC 24 |
| Finished | Oct 03 11:30:20 AM UTC 24 |
| Peak memory | 205724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760594240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1760594240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/34.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.2073032177 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 4791263662 ps |
| CPU time | 7.29 seconds |
| Started | Oct 03 11:30:31 AM UTC 24 |
| Finished | Oct 03 11:30:40 AM UTC 24 |
| Peak memory | 205960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073032177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2073032177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/35.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.1053413579 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 566529670 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 11:30:27 AM UTC 24 |
| Finished | Oct 03 11:30:30 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053413579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1053413579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/35.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.988435919 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 61037627369 ps |
| CPU time | 38.4 seconds |
| Started | Oct 03 11:30:47 AM UTC 24 |
| Finished | Oct 03 11:31:27 AM UTC 24 |
| Peak memory | 206060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988435919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.988435919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/36.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.3752376378 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 425976663 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 11:30:43 AM UTC 24 |
| Finished | Oct 03 11:30:46 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752376378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3752376378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/36.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.1245660648 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 40812122894 ps |
| CPU time | 17.73 seconds |
| Started | Oct 03 11:30:56 AM UTC 24 |
| Finished | Oct 03 11:31:15 AM UTC 24 |
| Peak memory | 206152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245660648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1245660648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/37.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.3536260207 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 586139254 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 11:30:53 AM UTC 24 |
| Finished | Oct 03 11:30:56 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536260207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3536260207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/37.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.410420254 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 21493603377 ps |
| CPU time | 16.59 seconds |
| Started | Oct 03 11:31:00 AM UTC 24 |
| Finished | Oct 03 11:31:18 AM UTC 24 |
| Peak memory | 206148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410420254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.410420254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/38.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.1657867189 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 368179298 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 11:30:59 AM UTC 24 |
| Finished | Oct 03 11:31:02 AM UTC 24 |
| Peak memory | 205512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657867189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1657867189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/38.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.2961166399 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 6431097755 ps |
| CPU time | 10.03 seconds |
| Started | Oct 03 11:31:07 AM UTC 24 |
| Finished | Oct 03 11:31:18 AM UTC 24 |
| Peak memory | 205944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961166399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2961166399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/39.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.3272439683 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 536336350 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 11:31:07 AM UTC 24 |
| Finished | Oct 03 11:31:09 AM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272439683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3272439683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/39.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.582211615 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 32839173338 ps |
| CPU time | 96.41 seconds |
| Started | Oct 03 11:26:34 AM UTC 24 |
| Finished | Oct 03 11:28:13 AM UTC 24 |
| Peak memory | 206016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582211615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.582211615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.2267231381 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7295826279 ps |
| CPU time | 20.23 seconds |
| Started | Oct 03 11:26:37 AM UTC 24 |
| Finished | Oct 03 11:26:59 AM UTC 24 |
| Peak memory | 234516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267231381 -assert nopostproc +UVM_TESTNAME=a on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2267231381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.1591972135 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 333616912 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 11:26:33 AM UTC 24 |
| Finished | Oct 03 11:26:36 AM UTC 24 |
| Peak memory | 205604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591972135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1591972135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/4.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.589402967 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 32882258654 ps |
| CPU time | 38.23 seconds |
| Started | Oct 03 11:31:12 AM UTC 24 |
| Finished | Oct 03 11:31:52 AM UTC 24 |
| Peak memory | 206132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589402967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.589402967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/40.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.2395038673 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 338070236 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 11:31:11 AM UTC 24 |
| Finished | Oct 03 11:31:14 AM UTC 24 |
| Peak memory | 205868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395038673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2395038673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/40.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.3127792612 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 32654803598 ps |
| CPU time | 24.55 seconds |
| Started | Oct 03 11:31:16 AM UTC 24 |
| Finished | Oct 03 11:31:41 AM UTC 24 |
| Peak memory | 206012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127792612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3127792612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/41.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.2073605416 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 597507329 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 11:31:15 AM UTC 24 |
| Finished | Oct 03 11:31:18 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073605416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2073605416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/41.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.4061237049 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 56784832979 ps |
| CPU time | 32.97 seconds |
| Started | Oct 03 11:31:19 AM UTC 24 |
| Finished | Oct 03 11:31:53 AM UTC 24 |
| Peak memory | 206128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061237049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4061237049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/42.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.139384557 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 579333920 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 11:31:19 AM UTC 24 |
| Finished | Oct 03 11:31:22 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139384557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.139384557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/42.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.226934588 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 17178842410 ps |
| CPU time | 13.77 seconds |
| Started | Oct 03 11:31:26 AM UTC 24 |
| Finished | Oct 03 11:31:41 AM UTC 24 |
| Peak memory | 206008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226934588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.226934588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/43.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.4252112628 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 398462696 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 11:31:24 AM UTC 24 |
| Finished | Oct 03 11:31:28 AM UTC 24 |
| Peak memory | 205724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252112628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4252112628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/43.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.3455671781 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 502676421 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 11:31:34 AM UTC 24 |
| Finished | Oct 03 11:31:36 AM UTC 24 |
| Peak memory | 203880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455671781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3455671781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/44.aon_timer_jump/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.645956294 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 10491032423 ps |
| CPU time | 18.52 seconds |
| Started | Oct 03 11:31:33 AM UTC 24 |
| Finished | Oct 03 11:31:52 AM UTC 24 |
| Peak memory | 206012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645956294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.645956294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/44.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.3824729118 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 579791311 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 11:31:31 AM UTC 24 |
| Finished | Oct 03 11:31:33 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824729118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3824729118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/44.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.4013780234 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 34566313435 ps |
| CPU time | 29.1 seconds |
| Started | Oct 03 11:31:42 AM UTC 24 |
| Finished | Oct 03 11:32:12 AM UTC 24 |
| Peak memory | 205944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013780234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4013780234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/45.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.3470674532 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 384518489 ps |
| CPU time | 0.86 seconds |
| Started | Oct 03 11:31:40 AM UTC 24 |
| Finished | Oct 03 11:31:42 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470674532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3470674532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/45.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.3426557092 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 19211622858 ps |
| CPU time | 45.75 seconds |
| Started | Oct 03 11:31:46 AM UTC 24 |
| Finished | Oct 03 11:32:34 AM UTC 24 |
| Peak memory | 206160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426557092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3426557092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/46.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.2034602662 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 533770343 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 11:31:45 AM UTC 24 |
| Finished | Oct 03 11:31:48 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034602662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2034602662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/46.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.3146568603 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 7992719096 ps |
| CPU time | 7.6 seconds |
| Started | Oct 03 11:31:54 AM UTC 24 |
| Finished | Oct 03 11:32:03 AM UTC 24 |
| Peak memory | 206000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146568603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3146568603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/47.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.3486344101 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 614362872 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 11:31:54 AM UTC 24 |
| Finished | Oct 03 11:31:56 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486344101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3486344101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/47.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.3691417637 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 490422364797 ps |
| CPU time | 195.06 seconds |
| Started | Oct 03 11:31:59 AM UTC 24 |
| Finished | Oct 03 11:35:17 AM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691417637 -assert nopostproc +UVM_TESTNA ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.3691417637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/47.aon_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.2076283064 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 6356498972 ps |
| CPU time | 35.17 seconds |
| Started | Oct 03 11:31:57 AM UTC 24 |
| Finished | Oct 03 11:32:34 AM UTC 24 |
| Peak memory | 222780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_ seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2076283064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 47.aon_timer_stress_all_with_rand_reset.2076283064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.1542041549 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 18199743645 ps |
| CPU time | 5.37 seconds |
| Started | Oct 03 11:32:03 AM UTC 24 |
| Finished | Oct 03 11:32:10 AM UTC 24 |
| Peak memory | 205952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542041549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1542041549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/48.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.1381517595 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 491146145 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 11:32:00 AM UTC 24 |
| Finished | Oct 03 11:32:03 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381517595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1381517595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/48.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.2630830030 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 44872755093 ps |
| CPU time | 17.61 seconds |
| Started | Oct 03 11:32:13 AM UTC 24 |
| Finished | Oct 03 11:32:32 AM UTC 24 |
| Peak memory | 206000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630830030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2630830030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/49.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.2469421897 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 382830061 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 11:32:10 AM UTC 24 |
| Finished | Oct 03 11:32:13 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469421897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2469421897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/49.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.4908239 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 18607106639 ps |
| CPU time | 8.46 seconds |
| Started | Oct 03 11:26:39 AM UTC 24 |
| Finished | Oct 03 11:26:49 AM UTC 24 |
| Peak memory | 205940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4908239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST _SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4908239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.2481497064 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 501060350 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 11:26:38 AM UTC 24 |
| Finished | Oct 03 11:26:41 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481497064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2481497064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/5.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.404901388 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7954601621 ps |
| CPU time | 6.79 seconds |
| Started | Oct 03 11:26:49 AM UTC 24 |
| Finished | Oct 03 11:26:57 AM UTC 24 |
| Peak memory | 205928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404901388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.404901388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.74320474 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 422147943 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 11:26:45 AM UTC 24 |
| Finished | Oct 03 11:26:48 AM UTC 24 |
| Peak memory | 205728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74320474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.74320474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/6.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.4266328581 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11114497881 ps |
| CPU time | 10.7 seconds |
| Started | Oct 03 11:26:56 AM UTC 24 |
| Finished | Oct 03 11:27:08 AM UTC 24 |
| Peak memory | 206132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266328581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4266328581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.2526778823 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 340355886 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 11:26:52 AM UTC 24 |
| Finished | Oct 03 11:26:55 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526778823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2526778823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/7.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.2999616529 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 41058127512 ps |
| CPU time | 72.71 seconds |
| Started | Oct 03 11:27:01 AM UTC 24 |
| Finished | Oct 03 11:28:15 AM UTC 24 |
| Peak memory | 205932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999616529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2999616529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.2970385991 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 421712964 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 11:27:00 AM UTC 24 |
| Finished | Oct 03 11:27:02 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970385991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2970385991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/8.aon_timer_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.4043898250 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 35034233057 ps |
| CPU time | 37.39 seconds |
| Started | Oct 03 11:27:03 AM UTC 24 |
| Finished | Oct 03 11:27:42 AM UTC 24 |
| Peak memory | 206148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043898250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.4043898250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_prescaler/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.2542725642 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 614650178 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 11:27:03 AM UTC 24 |
| Finished | Oct 03 11:27:06 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542725642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2542725642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/aon_timer-sim-vcs/9.aon_timer_smoke/latest |
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