Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 16972 1 T2 10 T3 10 T4 10
bark[1] 524 1 T24 21 T144 311 T105 31
bark[2] 320 1 T6 14 T50 149 T109 21
bark[3] 328 1 T35 230 T96 21 T134 21
bark[4] 369 1 T91 161 T96 7 T142 21
bark[5] 520 1 T18 14 T188 14 T162 14
bark[6] 233 1 T35 7 T24 21 T179 14
bark[7] 421 1 T201 14 T35 52 T57 21
bark[8] 285 1 T95 14 T187 96 T153 14
bark[9] 252 1 T19 41 T166 7 T105 7
bark[10] 405 1 T25 44 T142 30 T102 14
bark[11] 552 1 T14 21 T50 230 T105 198
bark[12] 418 1 T34 14 T142 21 T185 102
bark[13] 406 1 T50 45 T142 14 T109 40
bark[14] 235 1 T147 14 T142 5 T134 49
bark[15] 503 1 T25 21 T105 243 T130 7
bark[16] 335 1 T1 14 T138 21 T105 86
bark[17] 619 1 T32 14 T24 21 T48 7
bark[18] 537 1 T54 14 T46 232 T124 14
bark[19] 405 1 T33 14 T19 21 T49 21
bark[20] 227 1 T30 14 T25 21 T202 14
bark[21] 314 1 T19 5 T47 5 T49 7
bark[22] 417 1 T24 38 T25 94 T84 100
bark[23] 844 1 T8 14 T48 5 T96 47
bark[24] 260 1 T49 26 T104 7 T161 21
bark[25] 408 1 T133 14 T96 102 T84 21
bark[26] 210 1 T15 14 T205 14 T113 14
bark[27] 260 1 T7 14 T18 21 T151 14
bark[28] 183 1 T12 14 T49 35 T142 21
bark[29] 287 1 T18 14 T47 44 T48 26
bark[30] 511 1 T96 26 T172 14 T192 65
bark[31] 245 1 T14 21 T174 21 T173 21
bark_0 4700 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 16598 1 T2 9 T3 9 T4 9
bite[1] 444 1 T8 13 T34 13 T32 13
bite[2] 665 1 T201 13 T174 21 T84 222
bite[3] 434 1 T25 30 T47 4 T48 25
bite[4] 640 1 T35 215 T96 26 T184 30
bite[5] 152 1 T19 21 T25 13 T142 13
bite[6] 434 1 T24 21 T124 13 T155 13
bite[7] 377 1 T18 13 T205 13 T96 6
bite[8] 201 1 T105 6 T130 13 T196 13
bite[9] 333 1 T33 13 T24 38 T133 13
bite[10] 443 1 T25 94 T93 63 T109 21
bite[11] 283 1 T7 13 T30 13 T35 6
bite[12] 632 1 T54 13 T47 44 T49 21
bite[13] 136 1 T56 13 T179 13 T141 13
bite[14] 479 1 T18 13 T19 46 T46 231
bite[15] 273 1 T18 21 T84 99 T137 21
bite[16] 417 1 T14 21 T151 13 T96 21
bite[17] 327 1 T57 21 T95 13 T142 21
bite[18] 204 1 T50 44 T195 13 T161 21
bite[19] 534 1 T147 13 T50 148 T142 21
bite[20] 260 1 T19 4 T48 6 T96 101
bite[21] 161 1 T136 26 T132 13 T86 6
bite[22] 109 1 T104 6 T161 13 T90 21
bite[23] 437 1 T35 51 T49 35 T159 31
bite[24] 459 1 T142 13 T168 315 T137 21
bite[25] 348 1 T91 160 T207 13 T158 4
bite[26] 257 1 T1 13 T15 13 T202 13
bite[27] 786 1 T35 13 T25 21 T96 46
bite[28] 743 1 T12 13 T24 21 T142 4
bite[29] 385 1 T6 13 T50 229 T137 31
bite[30] 74 1 T19 40 T169 13 T171 21
bite[31] 256 1 T174 13 T168 21 T175 13
bite_0 5224 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30323 1 T1 21 T2 17 T3 17
auto[1] 3182 1 T5 7 T81 7 T82 7


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 417 1 T50 19 T212 9 T138 40
prescale[1] 756 1 T48 2 T93 2 T96 40
prescale[2] 222 1 T57 24 T91 2 T142 2
prescale[3] 279 1 T22 2 T136 19 T192 4
prescale[4] 733 1 T10 9 T35 114 T24 41
prescale[5] 416 1 T213 9 T214 9 T96 2
prescale[6] 270 1 T51 2 T99 9 T83 2
prescale[7] 509 1 T14 57 T19 9 T47 9
prescale[8] 350 1 T52 9 T48 2 T49 9
prescale[9] 266 1 T51 2 T159 2 T166 19
prescale[10] 375 1 T46 146 T57 23 T138 32
prescale[11] 383 1 T17 9 T19 4 T35 2
prescale[12] 457 1 T19 24 T48 2 T215 9
prescale[13] 337 1 T216 9 T96 2 T184 28
prescale[14] 397 1 T217 9 T49 2 T51 2
prescale[15] 463 1 T50 2 T96 54 T83 2
prescale[16] 228 1 T50 2 T159 56 T218 9
prescale[17] 394 1 T14 19 T19 19 T49 19
prescale[18] 424 1 T19 74 T46 2 T50 4
prescale[19] 280 1 T14 19 T35 31 T50 2
prescale[20] 157 1 T219 9 T220 9 T166 39
prescale[21] 488 1 T35 2 T55 9 T50 87
prescale[22] 324 1 T22 2 T94 9 T159 2
prescale[23] 360 1 T19 2 T221 9 T91 2
prescale[24] 565 1 T18 2 T39 9 T46 57
prescale[25] 267 1 T24 32 T47 19 T93 2
prescale[26] 589 1 T14 40 T49 2 T166 19
prescale[27] 271 1 T18 2 T46 45 T47 2
prescale[28] 244 1 T24 19 T159 9 T109 28
prescale[29] 457 1 T47 2 T50 94 T93 2
prescale[30] 373 1 T14 19 T19 2 T48 4
prescale[31] 431 1 T35 2 T46 2 T24 9
prescale_0 21023 1 T1 21 T2 17 T3 17


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22228 1 T1 21 T2 17 T3 17
auto[1] 11277 1 T5 9 T7 12 T13 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 33505 1 T1 21 T2 17 T3 17


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 18501 1 T1 1 T2 12 T3 12
wkup[1] 159 1 T24 21 T48 15 T49 21
wkup[2] 105 1 T14 21 T84 21 T87 21
wkup[3] 184 1 T50 21 T96 21 T144 21
wkup[4] 168 1 T147 15 T48 6 T96 21
wkup[5] 164 1 T24 21 T47 44 T166 15
wkup[6] 361 1 T19 21 T46 42 T160 15
wkup[7] 99 1 T6 15 T138 21 T173 21
wkup[8] 233 1 T1 15 T19 42 T46 26
wkup[9] 245 1 T35 21 T57 26 T184 21
wkup[10] 120 1 T15 15 T166 21 T144 21
wkup[11] 270 1 T35 21 T25 21 T47 6
wkup[12] 167 1 T50 26 T96 42 T142 6
wkup[13] 270 1 T35 21 T48 21 T91 21
wkup[14] 246 1 T50 21 T84 21 T104 52
wkup[15] 163 1 T50 26 T161 21 T137 21
wkup[16] 131 1 T83 8 T192 21 T110 21
wkup[17] 207 1 T84 21 T161 15 T136 21
wkup[18] 144 1 T142 30 T187 21 T128 21
wkup[19] 183 1 T25 30 T121 15 T105 30
wkup[20] 174 1 T96 21 T105 39 T185 21
wkup[21] 175 1 T96 26 T162 15 T85 6
wkup[22] 223 1 T133 15 T83 21 T109 21
wkup[23] 84 1 T144 21 T168 21 T89 21
wkup[24] 234 1 T57 21 T49 21 T142 21
wkup[25] 208 1 T161 21 T168 15 T136 26
wkup[26] 170 1 T83 35 T104 30 T164 21
wkup[27] 182 1 T18 15 T96 29 T104 21
wkup[28] 118 1 T105 50 T192 26 T125 21
wkup[29] 104 1 T30 15 T91 45 T166 8
wkup[30] 114 1 T35 15 T109 21 T168 21
wkup[31] 264 1 T35 30 T25 21 T91 30
wkup[32] 157 1 T201 15 T57 21 T96 21
wkup[33] 273 1 T7 15 T124 15 T50 21
wkup[34] 195 1 T19 6 T130 15 T136 21
wkup[35] 129 1 T32 15 T96 21 T173 21
wkup[36] 198 1 T138 21 T84 21 T144 21
wkup[37] 168 1 T57 26 T49 8 T174 21
wkup[38] 196 1 T19 21 T142 36 T192 21
wkup[39] 172 1 T25 21 T49 26 T161 21
wkup[40] 195 1 T54 15 T49 35 T195 15
wkup[41] 71 1 T18 21 T35 8 T96 21
wkup[42] 403 1 T46 31 T57 21 T179 15
wkup[43] 160 1 T105 45 T187 21 T106 15
wkup[44] 176 1 T166 21 T168 21 T88 15
wkup[45] 140 1 T56 15 T50 21 T130 21
wkup[46] 286 1 T202 15 T93 21 T109 21
wkup[47] 176 1 T98 15 T159 21 T105 21
wkup[48] 265 1 T19 21 T24 21 T50 56
wkup[49] 120 1 T144 21 T175 15 T110 21
wkup[50] 273 1 T46 30 T24 21 T25 15
wkup[51] 164 1 T50 21 T166 21 T197 21
wkup[52] 101 1 T34 15 T48 8 T151 15
wkup[53] 210 1 T8 15 T12 15 T14 21
wkup[54] 156 1 T19 21 T50 21 T109 21
wkup[55] 184 1 T33 15 T85 35 T168 21
wkup[56] 29 1 T152 8 T189 21 - -
wkup[57] 129 1 T205 15 T142 21 T114 15
wkup[58] 218 1 T50 21 T105 21 T168 42
wkup[59] 177 1 T142 21 T84 42 T110 30
wkup[60] 186 1 T130 35 T87 21 T198 26
wkup[61] 119 1 T25 21 T173 21 T128 20
wkup[62] 76 1 T84 21 T168 21 T192 8
wkup[63] 134 1 T46 21 T51 21 T96 24
wkup_0 3699 1 T1 5 T2 5 T3 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%