Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.81 99.32 95.61 100.00 98.38 99.51 46.03


Total test records in report: 427
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T131 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.1035733321 Oct 09 05:22:13 AM UTC 24 Oct 09 05:31:27 AM UTC 24 296539831633 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.2270801218 Oct 09 05:21:18 AM UTC 24 Oct 09 05:38:18 AM UTC 24 545811599218 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.431922296 Oct 09 04:45:22 AM UTC 24 Oct 09 04:45:24 AM UTC 24 1288442164 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.795354588 Oct 09 04:45:22 AM UTC 24 Oct 09 04:45:24 AM UTC 24 453365218 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.3295125405 Oct 09 04:45:22 AM UTC 24 Oct 09 04:45:24 AM UTC 24 405615706 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1833497544 Oct 09 04:45:22 AM UTC 24 Oct 09 04:45:25 AM UTC 24 380362252 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.2423063769 Oct 09 04:45:23 AM UTC 24 Oct 09 04:45:25 AM UTC 24 395943879 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1027877585 Oct 09 04:45:23 AM UTC 24 Oct 09 04:45:26 AM UTC 24 505558321 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3287149131 Oct 09 04:45:23 AM UTC 24 Oct 09 04:45:26 AM UTC 24 379939930 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.501958081 Oct 09 04:45:23 AM UTC 24 Oct 09 04:45:26 AM UTC 24 3043068075 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.60753175 Oct 09 04:45:22 AM UTC 24 Oct 09 04:45:26 AM UTC 24 864888784 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3516074583 Oct 09 04:45:25 AM UTC 24 Oct 09 04:45:26 AM UTC 24 527352346 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.1845544570 Oct 09 04:45:23 AM UTC 24 Oct 09 04:45:27 AM UTC 24 389114952 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1793741940 Oct 09 04:45:25 AM UTC 24 Oct 09 04:45:27 AM UTC 24 858473212 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3096001656 Oct 09 04:45:25 AM UTC 24 Oct 09 04:45:27 AM UTC 24 438259570 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.1820285864 Oct 09 04:45:25 AM UTC 24 Oct 09 04:45:27 AM UTC 24 475055905 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.3316609145 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:28 AM UTC 24 425817740 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.1824023962 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:28 AM UTC 24 325335596 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.75826556 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:28 AM UTC 24 384388390 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1870388188 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:28 AM UTC 24 431298360 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2573931841 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:28 AM UTC 24 457160325 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1163461490 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:28 AM UTC 24 656060742 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3870442292 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:28 AM UTC 24 661304864 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3459880832 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:29 AM UTC 24 1411974586 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3502226154 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:29 AM UTC 24 450293868 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2021685346 Oct 09 04:45:24 AM UTC 24 Oct 09 04:45:29 AM UTC 24 7708659544 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2518468458 Oct 09 04:45:28 AM UTC 24 Oct 09 04:45:29 AM UTC 24 735170699 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3703072909 Oct 09 04:45:28 AM UTC 24 Oct 09 04:45:29 AM UTC 24 558147010 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.2477571813 Oct 09 04:45:27 AM UTC 24 Oct 09 04:45:30 AM UTC 24 334550912 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1039273760 Oct 09 04:45:28 AM UTC 24 Oct 09 04:45:30 AM UTC 24 1094853095 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3828301571 Oct 09 04:45:28 AM UTC 24 Oct 09 04:45:30 AM UTC 24 411926766 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2956292400 Oct 09 04:45:22 AM UTC 24 Oct 09 04:45:30 AM UTC 24 4372339241 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.3128595176 Oct 09 04:45:28 AM UTC 24 Oct 09 04:45:30 AM UTC 24 489994859 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.1911302972 Oct 09 04:45:34 AM UTC 24 Oct 09 04:45:37 AM UTC 24 351361224 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2373729949 Oct 09 04:45:29 AM UTC 24 Oct 09 04:45:31 AM UTC 24 360473586 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.3266474012 Oct 09 04:45:28 AM UTC 24 Oct 09 04:45:31 AM UTC 24 607913871 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.283578837 Oct 09 04:45:29 AM UTC 24 Oct 09 04:45:31 AM UTC 24 349077783 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.6996176 Oct 09 04:45:29 AM UTC 24 Oct 09 04:45:31 AM UTC 24 1057474089 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.826923404 Oct 09 04:45:29 AM UTC 24 Oct 09 04:45:31 AM UTC 24 456862081 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3370009288 Oct 09 04:45:29 AM UTC 24 Oct 09 04:45:32 AM UTC 24 983075775 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.4005167236 Oct 09 04:45:34 AM UTC 24 Oct 09 04:45:37 AM UTC 24 462001922 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2095588507 Oct 09 04:45:29 AM UTC 24 Oct 09 04:45:32 AM UTC 24 599235339 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.612269680 Oct 09 04:45:30 AM UTC 24 Oct 09 04:45:32 AM UTC 24 331925703 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3328871773 Oct 09 04:45:30 AM UTC 24 Oct 09 04:45:32 AM UTC 24 296097325 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.799589450 Oct 09 04:45:30 AM UTC 24 Oct 09 04:45:32 AM UTC 24 376172846 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.809504919 Oct 09 04:45:30 AM UTC 24 Oct 09 04:45:33 AM UTC 24 387951764 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3540105438 Oct 09 04:45:30 AM UTC 24 Oct 09 04:45:33 AM UTC 24 695095026 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.20309579 Oct 09 04:45:28 AM UTC 24 Oct 09 04:45:33 AM UTC 24 8334072305 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.1630271388 Oct 09 04:45:30 AM UTC 24 Oct 09 04:45:33 AM UTC 24 381238151 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2791562679 Oct 09 04:45:32 AM UTC 24 Oct 09 04:45:37 AM UTC 24 2835117655 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3588138702 Oct 09 04:45:29 AM UTC 24 Oct 09 04:45:33 AM UTC 24 4615079267 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1698128370 Oct 09 04:45:30 AM UTC 24 Oct 09 04:45:33 AM UTC 24 1250262442 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.4011090524 Oct 09 04:45:32 AM UTC 24 Oct 09 04:45:34 AM UTC 24 484704766 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2746864007 Oct 09 04:45:32 AM UTC 24 Oct 09 04:45:34 AM UTC 24 377238582 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.1396676401 Oct 09 04:45:32 AM UTC 24 Oct 09 04:45:34 AM UTC 24 311613700 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2526437521 Oct 09 04:45:30 AM UTC 24 Oct 09 04:45:34 AM UTC 24 1097359469 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.624627366 Oct 09 04:45:32 AM UTC 24 Oct 09 04:45:34 AM UTC 24 2308076005 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1768356925 Oct 09 04:45:32 AM UTC 24 Oct 09 04:45:34 AM UTC 24 564536701 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.841960199 Oct 09 04:45:32 AM UTC 24 Oct 09 04:45:35 AM UTC 24 560604925 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.355201382 Oct 09 04:45:33 AM UTC 24 Oct 09 04:45:35 AM UTC 24 281463027 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.149257522 Oct 09 04:45:33 AM UTC 24 Oct 09 04:45:35 AM UTC 24 697949936 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.3317611472 Oct 09 04:45:33 AM UTC 24 Oct 09 04:45:35 AM UTC 24 459249604 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1083464920 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:35 AM UTC 24 8367650533 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3378102947 Oct 09 04:45:30 AM UTC 24 Oct 09 04:45:35 AM UTC 24 8650773073 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3977918972 Oct 09 04:45:23 AM UTC 24 Oct 09 04:45:36 AM UTC 24 11966752139 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3874008147 Oct 09 04:45:33 AM UTC 24 Oct 09 04:45:36 AM UTC 24 759829801 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4015635850 Oct 09 04:45:34 AM UTC 24 Oct 09 04:45:36 AM UTC 24 545693203 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1512622436 Oct 09 04:45:33 AM UTC 24 Oct 09 04:45:36 AM UTC 24 4319726118 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1672091677 Oct 09 04:45:33 AM UTC 24 Oct 09 04:45:37 AM UTC 24 2697887712 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.385435260 Oct 09 04:45:32 AM UTC 24 Oct 09 04:45:37 AM UTC 24 4425535327 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.3747463924 Oct 09 04:45:35 AM UTC 24 Oct 09 04:45:37 AM UTC 24 359709753 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.1038100012 Oct 09 04:45:34 AM UTC 24 Oct 09 04:45:38 AM UTC 24 353923461 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.921233743 Oct 09 04:45:36 AM UTC 24 Oct 09 04:45:38 AM UTC 24 417790485 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.73863439 Oct 09 04:45:34 AM UTC 24 Oct 09 04:45:38 AM UTC 24 599666806 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2891689274 Oct 09 04:45:36 AM UTC 24 Oct 09 04:45:38 AM UTC 24 374564431 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2803717957 Oct 09 04:45:36 AM UTC 24 Oct 09 04:45:38 AM UTC 24 962644626 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.3463351205 Oct 09 04:45:36 AM UTC 24 Oct 09 04:45:38 AM UTC 24 380955273 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3384733198 Oct 09 04:45:34 AM UTC 24 Oct 09 04:45:38 AM UTC 24 4904084221 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1734052224 Oct 09 04:45:36 AM UTC 24 Oct 09 04:45:38 AM UTC 24 4570270911 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.4210113582 Oct 09 04:45:26 AM UTC 24 Oct 09 04:45:39 AM UTC 24 8120898725 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.659276787 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:39 AM UTC 24 385906262 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.194754809 Oct 09 04:45:36 AM UTC 24 Oct 09 04:45:39 AM UTC 24 511561007 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.1441948650 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:39 AM UTC 24 559956211 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.2233272634 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:39 AM UTC 24 494082651 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3217179335 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:40 AM UTC 24 412629140 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3042732866 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:40 AM UTC 24 430429418 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.3663042319 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:40 AM UTC 24 410813931 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1710992018 Oct 09 04:45:34 AM UTC 24 Oct 09 04:45:40 AM UTC 24 4930269707 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1128549235 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:40 AM UTC 24 1381263742 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.2448870955 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:40 AM UTC 24 567004052 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2878250380 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:40 AM UTC 24 573985530 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1560112279 Oct 09 04:45:27 AM UTC 24 Oct 09 04:45:40 AM UTC 24 7159375490 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.468094492 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:41 AM UTC 24 349589967 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.247092687 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:41 AM UTC 24 459320955 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.2503016075 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:41 AM UTC 24 473383868 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.3240696158 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:41 AM UTC 24 470232567 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3218624244 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:41 AM UTC 24 1583575679 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2205240130 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:41 AM UTC 24 550504782 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2937779770 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:41 AM UTC 24 329947594 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3777801854 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:41 AM UTC 24 964737305 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.3545077690 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:41 AM UTC 24 546530419 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.2536729438 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:42 AM UTC 24 534571064 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2443974594 Oct 09 04:45:40 AM UTC 24 Oct 09 04:45:42 AM UTC 24 485559663 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.2777452183 Oct 09 04:45:40 AM UTC 24 Oct 09 04:45:43 AM UTC 24 403145008 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.932323032 Oct 09 04:45:41 AM UTC 24 Oct 09 04:45:43 AM UTC 24 324777635 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.2827120943 Oct 09 04:45:41 AM UTC 24 Oct 09 04:45:43 AM UTC 24 340845669 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.4293004151 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:43 AM UTC 24 1759316213 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.803264703 Oct 09 04:45:40 AM UTC 24 Oct 09 04:45:43 AM UTC 24 382195058 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3398434975 Oct 09 04:45:40 AM UTC 24 Oct 09 04:45:43 AM UTC 24 330803565 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.155348936 Oct 09 04:45:40 AM UTC 24 Oct 09 04:45:44 AM UTC 24 987194096 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.799823484 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:44 AM UTC 24 2425057006 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.1996110157 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:44 AM UTC 24 481503094 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.3566303628 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 291067657 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.2053126648 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:44 AM UTC 24 424923514 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3660894532 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:44 AM UTC 24 426711865 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2744980953 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:44 AM UTC 24 8071029601 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3108445376 Oct 09 04:45:34 AM UTC 24 Oct 09 04:45:44 AM UTC 24 2352912381 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.2149649505 Oct 09 04:45:40 AM UTC 24 Oct 09 04:45:44 AM UTC 24 487644559 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.2117462999 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:44 AM UTC 24 335347774 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.233005112 Oct 09 04:45:40 AM UTC 24 Oct 09 04:45:44 AM UTC 24 505006135 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4237847655 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:45 AM UTC 24 1809646407 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2314643343 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:45 AM UTC 24 345390878 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3774635160 Oct 09 04:45:43 AM UTC 24 Oct 09 04:45:45 AM UTC 24 318721341 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.3815414952 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:45 AM UTC 24 310849949 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2054086003 Oct 09 04:45:43 AM UTC 24 Oct 09 04:45:45 AM UTC 24 2198054816 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.3117819007 Oct 09 04:45:43 AM UTC 24 Oct 09 04:45:45 AM UTC 24 513471338 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2017903240 Oct 09 04:45:43 AM UTC 24 Oct 09 04:45:45 AM UTC 24 1301373154 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.59953369 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:45 AM UTC 24 2310309452 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.4075716141 Oct 09 04:45:43 AM UTC 24 Oct 09 04:45:45 AM UTC 24 540712994 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2567291220 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:45 AM UTC 24 1053402648 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.4181727925 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:45 AM UTC 24 341097351 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.4252373195 Oct 09 04:45:43 AM UTC 24 Oct 09 04:45:45 AM UTC 24 436455513 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.834663995 Oct 09 04:45:41 AM UTC 24 Oct 09 04:45:46 AM UTC 24 4082380073 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.2527007909 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 417408431 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.3117148588 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:46 AM UTC 24 497358551 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.3040290785 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:46 AM UTC 24 349324547 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.4243944339 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:46 AM UTC 24 355441459 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.2392740532 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:46 AM UTC 24 503629671 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.4124602624 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:46 AM UTC 24 348358174 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.1744124001 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:46 AM UTC 24 428122836 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2156473344 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:47 AM UTC 24 593323146 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.3416594776 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:47 AM UTC 24 401673063 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1214048145 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:47 AM UTC 24 8628813876 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.976931160 Oct 09 04:45:45 AM UTC 24 Oct 09 04:45:47 AM UTC 24 412632164 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3028272755 Oct 09 04:45:39 AM UTC 24 Oct 09 04:45:47 AM UTC 24 4078237998 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.3799241315 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:47 AM UTC 24 414648111 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3863398677 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:47 AM UTC 24 418886158 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2558001355 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:47 AM UTC 24 4343241771 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.1084643098 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:47 AM UTC 24 438146693 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.716094864 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 483624426 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1938626762 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 472020657 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.1483108420 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 513744165 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.1865748870 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 432277224 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.500155336 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 472878550 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.4075489503 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 497280514 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.3789179386 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 385464582 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.2573752211 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 341575949 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.4242242593 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 288115878 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.140725292 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 503459355 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.2645939107 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 305997073 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.3049968410 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 331076514 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1942225828 Oct 09 04:45:43 AM UTC 24 Oct 09 04:45:48 AM UTC 24 8443920777 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.212748158 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:48 AM UTC 24 473886292 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.4223465014 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:49 AM UTC 24 322594917 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.746191520 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:49 AM UTC 24 307458645 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.1415746280 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:49 AM UTC 24 479922107 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.2165546659 Oct 09 04:45:47 AM UTC 24 Oct 09 04:45:49 AM UTC 24 331827624 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3956581912 Oct 09 04:45:44 AM UTC 24 Oct 09 04:45:49 AM UTC 24 2172586381 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2308821472 Oct 09 04:45:46 AM UTC 24 Oct 09 04:45:49 AM UTC 24 373241438 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.4142484613 Oct 09 04:45:47 AM UTC 24 Oct 09 04:45:49 AM UTC 24 475898359 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.305744003 Oct 09 04:45:48 AM UTC 24 Oct 09 04:45:50 AM UTC 24 443979791 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1128178225 Oct 09 04:45:40 AM UTC 24 Oct 09 04:45:50 AM UTC 24 4493253076 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.3593793012 Oct 09 04:45:48 AM UTC 24 Oct 09 04:45:50 AM UTC 24 330292344 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.1543730610 Oct 09 04:45:48 AM UTC 24 Oct 09 04:45:50 AM UTC 24 423736579 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3871631973 Oct 09 04:45:37 AM UTC 24 Oct 09 04:45:50 AM UTC 24 7782778917 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3468440488 Oct 09 04:45:42 AM UTC 24 Oct 09 04:45:51 AM UTC 24 4275122572 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1202732701 Oct 09 04:45:44 AM UTC 24 Oct 09 04:46:01 AM UTC 24 8499049644 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.327184495
Short name T5
Test name
Test status
Simulation time 460513758 ps
CPU time 1.27 seconds
Started Oct 09 05:20:17 AM UTC 24
Finished Oct 09 05:20:20 AM UTC 24
Peak memory 205436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327184495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.327184495
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.3664500839
Short name T18
Test name
Test status
Simulation time 1782398200 ps
CPU time 11.69 seconds
Started Oct 09 05:20:21 AM UTC 24
Finished Oct 09 05:20:34 AM UTC 24
Peak memory 216236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3664500839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 3.aon_timer_stress_all_with_rand_reset.3664500839
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.4118864687
Short name T25
Test name
Test status
Simulation time 3605203563 ps
CPU time 9.7 seconds
Started Oct 09 05:20:43 AM UTC 24
Finished Oct 09 05:20:54 AM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118864687 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.4118864687
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.4240164559
Short name T14
Test name
Test status
Simulation time 146240345263 ps
CPU time 11.61 seconds
Started Oct 09 05:20:14 AM UTC 24
Finished Oct 09 05:20:27 AM UTC 24
Peak memory 207076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240164559 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.4240164559
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.3090305763
Short name T11
Test name
Test status
Simulation time 4144305885 ps
CPU time 7.11 seconds
Started Oct 09 05:20:14 AM UTC 24
Finished Oct 09 05:20:23 AM UTC 24
Peak memory 234172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090305763 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3090305763
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.431922296
Short name T36
Test name
Test status
Simulation time 1288442164 ps
CPU time 0.78 seconds
Started Oct 09 04:45:22 AM UTC 24
Finished Oct 09 04:45:24 AM UTC 24
Peak memory 202160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431922296 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.431922296
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.3781143168
Short name T50
Test name
Test status
Simulation time 13788498292 ps
CPU time 45.88 seconds
Started Oct 09 05:20:17 AM UTC 24
Finished Oct 09 05:21:06 AM UTC 24
Peak memory 216304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3781143168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 2.aon_timer_stress_all_with_rand_reset.3781143168
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.2270801218
Short name T111
Test name
Test status
Simulation time 545811599218 ps
CPU time 1009.46 seconds
Started Oct 09 05:21:18 AM UTC 24
Finished Oct 09 05:38:18 AM UTC 24
Peak memory 210744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270801218 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.2270801218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/26.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3870442292
Short name T60
Test name
Test status
Simulation time 661304864 ps
CPU time 1.26 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:28 AM UTC 24
Peak memory 201972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870442292 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.3870442292
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.3797508425
Short name T96
Test name
Test status
Simulation time 11359141416 ps
CPU time 30.26 seconds
Started Oct 09 05:20:40 AM UTC 24
Finished Oct 09 05:21:12 AM UTC 24
Peak memory 222940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3797508425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.aon_timer_stress_all_with_rand_reset.3797508425
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.1669422995
Short name T103
Test name
Test status
Simulation time 273271509890 ps
CPU time 101.53 seconds
Started Oct 09 05:21:39 AM UTC 24
Finished Oct 09 05:23:23 AM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669422995 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.1669422995
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/34.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.1035733321
Short name T131
Test name
Test status
Simulation time 296539831633 ps
CPU time 546.12 seconds
Started Oct 09 05:22:13 AM UTC 24
Finished Oct 09 05:31:27 AM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035733321 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.1035733321
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/47.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.2851109097
Short name T125
Test name
Test status
Simulation time 112911782629 ps
CPU time 56.19 seconds
Started Oct 09 05:21:52 AM UTC 24
Finished Oct 09 05:22:50 AM UTC 24
Peak memory 207120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851109097 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.2851109097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/39.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.417999736
Short name T105
Test name
Test status
Simulation time 16759665906 ps
CPU time 37.78 seconds
Started Oct 09 05:20:49 AM UTC 24
Finished Oct 09 05:21:28 AM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=417999736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 14.aon_timer_stress_all_with_rand_reset.417999736
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.3926163379
Short name T123
Test name
Test status
Simulation time 335301795096 ps
CPU time 573.43 seconds
Started Oct 09 05:20:29 AM UTC 24
Finished Oct 09 05:30:09 AM UTC 24
Peak memory 210524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926163379 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.3926163379
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.643395046
Short name T109
Test name
Test status
Simulation time 9157961835 ps
CPU time 14.33 seconds
Started Oct 09 05:21:05 AM UTC 24
Finished Oct 09 05:21:21 AM UTC 24
Peak memory 207288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643395046 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.643395046
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/21.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.1639707980
Short name T127
Test name
Test status
Simulation time 116296324982 ps
CPU time 215.08 seconds
Started Oct 09 05:21:25 AM UTC 24
Finished Oct 09 05:25:03 AM UTC 24
Peak memory 207256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639707980 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.1639707980
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/29.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.2098354614
Short name T100
Test name
Test status
Simulation time 163029352515 ps
CPU time 149.33 seconds
Started Oct 09 05:20:23 AM UTC 24
Finished Oct 09 05:22:55 AM UTC 24
Peak memory 207144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098354614 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.2098354614
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.1998296806
Short name T135
Test name
Test status
Simulation time 29946805570 ps
CPU time 22.91 seconds
Started Oct 09 05:22:06 AM UTC 24
Finished Oct 09 05:22:31 AM UTC 24
Peak memory 207200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998296806 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.1998296806
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/45.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.2472020272
Short name T143
Test name
Test status
Simulation time 344628480142 ps
CPU time 325.58 seconds
Started Oct 09 05:20:20 AM UTC 24
Finished Oct 09 05:25:51 AM UTC 24
Peak memory 207120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472020272 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.2472020272
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all.3571469264
Short name T117
Test name
Test status
Simulation time 117369435779 ps
CPU time 39.53 seconds
Started Oct 09 05:21:48 AM UTC 24
Finished Oct 09 05:22:29 AM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571469264 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.3571469264
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/37.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.364555081
Short name T149
Test name
Test status
Simulation time 58871004123 ps
CPU time 103.12 seconds
Started Oct 09 05:21:43 AM UTC 24
Finished Oct 09 05:23:28 AM UTC 24
Peak memory 207256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364555081 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.364555081
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/35.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2021685346
Short name T40
Test name
Test status
Simulation time 7708659544 ps
CPU time 4.04 seconds
Started Oct 09 04:45:24 AM UTC 24
Finished Oct 09 04:45:29 AM UTC 24
Peak memory 207392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021685346 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.2021685346
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.1229914245
Short name T137
Test name
Test status
Simulation time 135232112047 ps
CPU time 59.88 seconds
Started Oct 09 05:20:51 AM UTC 24
Finished Oct 09 05:21:53 AM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229914245 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.1229914245
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.278124055
Short name T161
Test name
Test status
Simulation time 91302832741 ps
CPU time 48.4 seconds
Started Oct 09 05:20:53 AM UTC 24
Finished Oct 09 05:21:42 AM UTC 24
Peak memory 207120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278124055 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.278124055
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all_with_rand_reset.1279882985
Short name T152
Test name
Test status
Simulation time 16828514959 ps
CPU time 17.77 seconds
Started Oct 09 05:22:12 AM UTC 24
Finished Oct 09 05:22:31 AM UTC 24
Peak memory 207396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1279882985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 47.aon_timer_stress_all_with_rand_reset.1279882985
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.456057537
Short name T24
Test name
Test status
Simulation time 79163784597 ps
CPU time 31.14 seconds
Started Oct 09 05:20:17 AM UTC 24
Finished Oct 09 05:20:50 AM UTC 24
Peak memory 207192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456057537 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.456057537
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.3557217912
Short name T168
Test name
Test status
Simulation time 12264083620 ps
CPU time 30.88 seconds
Started Oct 09 05:21:13 AM UTC 24
Finished Oct 09 05:21:45 AM UTC 24
Peak memory 222888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3557217912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 24.aon_timer_stress_all_with_rand_reset.3557217912
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.256499028
Short name T90
Test name
Test status
Simulation time 3435767631 ps
CPU time 19.36 seconds
Started Oct 09 05:22:22 AM UTC 24
Finished Oct 09 05:22:42 AM UTC 24
Peak memory 222808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=256499028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 49.aon_timer_stress_all_with_rand_reset.256499028
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.3317963025
Short name T107
Test name
Test status
Simulation time 140771120366 ps
CPU time 110.28 seconds
Started Oct 09 05:21:35 AM UTC 24
Finished Oct 09 05:23:27 AM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317963025 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.3317963025
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/33.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.3532104118
Short name T150
Test name
Test status
Simulation time 94153103739 ps
CPU time 34.33 seconds
Started Oct 09 05:22:01 AM UTC 24
Finished Oct 09 05:22:37 AM UTC 24
Peak memory 207152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532104118 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.3532104118
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/42.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.2039716266
Short name T84
Test name
Test status
Simulation time 12757610824 ps
CPU time 26.52 seconds
Started Oct 09 05:20:57 AM UTC 24
Finished Oct 09 05:21:25 AM UTC 24
Peak memory 216420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2039716266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 18.aon_timer_stress_all_with_rand_reset.2039716266
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all_with_rand_reset.2982290083
Short name T110
Test name
Test status
Simulation time 7084750325 ps
CPU time 24.76 seconds
Started Oct 09 05:21:35 AM UTC 24
Finished Oct 09 05:22:01 AM UTC 24
Peak memory 207472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2982290083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 33.aon_timer_stress_all_with_rand_reset.2982290083
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.828379968
Short name T129
Test name
Test status
Simulation time 170743526554 ps
CPU time 313.21 seconds
Started Oct 09 05:21:30 AM UTC 24
Finished Oct 09 05:26:47 AM UTC 24
Peak memory 207116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828379968 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.828379968
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/31.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.1583148406
Short name T56
Test name
Test status
Simulation time 444785379 ps
CPU time 1.68 seconds
Started Oct 09 05:20:52 AM UTC 24
Finished Oct 09 05:20:55 AM UTC 24
Peak memory 205320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583148406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1583148406
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.229791797
Short name T128
Test name
Test status
Simulation time 11452119293 ps
CPU time 33.02 seconds
Started Oct 09 05:21:47 AM UTC 24
Finished Oct 09 05:22:21 AM UTC 24
Peak memory 207388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=229791797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 37.aon_timer_stress_all_with_rand_reset.229791797
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.2103410473
Short name T101
Test name
Test status
Simulation time 380913322595 ps
CPU time 437.78 seconds
Started Oct 09 05:21:50 AM UTC 24
Finished Oct 09 05:29:14 AM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103410473 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.2103410473
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/38.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.2019577886
Short name T136
Test name
Test status
Simulation time 227739371862 ps
CPU time 58.33 seconds
Started Oct 09 05:20:49 AM UTC 24
Finished Oct 09 05:21:49 AM UTC 24
Peak memory 207192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019577886 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.2019577886
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.317442440
Short name T120
Test name
Test status
Simulation time 187326848675 ps
CPU time 95.64 seconds
Started Oct 09 05:20:57 AM UTC 24
Finished Oct 09 05:22:35 AM UTC 24
Peak memory 207160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317442440 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.317442440
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.744383610
Short name T139
Test name
Test status
Simulation time 335953069938 ps
CPU time 65.89 seconds
Started Oct 09 05:21:27 AM UTC 24
Finished Oct 09 05:22:35 AM UTC 24
Peak memory 207120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744383610 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.744383610
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/30.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.3937548157
Short name T108
Test name
Test status
Simulation time 187666967355 ps
CPU time 292.01 seconds
Started Oct 09 05:22:10 AM UTC 24
Finished Oct 09 05:27:06 AM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937548157 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.3937548157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/46.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.2370867762
Short name T122
Test name
Test status
Simulation time 89362426131 ps
CPU time 32.77 seconds
Started Oct 09 05:22:20 AM UTC 24
Finished Oct 09 05:22:54 AM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370867762 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.2370867762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/48.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.2230664754
Short name T166
Test name
Test status
Simulation time 15736916925 ps
CPU time 51.51 seconds
Started Oct 09 05:20:32 AM UTC 24
Finished Oct 09 05:21:25 AM UTC 24
Peak memory 207532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2230664754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 7.aon_timer_stress_all_with_rand_reset.2230664754
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.933508444
Short name T145
Test name
Test status
Simulation time 108963212219 ps
CPU time 195.31 seconds
Started Oct 09 05:21:01 AM UTC 24
Finished Oct 09 05:24:19 AM UTC 24
Peak memory 207176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933508444 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.933508444
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/20.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.73323148
Short name T104
Test name
Test status
Simulation time 4287792215 ps
CPU time 37.09 seconds
Started Oct 09 05:20:51 AM UTC 24
Finished Oct 09 05:21:30 AM UTC 24
Peak memory 207396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=73323148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 15.aon_timer_stress_all_with_rand_reset.73323148
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.2205156987
Short name T130
Test name
Test status
Simulation time 3564445355 ps
CPU time 23.83 seconds
Started Oct 09 05:21:22 AM UTC 24
Finished Oct 09 05:21:47 AM UTC 24
Peak memory 222984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2205156987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 28.aon_timer_stress_all_with_rand_reset.2205156987
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.3536401136
Short name T178
Test name
Test status
Simulation time 27588225069 ps
CPU time 26.75 seconds
Started Oct 09 05:22:01 AM UTC 24
Finished Oct 09 05:22:29 AM UTC 24
Peak memory 223612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3536401136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 42.aon_timer_stress_all_with_rand_reset.3536401136
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.569184097
Short name T142
Test name
Test status
Simulation time 2160004889 ps
CPU time 19.18 seconds
Started Oct 09 05:20:58 AM UTC 24
Finished Oct 09 05:21:19 AM UTC 24
Peak memory 207512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=569184097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 19.aon_timer_stress_all_with_rand_reset.569184097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.3822344870
Short name T140
Test name
Test status
Simulation time 47473642094 ps
CPU time 73.28 seconds
Started Oct 09 05:21:31 AM UTC 24
Finished Oct 09 05:22:47 AM UTC 24
Peak memory 207292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822344870 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.3822344870
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/32.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.2415377425
Short name T189
Test name
Test status
Simulation time 285176478221 ps
CPU time 518.72 seconds
Started Oct 09 05:20:47 AM UTC 24
Finished Oct 09 05:29:33 AM UTC 24
Peak memory 210456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415377425 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.2415377425
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.1766170011
Short name T88
Test name
Test status
Simulation time 5653733277 ps
CPU time 47.15 seconds
Started Oct 09 05:21:16 AM UTC 24
Finished Oct 09 05:22:05 AM UTC 24
Peak memory 223192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1766170011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 25.aon_timer_stress_all_with_rand_reset.1766170011
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.2941037421
Short name T19
Test name
Test status
Simulation time 3060851326 ps
CPU time 17.09 seconds
Started Oct 09 05:20:17 AM UTC 24
Finished Oct 09 05:20:36 AM UTC 24
Peak memory 216488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2941037421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 1.aon_timer_stress_all_with_rand_reset.2941037421
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.3831644446
Short name T89
Test name
Test status
Simulation time 8629679011 ps
CPU time 19.98 seconds
Started Oct 09 05:22:03 AM UTC 24
Finished Oct 09 05:22:24 AM UTC 24
Peak memory 222752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3831644446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 43.aon_timer_stress_all_with_rand_reset.3831644446
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.1037870411
Short name T134
Test name
Test status
Simulation time 46694976655 ps
CPU time 64.15 seconds
Started Oct 09 05:21:00 AM UTC 24
Finished Oct 09 05:22:05 AM UTC 24
Peak memory 207200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037870411 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.1037870411
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.3276508058
Short name T167
Test name
Test status
Simulation time 8245031960 ps
CPU time 27.86 seconds
Started Oct 09 05:21:50 AM UTC 24
Finished Oct 09 05:22:20 AM UTC 24
Peak memory 222824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3276508058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 38.aon_timer_stress_all_with_rand_reset.3276508058
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.610385386
Short name T35
Test name
Test status
Simulation time 19707755585 ps
CPU time 22.7 seconds
Started Oct 09 05:20:23 AM UTC 24
Finished Oct 09 05:20:47 AM UTC 24
Peak memory 222880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=610385386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 4.aon_timer_stress_all_with_rand_reset.610385386
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.2510745905
Short name T7
Test name
Test status
Simulation time 586807604 ps
CPU time 2.06 seconds
Started Oct 09 05:20:17 AM UTC 24
Finished Oct 09 05:20:21 AM UTC 24
Peak memory 205856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510745905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2510745905
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.501958081
Short name T44
Test name
Test status
Simulation time 3043068075 ps
CPU time 1.35 seconds
Started Oct 09 04:45:23 AM UTC 24
Finished Oct 09 04:45:26 AM UTC 24
Peak memory 204140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501958081 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.501958081
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.1340489047
Short name T86
Test name
Test status
Simulation time 4268114645 ps
CPU time 30.7 seconds
Started Oct 09 05:21:25 AM UTC 24
Finished Oct 09 05:21:57 AM UTC 24
Peak memory 216232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1340489047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.aon_timer_stress_all_with_rand_reset.1340489047
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.1190154116
Short name T185
Test name
Test status
Simulation time 15122035419 ps
CPU time 30.99 seconds
Started Oct 09 05:21:30 AM UTC 24
Finished Oct 09 05:22:02 AM UTC 24
Peak memory 220528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1190154116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 31.aon_timer_stress_all_with_rand_reset.1190154116
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.660891637
Short name T126
Test name
Test status
Simulation time 17846074032 ps
CPU time 52.61 seconds
Started Oct 09 05:22:04 AM UTC 24
Finished Oct 09 05:22:59 AM UTC 24
Peak memory 216496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=660891637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 44.aon_timer_stress_all_with_rand_reset.660891637
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.761852534
Short name T47
Test name
Test status
Simulation time 1990564486 ps
CPU time 16.7 seconds
Started Oct 09 05:20:36 AM UTC 24
Finished Oct 09 05:20:54 AM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=761852534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 9.aon_timer_stress_all_with_rand_reset.761852534
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.428297530
Short name T171
Test name
Test status
Simulation time 310463995426 ps
CPU time 275.23 seconds
Started Oct 09 05:20:23 AM UTC 24
Finished Oct 09 05:25:03 AM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428297530 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.428297530
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.2481093670
Short name T204
Test name
Test status
Simulation time 5553180526 ps
CPU time 37.39 seconds
Started Oct 09 05:22:06 AM UTC 24
Finished Oct 09 05:22:45 AM UTC 24
Peak memory 216292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2481093670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 45.aon_timer_stress_all_with_rand_reset.2481093670
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.3351653589
Short name T158
Test name
Test status
Simulation time 1697671685 ps
CPU time 14.98 seconds
Started Oct 09 05:22:17 AM UTC 24
Finished Oct 09 05:22:34 AM UTC 24
Peak memory 207268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3351653589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 48.aon_timer_stress_all_with_rand_reset.3351653589
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.716586344
Short name T173
Test name
Test status
Simulation time 89226517463 ps
CPU time 66.52 seconds
Started Oct 09 05:20:27 AM UTC 24
Finished Oct 09 05:21:35 AM UTC 24
Peak memory 207120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716586344 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.716586344
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.2507047911
Short name T138
Test name
Test status
Simulation time 163275865689 ps
CPU time 43.02 seconds
Started Oct 09 05:20:40 AM UTC 24
Finished Oct 09 05:21:25 AM UTC 24
Peak memory 207200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507047911 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.2507047911
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.4021056628
Short name T147
Test name
Test status
Simulation time 469109852 ps
CPU time 0.98 seconds
Started Oct 09 05:20:46 AM UTC 24
Finished Oct 09 05:20:48 AM UTC 24
Peak memory 205564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021056628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.4021056628
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.3028174715
Short name T98
Test name
Test status
Simulation time 476963076 ps
CPU time 1.31 seconds
Started Oct 09 05:21:10 AM UTC 24
Finished Oct 09 05:21:12 AM UTC 24
Peak memory 205200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028174715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3028174715
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/23.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.3217813350
Short name T112
Test name
Test status
Simulation time 528333663 ps
CPU time 1.37 seconds
Started Oct 09 05:22:04 AM UTC 24
Finished Oct 09 05:22:07 AM UTC 24
Peak memory 205736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217813350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3217813350
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/44.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.3670187457
Short name T169
Test name
Test status
Simulation time 468012919 ps
CPU time 1.11 seconds
Started Oct 09 05:22:21 AM UTC 24
Finished Oct 09 05:22:23 AM UTC 24
Peak memory 205732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670187457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3670187457
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/49.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.4079107781
Short name T30
Test name
Test status
Simulation time 512446471 ps
CPU time 2.1 seconds
Started Oct 09 05:20:32 AM UTC 24
Finished Oct 09 05:20:35 AM UTC 24
Peak memory 205920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079107781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.4079107781
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.538812273
Short name T121
Test name
Test status
Simulation time 424995264 ps
CPU time 1.72 seconds
Started Oct 09 05:21:04 AM UTC 24
Finished Oct 09 05:21:06 AM UTC 24
Peak memory 205736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538812273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.538812273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/21.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.3083760040
Short name T114
Test name
Test status
Simulation time 579569447 ps
CPU time 0.96 seconds
Started Oct 09 05:21:33 AM UTC 24
Finished Oct 09 05:21:36 AM UTC 24
Peak memory 205736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083760040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3083760040
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/33.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.543371276
Short name T198
Test name
Test status
Simulation time 2911323945 ps
CPU time 28.53 seconds
Started Oct 09 05:21:56 AM UTC 24
Finished Oct 09 05:22:26 AM UTC 24
Peak memory 207372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=543371276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 41.aon_timer_stress_all_with_rand_reset.543371276
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.2409973871
Short name T154
Test name
Test status
Simulation time 507442434 ps
CPU time 1.21 seconds
Started Oct 09 05:22:03 AM UTC 24
Finished Oct 09 05:22:05 AM UTC 24
Peak memory 205196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409973871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2409973871
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/43.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all_with_rand_reset.3722171280
Short name T199
Test name
Test status
Simulation time 3253585766 ps
CPU time 24.53 seconds
Started Oct 09 05:22:08 AM UTC 24
Finished Oct 09 05:22:34 AM UTC 24
Peak memory 207464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3722171280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 46.aon_timer_stress_all_with_rand_reset.3722171280
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.129070139
Short name T187
Test name
Test status
Simulation time 181659759037 ps
CPU time 73.44 seconds
Started Oct 09 05:20:35 AM UTC 24
Finished Oct 09 05:21:50 AM UTC 24
Peak memory 207092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129070139 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.129070139
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.3506823893
Short name T133
Test name
Test status
Simulation time 447238288 ps
CPU time 1.14 seconds
Started Oct 09 05:20:49 AM UTC 24
Finished Oct 09 05:20:52 AM UTC 24
Peak memory 205796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506823893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3506823893
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.122197872
Short name T151
Test name
Test status
Simulation time 533241009 ps
CPU time 2.32 seconds
Started Oct 09 05:20:58 AM UTC 24
Finished Oct 09 05:21:02 AM UTC 24
Peak memory 205720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122197872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.122197872
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.3324421106
Short name T194
Test name
Test status
Simulation time 386278011254 ps
CPU time 146.01 seconds
Started Oct 09 05:21:11 AM UTC 24
Finished Oct 09 05:23:40 AM UTC 24
Peak memory 207176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324421106 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.3324421106
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/23.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.442055767
Short name T160
Test name
Test status
Simulation time 625268816 ps
CPU time 1.02 seconds
Started Oct 09 05:21:13 AM UTC 24
Finished Oct 09 05:21:15 AM UTC 24
Peak memory 205796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442055767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.442055767
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/24.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.2881547072
Short name T164
Test name
Test status
Simulation time 129956654699 ps
CPU time 41.24 seconds
Started Oct 09 05:21:20 AM UTC 24
Finished Oct 09 05:22:03 AM UTC 24
Peak memory 207200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881547072 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.2881547072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/27.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.2317500388
Short name T175
Test name
Test status
Simulation time 550491813 ps
CPU time 2.36 seconds
Started Oct 09 05:21:43 AM UTC 24
Finished Oct 09 05:21:47 AM UTC 24
Peak memory 205280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317500388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2317500388
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/36.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.755390041
Short name T182
Test name
Test status
Simulation time 416647616626 ps
CPU time 185.45 seconds
Started Oct 09 05:21:46 AM UTC 24
Finished Oct 09 05:24:54 AM UTC 24
Peak memory 207220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755390041 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.755390041
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/36.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all_with_rand_reset.2875279855
Short name T119
Test name
Test status
Simulation time 5772591333 ps
CPU time 45.67 seconds
Started Oct 09 05:21:44 AM UTC 24
Finished Oct 09 05:22:32 AM UTC 24
Peak memory 216232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2875279855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 36.aon_timer_stress_all_with_rand_reset.2875279855
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.326994879
Short name T116
Test name
Test status
Simulation time 556335564 ps
CPU time 1.91 seconds
Started Oct 09 05:22:08 AM UTC 24
Finished Oct 09 05:22:11 AM UTC 24
Peak memory 205796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326994879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.326994879
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/46.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.2796110047
Short name T57
Test name
Test status
Simulation time 30073558446 ps
CPU time 10.23 seconds
Started Oct 09 05:20:45 AM UTC 24
Finished Oct 09 05:20:56 AM UTC 24
Peak memory 206960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796110047 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.2796110047
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.2376749513
Short name T155
Test name
Test status
Simulation time 580711477 ps
CPU time 1.45 seconds
Started Oct 09 05:20:57 AM UTC 24
Finished Oct 09 05:20:59 AM UTC 24
Peak memory 205736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376749513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2376749513
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.2914832123
Short name T159
Test name
Test status
Simulation time 2131192963 ps
CPU time 13.61 seconds
Started Oct 09 05:21:01 AM UTC 24
Finished Oct 09 05:21:16 AM UTC 24
Peak memory 223084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2914832123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 20.aon_timer_stress_all_with_rand_reset.2914832123
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.547959179
Short name T85
Test name
Test status
Simulation time 10467613801 ps
CPU time 20.93 seconds
Started Oct 09 05:21:11 AM UTC 24
Finished Oct 09 05:21:34 AM UTC 24
Peak memory 222700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=547959179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.aon_timer_stress_all_with_rand_reset.547959179
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.2947207632
Short name T190
Test name
Test status
Simulation time 265107832917 ps
CPU time 100.25 seconds
Started Oct 09 05:21:13 AM UTC 24
Finished Oct 09 05:22:56 AM UTC 24
Peak memory 207128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947207632 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.2947207632
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/24.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.1297970304
Short name T197
Test name
Test status
Simulation time 2967987237 ps
CPU time 25.86 seconds
Started Oct 09 05:21:17 AM UTC 24
Finished Oct 09 05:21:45 AM UTC 24
Peak memory 216288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1297970304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 26.aon_timer_stress_all_with_rand_reset.1297970304
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.6001108
Short name T165
Test name
Test status
Simulation time 174445621860 ps
CPU time 79.73 seconds
Started Oct 09 05:21:23 AM UTC 24
Finished Oct 09 05:22:45 AM UTC 24
Peak memory 207200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6001108 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.6001108
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/28.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.2716844697
Short name T148
Test name
Test status
Simulation time 458073203 ps
CPU time 1 seconds
Started Oct 09 05:21:23 AM UTC 24
Finished Oct 09 05:21:26 AM UTC 24
Peak memory 205200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716844697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2716844697
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/29.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.2709406736
Short name T172
Test name
Test status
Simulation time 574607612 ps
CPU time 1.78 seconds
Started Oct 09 05:21:40 AM UTC 24
Finished Oct 09 05:21:43 AM UTC 24
Peak memory 205796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709406736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2709406736
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/35.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.923761050
Short name T132
Test name
Test status
Simulation time 360015188 ps
CPU time 2.07 seconds
Started Oct 09 05:21:49 AM UTC 24
Finished Oct 09 05:21:52 AM UTC 24
Peak memory 205908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923761050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.923761050
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/38.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.3559534035
Short name T34
Test name
Test status
Simulation time 397542769 ps
CPU time 1.65 seconds
Started Oct 09 05:20:27 AM UTC 24
Finished Oct 09 05:20:30 AM UTC 24
Peak memory 205732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559534035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3559534035
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.358798876
Short name T144
Test name
Test status
Simulation time 17667505283 ps
CPU time 19.6 seconds
Started Oct 09 05:21:05 AM UTC 24
Finished Oct 09 05:21:26 AM UTC 24
Peak memory 207376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=358798876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 21.aon_timer_stress_all_with_rand_reset.358798876
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.2921173046
Short name T102
Test name
Test status
Simulation time 416369187 ps
CPU time 1.86 seconds
Started Oct 09 05:21:16 AM UTC 24
Finished Oct 09 05:21:19 AM UTC 24
Peak memory 205796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921173046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2921173046
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/25.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.2141907397
Short name T162
Test name
Test status
Simulation time 436191704 ps
CPU time 1.57 seconds
Started Oct 09 05:21:20 AM UTC 24
Finished Oct 09 05:21:22 AM UTC 24
Peak memory 205796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141907397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2141907397
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/27.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.1948623617
Short name T118
Test name
Test status
Simulation time 490612820 ps
CPU time 2.12 seconds
Started Oct 09 05:21:26 AM UTC 24
Finished Oct 09 05:21:29 AM UTC 24
Peak memory 205932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948623617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1948623617
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/30.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.4249511679
Short name T181
Test name
Test status
Simulation time 3741223587 ps
CPU time 18.61 seconds
Started Oct 09 05:21:26 AM UTC 24
Finished Oct 09 05:21:46 AM UTC 24
Peak memory 207600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4249511679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.aon_timer_stress_all_with_rand_reset.4249511679
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.2783996771
Short name T87
Test name
Test status
Simulation time 4357092444 ps
CPU time 9.47 seconds
Started Oct 09 05:21:52 AM UTC 24
Finished Oct 09 05:22:02 AM UTC 24
Peak memory 218256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2783996771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 39.aon_timer_stress_all_with_rand_reset.2783996771
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.4149795720
Short name T170
Test name
Test status
Simulation time 543590477 ps
CPU time 0.97 seconds
Started Oct 09 05:22:01 AM UTC 24
Finished Oct 09 05:22:03 AM UTC 24
Peak memory 205796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149795720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.4149795720
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/42.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.3252648016
Short name T157
Test name
Test status
Simulation time 72315089556 ps
CPU time 33.88 seconds
Started Oct 09 05:22:03 AM UTC 24
Finished Oct 09 05:22:39 AM UTC 24
Peak memory 207200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252648016 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.3252648016
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/43.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.3405214573
Short name T146
Test name
Test status
Simulation time 90447802423 ps
CPU time 170.98 seconds
Started Oct 09 05:22:06 AM UTC 24
Finished Oct 09 05:25:00 AM UTC 24
Peak memory 207200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405214573 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.3405214573
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/44.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.2952070859
Short name T48
Test name
Test status
Simulation time 3280627741 ps
CPU time 29.18 seconds
Started Oct 09 05:20:27 AM UTC 24
Finished Oct 09 05:20:58 AM UTC 24
Peak memory 216364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2952070859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 5.aon_timer_stress_all_with_rand_reset.2952070859
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.1021773833
Short name T93
Test name
Test status
Simulation time 3952168870 ps
CPU time 25.07 seconds
Started Oct 09 05:20:43 AM UTC 24
Finished Oct 09 05:21:09 AM UTC 24
Peak memory 207392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1021773833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 11.aon_timer_stress_all_with_rand_reset.1021773833
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.2890993213
Short name T49
Test name
Test status
Simulation time 2238448425 ps
CPU time 13.9 seconds
Started Oct 09 05:20:43 AM UTC 24
Finished Oct 09 05:20:58 AM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2890993213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 12.aon_timer_stress_all_with_rand_reset.2890993213
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.2810865816
Short name T124
Test name
Test status
Simulation time 539342446 ps
CPU time 1.28 seconds
Started Oct 09 05:20:49 AM UTC 24
Finished Oct 09 05:20:51 AM UTC 24
Peak memory 205736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810865816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2810865816
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.3015607494
Short name T174
Test name
Test status
Simulation time 2475622519 ps
CPU time 20.65 seconds
Started Oct 09 05:20:55 AM UTC 24
Finished Oct 09 05:21:17 AM UTC 24
Peak memory 223684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3015607494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 17.aon_timer_stress_all_with_rand_reset.3015607494
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.2281846914
Short name T83
Test name
Test status
Simulation time 1569974759 ps
CPU time 9.06 seconds
Started Oct 09 05:21:08 AM UTC 24
Finished Oct 09 05:21:18 AM UTC 24
Peak memory 216156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2281846914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 22.aon_timer_stress_all_with_rand_reset.2281846914
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all.1358695532
Short name T115
Test name
Test status
Simulation time 280337078055 ps
CPU time 261.01 seconds
Started Oct 09 05:21:16 AM UTC 24
Finished Oct 09 05:25:41 AM UTC 24
Peak memory 207264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358695532 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.1358695532
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/25.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.2012358340
Short name T192
Test name
Test status
Simulation time 13185523961 ps
CPU time 28.99 seconds
Started Oct 09 05:21:20 AM UTC 24
Finished Oct 09 05:21:50 AM UTC 24
Peak memory 207380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2012358340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 27.aon_timer_stress_all_with_rand_reset.2012358340
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.2790724256
Short name T183
Test name
Test status
Simulation time 153611192889 ps
CPU time 182.64 seconds
Started Oct 09 05:22:23 AM UTC 24
Finished Oct 09 05:25:29 AM UTC 24
Peak memory 207320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790724256 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.2790724256
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/49.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.3771906096
Short name T32
Test name
Test status
Simulation time 550521504 ps
CPU time 2.67 seconds
Started Oct 09 05:20:43 AM UTC 24
Finished Oct 09 05:20:46 AM UTC 24
Peak memory 205152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771906096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3771906096
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.1845724730
Short name T200
Test name
Test status
Simulation time 339656551016 ps
CPU time 585.15 seconds
Started Oct 09 05:21:08 AM UTC 24
Finished Oct 09 05:31:00 AM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845724730 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.1845724730
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/22.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.2588505141
Short name T195
Test name
Test status
Simulation time 493818481 ps
CPU time 1.25 seconds
Started Oct 09 05:21:37 AM UTC 24
Finished Oct 09 05:21:39 AM UTC 24
Peak memory 203888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588505141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2588505141
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/34.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.1006842731
Short name T163
Test name
Test status
Simulation time 579267944 ps
CPU time 1.33 seconds
Started Oct 09 05:21:52 AM UTC 24
Finished Oct 09 05:21:54 AM UTC 24
Peak memory 205320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006842731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1006842731
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/39.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.928253257
Short name T180
Test name
Test status
Simulation time 81499750279 ps
CPU time 137.95 seconds
Started Oct 09 05:21:55 AM UTC 24
Finished Oct 09 05:24:16 AM UTC 24
Peak memory 207192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928253257 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.928253257
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/40.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.989518439
Short name T141
Test name
Test status
Simulation time 1265895200 ps
CPU time 9.45 seconds
Started Oct 09 05:21:55 AM UTC 24
Finished Oct 09 05:22:06 AM UTC 24
Peak memory 223556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=989518439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 40.aon_timer_stress_all_with_rand_reset.989518439
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.1681837734
Short name T153
Test name
Test status
Simulation time 579303870 ps
CPU time 2.52 seconds
Started Oct 09 05:22:06 AM UTC 24
Finished Oct 09 05:22:10 AM UTC 24
Peak memory 205916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681837734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1681837734
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/45.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.1247171834
Short name T15
Test name
Test status
Simulation time 391892684 ps
CPU time 1.22 seconds
Started Oct 09 05:20:25 AM UTC 24
Finished Oct 09 05:20:27 AM UTC 24
Peak memory 203884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247171834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1247171834
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.518002941
Short name T206
Test name
Test status
Simulation time 90916716800 ps
CPU time 167.33 seconds
Started Oct 09 05:20:36 AM UTC 24
Finished Oct 09 05:23:27 AM UTC 24
Peak memory 207116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518002941 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.518002941
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.4230970566
Short name T205
Test name
Test status
Simulation time 620396459 ps
CPU time 0.88 seconds
Started Oct 09 05:20:43 AM UTC 24
Finished Oct 09 05:20:45 AM UTC 24
Peak memory 205424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230970566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.4230970566
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.1644484188
Short name T91
Test name
Test status
Simulation time 33202342738 ps
CPU time 19.7 seconds
Started Oct 09 05:20:47 AM UTC 24
Finished Oct 09 05:21:08 AM UTC 24
Peak memory 207592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1644484188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 13.aon_timer_stress_all_with_rand_reset.1644484188
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.2799807515
Short name T51
Test name
Test status
Simulation time 11695966827 ps
CPU time 13.08 seconds
Started Oct 09 05:20:52 AM UTC 24
Finished Oct 09 05:21:07 AM UTC 24
Peak memory 216296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2799807515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 16.aon_timer_stress_all_with_rand_reset.2799807515
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.3830628271
Short name T6
Test name
Test status
Simulation time 476847376 ps
CPU time 1.29 seconds
Started Oct 09 05:20:17 AM UTC 24
Finished Oct 09 05:20:20 AM UTC 24
Peak memory 203884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830628271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3830628271
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.46654207
Short name T8
Test name
Test status
Simulation time 417204158 ps
CPU time 1.02 seconds
Started Oct 09 05:20:21 AM UTC 24
Finished Oct 09 05:20:23 AM UTC 24
Peak memory 205760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46654207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.46654207
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.132649270
Short name T156
Test name
Test status
Simulation time 545525535 ps
CPU time 2.25 seconds
Started Oct 09 05:21:30 AM UTC 24
Finished Oct 09 05:21:33 AM UTC 24
Peak memory 205852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132649270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.132649270
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/31.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.3654725654
Short name T113
Test name
Test status
Simulation time 384356684 ps
CPU time 1.39 seconds
Started Oct 09 05:21:30 AM UTC 24
Finished Oct 09 05:21:33 AM UTC 24
Peak memory 205792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654725654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3654725654
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/32.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.1464515079
Short name T191
Test name
Test status
Simulation time 497153951 ps
CPU time 2.4 seconds
Started Oct 09 05:21:47 AM UTC 24
Finished Oct 09 05:21:50 AM UTC 24
Peak memory 205712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464515079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1464515079
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/37.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.1045548498
Short name T196
Test name
Test status
Simulation time 520171503 ps
CPU time 2.62 seconds
Started Oct 09 05:21:56 AM UTC 24
Finished Oct 09 05:22:00 AM UTC 24
Peak memory 205892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045548498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1045548498
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/41.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.3364395604
Short name T203
Test name
Test status
Simulation time 429395876 ps
CPU time 2.01 seconds
Started Oct 09 05:22:15 AM UTC 24
Finished Oct 09 05:22:19 AM UTC 24
Peak memory 203888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364395604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3364395604
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/48.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3468440488
Short name T426
Test name
Test status
Simulation time 4275122572 ps
CPU time 7.5 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:51 AM UTC 24
Peak memory 206716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468440488 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.3468440488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1512622436
Short name T209
Test name
Test status
Simulation time 4319726118 ps
CPU time 2.3 seconds
Started Oct 09 04:45:33 AM UTC 24
Finished Oct 09 04:45:36 AM UTC 24
Peak memory 206388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512622436 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.1512622436
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.1546292824
Short name T202
Test name
Test status
Simulation time 588678211 ps
CPU time 1.86 seconds
Started Oct 09 05:20:55 AM UTC 24
Finished Oct 09 05:20:58 AM UTC 24
Peak memory 205320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546292824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1546292824
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.1226218923
Short name T95
Test name
Test status
Simulation time 561337737 ps
CPU time 1.54 seconds
Started Oct 09 05:21:08 AM UTC 24
Finished Oct 09 05:21:11 AM UTC 24
Peak memory 203888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226218923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1226218923
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/22.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.1018198622
Short name T188
Test name
Test status
Simulation time 551630725 ps
CPU time 1.24 seconds
Started Oct 09 05:21:16 AM UTC 24
Finished Oct 09 05:21:19 AM UTC 24
Peak memory 205436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018198622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1018198622
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/26.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.2026502398
Short name T207
Test name
Test status
Simulation time 451556997 ps
CPU time 1.29 seconds
Started Oct 09 05:21:21 AM UTC 24
Finished Oct 09 05:21:23 AM UTC 24
Peak memory 203884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026502398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2026502398
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/28.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.534672447
Short name T12
Test name
Test status
Simulation time 443253264 ps
CPU time 1.23 seconds
Started Oct 09 05:20:23 AM UTC 24
Finished Oct 09 05:20:26 AM UTC 24
Peak memory 205908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534672447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.534672447
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.3039167245
Short name T106
Test name
Test status
Simulation time 575717442 ps
CPU time 1.35 seconds
Started Oct 09 05:21:54 AM UTC 24
Finished Oct 09 05:21:56 AM UTC 24
Peak memory 205852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039167245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3039167245
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/40.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.73724812
Short name T186
Test name
Test status
Simulation time 163506930047 ps
CPU time 207.48 seconds
Started Oct 09 05:21:57 AM UTC 24
Finished Oct 09 05:25:28 AM UTC 24
Peak memory 207228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73724812 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.73724812
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/41.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.3001890137
Short name T184
Test name
Test status
Simulation time 114183030544 ps
CPU time 40.96 seconds
Started Oct 09 05:20:32 AM UTC 24
Finished Oct 09 05:21:15 AM UTC 24
Peak memory 207192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001890137 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.3001890137
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.1360069718
Short name T46
Test name
Test status
Simulation time 2670958121 ps
CPU time 11.43 seconds
Started Oct 09 05:20:35 AM UTC 24
Finished Oct 09 05:20:48 AM UTC 24
Peak memory 216364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1360069718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 8.aon_timer_stress_all_with_rand_reset.1360069718
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.4167666059
Short name T54
Test name
Test status
Simulation time 535550159 ps
CPU time 2.68 seconds
Started Oct 09 05:20:36 AM UTC 24
Finished Oct 09 05:20:40 AM UTC 24
Peak memory 205320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167666059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4167666059
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1027877585
Short name T38
Test name
Test status
Simulation time 505558321 ps
CPU time 0.98 seconds
Started Oct 09 04:45:23 AM UTC 24
Finished Oct 09 04:45:26 AM UTC 24
Peak memory 201972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027877585 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.1027877585
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3977918972
Short name T71
Test name
Test status
Simulation time 11966752139 ps
CPU time 11.05 seconds
Started Oct 09 04:45:23 AM UTC 24
Finished Oct 09 04:45:36 AM UTC 24
Peak memory 205656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977918972 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.3977918972
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3287149131
Short name T43
Test name
Test status
Simulation time 379939930 ps
CPU time 1.17 seconds
Started Oct 09 04:45:23 AM UTC 24
Finished Oct 09 04:45:26 AM UTC 24
Peak memory 204104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3287149131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_csr_mem_rw_with_rand_reset.3287149131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.2423063769
Short name T37
Test name
Test status
Simulation time 395943879 ps
CPU time 0.91 seconds
Started Oct 09 04:45:23 AM UTC 24
Finished Oct 09 04:45:25 AM UTC 24
Peak memory 199976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423063769 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2423063769
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.3295125405
Short name T291
Test name
Test status
Simulation time 405615706 ps
CPU time 0.79 seconds
Started Oct 09 04:45:22 AM UTC 24
Finished Oct 09 04:45:24 AM UTC 24
Peak memory 201752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295125405 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3295125405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1833497544
Short name T292
Test name
Test status
Simulation time 380362252 ps
CPU time 1.12 seconds
Started Oct 09 04:45:22 AM UTC 24
Finished Oct 09 04:45:25 AM UTC 24
Peak memory 200032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833497544 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.1833497544
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.795354588
Short name T290
Test name
Test status
Simulation time 453365218 ps
CPU time 0.76 seconds
Started Oct 09 04:45:22 AM UTC 24
Finished Oct 09 04:45:24 AM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795354588 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.795354588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.60753175
Short name T293
Test name
Test status
Simulation time 864888784 ps
CPU time 2.92 seconds
Started Oct 09 04:45:22 AM UTC 24
Finished Oct 09 04:45:26 AM UTC 24
Peak memory 206872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60753175 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.60753175
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2956292400
Short name T41
Test name
Test status
Simulation time 4372339241 ps
CPU time 6.69 seconds
Started Oct 09 04:45:22 AM UTC 24
Finished Oct 09 04:45:30 AM UTC 24
Peak memory 205360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956292400 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.2956292400
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1083464920
Short name T70
Test name
Test status
Simulation time 8367650533 ps
CPU time 8.25 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:35 AM UTC 24
Peak memory 205584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083464920 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.1083464920
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1793741940
Short name T45
Test name
Test status
Simulation time 858473212 ps
CPU time 0.84 seconds
Started Oct 09 04:45:25 AM UTC 24
Finished Oct 09 04:45:27 AM UTC 24
Peak memory 201972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793741940 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.1793741940
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1870388188
Short name T222
Test name
Test status
Simulation time 431298360 ps
CPU time 1.05 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:28 AM UTC 24
Peak memory 204080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1870388188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_csr_mem_rw_with_rand_reset.1870388188
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.1824023962
Short name T58
Test name
Test status
Simulation time 325335596 ps
CPU time 1.04 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:28 AM UTC 24
Peak memory 199976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824023962 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1824023962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.1820285864
Short name T297
Test name
Test status
Simulation time 475055905 ps
CPU time 1.39 seconds
Started Oct 09 04:45:25 AM UTC 24
Finished Oct 09 04:45:27 AM UTC 24
Peak memory 199980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820285864 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1820285864
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3516074583
Short name T294
Test name
Test status
Simulation time 527352346 ps
CPU time 0.76 seconds
Started Oct 09 04:45:25 AM UTC 24
Finished Oct 09 04:45:26 AM UTC 24
Peak memory 199984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516074583 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.3516074583
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3096001656
Short name T296
Test name
Test status
Simulation time 438259570 ps
CPU time 1.24 seconds
Started Oct 09 04:45:25 AM UTC 24
Finished Oct 09 04:45:27 AM UTC 24
Peak memory 199912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096001656 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.3096001656
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3459880832
Short name T73
Test name
Test status
Simulation time 1411974586 ps
CPU time 1.5 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:29 AM UTC 24
Peak memory 202032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459880832 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.3459880832
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.1845544570
Short name T295
Test name
Test status
Simulation time 389114952 ps
CPU time 1.86 seconds
Started Oct 09 04:45:23 AM UTC 24
Finished Oct 09 04:45:27 AM UTC 24
Peak memory 207132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845544570 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1845544570
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3217179335
Short name T339
Test name
Test status
Simulation time 412629140 ps
CPU time 0.86 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:40 AM UTC 24
Peak memory 204136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3217179335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_ti
mer_csr_mem_rw_with_rand_reset.3217179335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.1441948650
Short name T337
Test name
Test status
Simulation time 559956211 ps
CPU time 0.91 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:39 AM UTC 24
Peak memory 201964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441948650 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1441948650
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.3663042319
Short name T341
Test name
Test status
Simulation time 410813931 ps
CPU time 1.29 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:40 AM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663042319 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3663042319
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1128549235
Short name T343
Test name
Test status
Simulation time 1381263742 ps
CPU time 1.42 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:40 AM UTC 24
Peak memory 201916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128549235 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.1128549235
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.2448870955
Short name T344
Test name
Test status
Simulation time 567004052 ps
CPU time 1.67 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:40 AM UTC 24
Peak memory 207020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448870955 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2448870955
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3871631973
Short name T425
Test name
Test status
Simulation time 7782778917 ps
CPU time 11.81 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:50 AM UTC 24
Peak memory 207120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871631973 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.3871631973
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.247092687
Short name T347
Test name
Test status
Simulation time 459320955 ps
CPU time 1.01 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:41 AM UTC 24
Peak memory 205340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=247092687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_tim
er_csr_mem_rw_with_rand_reset.247092687
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.2503016075
Short name T66
Test name
Test status
Simulation time 473383868 ps
CPU time 1.14 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:41 AM UTC 24
Peak memory 199916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503016075 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2503016075
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.2233272634
Short name T338
Test name
Test status
Simulation time 494082651 ps
CPU time 0.77 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:39 AM UTC 24
Peak memory 202024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233272634 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2233272634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3777801854
Short name T351
Test name
Test status
Simulation time 964737305 ps
CPU time 1.3 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:41 AM UTC 24
Peak memory 202032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777801854 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.3777801854
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2878250380
Short name T345
Test name
Test status
Simulation time 573985530 ps
CPU time 1.73 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:40 AM UTC 24
Peak memory 206964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878250380 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2878250380
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2558001355
Short name T399
Test name
Test status
Simulation time 4343241771 ps
CPU time 8.42 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:47 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558001355 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.2558001355
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2937779770
Short name T350
Test name
Test status
Simulation time 329947594 ps
CPU time 1.04 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:41 AM UTC 24
Peak memory 204076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2937779770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_ti
mer_csr_mem_rw_with_rand_reset.2937779770
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2205240130
Short name T67
Test name
Test status
Simulation time 550504782 ps
CPU time 1 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:41 AM UTC 24
Peak memory 201940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205240130 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2205240130
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.468094492
Short name T346
Test name
Test status
Simulation time 349589967 ps
CPU time 0.72 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:41 AM UTC 24
Peak memory 201964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468094492 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.468094492
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.799823484
Short name T362
Test name
Test status
Simulation time 2425057006 ps
CPU time 3.52 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:44 AM UTC 24
Peak memory 205492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799823484 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.799823484
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.2536729438
Short name T353
Test name
Test status
Simulation time 534571064 ps
CPU time 2.43 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:42 AM UTC 24
Peak memory 207088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536729438 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2536729438
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3028272755
Short name T396
Test name
Test status
Simulation time 4078237998 ps
CPU time 6.66 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:47 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028272755 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.3028272755
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2443974594
Short name T354
Test name
Test status
Simulation time 485559663 ps
CPU time 1.03 seconds
Started Oct 09 04:45:40 AM UTC 24
Finished Oct 09 04:45:42 AM UTC 24
Peak memory 204080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2443974594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_ti
mer_csr_mem_rw_with_rand_reset.2443974594
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.3545077690
Short name T352
Test name
Test status
Simulation time 546530419 ps
CPU time 0.97 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:41 AM UTC 24
Peak memory 199772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545077690 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3545077690
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.3240696158
Short name T348
Test name
Test status
Simulation time 470232567 ps
CPU time 0.81 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:41 AM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240696158 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3240696158
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3218624244
Short name T349
Test name
Test status
Simulation time 1583575679 ps
CPU time 0.89 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:41 AM UTC 24
Peak memory 202032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218624244 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.3218624244
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.4293004151
Short name T358
Test name
Test status
Simulation time 1759316213 ps
CPU time 2.49 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:43 AM UTC 24
Peak memory 206968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293004151 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.4293004151
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2744980953
Short name T367
Test name
Test status
Simulation time 8071029601 ps
CPU time 4.14 seconds
Started Oct 09 04:45:39 AM UTC 24
Finished Oct 09 04:45:44 AM UTC 24
Peak memory 207356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744980953 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.2744980953
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3398434975
Short name T360
Test name
Test status
Simulation time 330803565 ps
CPU time 1.45 seconds
Started Oct 09 04:45:40 AM UTC 24
Finished Oct 09 04:45:43 AM UTC 24
Peak memory 204136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3398434975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_ti
mer_csr_mem_rw_with_rand_reset.3398434975
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.803264703
Short name T359
Test name
Test status
Simulation time 382195058 ps
CPU time 1.26 seconds
Started Oct 09 04:45:40 AM UTC 24
Finished Oct 09 04:45:43 AM UTC 24
Peak memory 202024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803264703 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.803264703
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.2777452183
Short name T355
Test name
Test status
Simulation time 403145008 ps
CPU time 1.19 seconds
Started Oct 09 04:45:40 AM UTC 24
Finished Oct 09 04:45:43 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777452183 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2777452183
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.155348936
Short name T361
Test name
Test status
Simulation time 987194096 ps
CPU time 2.09 seconds
Started Oct 09 04:45:40 AM UTC 24
Finished Oct 09 04:45:44 AM UTC 24
Peak memory 203572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155348936 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.155348936
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.2149649505
Short name T369
Test name
Test status
Simulation time 487644559 ps
CPU time 3.06 seconds
Started Oct 09 04:45:40 AM UTC 24
Finished Oct 09 04:45:44 AM UTC 24
Peak memory 207128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149649505 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2149649505
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1128178225
Short name T422
Test name
Test status
Simulation time 4493253076 ps
CPU time 8.27 seconds
Started Oct 09 04:45:40 AM UTC 24
Finished Oct 09 04:45:50 AM UTC 24
Peak memory 207024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128178225 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.1128178225
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3660894532
Short name T366
Test name
Test status
Simulation time 426711865 ps
CPU time 1.27 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:44 AM UTC 24
Peak memory 204076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3660894532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti
mer_csr_mem_rw_with_rand_reset.3660894532
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.932323032
Short name T356
Test name
Test status
Simulation time 324777635 ps
CPU time 0.91 seconds
Started Oct 09 04:45:41 AM UTC 24
Finished Oct 09 04:45:43 AM UTC 24
Peak memory 199976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932323032 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.932323032
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.2827120943
Short name T357
Test name
Test status
Simulation time 340845669 ps
CPU time 0.95 seconds
Started Oct 09 04:45:41 AM UTC 24
Finished Oct 09 04:45:43 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827120943 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2827120943
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4237847655
Short name T372
Test name
Test status
Simulation time 1809646407 ps
CPU time 1.43 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 204140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237847655 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.4237847655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.233005112
Short name T371
Test name
Test status
Simulation time 505006135 ps
CPU time 2.93 seconds
Started Oct 09 04:45:40 AM UTC 24
Finished Oct 09 04:45:44 AM UTC 24
Peak memory 207020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233005112 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.233005112
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.834663995
Short name T384
Test name
Test status
Simulation time 4082380073 ps
CPU time 4.04 seconds
Started Oct 09 04:45:41 AM UTC 24
Finished Oct 09 04:45:46 AM UTC 24
Peak memory 207252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834663995 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.834663995
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2314643343
Short name T373
Test name
Test status
Simulation time 345390878 ps
CPU time 1.27 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 204076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2314643343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti
mer_csr_mem_rw_with_rand_reset.2314643343
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.2053126648
Short name T365
Test name
Test status
Simulation time 424923514 ps
CPU time 0.78 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:44 AM UTC 24
Peak memory 201964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053126648 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2053126648
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.1996110157
Short name T363
Test name
Test status
Simulation time 481503094 ps
CPU time 0.85 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:44 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996110157 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1996110157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2567291220
Short name T381
Test name
Test status
Simulation time 1053402648 ps
CPU time 1.91 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 202092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567291220 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.2567291220
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.3117148588
Short name T386
Test name
Test status
Simulation time 497358551 ps
CPU time 2.54 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:46 AM UTC 24
Peak memory 207284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117148588 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3117148588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3774635160
Short name T374
Test name
Test status
Simulation time 318721341 ps
CPU time 1.01 seconds
Started Oct 09 04:45:43 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 204076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3774635160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti
mer_csr_mem_rw_with_rand_reset.3774635160
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.3815414952
Short name T375
Test name
Test status
Simulation time 310849949 ps
CPU time 1.23 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 201940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815414952 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3815414952
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.2117462999
Short name T370
Test name
Test status
Simulation time 335347774 ps
CPU time 0.88 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:44 AM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117462999 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2117462999
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2017903240
Short name T378
Test name
Test status
Simulation time 1301373154 ps
CPU time 1.6 seconds
Started Oct 09 04:45:43 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 202032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017903240 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.2017903240
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.4181727925
Short name T382
Test name
Test status
Simulation time 341097351 ps
CPU time 1.88 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 207020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181727925 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.4181727925
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1214048145
Short name T394
Test name
Test status
Simulation time 8628813876 ps
CPU time 3.09 seconds
Started Oct 09 04:45:42 AM UTC 24
Finished Oct 09 04:45:47 AM UTC 24
Peak memory 206976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214048145 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.1214048145
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2156473344
Short name T392
Test name
Test status
Simulation time 593323146 ps
CPU time 1.33 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:47 AM UTC 24
Peak memory 205456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2156473344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_ti
mer_csr_mem_rw_with_rand_reset.2156473344
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.4252373195
Short name T383
Test name
Test status
Simulation time 436455513 ps
CPU time 1.48 seconds
Started Oct 09 04:45:43 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 201964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252373195 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4252373195
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.3117819007
Short name T377
Test name
Test status
Simulation time 513471338 ps
CPU time 1.28 seconds
Started Oct 09 04:45:43 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 199976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117819007 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3117819007
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2054086003
Short name T376
Test name
Test status
Simulation time 2198054816 ps
CPU time 1 seconds
Started Oct 09 04:45:43 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 204080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054086003 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.2054086003
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.4075716141
Short name T380
Test name
Test status
Simulation time 540712994 ps
CPU time 1.46 seconds
Started Oct 09 04:45:43 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 207064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075716141 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.4075716141
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1942225828
Short name T211
Test name
Test status
Simulation time 8443920777 ps
CPU time 4.58 seconds
Started Oct 09 04:45:43 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 207100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942225828 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.1942225828
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3863398677
Short name T398
Test name
Test status
Simulation time 418886158 ps
CPU time 1.64 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:47 AM UTC 24
Peak memory 204136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3863398677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti
mer_csr_mem_rw_with_rand_reset.3863398677
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.3416594776
Short name T393
Test name
Test status
Simulation time 401673063 ps
CPU time 1.33 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:47 AM UTC 24
Peak memory 201648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416594776 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3416594776
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.2392740532
Short name T389
Test name
Test status
Simulation time 503629671 ps
CPU time 1.04 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:46 AM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392740532 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2392740532
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3956581912
Short name T418
Test name
Test status
Simulation time 2172586381 ps
CPU time 3.46 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:49 AM UTC 24
Peak memory 205416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956581912 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.3956581912
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.1084643098
Short name T400
Test name
Test status
Simulation time 438146693 ps
CPU time 2.12 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:47 AM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084643098 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1084643098
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1202732701
Short name T427
Test name
Test status
Simulation time 8499049644 ps
CPU time 15.48 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:46:01 AM UTC 24
Peak memory 206988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202732701 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.1202732701
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2518468458
Short name T80
Test name
Test status
Simulation time 735170699 ps
CPU time 0.76 seconds
Started Oct 09 04:45:28 AM UTC 24
Finished Oct 09 04:45:29 AM UTC 24
Peak memory 201972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518468458 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.2518468458
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1560112279
Short name T72
Test name
Test status
Simulation time 7159375490 ps
CPU time 11.78 seconds
Started Oct 09 04:45:27 AM UTC 24
Finished Oct 09 04:45:40 AM UTC 24
Peak memory 205580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560112279 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.1560112279
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1163461490
Short name T59
Test name
Test status
Simulation time 656060742 ps
CPU time 0.81 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:28 AM UTC 24
Peak memory 199924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163461490 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.1163461490
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3828301571
Short name T303
Test name
Test status
Simulation time 411926766 ps
CPU time 1.32 seconds
Started Oct 09 04:45:28 AM UTC 24
Finished Oct 09 04:45:30 AM UTC 24
Peak memory 204140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3828301571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_tim
er_csr_mem_rw_with_rand_reset.3828301571
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.2477571813
Short name T74
Test name
Test status
Simulation time 334550912 ps
CPU time 1.18 seconds
Started Oct 09 04:45:27 AM UTC 24
Finished Oct 09 04:45:30 AM UTC 24
Peak memory 202024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477571813 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2477571813
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.3316609145
Short name T298
Test name
Test status
Simulation time 425817740 ps
CPU time 0.74 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:28 AM UTC 24
Peak memory 199980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316609145 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3316609145
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2573931841
Short name T300
Test name
Test status
Simulation time 457160325 ps
CPU time 0.72 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:28 AM UTC 24
Peak memory 200044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573931841 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.2573931841
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.75826556
Short name T299
Test name
Test status
Simulation time 384388390 ps
CPU time 0.71 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:28 AM UTC 24
Peak memory 199916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75826556 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.75826556
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1039273760
Short name T75
Test name
Test status
Simulation time 1094853095 ps
CPU time 1.25 seconds
Started Oct 09 04:45:28 AM UTC 24
Finished Oct 09 04:45:30 AM UTC 24
Peak memory 202032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039273760 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.1039273760
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.3502226154
Short name T301
Test name
Test status
Simulation time 450293868 ps
CPU time 1.55 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:29 AM UTC 24
Peak memory 207092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502226154 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3502226154
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.4210113582
Short name T210
Test name
Test status
Simulation time 8120898725 ps
CPU time 11.13 seconds
Started Oct 09 04:45:26 AM UTC 24
Finished Oct 09 04:45:39 AM UTC 24
Peak memory 206852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210113582 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.4210113582
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.3040290785
Short name T387
Test name
Test status
Simulation time 349324547 ps
CPU time 0.82 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:46 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040290785 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3040290785
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/20.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.4243944339
Short name T388
Test name
Test status
Simulation time 355441459 ps
CPU time 0.74 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:46 AM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243944339 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.4243944339
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/21.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.1744124001
Short name T391
Test name
Test status
Simulation time 428122836 ps
CPU time 0.87 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:46 AM UTC 24
Peak memory 199844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744124001 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1744124001
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/22.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.3799241315
Short name T397
Test name
Test status
Simulation time 414648111 ps
CPU time 1.3 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:47 AM UTC 24
Peak memory 201892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799241315 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3799241315
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/23.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.4124602624
Short name T390
Test name
Test status
Simulation time 348358174 ps
CPU time 0.73 seconds
Started Oct 09 04:45:44 AM UTC 24
Finished Oct 09 04:45:46 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124602624 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4124602624
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/24.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.976931160
Short name T395
Test name
Test status
Simulation time 412632164 ps
CPU time 1.06 seconds
Started Oct 09 04:45:45 AM UTC 24
Finished Oct 09 04:45:47 AM UTC 24
Peak memory 201964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976931160 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.976931160
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/25.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.1865748870
Short name T404
Test name
Test status
Simulation time 432277224 ps
CPU time 1.33 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865748870 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1865748870
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/26.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.1938626762
Short name T402
Test name
Test status
Simulation time 472020657 ps
CPU time 1.05 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938626762 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1938626762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/27.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.4075489503
Short name T406
Test name
Test status
Simulation time 497280514 ps
CPU time 1.16 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075489503 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4075489503
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/28.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.2527007909
Short name T385
Test name
Test status
Simulation time 417408431 ps
CPU time 1.23 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527007909 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2527007909
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/29.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2095588507
Short name T62
Test name
Test status
Simulation time 599235339 ps
CPU time 1.85 seconds
Started Oct 09 04:45:29 AM UTC 24
Finished Oct 09 04:45:32 AM UTC 24
Peak memory 201972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095588507 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.2095588507
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3588138702
Short name T63
Test name
Test status
Simulation time 4615079267 ps
CPU time 3.32 seconds
Started Oct 09 04:45:29 AM UTC 24
Finished Oct 09 04:45:33 AM UTC 24
Peak memory 205576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588138702 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.3588138702
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3370009288
Short name T309
Test name
Test status
Simulation time 983075775 ps
CPU time 1.89 seconds
Started Oct 09 04:45:29 AM UTC 24
Finished Oct 09 04:45:32 AM UTC 24
Peak memory 199348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370009288 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.3370009288
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.826923404
Short name T308
Test name
Test status
Simulation time 456862081 ps
CPU time 1.34 seconds
Started Oct 09 04:45:29 AM UTC 24
Finished Oct 09 04:45:31 AM UTC 24
Peak memory 204080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=826923404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_time
r_csr_mem_rw_with_rand_reset.826923404
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.283578837
Short name T307
Test name
Test status
Simulation time 349077783 ps
CPU time 1.07 seconds
Started Oct 09 04:45:29 AM UTC 24
Finished Oct 09 04:45:31 AM UTC 24
Peak memory 199916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283578837 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.283578837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3703072909
Short name T302
Test name
Test status
Simulation time 558147010 ps
CPU time 0.65 seconds
Started Oct 09 04:45:28 AM UTC 24
Finished Oct 09 04:45:29 AM UTC 24
Peak memory 199864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703072909 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3703072909
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2373729949
Short name T305
Test name
Test status
Simulation time 360473586 ps
CPU time 0.71 seconds
Started Oct 09 04:45:29 AM UTC 24
Finished Oct 09 04:45:31 AM UTC 24
Peak memory 199984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373729949 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.2373729949
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.3128595176
Short name T304
Test name
Test status
Simulation time 489994859 ps
CPU time 1.32 seconds
Started Oct 09 04:45:28 AM UTC 24
Finished Oct 09 04:45:30 AM UTC 24
Peak memory 199912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128595176 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.3128595176
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.6996176
Short name T76
Test name
Test status
Simulation time 1057474089 ps
CPU time 1.19 seconds
Started Oct 09 04:45:29 AM UTC 24
Finished Oct 09 04:45:31 AM UTC 24
Peak memory 202036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6996176 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.6996176
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.3266474012
Short name T306
Test name
Test status
Simulation time 607913871 ps
CPU time 2.26 seconds
Started Oct 09 04:45:28 AM UTC 24
Finished Oct 09 04:45:31 AM UTC 24
Peak memory 206960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266474012 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3266474012
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.20309579
Short name T42
Test name
Test status
Simulation time 8334072305 ps
CPU time 4.21 seconds
Started Oct 09 04:45:28 AM UTC 24
Finished Oct 09 04:45:33 AM UTC 24
Peak memory 206772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20309579 -assert nopostproc +UVM_TEST
NAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.20309579
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.4242242593
Short name T409
Test name
Test status
Simulation time 288115878 ps
CPU time 1.16 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242242593 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.4242242593
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/30.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.3789179386
Short name T407
Test name
Test status
Simulation time 385464582 ps
CPU time 1.15 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789179386 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3789179386
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/31.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.716094864
Short name T401
Test name
Test status
Simulation time 483624426 ps
CPU time 0.78 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 199916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716094864 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.716094864
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/32.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.3566303628
Short name T364
Test name
Test status
Simulation time 291067657 ps
CPU time 1.2 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 199916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566303628 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3566303628
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/33.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.500155336
Short name T405
Test name
Test status
Simulation time 472878550 ps
CPU time 0.99 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 199916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500155336 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.500155336
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/34.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.1483108420
Short name T403
Test name
Test status
Simulation time 513744165 ps
CPU time 0.88 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483108420 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1483108420
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/35.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.2573752211
Short name T408
Test name
Test status
Simulation time 341575949 ps
CPU time 0.85 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573752211 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2573752211
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/36.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.1415746280
Short name T416
Test name
Test status
Simulation time 479922107 ps
CPU time 1.3 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:49 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415746280 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1415746280
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/37.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.3049968410
Short name T412
Test name
Test status
Simulation time 331076514 ps
CPU time 0.95 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049968410 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3049968410
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/38.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.140725292
Short name T410
Test name
Test status
Simulation time 503459355 ps
CPU time 0.88 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 201964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140725292 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.140725292
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/39.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3540105438
Short name T315
Test name
Test status
Simulation time 695095026 ps
CPU time 1.13 seconds
Started Oct 09 04:45:30 AM UTC 24
Finished Oct 09 04:45:33 AM UTC 24
Peak memory 201972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540105438 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.3540105438
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1698128370
Short name T64
Test name
Test status
Simulation time 1250262442 ps
CPU time 1.87 seconds
Started Oct 09 04:45:30 AM UTC 24
Finished Oct 09 04:45:33 AM UTC 24
Peak memory 204020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698128370 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.1698128370
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2526437521
Short name T69
Test name
Test status
Simulation time 1097359469 ps
CPU time 2.57 seconds
Started Oct 09 04:45:30 AM UTC 24
Finished Oct 09 04:45:34 AM UTC 24
Peak memory 203392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526437521 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.2526437521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2746864007
Short name T318
Test name
Test status
Simulation time 377238582 ps
CPU time 1.04 seconds
Started Oct 09 04:45:32 AM UTC 24
Finished Oct 09 04:45:34 AM UTC 24
Peak memory 204080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2746864007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim
er_csr_mem_rw_with_rand_reset.2746864007
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.809504919
Short name T314
Test name
Test status
Simulation time 387951764 ps
CPU time 1.13 seconds
Started Oct 09 04:45:30 AM UTC 24
Finished Oct 09 04:45:33 AM UTC 24
Peak memory 201964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809504919 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.809504919
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.799589450
Short name T313
Test name
Test status
Simulation time 376172846 ps
CPU time 1.21 seconds
Started Oct 09 04:45:30 AM UTC 24
Finished Oct 09 04:45:32 AM UTC 24
Peak memory 199980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799589450 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.799589450
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3328871773
Short name T312
Test name
Test status
Simulation time 296097325 ps
CPU time 0.97 seconds
Started Oct 09 04:45:30 AM UTC 24
Finished Oct 09 04:45:32 AM UTC 24
Peak memory 199984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328871773 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.3328871773
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.612269680
Short name T311
Test name
Test status
Simulation time 331925703 ps
CPU time 0.8 seconds
Started Oct 09 04:45:30 AM UTC 24
Finished Oct 09 04:45:32 AM UTC 24
Peak memory 199916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612269680 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.612269680
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.624627366
Short name T78
Test name
Test status
Simulation time 2308076005 ps
CPU time 1.45 seconds
Started Oct 09 04:45:32 AM UTC 24
Finished Oct 09 04:45:34 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624627366 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.624627366
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.1630271388
Short name T316
Test name
Test status
Simulation time 381238151 ps
CPU time 2.01 seconds
Started Oct 09 04:45:30 AM UTC 24
Finished Oct 09 04:45:33 AM UTC 24
Peak memory 207224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630271388 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1630271388
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3378102947
Short name T208
Test name
Test status
Simulation time 8650773073 ps
CPU time 4.17 seconds
Started Oct 09 04:45:30 AM UTC 24
Finished Oct 09 04:45:35 AM UTC 24
Peak memory 206796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378102947 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.3378102947
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.2645939107
Short name T411
Test name
Test status
Simulation time 305997073 ps
CPU time 0.78 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 202024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645939107 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2645939107
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/40.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.212748158
Short name T413
Test name
Test status
Simulation time 473886292 ps
CPU time 0.85 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:48 AM UTC 24
Peak memory 201752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212748158 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.212748158
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/41.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.2308821472
Short name T419
Test name
Test status
Simulation time 373241438 ps
CPU time 1.26 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:49 AM UTC 24
Peak memory 199900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308821472 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2308821472
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/42.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.746191520
Short name T415
Test name
Test status
Simulation time 307458645 ps
CPU time 0.9 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:49 AM UTC 24
Peak memory 199916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746191520 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.746191520
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/43.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.4223465014
Short name T414
Test name
Test status
Simulation time 322594917 ps
CPU time 0.84 seconds
Started Oct 09 04:45:46 AM UTC 24
Finished Oct 09 04:45:49 AM UTC 24
Peak memory 201828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223465014 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4223465014
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/44.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.4142484613
Short name T420
Test name
Test status
Simulation time 475898359 ps
CPU time 1.28 seconds
Started Oct 09 04:45:47 AM UTC 24
Finished Oct 09 04:45:49 AM UTC 24
Peak memory 199824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142484613 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.4142484613
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/45.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.2165546659
Short name T417
Test name
Test status
Simulation time 331827624 ps
CPU time 0.89 seconds
Started Oct 09 04:45:47 AM UTC 24
Finished Oct 09 04:45:49 AM UTC 24
Peak memory 199908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165546659 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2165546659
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/46.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.305744003
Short name T421
Test name
Test status
Simulation time 443979791 ps
CPU time 0.66 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:45:50 AM UTC 24
Peak memory 199916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305744003 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.305744003
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/47.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.3593793012
Short name T423
Test name
Test status
Simulation time 330292344 ps
CPU time 0.85 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:45:50 AM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593793012 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3593793012
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/48.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.1543730610
Short name T424
Test name
Test status
Simulation time 423736579 ps
CPU time 0.85 seconds
Started Oct 09 04:45:48 AM UTC 24
Finished Oct 09 04:45:50 AM UTC 24
Peak memory 201956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543730610 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1543730610
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/49.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1768356925
Short name T319
Test name
Test status
Simulation time 564536701 ps
CPU time 1.2 seconds
Started Oct 09 04:45:32 AM UTC 24
Finished Oct 09 04:45:34 AM UTC 24
Peak memory 207076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1768356925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_tim
er_csr_mem_rw_with_rand_reset.1768356925
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.1396676401
Short name T68
Test name
Test status
Simulation time 311613700 ps
CPU time 0.77 seconds
Started Oct 09 04:45:32 AM UTC 24
Finished Oct 09 04:45:34 AM UTC 24
Peak memory 202024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396676401 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1396676401
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.4011090524
Short name T317
Test name
Test status
Simulation time 484704766 ps
CPU time 0.75 seconds
Started Oct 09 04:45:32 AM UTC 24
Finished Oct 09 04:45:34 AM UTC 24
Peak memory 199980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011090524 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.4011090524
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2791562679
Short name T77
Test name
Test status
Simulation time 2835117655 ps
CPU time 3.8 seconds
Started Oct 09 04:45:32 AM UTC 24
Finished Oct 09 04:45:37 AM UTC 24
Peak memory 205492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791562679 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.2791562679
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.841960199
Short name T320
Test name
Test status
Simulation time 560604925 ps
CPU time 2.12 seconds
Started Oct 09 04:45:32 AM UTC 24
Finished Oct 09 04:45:35 AM UTC 24
Peak memory 206880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841960199 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.841960199
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.385435260
Short name T325
Test name
Test status
Simulation time 4425535327 ps
CPU time 3.99 seconds
Started Oct 09 04:45:32 AM UTC 24
Finished Oct 09 04:45:37 AM UTC 24
Peak memory 206920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385435260 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.385435260
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.149257522
Short name T321
Test name
Test status
Simulation time 697949936 ps
CPU time 1.14 seconds
Started Oct 09 04:45:33 AM UTC 24
Finished Oct 09 04:45:35 AM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=149257522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_time
r_csr_mem_rw_with_rand_reset.149257522
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.355201382
Short name T65
Test name
Test status
Simulation time 281463027 ps
CPU time 0.99 seconds
Started Oct 09 04:45:33 AM UTC 24
Finished Oct 09 04:45:35 AM UTC 24
Peak memory 201964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355201382 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.355201382
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.3317611472
Short name T322
Test name
Test status
Simulation time 459249604 ps
CPU time 1.31 seconds
Started Oct 09 04:45:33 AM UTC 24
Finished Oct 09 04:45:35 AM UTC 24
Peak memory 199980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317611472 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3317611472
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1672091677
Short name T79
Test name
Test status
Simulation time 2697887712 ps
CPU time 2.38 seconds
Started Oct 09 04:45:33 AM UTC 24
Finished Oct 09 04:45:37 AM UTC 24
Peak memory 205556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672091677 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.1672091677
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.3874008147
Short name T323
Test name
Test status
Simulation time 759829801 ps
CPU time 2.19 seconds
Started Oct 09 04:45:33 AM UTC 24
Finished Oct 09 04:45:36 AM UTC 24
Peak memory 207080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874008147 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3874008147
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4015635850
Short name T324
Test name
Test status
Simulation time 545693203 ps
CPU time 0.87 seconds
Started Oct 09 04:45:34 AM UTC 24
Finished Oct 09 04:45:36 AM UTC 24
Peak memory 203512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4015635850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim
er_csr_mem_rw_with_rand_reset.4015635850
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.1911302972
Short name T61
Test name
Test status
Simulation time 351361224 ps
CPU time 1.24 seconds
Started Oct 09 04:45:34 AM UTC 24
Finished Oct 09 04:45:37 AM UTC 24
Peak memory 202024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911302972 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1911302972
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.4005167236
Short name T310
Test name
Test status
Simulation time 462001922 ps
CPU time 1.16 seconds
Started Oct 09 04:45:34 AM UTC 24
Finished Oct 09 04:45:37 AM UTC 24
Peak memory 199956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005167236 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4005167236
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3108445376
Short name T368
Test name
Test status
Simulation time 2352912381 ps
CPU time 8.62 seconds
Started Oct 09 04:45:34 AM UTC 24
Finished Oct 09 04:45:44 AM UTC 24
Peak memory 205684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108445376 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.3108445376
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.1038100012
Short name T327
Test name
Test status
Simulation time 353923461 ps
CPU time 2.13 seconds
Started Oct 09 04:45:34 AM UTC 24
Finished Oct 09 04:45:38 AM UTC 24
Peak memory 207096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038100012 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1038100012
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1710992018
Short name T342
Test name
Test status
Simulation time 4930269707 ps
CPU time 4.29 seconds
Started Oct 09 04:45:34 AM UTC 24
Finished Oct 09 04:45:40 AM UTC 24
Peak memory 205508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710992018 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.1710992018
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2891689274
Short name T330
Test name
Test status
Simulation time 374564431 ps
CPU time 1.12 seconds
Started Oct 09 04:45:36 AM UTC 24
Finished Oct 09 04:45:38 AM UTC 24
Peak memory 204812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2891689274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim
er_csr_mem_rw_with_rand_reset.2891689274
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.921233743
Short name T328
Test name
Test status
Simulation time 417790485 ps
CPU time 0.93 seconds
Started Oct 09 04:45:36 AM UTC 24
Finished Oct 09 04:45:38 AM UTC 24
Peak memory 199916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921233743 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.921233743
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.3747463924
Short name T326
Test name
Test status
Simulation time 359709753 ps
CPU time 1.08 seconds
Started Oct 09 04:45:35 AM UTC 24
Finished Oct 09 04:45:37 AM UTC 24
Peak memory 202028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747463924 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3747463924
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2803717957
Short name T331
Test name
Test status
Simulation time 962644626 ps
CPU time 1.15 seconds
Started Oct 09 04:45:36 AM UTC 24
Finished Oct 09 04:45:38 AM UTC 24
Peak memory 202032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803717957 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.2803717957
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.73863439
Short name T329
Test name
Test status
Simulation time 599666806 ps
CPU time 2.17 seconds
Started Oct 09 04:45:34 AM UTC 24
Finished Oct 09 04:45:38 AM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73863439 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.73863439
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3384733198
Short name T333
Test name
Test status
Simulation time 4904084221 ps
CPU time 2.59 seconds
Started Oct 09 04:45:34 AM UTC 24
Finished Oct 09 04:45:38 AM UTC 24
Peak memory 205696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384733198 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.3384733198
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3042732866
Short name T340
Test name
Test status
Simulation time 430429418 ps
CPU time 1.11 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:40 AM UTC 24
Peak memory 205964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3042732866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_tim
er_csr_mem_rw_with_rand_reset.3042732866
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.659276787
Short name T335
Test name
Test status
Simulation time 385906262 ps
CPU time 0.64 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:39 AM UTC 24
Peak memory 199556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659276787 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.659276787
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.3463351205
Short name T332
Test name
Test status
Simulation time 380955273 ps
CPU time 1.12 seconds
Started Oct 09 04:45:36 AM UTC 24
Finished Oct 09 04:45:38 AM UTC 24
Peak memory 199980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463351205 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3463351205
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.59953369
Short name T379
Test name
Test status
Simulation time 2310309452 ps
CPU time 6.91 seconds
Started Oct 09 04:45:37 AM UTC 24
Finished Oct 09 04:45:45 AM UTC 24
Peak memory 205620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59953369 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.59953369
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.194754809
Short name T336
Test name
Test status
Simulation time 511561007 ps
CPU time 2.04 seconds
Started Oct 09 04:45:36 AM UTC 24
Finished Oct 09 04:45:39 AM UTC 24
Peak memory 207096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194754809 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.194754809
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1734052224
Short name T334
Test name
Test status
Simulation time 4570270911 ps
CPU time 1.46 seconds
Started Oct 09 04:45:36 AM UTC 24
Finished Oct 09 04:45:38 AM UTC 24
Peak memory 205828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734052224 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.1734052224
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.2427469064
Short name T1
Test name
Test status
Simulation time 485415764 ps
CPU time 0.79 seconds
Started Oct 09 05:20:14 AM UTC 24
Finished Oct 09 05:20:16 AM UTC 24
Peak memory 205116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427469064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2427469064
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.753966118
Short name T10
Test name
Test status
Simulation time 5760961772 ps
CPU time 8.84 seconds
Started Oct 09 05:20:14 AM UTC 24
Finished Oct 09 05:20:24 AM UTC 24
Peak memory 205932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753966118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.753966118
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.1904775412
Short name T2
Test name
Test status
Simulation time 552406398 ps
CPU time 1.17 seconds
Started Oct 09 05:20:14 AM UTC 24
Finished Oct 09 05:20:16 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904775412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1904775412
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/0.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.2679225131
Short name T217
Test name
Test status
Simulation time 18535788721 ps
CPU time 31.99 seconds
Started Oct 09 05:20:17 AM UTC 24
Finished Oct 09 05:20:51 AM UTC 24
Peak memory 206064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679225131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2679225131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.1798850874
Short name T27
Test name
Test status
Simulation time 7905209407 ps
CPU time 22.9 seconds
Started Oct 09 05:20:17 AM UTC 24
Finished Oct 09 05:20:42 AM UTC 24
Peak memory 234700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798850874 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1798850874
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.3691326007
Short name T4
Test name
Test status
Simulation time 521503980 ps
CPU time 0.74 seconds
Started Oct 09 05:20:17 AM UTC 24
Finished Oct 09 05:20:19 AM UTC 24
Peak memory 205728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691326007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3691326007
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/1.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.3769861195
Short name T201
Test name
Test status
Simulation time 555609381 ps
CPU time 1.42 seconds
Started Oct 09 05:20:38 AM UTC 24
Finished Oct 09 05:20:41 AM UTC 24
Peak memory 205852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769861195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3769861195
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.125928905
Short name T219
Test name
Test status
Simulation time 40266246092 ps
CPU time 13.11 seconds
Started Oct 09 05:20:37 AM UTC 24
Finished Oct 09 05:20:52 AM UTC 24
Peak memory 206080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125928905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.125928905
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.3387434608
Short name T81
Test name
Test status
Simulation time 393984128 ps
CPU time 1.6 seconds
Started Oct 09 05:20:37 AM UTC 24
Finished Oct 09 05:20:40 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387434608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3387434608
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/10.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.1898899242
Short name T235
Test name
Test status
Simulation time 58699339950 ps
CPU time 38.18 seconds
Started Oct 09 05:20:43 AM UTC 24
Finished Oct 09 05:21:22 AM UTC 24
Peak memory 206020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898899242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1898899242
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.3354476343
Short name T82
Test name
Test status
Simulation time 529977729 ps
CPU time 2.37 seconds
Started Oct 09 05:20:43 AM UTC 24
Finished Oct 09 05:20:46 AM UTC 24
Peak memory 205720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354476343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3354476343
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/11.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.566161224
Short name T218
Test name
Test status
Simulation time 21941885421 ps
CPU time 43.34 seconds
Started Oct 09 05:20:43 AM UTC 24
Finished Oct 09 05:21:28 AM UTC 24
Peak memory 205936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566161224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.566161224
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.752398388
Short name T31
Test name
Test status
Simulation time 589270566 ps
CPU time 1.43 seconds
Started Oct 09 05:20:43 AM UTC 24
Finished Oct 09 05:20:46 AM UTC 24
Peak memory 203868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752398388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.752398388
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/12.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.974348645
Short name T221
Test name
Test status
Simulation time 30887682595 ps
CPU time 8.34 seconds
Started Oct 09 05:20:46 AM UTC 24
Finished Oct 09 05:20:56 AM UTC 24
Peak memory 205872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974348645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.974348645
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.11313849
Short name T223
Test name
Test status
Simulation time 507192241 ps
CPU time 2.67 seconds
Started Oct 09 05:20:45 AM UTC 24
Finished Oct 09 05:20:48 AM UTC 24
Peak memory 205636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11313849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.11313849
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/13.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.3745484616
Short name T276
Test name
Test status
Simulation time 46865976096 ps
CPU time 82.77 seconds
Started Oct 09 05:20:48 AM UTC 24
Finished Oct 09 05:22:12 AM UTC 24
Peak memory 206020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745484616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3745484616
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.4224990494
Short name T224
Test name
Test status
Simulation time 614287171 ps
CPU time 1.26 seconds
Started Oct 09 05:20:47 AM UTC 24
Finished Oct 09 05:20:50 AM UTC 24
Peak memory 205608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224990494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.4224990494
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/14.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.1010068431
Short name T215
Test name
Test status
Simulation time 17004424816 ps
CPU time 7.89 seconds
Started Oct 09 05:20:49 AM UTC 24
Finished Oct 09 05:20:58 AM UTC 24
Peak memory 206100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010068431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1010068431
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.2657740833
Short name T225
Test name
Test status
Simulation time 348441238 ps
CPU time 1.48 seconds
Started Oct 09 05:20:49 AM UTC 24
Finished Oct 09 05:20:52 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657740833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2657740833
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/15.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.3043435742
Short name T214
Test name
Test status
Simulation time 7041711612 ps
CPU time 3.39 seconds
Started Oct 09 05:20:51 AM UTC 24
Finished Oct 09 05:20:56 AM UTC 24
Peak memory 206092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043435742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3043435742
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.1414746986
Short name T226
Test name
Test status
Simulation time 582712208 ps
CPU time 2.37 seconds
Started Oct 09 05:20:51 AM UTC 24
Finished Oct 09 05:20:55 AM UTC 24
Peak memory 205704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414746986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1414746986
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/16.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.1726190217
Short name T94
Test name
Test status
Simulation time 29330388367 ps
CPU time 16.1 seconds
Started Oct 09 05:20:53 AM UTC 24
Finished Oct 09 05:21:10 AM UTC 24
Peak memory 206100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726190217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1726190217
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.1227367536
Short name T227
Test name
Test status
Simulation time 547631860 ps
CPU time 1.83 seconds
Started Oct 09 05:20:53 AM UTC 24
Finished Oct 09 05:20:55 AM UTC 24
Peak memory 205904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227367536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1227367536
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/17.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.3755385890
Short name T283
Test name
Test status
Simulation time 51577646501 ps
CPU time 89.25 seconds
Started Oct 09 05:20:57 AM UTC 24
Finished Oct 09 05:22:28 AM UTC 24
Peak memory 205940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755385890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3755385890
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.3087629722
Short name T228
Test name
Test status
Simulation time 521156195 ps
CPU time 1.39 seconds
Started Oct 09 05:20:55 AM UTC 24
Finished Oct 09 05:20:58 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087629722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3087629722
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/18.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.361360538
Short name T236
Test name
Test status
Simulation time 39397055275 ps
CPU time 24.11 seconds
Started Oct 09 05:20:57 AM UTC 24
Finished Oct 09 05:21:23 AM UTC 24
Peak memory 206008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361360538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.361360538
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.1031719940
Short name T229
Test name
Test status
Simulation time 478598028 ps
CPU time 1.8 seconds
Started Oct 09 05:20:57 AM UTC 24
Finished Oct 09 05:21:00 AM UTC 24
Peak memory 205692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031719940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1031719940
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/19.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.3202414625
Short name T39
Test name
Test status
Simulation time 31712083172 ps
CPU time 15.12 seconds
Started Oct 09 05:20:17 AM UTC 24
Finished Oct 09 05:20:34 AM UTC 24
Peak memory 206088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202414625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3202414625
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.1032362002
Short name T21
Test name
Test status
Simulation time 4233148992 ps
CPU time 4.05 seconds
Started Oct 09 05:20:20 AM UTC 24
Finished Oct 09 05:20:26 AM UTC 24
Peak memory 234236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032362002 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1032362002
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.2783827266
Short name T179
Test name
Test status
Simulation time 430112937 ps
CPU time 2.5 seconds
Started Oct 09 05:21:00 AM UTC 24
Finished Oct 09 05:21:03 AM UTC 24
Peak memory 205716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783827266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2783827266
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/20.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.4055806894
Short name T99
Test name
Test status
Simulation time 8548892040 ps
CPU time 13.21 seconds
Started Oct 09 05:21:00 AM UTC 24
Finished Oct 09 05:21:14 AM UTC 24
Peak memory 206012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055806894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.4055806894
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/20.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.599631414
Short name T230
Test name
Test status
Simulation time 527106418 ps
CPU time 1.5 seconds
Started Oct 09 05:21:00 AM UTC 24
Finished Oct 09 05:21:02 AM UTC 24
Peak memory 205548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599631414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.599631414
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/20.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.1907946529
Short name T220
Test name
Test status
Simulation time 40117181318 ps
CPU time 18.77 seconds
Started Oct 09 05:21:04 AM UTC 24
Finished Oct 09 05:21:24 AM UTC 24
Peak memory 206076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907946529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1907946529
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/21.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.4047164202
Short name T3
Test name
Test status
Simulation time 482639755 ps
CPU time 1.21 seconds
Started Oct 09 05:21:03 AM UTC 24
Finished Oct 09 05:21:06 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047164202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4047164202
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/21.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.2181200183
Short name T243
Test name
Test status
Simulation time 41155987818 ps
CPU time 25.02 seconds
Started Oct 09 05:21:06 AM UTC 24
Finished Oct 09 05:21:33 AM UTC 24
Peak memory 206144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181200183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2181200183
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/22.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.2430978427
Short name T92
Test name
Test status
Simulation time 482146408 ps
CPU time 1.31 seconds
Started Oct 09 05:21:06 AM UTC 24
Finished Oct 09 05:21:09 AM UTC 24
Peak memory 203868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430978427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2430978427
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/22.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.1164603676
Short name T232
Test name
Test status
Simulation time 6614517465 ps
CPU time 4.16 seconds
Started Oct 09 05:21:10 AM UTC 24
Finished Oct 09 05:21:15 AM UTC 24
Peak memory 206032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164603676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1164603676
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/23.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.3716371222
Short name T97
Test name
Test status
Simulation time 519415290 ps
CPU time 1.09 seconds
Started Oct 09 05:21:10 AM UTC 24
Finished Oct 09 05:21:12 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716371222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3716371222
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/23.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.2387003710
Short name T239
Test name
Test status
Simulation time 9491954715 ps
CPU time 16.23 seconds
Started Oct 09 05:21:11 AM UTC 24
Finished Oct 09 05:21:29 AM UTC 24
Peak memory 205940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387003710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2387003710
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/24.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.1420724494
Short name T231
Test name
Test status
Simulation time 571448566 ps
CPU time 1.69 seconds
Started Oct 09 05:21:11 AM UTC 24
Finished Oct 09 05:21:14 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420724494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1420724494
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/24.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.126360719
Short name T212
Test name
Test status
Simulation time 794841084 ps
CPU time 1.36 seconds
Started Oct 09 05:21:16 AM UTC 24
Finished Oct 09 05:21:18 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126360719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.126360719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/25.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.3580992413
Short name T233
Test name
Test status
Simulation time 541605992 ps
CPU time 2.24 seconds
Started Oct 09 05:21:13 AM UTC 24
Finished Oct 09 05:21:17 AM UTC 24
Peak memory 205732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580992413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3580992413
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/25.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.870267265
Short name T253
Test name
Test status
Simulation time 59985101415 ps
CPU time 31.08 seconds
Started Oct 09 05:21:16 AM UTC 24
Finished Oct 09 05:21:49 AM UTC 24
Peak memory 206016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870267265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.870267265
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/26.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.455096253
Short name T176
Test name
Test status
Simulation time 523761363 ps
CPU time 1.33 seconds
Started Oct 09 05:21:16 AM UTC 24
Finished Oct 09 05:21:19 AM UTC 24
Peak memory 205728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455096253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.455096253
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/26.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.1116868548
Short name T238
Test name
Test status
Simulation time 2775227278 ps
CPU time 5.6 seconds
Started Oct 09 05:21:19 AM UTC 24
Finished Oct 09 05:21:25 AM UTC 24
Peak memory 205876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116868548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1116868548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/27.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.606421235
Short name T234
Test name
Test status
Simulation time 368001613 ps
CPU time 1.28 seconds
Started Oct 09 05:21:19 AM UTC 24
Finished Oct 09 05:21:21 AM UTC 24
Peak memory 205784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606421235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.606421235
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/27.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.1268955274
Short name T288
Test name
Test status
Simulation time 51005031115 ps
CPU time 94.28 seconds
Started Oct 09 05:21:20 AM UTC 24
Finished Oct 09 05:22:56 AM UTC 24
Peak memory 206164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268955274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1268955274
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/28.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.1507817562
Short name T237
Test name
Test status
Simulation time 518400387 ps
CPU time 1.84 seconds
Started Oct 09 05:21:20 AM UTC 24
Finished Oct 09 05:21:23 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507817562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1507817562
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/28.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.3919883077
Short name T284
Test name
Test status
Simulation time 54475512998 ps
CPU time 66.26 seconds
Started Oct 09 05:21:23 AM UTC 24
Finished Oct 09 05:22:31 AM UTC 24
Peak memory 206100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919883077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3919883077
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/29.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.825645000
Short name T177
Test name
Test status
Simulation time 450462686 ps
CPU time 1.16 seconds
Started Oct 09 05:21:23 AM UTC 24
Finished Oct 09 05:21:26 AM UTC 24
Peak memory 205728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825645000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.825645000
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/29.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.23568270
Short name T17
Test name
Test status
Simulation time 14749323946 ps
CPU time 8.82 seconds
Started Oct 09 05:20:21 AM UTC 24
Finished Oct 09 05:20:31 AM UTC 24
Peak memory 205936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23568270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.23568270
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.2137513740
Short name T23
Test name
Test status
Simulation time 8361796963 ps
CPU time 14.41 seconds
Started Oct 09 05:20:23 AM UTC 24
Finished Oct 09 05:20:39 AM UTC 24
Peak memory 234628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137513740 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2137513740
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.3241120048
Short name T9
Test name
Test status
Simulation time 581478508 ps
CPU time 1.24 seconds
Started Oct 09 05:20:21 AM UTC 24
Finished Oct 09 05:20:23 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241120048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3241120048
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/3.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.1197047768
Short name T245
Test name
Test status
Simulation time 6121350994 ps
CPU time 10.03 seconds
Started Oct 09 05:21:26 AM UTC 24
Finished Oct 09 05:21:37 AM UTC 24
Peak memory 206092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197047768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1197047768
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/30.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.2388388493
Short name T241
Test name
Test status
Simulation time 576725989 ps
CPU time 2.82 seconds
Started Oct 09 05:21:26 AM UTC 24
Finished Oct 09 05:21:30 AM UTC 24
Peak memory 205632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388388493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2388388493
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/30.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.790730111
Short name T248
Test name
Test status
Simulation time 4347419132 ps
CPU time 13.05 seconds
Started Oct 09 05:21:27 AM UTC 24
Finished Oct 09 05:21:41 AM UTC 24
Peak memory 205952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790730111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.790730111
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/31.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.4092842233
Short name T240
Test name
Test status
Simulation time 405326701 ps
CPU time 0.86 seconds
Started Oct 09 05:21:27 AM UTC 24
Finished Oct 09 05:21:29 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092842233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4092842233
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/31.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.668462312
Short name T255
Test name
Test status
Simulation time 50136798267 ps
CPU time 19.11 seconds
Started Oct 09 05:21:30 AM UTC 24
Finished Oct 09 05:21:50 AM UTC 24
Peak memory 206024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668462312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.668462312
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/32.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.504320916
Short name T242
Test name
Test status
Simulation time 500767215 ps
CPU time 1.36 seconds
Started Oct 09 05:21:30 AM UTC 24
Finished Oct 09 05:21:32 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504320916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.504320916
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/32.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.46913371
Short name T266
Test name
Test status
Simulation time 2942922794 ps
CPU time 29.26 seconds
Started Oct 09 05:21:31 AM UTC 24
Finished Oct 09 05:22:02 AM UTC 24
Peak memory 223792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=46913371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 32.aon_timer_stress_all_with_rand_reset.46913371
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.3759373007
Short name T244
Test name
Test status
Simulation time 651719744 ps
CPU time 1.63 seconds
Started Oct 09 05:21:33 AM UTC 24
Finished Oct 09 05:21:36 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759373007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3759373007
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/33.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.1418509218
Short name T246
Test name
Test status
Simulation time 507432532 ps
CPU time 2.56 seconds
Started Oct 09 05:21:33 AM UTC 24
Finished Oct 09 05:21:37 AM UTC 24
Peak memory 205448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418509218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1418509218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/33.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.2238072161
Short name T260
Test name
Test status
Simulation time 8430343317 ps
CPU time 16.33 seconds
Started Oct 09 05:21:37 AM UTC 24
Finished Oct 09 05:21:55 AM UTC 24
Peak memory 206020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238072161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2238072161
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/34.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.1516673337
Short name T247
Test name
Test status
Simulation time 422457544 ps
CPU time 2.24 seconds
Started Oct 09 05:21:37 AM UTC 24
Finished Oct 09 05:21:40 AM UTC 24
Peak memory 205732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516673337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1516673337
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/34.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.264183126
Short name T277
Test name
Test status
Simulation time 8885015597 ps
CPU time 33.88 seconds
Started Oct 09 05:21:37 AM UTC 24
Finished Oct 09 05:22:13 AM UTC 24
Peak memory 223096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=264183126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 34.aon_timer_stress_all_with_rand_reset.264183126
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.998028818
Short name T252
Test name
Test status
Simulation time 12030742225 ps
CPU time 8.03 seconds
Started Oct 09 05:21:39 AM UTC 24
Finished Oct 09 05:21:48 AM UTC 24
Peak memory 206096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998028818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.998028818
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/35.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.3796793090
Short name T249
Test name
Test status
Simulation time 543641476 ps
CPU time 1.38 seconds
Started Oct 09 05:21:39 AM UTC 24
Finished Oct 09 05:21:42 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796793090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3796793090
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/35.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.3161515331
Short name T267
Test name
Test status
Simulation time 16626296545 ps
CPU time 19 seconds
Started Oct 09 05:21:43 AM UTC 24
Finished Oct 09 05:22:03 AM UTC 24
Peak memory 206108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161515331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3161515331
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/36.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.3255143832
Short name T250
Test name
Test status
Simulation time 555137794 ps
CPU time 1.01 seconds
Started Oct 09 05:21:43 AM UTC 24
Finished Oct 09 05:21:45 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255143832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3255143832
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/36.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.2592701168
Short name T259
Test name
Test status
Simulation time 8562842235 ps
CPU time 7.59 seconds
Started Oct 09 05:21:46 AM UTC 24
Finished Oct 09 05:21:54 AM UTC 24
Peak memory 205940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592701168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2592701168
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/37.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.2757479624
Short name T251
Test name
Test status
Simulation time 423690825 ps
CPU time 1.56 seconds
Started Oct 09 05:21:46 AM UTC 24
Finished Oct 09 05:21:48 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757479624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2757479624
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/37.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.3885529603
Short name T261
Test name
Test status
Simulation time 32074214419 ps
CPU time 5.28 seconds
Started Oct 09 05:21:49 AM UTC 24
Finished Oct 09 05:21:56 AM UTC 24
Peak memory 206084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885529603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3885529603
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/38.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.4164576503
Short name T256
Test name
Test status
Simulation time 441919092 ps
CPU time 1.51 seconds
Started Oct 09 05:21:48 AM UTC 24
Finished Oct 09 05:21:51 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164576503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4164576503
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/38.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.3802092895
Short name T254
Test name
Test status
Simulation time 8053460809 ps
CPU time 8.92 seconds
Started Oct 09 05:21:52 AM UTC 24
Finished Oct 09 05:22:02 AM UTC 24
Peak memory 206156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802092895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3802092895
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/39.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.716715239
Short name T258
Test name
Test status
Simulation time 372489465 ps
CPU time 1.87 seconds
Started Oct 09 05:21:51 AM UTC 24
Finished Oct 09 05:21:54 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716715239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.716715239
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/39.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.1851423628
Short name T52
Test name
Test status
Simulation time 16269707255 ps
CPU time 11.46 seconds
Started Oct 09 05:20:23 AM UTC 24
Finished Oct 09 05:20:36 AM UTC 24
Peak memory 206016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851423628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1851423628
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.4230943060
Short name T28
Test name
Test status
Simulation time 7672686741 ps
CPU time 20.56 seconds
Started Oct 09 05:20:25 AM UTC 24
Finished Oct 09 05:20:47 AM UTC 24
Peak memory 234552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230943060 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.4230943060
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.984742189
Short name T13
Test name
Test status
Simulation time 553232743 ps
CPU time 2.23 seconds
Started Oct 09 05:20:23 AM UTC 24
Finished Oct 09 05:20:27 AM UTC 24
Peak memory 205744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984742189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.984742189
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/4.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.222354099
Short name T268
Test name
Test status
Simulation time 16353387146 ps
CPU time 10.35 seconds
Started Oct 09 05:21:53 AM UTC 24
Finished Oct 09 05:22:04 AM UTC 24
Peak memory 206088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222354099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.222354099
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/40.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.412300686
Short name T257
Test name
Test status
Simulation time 496783803 ps
CPU time 1.21 seconds
Started Oct 09 05:21:52 AM UTC 24
Finished Oct 09 05:21:54 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412300686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.412300686
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/40.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.34792102
Short name T263
Test name
Test status
Simulation time 3168161011 ps
CPU time 2.99 seconds
Started Oct 09 05:21:55 AM UTC 24
Finished Oct 09 05:21:59 AM UTC 24
Peak memory 205744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34792102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.34792102
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/41.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.2271902974
Short name T262
Test name
Test status
Simulation time 450589806 ps
CPU time 2.37 seconds
Started Oct 09 05:21:55 AM UTC 24
Finished Oct 09 05:21:59 AM UTC 24
Peak memory 205732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271902974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2271902974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/41.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.5181460
Short name T274
Test name
Test status
Simulation time 40490367636 ps
CPU time 10.89 seconds
Started Oct 09 05:22:00 AM UTC 24
Finished Oct 09 05:22:12 AM UTC 24
Peak memory 206152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5181460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST
_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.5181460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/42.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.761588346
Short name T264
Test name
Test status
Simulation time 564030254 ps
CPU time 1.65 seconds
Started Oct 09 05:21:58 AM UTC 24
Finished Oct 09 05:22:00 AM UTC 24
Peak memory 203888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761588346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.761588346
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/42.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.258031731
Short name T282
Test name
Test status
Simulation time 42660239104 ps
CPU time 22.61 seconds
Started Oct 09 05:22:02 AM UTC 24
Finished Oct 09 05:22:26 AM UTC 24
Peak memory 206024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258031731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.258031731
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/43.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.3180328780
Short name T269
Test name
Test status
Simulation time 584473071 ps
CPU time 1.62 seconds
Started Oct 09 05:22:02 AM UTC 24
Finished Oct 09 05:22:05 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180328780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3180328780
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/43.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.3644341407
Short name T280
Test name
Test status
Simulation time 6787156174 ps
CPU time 14.14 seconds
Started Oct 09 05:22:03 AM UTC 24
Finished Oct 09 05:22:19 AM UTC 24
Peak memory 206020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644341407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3644341407
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/44.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.2327523577
Short name T271
Test name
Test status
Simulation time 381587143 ps
CPU time 2.16 seconds
Started Oct 09 05:22:03 AM UTC 24
Finished Oct 09 05:22:07 AM UTC 24
Peak memory 205660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327523577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2327523577
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/44.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.4076747221
Short name T287
Test name
Test status
Simulation time 22013019453 ps
CPU time 42.32 seconds
Started Oct 09 05:22:06 AM UTC 24
Finished Oct 09 05:22:50 AM UTC 24
Peak memory 206004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076747221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4076747221
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/45.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.3455124767
Short name T272
Test name
Test status
Simulation time 430777801 ps
CPU time 1.65 seconds
Started Oct 09 05:22:06 AM UTC 24
Finished Oct 09 05:22:09 AM UTC 24
Peak memory 205728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455124767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3455124767
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/45.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.1960069349
Short name T279
Test name
Test status
Simulation time 4601726745 ps
CPU time 9.53 seconds
Started Oct 09 05:22:08 AM UTC 24
Finished Oct 09 05:22:18 AM UTC 24
Peak memory 206028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960069349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1960069349
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/46.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.2821238180
Short name T273
Test name
Test status
Simulation time 441955344 ps
CPU time 1.75 seconds
Started Oct 09 05:22:07 AM UTC 24
Finished Oct 09 05:22:09 AM UTC 24
Peak memory 205728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821238180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2821238180
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/46.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.2127397410
Short name T193
Test name
Test status
Simulation time 436316960 ps
CPU time 1.1 seconds
Started Oct 09 05:22:12 AM UTC 24
Finished Oct 09 05:22:14 AM UTC 24
Peak memory 205380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127397410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2127397410
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/47.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.2815522103
Short name T286
Test name
Test status
Simulation time 28433201704 ps
CPU time 30.31 seconds
Started Oct 09 05:22:11 AM UTC 24
Finished Oct 09 05:22:43 AM UTC 24
Peak memory 206020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815522103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2815522103
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/47.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.3279523588
Short name T275
Test name
Test status
Simulation time 392228424 ps
CPU time 1.02 seconds
Started Oct 09 05:22:10 AM UTC 24
Finished Oct 09 05:22:12 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279523588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3279523588
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/47.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.1480604306
Short name T285
Test name
Test status
Simulation time 8006900135 ps
CPU time 22.8 seconds
Started Oct 09 05:22:13 AM UTC 24
Finished Oct 09 05:22:38 AM UTC 24
Peak memory 206092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480604306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1480604306
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/48.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.1101997078
Short name T278
Test name
Test status
Simulation time 536319030 ps
CPU time 1.44 seconds
Started Oct 09 05:22:13 AM UTC 24
Finished Oct 09 05:22:16 AM UTC 24
Peak memory 205588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101997078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1101997078
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/48.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.2346530554
Short name T289
Test name
Test status
Simulation time 53468359676 ps
CPU time 41.21 seconds
Started Oct 09 05:22:21 AM UTC 24
Finished Oct 09 05:23:03 AM UTC 24
Peak memory 206020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346530554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2346530554
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/49.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.3649479512
Short name T281
Test name
Test status
Simulation time 369041775 ps
CPU time 1.02 seconds
Started Oct 09 05:22:20 AM UTC 24
Finished Oct 09 05:22:22 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649479512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3649479512
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/49.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.4055990449
Short name T216
Test name
Test status
Simulation time 26984781730 ps
CPU time 17.41 seconds
Started Oct 09 05:20:25 AM UTC 24
Finished Oct 09 05:20:44 AM UTC 24
Peak memory 206080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055990449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4055990449
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.3457394919
Short name T29
Test name
Test status
Simulation time 433841465 ps
CPU time 2.17 seconds
Started Oct 09 05:20:25 AM UTC 24
Finished Oct 09 05:20:28 AM UTC 24
Peak memory 205524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457394919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3457394919
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/5.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.3803673716
Short name T55
Test name
Test status
Simulation time 40476876644 ps
CPU time 19.28 seconds
Started Oct 09 05:20:27 AM UTC 24
Finished Oct 09 05:20:48 AM UTC 24
Peak memory 205960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803673716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3803673716
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.2147016597
Short name T26
Test name
Test status
Simulation time 501635846 ps
CPU time 1.53 seconds
Started Oct 09 05:20:27 AM UTC 24
Finished Oct 09 05:20:30 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147016597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2147016597
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.1074526729
Short name T22
Test name
Test status
Simulation time 2397751879 ps
CPU time 11.23 seconds
Started Oct 09 05:20:29 AM UTC 24
Finished Oct 09 05:20:41 AM UTC 24
Peak memory 207372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1074526729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 6.aon_timer_stress_all_with_rand_reset.1074526729
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.532853444
Short name T270
Test name
Test status
Simulation time 56099321842 ps
CPU time 94.36 seconds
Started Oct 09 05:20:30 AM UTC 24
Finished Oct 09 05:22:06 AM UTC 24
Peak memory 205948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532853444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.532853444
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.3155543078
Short name T16
Test name
Test status
Simulation time 478351929 ps
CPU time 0.89 seconds
Started Oct 09 05:20:29 AM UTC 24
Finished Oct 09 05:20:31 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155543078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3155543078
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/7.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.3842307566
Short name T33
Test name
Test status
Simulation time 381314972 ps
CPU time 1.88 seconds
Started Oct 09 05:20:32 AM UTC 24
Finished Oct 09 05:20:36 AM UTC 24
Peak memory 205432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842307566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3842307566
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.1350895025
Short name T213
Test name
Test status
Simulation time 10274571538 ps
CPU time 15.88 seconds
Started Oct 09 05:20:32 AM UTC 24
Finished Oct 09 05:20:50 AM UTC 24
Peak memory 206080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350895025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1350895025
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.4105280263
Short name T20
Test name
Test status
Simulation time 464477401 ps
CPU time 1.21 seconds
Started Oct 09 05:20:32 AM UTC 24
Finished Oct 09 05:20:35 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105280263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4105280263
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/8.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.1030928925
Short name T265
Test name
Test status
Simulation time 39647069174 ps
CPU time 84.65 seconds
Started Oct 09 05:20:35 AM UTC 24
Finished Oct 09 05:22:02 AM UTC 24
Peak memory 206036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030928925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1030928925
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.1679222085
Short name T53
Test name
Test status
Simulation time 570097208 ps
CPU time 0.9 seconds
Started Oct 09 05:20:35 AM UTC 24
Finished Oct 09 05:20:37 AM UTC 24
Peak memory 205844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679222085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1679222085
Directory /workspaces/repo/scratch/os_regression_2024_10_08/aon_timer-sim-vcs/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%