Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 17263 1 T1 10 T5 10 T6 11
bark[1] 428 1 T45 7 T139 14 T129 21
bark[2] 232 1 T129 21 T126 64 T105 7
bark[3] 261 1 T37 14 T106 21 T176 5
bark[4] 437 1 T200 14 T28 42 T112 5
bark[5] 201 1 T163 14 T121 14 T114 21
bark[6] 367 1 T48 26 T28 26 T132 14
bark[7] 227 1 T51 14 T46 14 T112 21
bark[8] 347 1 T23 197 T35 14 T117 26
bark[9] 307 1 T49 45 T195 5 T159 14
bark[10] 307 1 T48 5 T106 21 T175 7
bark[11] 245 1 T49 93 T117 21 T135 21
bark[12] 289 1 T100 14 T181 14 T185 7
bark[13] 283 1 T101 14 T49 5 T137 14
bark[14] 260 1 T141 14 T184 14 T140 14
bark[15] 599 1 T4 14 T20 14 T131 21
bark[16] 612 1 T17 14 T46 21 T27 21
bark[17] 362 1 T15 14 T31 26 T129 21
bark[18] 304 1 T23 14 T45 85 T31 21
bark[19] 247 1 T23 130 T28 14 T87 5
bark[20] 193 1 T27 35 T135 26 T88 7
bark[21] 481 1 T8 14 T27 21 T129 26
bark[22] 530 1 T2 14 T14 14 T203 14
bark[23] 770 1 T117 154 T143 21 T88 296
bark[24] 228 1 T21 14 T34 14 T31 21
bark[25] 154 1 T30 14 T143 21 T162 26
bark[26] 736 1 T13 14 T24 29 T31 21
bark[27] 166 1 T3 14 T48 21 T195 7
bark[28] 525 1 T109 43 T87 21 T197 116
bark[29] 261 1 T36 14 T134 59 T104 21
bark[30] 458 1 T27 21 T29 21 T112 158
bark[31] 327 1 T28 26 T117 5 T174 21
bark_0 4423 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 17319 1 T1 9 T5 9 T6 10
bite[1] 495 1 T3 13 T100 13 T129 45
bite[2] 276 1 T20 13 T141 13 T48 4
bite[3] 455 1 T14 13 T112 21 T135 21
bite[4] 686 1 T28 26 T185 257 T190 67
bite[5] 457 1 T135 26 T106 30 T88 295
bite[6] 287 1 T23 13 T46 13 T27 21
bite[7] 360 1 T15 13 T28 13 T29 26
bite[8] 253 1 T23 129 T51 13 T117 25
bite[9] 204 1 T34 13 T31 21 T195 6
bite[10] 599 1 T45 98 T31 21 T112 4
bite[11] 340 1 T37 13 T27 21 T174 110
bite[12] 316 1 T36 13 T142 13 T145 21
bite[13] 206 1 T27 21 T117 21 T87 21
bite[14] 414 1 T49 44 T28 26 T139 13
bite[15] 373 1 T8 13 T109 42 T143 30
bite[16] 174 1 T156 13 T48 4 T106 21
bite[17] 431 1 T2 13 T23 204 T185 25
bite[18] 278 1 T17 13 T27 35 T147 13
bite[19] 182 1 T184 13 T140 13 T190 25
bite[20] 148 1 T29 13 T126 4 T155 47
bite[21] 208 1 T143 21 T157 13 T154 13
bite[22] 343 1 T200 13 T203 13 T31 21
bite[23] 304 1 T27 21 T48 25 T129 21
bite[24] 204 1 T159 13 T129 26 T175 6
bite[25] 487 1 T24 28 T30 13 T109 105
bite[26] 491 1 T4 13 T35 13 T112 157
bite[27] 157 1 T21 13 T28 42 T137 13
bite[28] 468 1 T31 25 T49 92 T143 45
bite[29] 257 1 T30 21 T48 21 T106 21
bite[30] 234 1 T117 21 T175 6 T196 4
bite[31] 533 1 T13 13 T101 13 T46 21
bite_0 4891 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28198 1 T1 17 T2 21 T3 21
auto[1] 4632 1 T6 7 T18 7 T86 7


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 387 1 T212 9 T47 28 T129 23
prescale[1] 573 1 T31 28 T129 19 T176 2
prescale[2] 469 1 T25 2 T55 9 T28 59
prescale[3] 382 1 T213 9 T47 2 T29 19
prescale[4] 220 1 T214 9 T112 2 T135 28
prescale[5] 473 1 T23 26 T31 11 T215 51
prescale[6] 393 1 T23 19 T215 19 T112 9
prescale[7] 360 1 T129 19 T109 19 T199 2
prescale[8] 531 1 T53 9 T30 2 T46 51
prescale[9] 410 1 T23 59 T25 2 T215 42
prescale[10] 264 1 T27 32 T215 38 T216 9
prescale[11] 209 1 T31 4 T56 9 T48 2
prescale[12] 493 1 T30 44 T48 48 T88 87
prescale[13] 311 1 T195 2 T180 2 T109 36
prescale[14] 284 1 T54 9 T30 2 T49 2
prescale[15] 440 1 T175 2 T88 70 T89 2
prescale[16] 268 1 T23 19 T45 2 T46 2
prescale[17] 421 1 T117 36 T106 2 T199 2
prescale[18] 455 1 T99 9 T27 23 T217 9
prescale[19] 238 1 T30 2 T47 2 T215 2
prescale[20] 412 1 T24 2 T45 2 T49 19
prescale[21] 301 1 T23 2 T112 7 T117 28
prescale[22] 589 1 T218 9 T48 2 T215 60
prescale[23] 233 1 T219 9 T180 2 T129 19
prescale[24] 287 1 T215 19 T29 19 T185 61
prescale[25] 349 1 T45 2 T117 2 T174 70
prescale[26] 707 1 T31 24 T46 2 T29 23
prescale[27] 512 1 T220 9 T24 2 T215 19
prescale[28] 242 1 T23 2 T25 2 T31 30
prescale[29] 301 1 T102 9 T112 68 T90 2
prescale[30] 597 1 T25 2 T48 2 T28 49
prescale[31] 543 1 T23 28 T44 9 T49 2
prescale_0 20176 1 T1 17 T2 21 T3 21


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21396 1 T1 17 T2 9 T3 9
auto[1] 11434 1 T2 12 T3 12 T4 12


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 32830 1 T1 17 T2 21 T3 21


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 19165 1 T1 12 T2 1 T3 1
wkup[1] 234 1 T117 21 T197 21 T126 21
wkup[2] 228 1 T200 15 T49 21 T112 21
wkup[3] 218 1 T48 21 T49 8 T215 21
wkup[4] 227 1 T2 15 T36 15 T174 21
wkup[5] 130 1 T23 40 T48 6 T49 21
wkup[6] 137 1 T3 15 T31 21 T126 30
wkup[7] 185 1 T159 15 T117 45 T132 15
wkup[8] 134 1 T174 21 T92 15 T114 26
wkup[9] 77 1 T185 21 T89 35 T190 21
wkup[10] 181 1 T117 42 T175 6 T143 21
wkup[11] 131 1 T117 21 T174 21 T158 26
wkup[12] 159 1 T27 21 T117 6 T176 6
wkup[13] 145 1 T196 21 T158 31 T108 21
wkup[14] 137 1 T48 21 T126 6 T105 21
wkup[15] 98 1 T24 15 T174 21 T201 15
wkup[16] 204 1 T31 21 T46 21 T117 6
wkup[17] 84 1 T168 21 T127 21 T164 21
wkup[18] 185 1 T24 26 T139 15 T88 8
wkup[19] 206 1 T8 15 T21 15 T35 15
wkup[20] 132 1 T48 6 T112 15 T175 6
wkup[21] 196 1 T190 21 T105 15 T160 21
wkup[22] 98 1 T117 21 T185 47 T162 30
wkup[23] 267 1 T34 15 T27 35 T48 21
wkup[24] 180 1 T23 26 T117 21 T142 15
wkup[25] 198 1 T31 15 T156 15 T109 21
wkup[26] 104 1 T23 15 T143 26 T190 21
wkup[27] 171 1 T169 15 T129 21 T106 21
wkup[28] 183 1 T14 15 T49 6 T117 21
wkup[29] 130 1 T27 21 T109 21 T199 21
wkup[30] 269 1 T23 47 T184 15 T109 21
wkup[31] 132 1 T45 21 T46 21 T174 21
wkup[32] 183 1 T31 21 T109 21 T185 21
wkup[33] 191 1 T51 15 T203 15 T46 15
wkup[34] 206 1 T17 15 T31 21 T87 15
wkup[35] 225 1 T13 15 T112 21 T167 15
wkup[36] 162 1 T112 21 T174 21 T94 15
wkup[37] 146 1 T129 21 T109 21 T185 39
wkup[38] 157 1 T117 21 T109 21 T134 21
wkup[39] 78 1 T89 21 T136 15 T138 21
wkup[40] 120 1 T117 21 T127 21 T149 15
wkup[41] 247 1 T31 21 T46 15 T195 8
wkup[42] 84 1 T48 21 T168 21 T152 21
wkup[43] 84 1 T196 6 T173 15 T128 21
wkup[44] 215 1 T27 15 T28 26 T197 8
wkup[45] 78 1 T143 21 T91 6 T144 30
wkup[46] 110 1 T45 8 T28 15 T109 21
wkup[47] 192 1 T141 15 T91 15 T104 30
wkup[48] 238 1 T28 21 T140 15 T117 21
wkup[49] 203 1 T30 15 T175 8 T125 15
wkup[50] 110 1 T28 26 T106 21 T126 21
wkup[51] 99 1 T100 15 T28 21 T135 21
wkup[52] 133 1 T147 15 T126 21 T164 31
wkup[53] 152 1 T45 21 T48 21 T117 21
wkup[54] 266 1 T30 21 T180 21 T29 26
wkup[55] 104 1 T181 15 T29 21 T135 26
wkup[56] 215 1 T29 15 T185 26 T164 15
wkup[57] 236 1 T4 15 T112 21 T106 30
wkup[58] 137 1 T37 15 T27 21 T88 15
wkup[59] 233 1 T129 26 T179 15 T175 8
wkup[60] 152 1 T101 15 T106 21 T87 6
wkup[61] 93 1 T15 15 T23 21 T198 15
wkup[62] 120 1 T27 21 T112 6 T134 21
wkup[63] 128 1 T20 15 T204 15 T168 21
wkup_0 3408 1 T1 5 T2 5 T3 5

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