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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.40 99.32 95.61 100.00 98.38 99.51 43.56


Total test records in report: 424
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T293 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.2054336327 Oct 11 11:44:25 PM UTC 24 Oct 11 11:44:27 PM UTC 24 492158002 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.824069062 Oct 11 11:44:25 PM UTC 24 Oct 11 11:44:27 PM UTC 24 479862716 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4211973260 Oct 11 11:44:23 PM UTC 24 Oct 11 11:44:28 PM UTC 24 4173171638 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.2673967435 Oct 11 11:44:23 PM UTC 24 Oct 11 11:44:28 PM UTC 24 446102523 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1273544534 Oct 11 11:44:26 PM UTC 24 Oct 11 11:44:28 PM UTC 24 717017771 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.2571614362 Oct 11 11:44:26 PM UTC 24 Oct 11 11:44:28 PM UTC 24 447181026 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1072320953 Oct 11 11:44:25 PM UTC 24 Oct 11 11:44:28 PM UTC 24 920123456 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.300813749 Oct 11 11:44:26 PM UTC 24 Oct 11 11:44:28 PM UTC 24 271740867 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1773640305 Oct 11 11:44:26 PM UTC 24 Oct 11 11:44:29 PM UTC 24 527250576 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.726391623 Oct 11 11:44:27 PM UTC 24 Oct 11 11:44:29 PM UTC 24 553240570 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.3787476917 Oct 11 11:44:26 PM UTC 24 Oct 11 11:44:29 PM UTC 24 1267770921 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3553173469 Oct 11 11:44:27 PM UTC 24 Oct 11 11:44:29 PM UTC 24 437372921 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3827694567 Oct 11 11:44:27 PM UTC 24 Oct 11 11:44:29 PM UTC 24 516989798 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1592089355 Oct 11 11:44:27 PM UTC 24 Oct 11 11:44:29 PM UTC 24 632813179 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.467646974 Oct 11 11:44:27 PM UTC 24 Oct 11 11:44:30 PM UTC 24 784054227 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3876309674 Oct 11 11:44:29 PM UTC 24 Oct 11 11:44:31 PM UTC 24 460748887 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2908569003 Oct 11 11:44:27 PM UTC 24 Oct 11 11:44:31 PM UTC 24 7525712724 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.2545721326 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:32 PM UTC 24 540425564 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2948056192 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:32 PM UTC 24 385424849 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3563622192 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:32 PM UTC 24 366757637 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.772756651 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:32 PM UTC 24 356390733 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.3702815790 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:32 PM UTC 24 282502447 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2661403751 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:33 PM UTC 24 506533259 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.118409085 Oct 11 11:44:31 PM UTC 24 Oct 11 11:44:33 PM UTC 24 440630157 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.804581641 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:33 PM UTC 24 1105022341 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2490998830 Oct 11 11:44:29 PM UTC 24 Oct 11 11:44:33 PM UTC 24 2970742060 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4034956669 Oct 11 11:44:31 PM UTC 24 Oct 11 11:44:33 PM UTC 24 807236936 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.400712486 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:33 PM UTC 24 402108970 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.3441169196 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:33 PM UTC 24 559063450 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3414529571 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:33 PM UTC 24 526073861 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3380591246 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:33 PM UTC 24 2085668173 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3526629327 Oct 11 11:44:31 PM UTC 24 Oct 11 11:44:33 PM UTC 24 638852624 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2507879139 Oct 11 11:44:31 PM UTC 24 Oct 11 11:44:33 PM UTC 24 2535052129 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2194309734 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:33 PM UTC 24 406501316 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3311392017 Oct 11 11:44:26 PM UTC 24 Oct 11 11:44:33 PM UTC 24 13484998061 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2900679324 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:33 PM UTC 24 464154809 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.781184419 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:34 PM UTC 24 4700433996 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.3749052065 Oct 11 11:44:32 PM UTC 24 Oct 11 11:44:34 PM UTC 24 336625903 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2844909965 Oct 11 11:44:32 PM UTC 24 Oct 11 11:44:34 PM UTC 24 424763756 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3750114245 Oct 11 11:44:32 PM UTC 24 Oct 11 11:44:35 PM UTC 24 369952773 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.773251862 Oct 11 11:44:33 PM UTC 24 Oct 11 11:44:35 PM UTC 24 321935167 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3716310758 Oct 11 11:44:32 PM UTC 24 Oct 11 11:44:35 PM UTC 24 468744259 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3400810469 Oct 11 11:44:32 PM UTC 24 Oct 11 11:44:35 PM UTC 24 816677815 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.2504693403 Oct 11 11:44:32 PM UTC 24 Oct 11 11:44:35 PM UTC 24 527414266 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3989088101 Oct 11 11:44:31 PM UTC 24 Oct 11 11:44:35 PM UTC 24 6046320051 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1689384675 Oct 11 11:44:32 PM UTC 24 Oct 11 11:44:35 PM UTC 24 998750322 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2526453744 Oct 11 11:44:33 PM UTC 24 Oct 11 11:44:35 PM UTC 24 672519246 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2747980457 Oct 11 11:44:33 PM UTC 24 Oct 11 11:44:36 PM UTC 24 2662646399 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.3227113989 Oct 11 11:44:34 PM UTC 24 Oct 11 11:44:36 PM UTC 24 459046906 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.3569900378 Oct 11 11:44:34 PM UTC 24 Oct 11 11:44:36 PM UTC 24 352590550 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3765225022 Oct 11 11:44:26 PM UTC 24 Oct 11 11:44:36 PM UTC 24 2923900463 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.478242174 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:36 PM UTC 24 4387435428 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.1522933372 Oct 11 11:44:32 PM UTC 24 Oct 11 11:44:36 PM UTC 24 403140271 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.3577887677 Oct 11 11:44:33 PM UTC 24 Oct 11 11:44:36 PM UTC 24 807420045 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3835556214 Oct 11 11:44:30 PM UTC 24 Oct 11 11:44:37 PM UTC 24 5874260412 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.3527081668 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:37 PM UTC 24 647014959 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.268261208 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:37 PM UTC 24 462780131 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.1762735490 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:37 PM UTC 24 485515256 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1164021559 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:37 PM UTC 24 447858388 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.1674472094 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:38 PM UTC 24 477402700 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.2439948589 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:38 PM UTC 24 454304476 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1987653595 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:38 PM UTC 24 571384815 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3609594151 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:38 PM UTC 24 2172935385 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.3213404502 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:38 PM UTC 24 426640632 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1873657184 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:38 PM UTC 24 522925517 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.60217869 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:39 PM UTC 24 2063894804 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.2060759765 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:38 PM UTC 24 484417491 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.1349687127 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:38 PM UTC 24 566514970 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.965527645 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:39 PM UTC 24 385831660 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.1973046593 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:39 PM UTC 24 395965947 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.3182486650 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:39 PM UTC 24 531386554 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.4024691696 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:39 PM UTC 24 502579905 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4160621231 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:39 PM UTC 24 4113767434 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.4071685158 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:39 PM UTC 24 373348715 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3406678690 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:39 PM UTC 24 422660280 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2983336767 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:39 PM UTC 24 321020929 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4065224666 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:39 PM UTC 24 1446237940 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.18778787 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:40 PM UTC 24 455369463 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.3973397909 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:40 PM UTC 24 407995126 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.4293187204 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:40 PM UTC 24 544770063 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1374089206 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:40 PM UTC 24 8364913604 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.769116511 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:40 PM UTC 24 2218208679 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.612251517 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:40 PM UTC 24 799776144 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.613075360 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:40 PM UTC 24 575443561 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.840899656 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:40 PM UTC 24 1341288923 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2967874206 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:40 PM UTC 24 446387198 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3340913982 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 513092387 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2838770403 Oct 11 11:44:43 PM UTC 24 Oct 11 11:44:48 PM UTC 24 4673145529 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.130255897 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:41 PM UTC 24 427286060 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.874929658 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:41 PM UTC 24 363142993 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2609618306 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:41 PM UTC 24 434630366 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1004515261 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:41 PM UTC 24 486332890 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3333991909 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:41 PM UTC 24 546109961 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.789164905 Oct 11 11:44:32 PM UTC 24 Oct 11 11:44:41 PM UTC 24 8191202963 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.665784997 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:42 PM UTC 24 400383880 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1222302708 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:42 PM UTC 24 2228331722 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3134499422 Oct 11 11:44:33 PM UTC 24 Oct 11 11:44:42 PM UTC 24 8554539445 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2602792091 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:42 PM UTC 24 415656837 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3927564555 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:42 PM UTC 24 1225746107 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.4009516429 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:42 PM UTC 24 310781540 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.503675418 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:42 PM UTC 24 344303896 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.3566235450 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:42 PM UTC 24 415520299 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.4216077676 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:43 PM UTC 24 426080119 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.2657687974 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:43 PM UTC 24 809940378 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.142269845 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:43 PM UTC 24 412346444 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.669060566 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:43 PM UTC 24 483985671 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1130136974 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:43 PM UTC 24 475158633 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.1053702145 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:43 PM UTC 24 508005700 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3359342886 Oct 11 11:44:35 PM UTC 24 Oct 11 11:44:43 PM UTC 24 4407972111 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.3014270586 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:43 PM UTC 24 498885858 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.947277843 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:43 PM UTC 24 428410377 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2247105239 Oct 11 11:44:26 PM UTC 24 Oct 11 11:44:43 PM UTC 24 8408707151 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4141273697 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:43 PM UTC 24 1501072813 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1781179914 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:43 PM UTC 24 469869841 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4162412325 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:44 PM UTC 24 495038696 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1550318315 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:44 PM UTC 24 2114363762 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2213720335 Oct 11 11:44:40 PM UTC 24 Oct 11 11:44:44 PM UTC 24 4243878394 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2981613351 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:44 PM UTC 24 8048989924 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.3256064341 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:44 PM UTC 24 432830715 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.419814625 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:44 PM UTC 24 2646303787 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.2728292432 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:44 PM UTC 24 613512499 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3277692115 Oct 11 11:44:42 PM UTC 24 Oct 11 11:44:45 PM UTC 24 469211954 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.1318159680 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:45 PM UTC 24 441832115 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.933076997 Oct 11 11:44:43 PM UTC 24 Oct 11 11:44:45 PM UTC 24 333885304 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.1101887704 Oct 11 11:44:42 PM UTC 24 Oct 11 11:44:45 PM UTC 24 345517269 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.381629715 Oct 11 11:44:43 PM UTC 24 Oct 11 11:44:45 PM UTC 24 505374038 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2763801020 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:45 PM UTC 24 8334612028 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.50042696 Oct 11 11:44:43 PM UTC 24 Oct 11 11:44:45 PM UTC 24 298436499 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.860911232 Oct 11 11:44:43 PM UTC 24 Oct 11 11:44:45 PM UTC 24 451992532 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.940132873 Oct 11 11:44:43 PM UTC 24 Oct 11 11:44:45 PM UTC 24 513658371 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.65189496 Oct 11 11:44:43 PM UTC 24 Oct 11 11:44:45 PM UTC 24 573553783 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2816016804 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:46 PM UTC 24 332111483 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2100219689 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:46 PM UTC 24 2125979995 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3606624312 Oct 11 11:44:42 PM UTC 24 Oct 11 11:44:46 PM UTC 24 1452349327 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2621805087 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:46 PM UTC 24 2424791230 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.3736679460 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:46 PM UTC 24 513402734 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.2802620237 Oct 11 11:44:42 PM UTC 24 Oct 11 11:44:46 PM UTC 24 1001297693 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.3177326047 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:46 PM UTC 24 402677989 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.246687814 Oct 11 11:44:43 PM UTC 24 Oct 11 11:44:46 PM UTC 24 1221671530 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2694999934 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:46 PM UTC 24 603605151 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.2229468379 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:46 PM UTC 24 288620920 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.744534181 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:46 PM UTC 24 287650784 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.3361481903 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:46 PM UTC 24 417575123 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.3011711209 Oct 11 11:44:45 PM UTC 24 Oct 11 11:44:46 PM UTC 24 502870500 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.29597285 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:46 PM UTC 24 511335088 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3361974256 Oct 11 11:44:45 PM UTC 24 Oct 11 11:44:47 PM UTC 24 517106276 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.2922197799 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:47 PM UTC 24 324686201 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3478826800 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:47 PM UTC 24 525028626 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.844183941 Oct 11 11:44:45 PM UTC 24 Oct 11 11:44:47 PM UTC 24 441187683 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.2735583982 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:47 PM UTC 24 477188818 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.3316874240 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:47 PM UTC 24 449231554 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2570295722 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:47 PM UTC 24 8692214752 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.676684054 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:47 PM UTC 24 450292408 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.4202111079 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 478247027 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.1718935675 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:47 PM UTC 24 451122973 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2875988031 Oct 11 11:44:39 PM UTC 24 Oct 11 11:44:48 PM UTC 24 3973021855 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.2079945144 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 436498924 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.2471342028 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 285030020 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.1399186924 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 335171898 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1695507228 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 327009921 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.729997900 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 335249657 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.445247516 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 350749611 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.535121931 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 337822731 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.69616234 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 464040244 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.3157701054 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 389144378 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.73668513 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:48 PM UTC 24 420018727 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.858496470 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:49 PM UTC 24 350150202 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.1578650513 Oct 11 11:44:46 PM UTC 24 Oct 11 11:44:49 PM UTC 24 457528865 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.735254738 Oct 11 11:44:44 PM UTC 24 Oct 11 11:44:49 PM UTC 24 2357700631 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.466339340 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:50 PM UTC 24 4417536040 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3483602523 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:53 PM UTC 24 8554492513 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.977725423 Oct 11 11:44:41 PM UTC 24 Oct 11 11:44:54 PM UTC 24 8338919135 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.304737497 Oct 11 11:44:37 PM UTC 24 Oct 11 11:44:55 PM UTC 24 8723753001 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1825109454 Oct 11 11:44:43 PM UTC 24 Oct 11 11:44:58 PM UTC 24 8016847372 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/1.aon_timer_jump.229579732
Short name T3
Test name
Test status
Simulation time 478569623 ps
CPU time 0.81 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:50 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229579732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.229579732
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all_with_rand_reset.1276435605
Short name T30
Test name
Test status
Simulation time 1523396077 ps
CPU time 8.11 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:45:02 PM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1276435605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.aon_timer_stress_all_with_rand_reset.1276435605
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/4.aon_timer_jump.511218275
Short name T13
Test name
Test status
Simulation time 605804226 ps
CPU time 0.97 seconds
Started Oct 11 11:44:49 PM UTC 24
Finished Oct 11 11:44:51 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511218275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.511218275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4211973260
Short name T38
Test name
Test status
Simulation time 4173171638 ps
CPU time 3.11 seconds
Started Oct 11 11:44:23 PM UTC 24
Finished Oct 11 11:44:28 PM UTC 24
Peak memory 200948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211973260 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.4211973260
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all_with_rand_reset.1436365177
Short name T45
Test name
Test status
Simulation time 6556703394 ps
CPU time 14.28 seconds
Started Oct 11 11:44:47 PM UTC 24
Finished Oct 11 11:45:03 PM UTC 24
Peak memory 217724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1436365177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.aon_timer_stress_all_with_rand_reset.1436365177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all.3951983535
Short name T27
Test name
Test status
Simulation time 30482780742 ps
CPU time 8.9 seconds
Started Oct 11 11:44:58 PM UTC 24
Finished Oct 11 11:45:08 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951983535 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.3951983535
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.804581641
Short name T60
Test name
Test status
Simulation time 1105022341 ps
CPU time 1.54 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804581641 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.804581641
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all_with_rand_reset.3221940977
Short name T117
Test name
Test status
Simulation time 9985784114 ps
CPU time 31.32 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:45:26 PM UTC 24
Peak memory 218172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3221940977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 11.aon_timer_stress_all_with_rand_reset.3221940977
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all.1574524422
Short name T119
Test name
Test status
Simulation time 159326557452 ps
CPU time 58.05 seconds
Started Oct 11 11:45:18 PM UTC 24
Finished Oct 11 11:46:17 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574524422 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.1574524422
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/27.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all.1373356616
Short name T120
Test name
Test status
Simulation time 76853127629 ps
CPU time 113.25 seconds
Started Oct 11 11:44:51 PM UTC 24
Finished Oct 11 11:46:47 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373356616 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.1373356616
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/0.aon_timer_sec_cm.4183108067
Short name T26
Test name
Test status
Simulation time 4327230343 ps
CPU time 3.59 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:52 PM UTC 24
Peak memory 233940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183108067 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4183108067
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all_with_rand_reset.11724198
Short name T23
Test name
Test status
Simulation time 6541302581 ps
CPU time 7.06 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:56 PM UTC 24
Peak memory 218800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=11724198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 1.aon_timer_stress_all_with_rand_reset.11724198
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all_with_rand_reset.2008893286
Short name T108
Test name
Test status
Simulation time 18095687894 ps
CPU time 49.97 seconds
Started Oct 11 11:45:47 PM UTC 24
Finished Oct 11 11:46:39 PM UTC 24
Peak memory 218052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2008893286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 38.aon_timer_stress_all_with_rand_reset.2008893286
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all.1388059711
Short name T111
Test name
Test status
Simulation time 53425248453 ps
CPU time 76.77 seconds
Started Oct 11 11:45:34 PM UTC 24
Finished Oct 11 11:46:52 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388059711 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.1388059711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/32.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/0.aon_timer_stress_all.4239869991
Short name T129
Test name
Test status
Simulation time 97028455448 ps
CPU time 39.3 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:45:28 PM UTC 24
Peak memory 203472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239869991 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.4239869991
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/11.aon_timer_stress_all.1595045339
Short name T130
Test name
Test status
Simulation time 185504835098 ps
CPU time 155.63 seconds
Started Oct 11 11:44:54 PM UTC 24
Finished Oct 11 11:47:33 PM UTC 24
Peak memory 203288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595045339 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.1595045339
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all.942731435
Short name T124
Test name
Test status
Simulation time 439318204169 ps
CPU time 614.26 seconds
Started Oct 11 11:45:49 PM UTC 24
Finished Oct 11 11:56:10 PM UTC 24
Peak memory 206564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942731435 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.942731435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/39.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all.2895392159
Short name T138
Test name
Test status
Simulation time 129449083497 ps
CPU time 223.67 seconds
Started Oct 11 11:44:51 PM UTC 24
Finished Oct 11 11:48:38 PM UTC 24
Peak memory 203272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895392159 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.2895392159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all_with_rand_reset.1888492097
Short name T106
Test name
Test status
Simulation time 7534195504 ps
CPU time 38.76 seconds
Started Oct 11 11:44:49 PM UTC 24
Finished Oct 11 11:45:30 PM UTC 24
Peak memory 209064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1888492097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 4.aon_timer_stress_all_with_rand_reset.1888492097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all.661207254
Short name T110
Test name
Test status
Simulation time 109373609135 ps
CPU time 114.85 seconds
Started Oct 11 11:45:55 PM UTC 24
Finished Oct 11 11:47:52 PM UTC 24
Peak memory 203268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661207254 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.661207254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/42.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all.2098889908
Short name T122
Test name
Test status
Simulation time 139475864254 ps
CPU time 225.33 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:48:51 PM UTC 24
Peak memory 203412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098889908 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.2098889908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all.3890607670
Short name T161
Test name
Test status
Simulation time 324040616437 ps
CPU time 223.61 seconds
Started Oct 11 11:45:51 PM UTC 24
Finished Oct 11 11:49:38 PM UTC 24
Peak memory 203672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890607670 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.3890607670
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/40.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all.2108950824
Short name T143
Test name
Test status
Simulation time 68168920841 ps
CPU time 25.91 seconds
Started Oct 11 11:45:07 PM UTC 24
Finished Oct 11 11:45:35 PM UTC 24
Peak memory 203608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108950824 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.2108950824
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/20.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/47.aon_timer_stress_all.1832528427
Short name T151
Test name
Test status
Simulation time 178050172278 ps
CPU time 348.68 seconds
Started Oct 11 11:46:07 PM UTC 24
Finished Oct 11 11:52:03 PM UTC 24
Peak memory 203356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832528427 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.1832528427
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/47.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/15.aon_timer_stress_all_with_rand_reset.649983221
Short name T126
Test name
Test status
Simulation time 9831690756 ps
CPU time 50.65 seconds
Started Oct 11 11:44:58 PM UTC 24
Finished Oct 11 11:45:50 PM UTC 24
Peak memory 214632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=649983221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 15.aon_timer_stress_all_with_rand_reset.649983221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/7.aon_timer_stress_all_with_rand_reset.1251127341
Short name T31
Test name
Test status
Simulation time 4746420619 ps
CPU time 11.03 seconds
Started Oct 11 11:44:51 PM UTC 24
Finished Oct 11 11:45:03 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1251127341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 7.aon_timer_stress_all_with_rand_reset.1251127341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all.1611842887
Short name T148
Test name
Test status
Simulation time 181664024278 ps
CPU time 93.4 seconds
Started Oct 11 11:45:24 PM UTC 24
Finished Oct 11 11:47:00 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611842887 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.1611842887
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/29.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all.2909469802
Short name T103
Test name
Test status
Simulation time 312321273639 ps
CPU time 511.53 seconds
Started Oct 11 11:46:15 PM UTC 24
Finished Oct 11 11:54:52 PM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909469802 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.2909469802
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/49.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all_with_rand_reset.3802675765
Short name T109
Test name
Test status
Simulation time 43825503055 ps
CPU time 25.22 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:45:29 PM UTC 24
Peak memory 223844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3802675765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 18.aon_timer_stress_all_with_rand_reset.3802675765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/36.aon_timer_stress_all.2408361271
Short name T136
Test name
Test status
Simulation time 247352456192 ps
CPU time 139.41 seconds
Started Oct 11 11:45:43 PM UTC 24
Finished Oct 11 11:48:05 PM UTC 24
Peak memory 203416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408361271 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.2408361271
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/36.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/10.aon_timer_stress_all.2917118312
Short name T28
Test name
Test status
Simulation time 259594087479 ps
CPU time 22.93 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:45:17 PM UTC 24
Peak memory 203288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917118312 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.2917118312
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all.1621981658
Short name T113
Test name
Test status
Simulation time 101179155458 ps
CPU time 160.42 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:47:31 PM UTC 24
Peak memory 206628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621981658 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.1621981658
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all.1032744922
Short name T162
Test name
Test status
Simulation time 181163883555 ps
CPU time 79.24 seconds
Started Oct 11 11:45:41 PM UTC 24
Finished Oct 11 11:47:02 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032744922 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.1032744922
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/35.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all.3490032815
Short name T123
Test name
Test status
Simulation time 274661858037 ps
CPU time 184.92 seconds
Started Oct 11 11:45:57 PM UTC 24
Finished Oct 11 11:49:12 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490032815 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.3490032815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/43.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all_with_rand_reset.2682593912
Short name T144
Test name
Test status
Simulation time 3583275538 ps
CPU time 27.56 seconds
Started Oct 11 11:46:00 PM UTC 24
Finished Oct 11 11:46:38 PM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2682593912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 45.aon_timer_stress_all_with_rand_reset.2682593912
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all.2614083551
Short name T128
Test name
Test status
Simulation time 115642179325 ps
CPU time 174.42 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:47:59 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614083551 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.2614083551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/7.aon_timer_jump.796486608
Short name T15
Test name
Test status
Simulation time 582416190 ps
CPU time 0.87 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:44:52 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796486608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.796486608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all.2553812453
Short name T131
Test name
Test status
Simulation time 79620507678 ps
CPU time 51.16 seconds
Started Oct 11 11:44:57 PM UTC 24
Finished Oct 11 11:45:51 PM UTC 24
Peak memory 203608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553812453 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.2553812453
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all_with_rand_reset.666546839
Short name T92
Test name
Test status
Simulation time 2846327171 ps
CPU time 18.16 seconds
Started Oct 11 11:45:30 PM UTC 24
Finished Oct 11 11:45:49 PM UTC 24
Peak memory 217960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=666546839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 31.aon_timer_stress_all_with_rand_reset.666546839
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/38.aon_timer_stress_all.1149550992
Short name T166
Test name
Test status
Simulation time 131550073742 ps
CPU time 82.72 seconds
Started Oct 11 11:45:47 PM UTC 24
Finished Oct 11 11:47:12 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149550992 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.1149550992
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/38.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all.3579344519
Short name T145
Test name
Test status
Simulation time 233946830229 ps
CPU time 370.6 seconds
Started Oct 11 11:45:59 PM UTC 24
Finished Oct 11 11:52:24 PM UTC 24
Peak memory 206576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579344519 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.3579344519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/44.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all.3786114691
Short name T29
Test name
Test status
Simulation time 25679784399 ps
CPU time 15.49 seconds
Started Oct 11 11:45:05 PM UTC 24
Finished Oct 11 11:45:22 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786114691 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.3786114691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/4.aon_timer_stress_all.3773292444
Short name T152
Test name
Test status
Simulation time 174398755055 ps
CPU time 243.05 seconds
Started Oct 11 11:44:49 PM UTC 24
Finished Oct 11 11:48:56 PM UTC 24
Peak memory 206580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773292444 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.3773292444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/16.aon_timer_stress_all_with_rand_reset.916787534
Short name T174
Test name
Test status
Simulation time 3269589191 ps
CPU time 23.13 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:45:27 PM UTC 24
Peak memory 217048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=916787534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.aon_timer_stress_all_with_rand_reset.916787534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all.206923045
Short name T104
Test name
Test status
Simulation time 59824460446 ps
CPU time 68.95 seconds
Started Oct 11 11:45:07 PM UTC 24
Finished Oct 11 11:46:18 PM UTC 24
Peak memory 203244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206923045 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.206923045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/21.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all.2457438464
Short name T107
Test name
Test status
Simulation time 349364467136 ps
CPU time 70.59 seconds
Started Oct 11 11:45:17 PM UTC 24
Finished Oct 11 11:46:30 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457438464 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.2457438464
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/26.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all.740424716
Short name T134
Test name
Test status
Simulation time 44643081354 ps
CPU time 20.69 seconds
Started Oct 11 11:45:22 PM UTC 24
Finished Oct 11 11:45:44 PM UTC 24
Peak memory 203272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740424716 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.740424716
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/28.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/28.aon_timer_stress_all_with_rand_reset.4202024403
Short name T89
Test name
Test status
Simulation time 9255354776 ps
CPU time 22.03 seconds
Started Oct 11 11:45:20 PM UTC 24
Finished Oct 11 11:45:43 PM UTC 24
Peak memory 221332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4202024403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 28.aon_timer_stress_all_with_rand_reset.4202024403
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all.54443061
Short name T150
Test name
Test status
Simulation time 266716512941 ps
CPU time 173.67 seconds
Started Oct 11 11:45:52 PM UTC 24
Finished Oct 11 11:48:49 PM UTC 24
Peak memory 203664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54443061 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.54443061
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/41.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all.2958124337
Short name T135
Test name
Test status
Simulation time 88992753625 ps
CPU time 38.43 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:45:30 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958124337 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.2958124337
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/35.aon_timer_stress_all_with_rand_reset.423097140
Short name T114
Test name
Test status
Simulation time 2762251468 ps
CPU time 13.2 seconds
Started Oct 11 11:45:41 PM UTC 24
Finished Oct 11 11:45:55 PM UTC 24
Peak memory 208960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=423097140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 35.aon_timer_stress_all_with_rand_reset.423097140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/39.aon_timer_stress_all_with_rand_reset.3186335065
Short name T178
Test name
Test status
Simulation time 8048188576 ps
CPU time 15.77 seconds
Started Oct 11 11:45:49 PM UTC 24
Finished Oct 11 11:46:06 PM UTC 24
Peak memory 217988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3186335065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 39.aon_timer_stress_all_with_rand_reset.3186335065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all.2040929076
Short name T116
Test name
Test status
Simulation time 101705531372 ps
CPU time 148.83 seconds
Started Oct 11 11:46:13 PM UTC 24
Finished Oct 11 11:48:44 PM UTC 24
Peak memory 203608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040929076 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.2040929076
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/48.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3765225022
Short name T80
Test name
Test status
Simulation time 2923900463 ps
CPU time 8.7 seconds
Started Oct 11 11:44:26 PM UTC 24
Finished Oct 11 11:44:36 PM UTC 24
Peak memory 200940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765225022 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.3765225022
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/2.aon_timer_stress_all_with_rand_reset.2367391012
Short name T48
Test name
Test status
Simulation time 2427642002 ps
CPU time 21.18 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:45:11 PM UTC 24
Peak memory 209000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2367391012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 2.aon_timer_stress_all_with_rand_reset.2367391012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all.3526832030
Short name T172
Test name
Test status
Simulation time 184906167560 ps
CPU time 257.2 seconds
Started Oct 11 11:45:10 PM UTC 24
Finished Oct 11 11:49:30 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526832030 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.3526832030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/22.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/31.aon_timer_stress_all.1992595693
Short name T158
Test name
Test status
Simulation time 159362657519 ps
CPU time 56.82 seconds
Started Oct 11 11:45:30 PM UTC 24
Finished Oct 11 11:46:28 PM UTC 24
Peak memory 203272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992595693 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.1992595693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/31.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all.3603318876
Short name T127
Test name
Test status
Simulation time 43612564971 ps
CPU time 37.74 seconds
Started Oct 11 11:45:38 PM UTC 24
Finished Oct 11 11:46:18 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603318876 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.3603318876
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/34.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/40.aon_timer_stress_all_with_rand_reset.1783041660
Short name T155
Test name
Test status
Simulation time 9578802776 ps
CPU time 23.92 seconds
Started Oct 11 11:45:50 PM UTC 24
Finished Oct 11 11:46:15 PM UTC 24
Peak memory 216828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1783041660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 40.aon_timer_stress_all_with_rand_reset.1783041660
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/44.aon_timer_stress_all_with_rand_reset.4203144968
Short name T186
Test name
Test status
Simulation time 10985432964 ps
CPU time 45.35 seconds
Started Oct 11 11:45:58 PM UTC 24
Finished Oct 11 11:46:56 PM UTC 24
Peak memory 209032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4203144968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 44.aon_timer_stress_all_with_rand_reset.4203144968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/45.aon_timer_stress_all.752987975
Short name T133
Test name
Test status
Simulation time 107520634401 ps
CPU time 168.5 seconds
Started Oct 11 11:46:00 PM UTC 24
Finished Oct 11 11:49:01 PM UTC 24
Peak memory 203408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752987975 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.752987975
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/45.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/13.aon_timer_jump.2450950461
Short name T35
Test name
Test status
Simulation time 403706151 ps
CPU time 1.47 seconds
Started Oct 11 11:44:56 PM UTC 24
Finished Oct 11 11:44:59 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450950461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2450950461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/18.aon_timer_jump.2599539772
Short name T101
Test name
Test status
Simulation time 415806801 ps
CPU time 1.31 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:45:05 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599539772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2599539772
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/26.aon_timer_jump.3076439873
Short name T159
Test name
Test status
Simulation time 346483205 ps
CPU time 1.42 seconds
Started Oct 11 11:45:15 PM UTC 24
Finished Oct 11 11:45:18 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076439873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3076439873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/26.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/27.aon_timer_jump.2816173188
Short name T169
Test name
Test status
Simulation time 334677939 ps
CPU time 1.85 seconds
Started Oct 11 11:45:18 PM UTC 24
Finished Oct 11 11:45:21 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816173188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2816173188
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/27.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all_with_rand_reset.2558674514
Short name T185
Test name
Test status
Simulation time 18304704347 ps
CPU time 50.94 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:45:41 PM UTC 24
Peak memory 209188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2558674514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 3.aon_timer_stress_all_with_rand_reset.2558674514
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/33.aon_timer_stress_all.1847953347
Short name T170
Test name
Test status
Simulation time 88263504562 ps
CPU time 77.33 seconds
Started Oct 11 11:45:36 PM UTC 24
Finished Oct 11 11:46:55 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847953347 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.1847953347
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/33.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/5.aon_timer_stress_all_with_rand_reset.3645990065
Short name T112
Test name
Test status
Simulation time 3860664676 ps
CPU time 33 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:45:24 PM UTC 24
Peak memory 214704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3645990065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 5.aon_timer_stress_all_with_rand_reset.3645990065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/8.aon_timer_jump.3673621509
Short name T20
Test name
Test status
Simulation time 563343674 ps
CPU time 0.99 seconds
Started Oct 11 11:44:51 PM UTC 24
Finished Oct 11 11:44:53 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673621509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3673621509
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/20.aon_timer_jump.2045461753
Short name T156
Test name
Test status
Simulation time 481533157 ps
CPU time 1.94 seconds
Started Oct 11 11:45:05 PM UTC 24
Finished Oct 11 11:45:08 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045461753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2045461753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/20.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all.3489379294
Short name T149
Test name
Test status
Simulation time 93659143842 ps
CPU time 73.25 seconds
Started Oct 11 11:45:12 PM UTC 24
Finished Oct 11 11:46:27 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489379294 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.3489379294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/23.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/27.aon_timer_stress_all_with_rand_reset.210020324
Short name T87
Test name
Test status
Simulation time 2060814200 ps
CPU time 14.04 seconds
Started Oct 11 11:45:18 PM UTC 24
Finished Oct 11 11:45:33 PM UTC 24
Peak memory 217784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=210020324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 27.aon_timer_stress_all_with_rand_reset.210020324
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/32.aon_timer_jump.3354119495
Short name T125
Test name
Test status
Simulation time 378162839 ps
CPU time 1.58 seconds
Started Oct 11 11:45:30 PM UTC 24
Finished Oct 11 11:45:33 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354119495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3354119495
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/32.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/43.aon_timer_jump.719213793
Short name T165
Test name
Test status
Simulation time 544839644 ps
CPU time 0.96 seconds
Started Oct 11 11:45:56 PM UTC 24
Finished Oct 11 11:45:58 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719213793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.719213793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/43.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/43.aon_timer_stress_all_with_rand_reset.86556274
Short name T160
Test name
Test status
Simulation time 3477950122 ps
CPU time 8.28 seconds
Started Oct 11 11:45:57 PM UTC 24
Finished Oct 11 11:46:13 PM UTC 24
Peak memory 220848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=86556274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 43.aon_timer_stress_all_with_rand_reset.86556274
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/45.aon_timer_jump.184325366
Short name T173
Test name
Test status
Simulation time 507106503 ps
CPU time 2.31 seconds
Started Oct 11 11:45:59 PM UTC 24
Finished Oct 11 11:46:13 PM UTC 24
Peak memory 203148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184325366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.184325366
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/45.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all.3748979053
Short name T171
Test name
Test status
Simulation time 267801599718 ps
CPU time 441.32 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:52:17 PM UTC 24
Peak memory 206564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748979053 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.3748979053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/0.aon_timer_jump.4194768548
Short name T2
Test name
Test status
Simulation time 379664005 ps
CPU time 0.92 seconds
Started Oct 11 11:44:47 PM UTC 24
Finished Oct 11 11:44:50 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194768548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4194768548
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/21.aon_timer_jump.334422325
Short name T141
Test name
Test status
Simulation time 580626010 ps
CPU time 0.93 seconds
Started Oct 11 11:45:07 PM UTC 24
Finished Oct 11 11:45:10 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334422325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.334422325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/21.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/22.aon_timer_jump.3808629495
Short name T147
Test name
Test status
Simulation time 473476291 ps
CPU time 0.89 seconds
Started Oct 11 11:45:10 PM UTC 24
Finished Oct 11 11:45:12 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808629495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3808629495
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/22.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/29.aon_timer_jump.3641672539
Short name T167
Test name
Test status
Simulation time 599803604 ps
CPU time 0.99 seconds
Started Oct 11 11:45:24 PM UTC 24
Finished Oct 11 11:45:26 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641672539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3641672539
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/29.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/41.aon_timer_jump.1032545353
Short name T142
Test name
Test status
Simulation time 422078385 ps
CPU time 1.17 seconds
Started Oct 11 11:45:51 PM UTC 24
Finished Oct 11 11:45:53 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032545353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1032545353
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/41.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all.1385475871
Short name T189
Test name
Test status
Simulation time 417333829139 ps
CPU time 50.43 seconds
Started Oct 11 11:45:12 PM UTC 24
Finished Oct 11 11:46:04 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385475871 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.1385475871
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/24.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/24.aon_timer_stress_all_with_rand_reset.2813141863
Short name T88
Test name
Test status
Simulation time 12593647064 ps
CPU time 25.8 seconds
Started Oct 11 11:45:12 PM UTC 24
Finished Oct 11 11:45:39 PM UTC 24
Peak memory 220728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2813141863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 24.aon_timer_stress_all_with_rand_reset.2813141863
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/25.aon_timer_jump.4261325530
Short name T140
Test name
Test status
Simulation time 436065003 ps
CPU time 1.15 seconds
Started Oct 11 11:45:13 PM UTC 24
Finished Oct 11 11:45:15 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261325530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4261325530
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/25.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/37.aon_timer_stress_all_with_rand_reset.1396667725
Short name T168
Test name
Test status
Simulation time 11659275308 ps
CPU time 28.1 seconds
Started Oct 11 11:45:45 PM UTC 24
Finished Oct 11 11:46:15 PM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1396667725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 37.aon_timer_stress_all_with_rand_reset.1396667725
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/47.aon_timer_jump.1604587898
Short name T118
Test name
Test status
Simulation time 450136406 ps
CPU time 0.95 seconds
Started Oct 11 11:46:06 PM UTC 24
Finished Oct 11 11:46:08 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604587898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1604587898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/47.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/49.aon_timer_stress_all_with_rand_reset.2816347920
Short name T164
Test name
Test status
Simulation time 6805102573 ps
CPU time 9.95 seconds
Started Oct 11 11:46:14 PM UTC 24
Finished Oct 11 11:46:26 PM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2816347920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 49.aon_timer_stress_all_with_rand_reset.2816347920
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/0.aon_timer_smoke.3834463878
Short name T1
Test name
Test status
Simulation time 438989930 ps
CPU time 0.79 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 202576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834463878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3834463878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/10.aon_timer_jump.2373316903
Short name T34
Test name
Test status
Simulation time 430011400 ps
CPU time 1.13 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:44:55 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373316903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2373316903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all.4022702003
Short name T182
Test name
Test status
Simulation time 274253797369 ps
CPU time 63.09 seconds
Started Oct 11 11:44:55 PM UTC 24
Finished Oct 11 11:45:59 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022702003 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.4022702003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/15.aon_timer_jump.3659870238
Short name T37
Test name
Test status
Simulation time 589164339 ps
CPU time 1.24 seconds
Started Oct 11 11:44:57 PM UTC 24
Finished Oct 11 11:45:00 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659870238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3659870238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/18.aon_timer_stress_all.3450553640
Short name T115
Test name
Test status
Simulation time 159451000095 ps
CPU time 271.83 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:49:38 PM UTC 24
Peak memory 203416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450553640 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.3450553640
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/19.aon_timer_stress_all_with_rand_reset.1013340137
Short name T105
Test name
Test status
Simulation time 5480593395 ps
CPU time 49.33 seconds
Started Oct 11 11:45:05 PM UTC 24
Finished Oct 11 11:45:56 PM UTC 24
Peak memory 220868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1013340137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 19.aon_timer_stress_all_with_rand_reset.1013340137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/2.aon_timer_jump.1862838041
Short name T4
Test name
Test status
Simulation time 407436909 ps
CPU time 1 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:50 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862838041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1862838041
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/29.aon_timer_stress_all_with_rand_reset.1307502873
Short name T93
Test name
Test status
Simulation time 11032550463 ps
CPU time 24.07 seconds
Started Oct 11 11:45:24 PM UTC 24
Finished Oct 11 11:45:50 PM UTC 24
Peak memory 218056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1307502873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.aon_timer_stress_all_with_rand_reset.1307502873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/48.aon_timer_jump.1710359525
Short name T154
Test name
Test status
Simulation time 580151898 ps
CPU time 2.74 seconds
Started Oct 11 11:46:09 PM UTC 24
Finished Oct 11 11:46:13 PM UTC 24
Peak memory 203548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710359525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1710359525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/48.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/11.aon_timer_jump.2152195681
Short name T21
Test name
Test status
Simulation time 533995482 ps
CPU time 0.85 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:44:55 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152195681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2152195681
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all_with_rand_reset.2654514573
Short name T49
Test name
Test status
Simulation time 3426090713 ps
CPU time 14.04 seconds
Started Oct 11 11:44:56 PM UTC 24
Finished Oct 11 11:45:11 PM UTC 24
Peak memory 217464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2654514573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 13.aon_timer_stress_all_with_rand_reset.2654514573
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/25.aon_timer_stress_all_with_rand_reset.879278382
Short name T197
Test name
Test status
Simulation time 1952571013 ps
CPU time 19.21 seconds
Started Oct 11 11:45:15 PM UTC 24
Finished Oct 11 11:45:36 PM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=879278382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 25.aon_timer_stress_all_with_rand_reset.879278382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/26.aon_timer_stress_all_with_rand_reset.4230498451
Short name T91
Test name
Test status
Simulation time 8621760310 ps
CPU time 29.81 seconds
Started Oct 11 11:45:15 PM UTC 24
Finished Oct 11 11:45:47 PM UTC 24
Peak memory 218028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4230498451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 26.aon_timer_stress_all_with_rand_reset.4230498451
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/35.aon_timer_jump.1983839863
Short name T153
Test name
Test status
Simulation time 490287183 ps
CPU time 1.02 seconds
Started Oct 11 11:45:40 PM UTC 24
Finished Oct 11 11:45:42 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983839863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1983839863
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/35.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_intg_err.789164905
Short name T207
Test name
Test status
Simulation time 8191202963 ps
CPU time 8.04 seconds
Started Oct 11 11:44:32 PM UTC 24
Finished Oct 11 11:44:41 PM UTC 24
Peak memory 206360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789164905 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.789164905
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/12.aon_timer_jump.3991348180
Short name T51
Test name
Test status
Simulation time 603813186 ps
CPU time 0.95 seconds
Started Oct 11 11:44:54 PM UTC 24
Finished Oct 11 11:44:56 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991348180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3991348180
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all.422069894
Short name T187
Test name
Test status
Simulation time 610033637274 ps
CPU time 1220.38 seconds
Started Oct 11 11:45:27 PM UTC 24
Finished Oct 12 12:06:00 AM UTC 24
Peak memory 206636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422069894 -assert nopostproc +UVM_TESTNAM
E=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.422069894
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/30.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/30.aon_timer_stress_all_with_rand_reset.959484285
Short name T190
Test name
Test status
Simulation time 3984372267 ps
CPU time 20.26 seconds
Started Oct 11 11:45:27 PM UTC 24
Finished Oct 11 11:45:48 PM UTC 24
Peak memory 216704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=959484285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 30.aon_timer_stress_all_with_rand_reset.959484285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/31.aon_timer_jump.2593450356
Short name T132
Test name
Test status
Simulation time 422688085 ps
CPU time 1.26 seconds
Started Oct 11 11:45:29 PM UTC 24
Finished Oct 11 11:45:31 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593450356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2593450356
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/31.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/33.aon_timer_jump.1909687421
Short name T157
Test name
Test status
Simulation time 427249469 ps
CPU time 1.03 seconds
Started Oct 11 11:45:36 PM UTC 24
Finished Oct 11 11:45:38 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909687421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1909687421
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/33.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/36.aon_timer_jump.2440221010
Short name T201
Test name
Test status
Simulation time 604204934 ps
CPU time 2.93 seconds
Started Oct 11 11:45:43 PM UTC 24
Finished Oct 11 11:45:47 PM UTC 24
Peak memory 203484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440221010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2440221010
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/36.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/37.aon_timer_jump.2636757422
Short name T163
Test name
Test status
Simulation time 506047092 ps
CPU time 1.2 seconds
Started Oct 11 11:45:45 PM UTC 24
Finished Oct 11 11:45:47 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636757422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2636757422
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/37.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/42.aon_timer_jump.623714383
Short name T146
Test name
Test status
Simulation time 527982176 ps
CPU time 1.91 seconds
Started Oct 11 11:45:54 PM UTC 24
Finished Oct 11 11:45:56 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623714383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.623714383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/42.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/44.aon_timer_jump.1506268410
Short name T177
Test name
Test status
Simulation time 643558671 ps
CPU time 1.81 seconds
Started Oct 11 11:45:58 PM UTC 24
Finished Oct 11 11:46:12 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506268410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1506268410
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/44.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/5.aon_timer_jump.977256330
Short name T17
Test name
Test status
Simulation time 548103087 ps
CPU time 1.45 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:44:52 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977256330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.977256330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/8.aon_timer_stress_all_with_rand_reset.534176584
Short name T199
Test name
Test status
Simulation time 15335591138 ps
CPU time 47.14 seconds
Started Oct 11 11:44:51 PM UTC 24
Finished Oct 11 11:45:40 PM UTC 24
Peak memory 220852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=534176584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.aon_timer_stress_all_with_rand_reset.534176584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all.2230041606
Short name T188
Test name
Test status
Simulation time 340505124161 ps
CPU time 134.76 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:47:10 PM UTC 24
Peak memory 203284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230041606 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.2230041606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/9.aon_timer_stress_all_with_rand_reset.4208132507
Short name T46
Test name
Test status
Simulation time 6433093834 ps
CPU time 13.13 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:45:07 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4208132507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 9.aon_timer_stress_all_with_rand_reset.4208132507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/13.aon_timer_stress_all.2775572837
Short name T205
Test name
Test status
Simulation time 393027090295 ps
CPU time 323.02 seconds
Started Oct 11 11:44:56 PM UTC 24
Finished Oct 11 11:50:23 PM UTC 24
Peak memory 206580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775572837 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.2775572837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/14.aon_timer_stress_all_with_rand_reset.24832637
Short name T24
Test name
Test status
Simulation time 989000255 ps
CPU time 3.53 seconds
Started Oct 11 11:44:56 PM UTC 24
Finished Oct 11 11:45:01 PM UTC 24
Peak memory 219808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=24832637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 14.aon_timer_stress_all_with_rand_reset.24832637
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/16.aon_timer_jump.1088595132
Short name T203
Test name
Test status
Simulation time 513237593 ps
CPU time 1.61 seconds
Started Oct 11 11:45:00 PM UTC 24
Finished Oct 11 11:45:03 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088595132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1088595132
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/22.aon_timer_stress_all_with_rand_reset.897111265
Short name T176
Test name
Test status
Simulation time 2441682747 ps
CPU time 19.05 seconds
Started Oct 11 11:45:10 PM UTC 24
Finished Oct 11 11:45:30 PM UTC 24
Peak memory 217336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=897111265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.aon_timer_stress_all_with_rand_reset.897111265
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/23.aon_timer_jump.2713250549
Short name T137
Test name
Test status
Simulation time 555218227 ps
CPU time 1.64 seconds
Started Oct 11 11:45:10 PM UTC 24
Finished Oct 11 11:45:13 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713250549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2713250549
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/23.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/24.aon_timer_jump.278531545
Short name T184
Test name
Test status
Simulation time 519143739 ps
CPU time 1.02 seconds
Started Oct 11 11:45:12 PM UTC 24
Finished Oct 11 11:45:14 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278531545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.278531545
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/24.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/30.aon_timer_jump.4015600227
Short name T179
Test name
Test status
Simulation time 342721806 ps
CPU time 2.06 seconds
Started Oct 11 11:45:27 PM UTC 24
Finished Oct 11 11:45:30 PM UTC 24
Peak memory 203136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015600227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4015600227
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/30.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/39.aon_timer_jump.2769694520
Short name T183
Test name
Test status
Simulation time 516291361 ps
CPU time 1.47 seconds
Started Oct 11 11:45:49 PM UTC 24
Finished Oct 11 11:45:51 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769694520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2769694520
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/39.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/46.aon_timer_jump.2780514966
Short name T192
Test name
Test status
Simulation time 564381061 ps
CPU time 1.02 seconds
Started Oct 11 11:46:02 PM UTC 24
Finished Oct 11 11:46:07 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780514966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2780514966
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/46.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/49.aon_timer_jump.2009562972
Short name T202
Test name
Test status
Simulation time 535761487 ps
CPU time 1.79 seconds
Started Oct 11 11:46:14 PM UTC 24
Finished Oct 11 11:46:18 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009562972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2009562972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/49.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/9.aon_timer_jump.2981238196
Short name T200
Test name
Test status
Simulation time 584409754 ps
CPU time 1.43 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:44:55 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981238196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2981238196
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/20.aon_timer_stress_all_with_rand_reset.1794402005
Short name T175
Test name
Test status
Simulation time 2439235083 ps
CPU time 22.69 seconds
Started Oct 11 11:45:07 PM UTC 24
Finished Oct 11 11:45:31 PM UTC 24
Peak memory 209064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1794402005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 20.aon_timer_stress_all_with_rand_reset.1794402005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/21.aon_timer_stress_all_with_rand_reset.3026260478
Short name T180
Test name
Test status
Simulation time 1968171262 ps
CPU time 9.3 seconds
Started Oct 11 11:45:07 PM UTC 24
Finished Oct 11 11:45:18 PM UTC 24
Peak memory 219804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3026260478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 21.aon_timer_stress_all_with_rand_reset.3026260478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/23.aon_timer_stress_all_with_rand_reset.4210834360
Short name T195
Test name
Test status
Simulation time 668363962 ps
CPU time 3.15 seconds
Started Oct 11 11:45:10 PM UTC 24
Finished Oct 11 11:45:14 PM UTC 24
Peak memory 209192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4210834360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 23.aon_timer_stress_all_with_rand_reset.4210834360
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/28.aon_timer_jump.117668194
Short name T139
Test name
Test status
Simulation time 591105195 ps
CPU time 1.25 seconds
Started Oct 11 11:45:20 PM UTC 24
Finished Oct 11 11:45:22 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117668194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.117668194
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/28.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/3.aon_timer_stress_all.1906293013
Short name T194
Test name
Test status
Simulation time 138568497231 ps
CPU time 113.62 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:46:44 PM UTC 24
Peak memory 203412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906293013 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.1906293013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/34.aon_timer_jump.1928772304
Short name T204
Test name
Test status
Simulation time 388163355 ps
CPU time 1.76 seconds
Started Oct 11 11:45:36 PM UTC 24
Finished Oct 11 11:45:39 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928772304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1928772304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/34.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/34.aon_timer_stress_all_with_rand_reset.1363016491
Short name T196
Test name
Test status
Simulation time 1259192481 ps
CPU time 9.52 seconds
Started Oct 11 11:45:38 PM UTC 24
Finished Oct 11 11:45:49 PM UTC 24
Peak memory 208864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1363016491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 34.aon_timer_stress_all_with_rand_reset.1363016491
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/38.aon_timer_jump.3752753735
Short name T121
Test name
Test status
Simulation time 352725534 ps
CPU time 1.93 seconds
Started Oct 11 11:45:47 PM UTC 24
Finished Oct 11 11:45:50 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752753735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3752753735
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/38.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/46.aon_timer_stress_all.3402611670
Short name T191
Test name
Test status
Simulation time 29995526693 ps
CPU time 47.13 seconds
Started Oct 11 11:46:03 PM UTC 24
Finished Oct 11 11:46:53 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402611670 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.3402611670
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/46.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1773640305
Short name T40
Test name
Test status
Simulation time 527250576 ps
CPU time 1.73 seconds
Started Oct 11 11:44:26 PM UTC 24
Finished Oct 11 11:44:29 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773640305 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.1773640305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3311392017
Short name T64
Test name
Test status
Simulation time 13484998061 ps
CPU time 6.3 seconds
Started Oct 11 11:44:26 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 201288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311392017 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.3311392017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1072320953
Short name T84
Test name
Test status
Simulation time 920123456 ps
CPU time 2.5 seconds
Started Oct 11 11:44:25 PM UTC 24
Finished Oct 11 11:44:28 PM UTC 24
Peak memory 200952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072320953 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.1072320953
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1273544534
Short name T43
Test name
Test status
Simulation time 717017771 ps
CPU time 0.94 seconds
Started Oct 11 11:44:26 PM UTC 24
Finished Oct 11 11:44:28 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1273544534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_csr_mem_rw_with_rand_reset.1273544534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_csr_rw.2571614362
Short name T39
Test name
Test status
Simulation time 447181026 ps
CPU time 1.13 seconds
Started Oct 11 11:44:26 PM UTC 24
Finished Oct 11 11:44:28 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571614362 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2571614362
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_intr_test.162497593
Short name T292
Test name
Test status
Simulation time 342183057 ps
CPU time 0.89 seconds
Started Oct 11 11:44:24 PM UTC 24
Finished Oct 11 11:44:26 PM UTC 24
Peak memory 200292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162497593 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.162497593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_partial_access.824069062
Short name T294
Test name
Test status
Simulation time 479862716 ps
CPU time 1.56 seconds
Started Oct 11 11:44:25 PM UTC 24
Finished Oct 11 11:44:27 PM UTC 24
Peak memory 199692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824069062 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.824069062
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_mem_walk.2054336327
Short name T293
Test name
Test status
Simulation time 492158002 ps
CPU time 1.68 seconds
Started Oct 11 11:44:25 PM UTC 24
Finished Oct 11 11:44:27 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054336327 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.2054336327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/0.aon_timer_tl_errors.2673967435
Short name T295
Test name
Test status
Simulation time 446102523 ps
CPU time 3.1 seconds
Started Oct 11 11:44:23 PM UTC 24
Finished Oct 11 11:44:28 PM UTC 24
Peak memory 201204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673967435 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2673967435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1592089355
Short name T58
Test name
Test status
Simulation time 632813179 ps
CPU time 1.05 seconds
Started Oct 11 11:44:27 PM UTC 24
Finished Oct 11 11:44:29 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592089355 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.1592089355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2908569003
Short name T59
Test name
Test status
Simulation time 7525712724 ps
CPU time 2.99 seconds
Started Oct 11 11:44:27 PM UTC 24
Finished Oct 11 11:44:31 PM UTC 24
Peak memory 201228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908569003 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.2908569003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.467646974
Short name T85
Test name
Test status
Simulation time 784054227 ps
CPU time 1.74 seconds
Started Oct 11 11:44:27 PM UTC 24
Finished Oct 11 11:44:30 PM UTC 24
Peak memory 199684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467646974 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.467646974
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3876309674
Short name T221
Test name
Test status
Simulation time 460748887 ps
CPU time 1.07 seconds
Started Oct 11 11:44:29 PM UTC 24
Finished Oct 11 11:44:31 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3876309674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_csr_mem_rw_with_rand_reset.3876309674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_csr_rw.726391623
Short name T57
Test name
Test status
Simulation time 553240570 ps
CPU time 0.79 seconds
Started Oct 11 11:44:27 PM UTC 24
Finished Oct 11 11:44:29 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726391623 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.726391623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_intr_test.300813749
Short name T296
Test name
Test status
Simulation time 271740867 ps
CPU time 1.16 seconds
Started Oct 11 11:44:26 PM UTC 24
Finished Oct 11 11:44:28 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300813749 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.300813749
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3827694567
Short name T299
Test name
Test status
Simulation time 516989798 ps
CPU time 1.06 seconds
Started Oct 11 11:44:27 PM UTC 24
Finished Oct 11 11:44:29 PM UTC 24
Peak memory 199752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827694567 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.3827694567
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_mem_walk.3553173469
Short name T298
Test name
Test status
Simulation time 437372921 ps
CPU time 0.97 seconds
Started Oct 11 11:44:27 PM UTC 24
Finished Oct 11 11:44:29 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553173469 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.3553173469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2490998830
Short name T75
Test name
Test status
Simulation time 2970742060 ps
CPU time 2.74 seconds
Started Oct 11 11:44:29 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 200940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490998830 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.2490998830
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_errors.3787476917
Short name T297
Test name
Test status
Simulation time 1267770921 ps
CPU time 2.11 seconds
Started Oct 11 11:44:26 PM UTC 24
Finished Oct 11 11:44:29 PM UTC 24
Peak memory 201260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787476917 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3787476917
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2247105239
Short name T367
Test name
Test status
Simulation time 8408707151 ps
CPU time 16.09 seconds
Started Oct 11 11:44:26 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 206196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247105239 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.2247105239
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2983336767
Short name T336
Test name
Test status
Simulation time 321020929 ps
CPU time 1.05 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:39 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2983336767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_ti
mer_csr_mem_rw_with_rand_reset.2983336767
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_csr_rw.18778787
Short name T337
Test name
Test status
Simulation time 455369463 ps
CPU time 1.47 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:40 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18778787 -assert nopostproc +UVM_TESTNAME=aon_
timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.18778787
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_intr_test.4024691696
Short name T333
Test name
Test status
Simulation time 502579905 ps
CPU time 0.74 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:39 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024691696 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4024691696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.769116511
Short name T340
Test name
Test status
Simulation time 2218208679 ps
CPU time 1.74 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:40 PM UTC 24
Peak memory 199812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769116511 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.769116511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_errors.612251517
Short name T341
Test name
Test status
Simulation time 799776144 ps
CPU time 1.89 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:40 PM UTC 24
Peak memory 201656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612251517 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.612251517
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/10.aon_timer_tl_intg_err.304737497
Short name T423
Test name
Test status
Simulation time 8723753001 ps
CPU time 16.67 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:55 PM UTC 24
Peak memory 205936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304737497 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.304737497
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.874929658
Short name T348
Test name
Test status
Simulation time 363142993 ps
CPU time 1.14 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:41 PM UTC 24
Peak memory 199676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=874929658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_tim
er_csr_mem_rw_with_rand_reset.874929658
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_csr_rw.4293187204
Short name T339
Test name
Test status
Simulation time 544770063 ps
CPU time 1.24 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:40 PM UTC 24
Peak memory 201664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293187204 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4293187204
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_intr_test.4071685158
Short name T334
Test name
Test status
Simulation time 373348715 ps
CPU time 0.77 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:39 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071685158 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4071685158
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2100219689
Short name T384
Test name
Test status
Simulation time 2125979995 ps
CPU time 6.05 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 201072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100219689 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.2100219689
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_errors.2967874206
Short name T344
Test name
Test status
Simulation time 446387198 ps
CPU time 1.95 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:40 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967874206 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2967874206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2981613351
Short name T210
Test name
Test status
Simulation time 8048989924 ps
CPU time 5.78 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:44 PM UTC 24
Peak memory 206632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981613351 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.2981613351
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3333991909
Short name T351
Test name
Test status
Simulation time 546109961 ps
CPU time 1.25 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:41 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3333991909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_ti
mer_csr_mem_rw_with_rand_reset.3333991909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_csr_rw.2609618306
Short name T349
Test name
Test status
Simulation time 434630366 ps
CPU time 1.12 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:41 PM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609618306 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2609618306
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_intr_test.130255897
Short name T347
Test name
Test status
Simulation time 427286060 ps
CPU time 0.78 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:41 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130255897 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.130255897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1222302708
Short name T353
Test name
Test status
Simulation time 2228331722 ps
CPU time 1.68 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:42 PM UTC 24
Peak memory 199688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222302708 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.1222302708
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_errors.503675418
Short name T357
Test name
Test status
Simulation time 344303896 ps
CPU time 2.5 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:42 PM UTC 24
Peak memory 201228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503675418 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.503675418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2763801020
Short name T378
Test name
Test status
Simulation time 8334612028 ps
CPU time 4.78 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:45 PM UTC 24
Peak memory 206280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763801020 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.2763801020
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.665784997
Short name T352
Test name
Test status
Simulation time 400383880 ps
CPU time 1.29 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:42 PM UTC 24
Peak memory 199676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=665784997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_tim
er_csr_mem_rw_with_rand_reset.665784997
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_csr_rw.2602792091
Short name T355
Test name
Test status
Simulation time 415656837 ps
CPU time 1.57 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:42 PM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602792091 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2602792091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_intr_test.1004515261
Short name T350
Test name
Test status
Simulation time 486332890 ps
CPU time 1.05 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:41 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004515261 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1004515261
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2621805087
Short name T386
Test name
Test status
Simulation time 2424791230 ps
CPU time 5.57 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 201008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621805087 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.2621805087
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_errors.2657687974
Short name T360
Test name
Test status
Simulation time 809940378 ps
CPU time 2.53 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 201144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657687974 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2657687974
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2875988031
Short name T406
Test name
Test status
Simulation time 3973021855 ps
CPU time 7.36 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 205844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875988031 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.2875988031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1130136974
Short name T363
Test name
Test status
Simulation time 475158633 ps
CPU time 1.34 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1130136974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_ti
mer_csr_mem_rw_with_rand_reset.1130136974
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_csr_rw.4009516429
Short name T68
Test name
Test status
Simulation time 310781540 ps
CPU time 0.75 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:42 PM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009516429 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.4009516429
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_intr_test.3566235450
Short name T358
Test name
Test status
Simulation time 415520299 ps
CPU time 0.81 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:42 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566235450 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3566235450
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.4141273697
Short name T368
Test name
Test status
Simulation time 1501072813 ps
CPU time 1.71 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 199688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141273697 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.4141273697
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_errors.4216077676
Short name T359
Test name
Test status
Simulation time 426080119 ps
CPU time 2.17 seconds
Started Oct 11 11:44:39 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216077676 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.4216077676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2213720335
Short name T208
Test name
Test status
Simulation time 4243878394 ps
CPU time 2.49 seconds
Started Oct 11 11:44:40 PM UTC 24
Finished Oct 11 11:44:44 PM UTC 24
Peak memory 205700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213720335 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.2213720335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4162412325
Short name T370
Test name
Test status
Simulation time 495038696 ps
CPU time 1.74 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:44 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4162412325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_ti
mer_csr_mem_rw_with_rand_reset.4162412325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_csr_rw.3014270586
Short name T366
Test name
Test status
Simulation time 498885858 ps
CPU time 1.34 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014270586 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3014270586
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_intr_test.1053702145
Short name T364
Test name
Test status
Simulation time 508005700 ps
CPU time 1.36 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053702145 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1053702145
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.419814625
Short name T373
Test name
Test status
Simulation time 2646303787 ps
CPU time 2.43 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:44 PM UTC 24
Peak memory 201136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419814625 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.419814625
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_errors.3256064341
Short name T372
Test name
Test status
Simulation time 432830715 ps
CPU time 2.41 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:44 PM UTC 24
Peak memory 201284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256064341 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3256064341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2570295722
Short name T211
Test name
Test status
Simulation time 8692214752 ps
CPU time 5.08 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:47 PM UTC 24
Peak memory 206540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570295722 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.2570295722
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1781179914
Short name T369
Test name
Test status
Simulation time 469869841 ps
CPU time 1.32 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 199660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1781179914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_ti
mer_csr_mem_rw_with_rand_reset.1781179914
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_csr_rw.947277843
Short name T69
Test name
Test status
Simulation time 428410377 ps
CPU time 1.19 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947277843 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.947277843
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_intr_test.142269845
Short name T361
Test name
Test status
Simulation time 412346444 ps
CPU time 0.71 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142269845 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.142269845
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1550318315
Short name T371
Test name
Test status
Simulation time 2114363762 ps
CPU time 1.64 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:44 PM UTC 24
Peak memory 199724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550318315 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.1550318315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_errors.2728292432
Short name T374
Test name
Test status
Simulation time 613512499 ps
CPU time 2.44 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:44 PM UTC 24
Peak memory 201224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728292432 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2728292432
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/16.aon_timer_tl_intg_err.466339340
Short name T420
Test name
Test status
Simulation time 4417536040 ps
CPU time 8.05 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:50 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466339340 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.466339340
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3277692115
Short name T375
Test name
Test status
Simulation time 469211954 ps
CPU time 1.11 seconds
Started Oct 11 11:44:42 PM UTC 24
Finished Oct 11 11:44:45 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3277692115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_ti
mer_csr_mem_rw_with_rand_reset.3277692115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_csr_rw.1101887704
Short name T70
Test name
Test status
Simulation time 345517269 ps
CPU time 1.2 seconds
Started Oct 11 11:44:42 PM UTC 24
Finished Oct 11 11:44:45 PM UTC 24
Peak memory 199616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101887704 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1101887704
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_intr_test.669060566
Short name T362
Test name
Test status
Simulation time 483985671 ps
CPU time 0.84 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669060566 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.669060566
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3606624312
Short name T385
Test name
Test status
Simulation time 1452349327 ps
CPU time 2.42 seconds
Started Oct 11 11:44:42 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 200648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606624312 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.3606624312
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_errors.1318159680
Short name T376
Test name
Test status
Simulation time 441832115 ps
CPU time 2.22 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:45 PM UTC 24
Peak memory 201172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318159680 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1318159680
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/17.aon_timer_tl_intg_err.977725423
Short name T422
Test name
Test status
Simulation time 8338919135 ps
CPU time 11.25 seconds
Started Oct 11 11:44:41 PM UTC 24
Finished Oct 11 11:44:54 PM UTC 24
Peak memory 201404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977725423 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.977725423
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.940132873
Short name T381
Test name
Test status
Simulation time 513658371 ps
CPU time 1.5 seconds
Started Oct 11 11:44:43 PM UTC 24
Finished Oct 11 11:44:45 PM UTC 24
Peak memory 199676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=940132873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_tim
er_csr_mem_rw_with_rand_reset.940132873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_csr_rw.50042696
Short name T379
Test name
Test status
Simulation time 298436499 ps
CPU time 1.15 seconds
Started Oct 11 11:44:43 PM UTC 24
Finished Oct 11 11:44:45 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50042696 -assert nopostproc +UVM_TESTNAME=aon_
timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.50042696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_intr_test.860911232
Short name T380
Test name
Test status
Simulation time 451992532 ps
CPU time 1.3 seconds
Started Oct 11 11:44:43 PM UTC 24
Finished Oct 11 11:44:45 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860911232 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.860911232
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.246687814
Short name T390
Test name
Test status
Simulation time 1221671530 ps
CPU time 2.43 seconds
Started Oct 11 11:44:43 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 200872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246687814 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.246687814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_errors.2802620237
Short name T388
Test name
Test status
Simulation time 1001297693 ps
CPU time 2.52 seconds
Started Oct 11 11:44:42 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802620237 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2802620237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1825109454
Short name T424
Test name
Test status
Simulation time 8016847372 ps
CPU time 13.81 seconds
Started Oct 11 11:44:43 PM UTC 24
Finished Oct 11 11:44:58 PM UTC 24
Peak memory 201224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825109454 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.1825109454
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3478826800
Short name T399
Test name
Test status
Simulation time 525028626 ps
CPU time 1.54 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:47 PM UTC 24
Peak memory 199672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3478826800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_ti
mer_csr_mem_rw_with_rand_reset.3478826800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_csr_rw.381629715
Short name T71
Test name
Test status
Simulation time 505374038 ps
CPU time 0.82 seconds
Started Oct 11 11:44:43 PM UTC 24
Finished Oct 11 11:44:45 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381629715 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.381629715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_intr_test.933076997
Short name T377
Test name
Test status
Simulation time 333885304 ps
CPU time 0.79 seconds
Started Oct 11 11:44:43 PM UTC 24
Finished Oct 11 11:44:45 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933076997 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.933076997
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.735254738
Short name T419
Test name
Test status
Simulation time 2357700631 ps
CPU time 3.9 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:49 PM UTC 24
Peak memory 200936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735254738 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.735254738
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_errors.65189496
Short name T382
Test name
Test status
Simulation time 573553783 ps
CPU time 1.77 seconds
Started Oct 11 11:44:43 PM UTC 24
Finished Oct 11 11:44:45 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65189496 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.65189496
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2838770403
Short name T346
Test name
Test status
Simulation time 4673145529 ps
CPU time 3.83 seconds
Started Oct 11 11:44:43 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 200940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838770403 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.2838770403
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_aliasing.400712486
Short name T62
Test name
Test status
Simulation time 402108970 ps
CPU time 1.57 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400712486 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.400712486
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3835556214
Short name T67
Test name
Test status
Simulation time 5874260412 ps
CPU time 5.43 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:37 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835556214 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.3835556214
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3414529571
Short name T307
Test name
Test status
Simulation time 526073861 ps
CPU time 1.55 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3414529571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_tim
er_csr_mem_rw_with_rand_reset.3414529571
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_csr_rw.3441169196
Short name T306
Test name
Test status
Simulation time 559063450 ps
CPU time 1.64 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441169196 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3441169196
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_intr_test.2545721326
Short name T300
Test name
Test status
Simulation time 540425564 ps
CPU time 0.62 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:32 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545721326 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2545721326
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2948056192
Short name T301
Test name
Test status
Simulation time 385424849 ps
CPU time 0.91 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:32 PM UTC 24
Peak memory 199752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948056192 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.2948056192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_mem_walk.772756651
Short name T303
Test name
Test status
Simulation time 356390733 ps
CPU time 1.21 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:32 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772756651 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.772756651
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3380591246
Short name T76
Test name
Test status
Simulation time 2085668173 ps
CPU time 1.78 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380591246 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.3380591246
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_errors.2661403751
Short name T305
Test name
Test status
Simulation time 506533259 ps
CPU time 1.57 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661403751 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2661403751
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/2.aon_timer_tl_intg_err.478242174
Short name T42
Test name
Test status
Simulation time 4387435428 ps
CPU time 4.79 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:36 PM UTC 24
Peak memory 201220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478242174 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.478242174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/20.aon_timer_intr_test.2816016804
Short name T383
Test name
Test status
Simulation time 332111483 ps
CPU time 0.68 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816016804 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2816016804
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/20.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/21.aon_timer_intr_test.744534181
Short name T393
Test name
Test status
Simulation time 287650784 ps
CPU time 1.06 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744534181 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.744534181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/21.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/22.aon_timer_intr_test.29597285
Short name T396
Test name
Test status
Simulation time 511335088 ps
CPU time 1.29 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29597285 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.29597285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/22.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/23.aon_timer_intr_test.3361481903
Short name T394
Test name
Test status
Simulation time 417575123 ps
CPU time 1.01 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361481903 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3361481903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/23.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/24.aon_timer_intr_test.2229468379
Short name T392
Test name
Test status
Simulation time 288620920 ps
CPU time 0.92 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229468379 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2229468379
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/24.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/25.aon_timer_intr_test.676684054
Short name T403
Test name
Test status
Simulation time 450292408 ps
CPU time 1.58 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:47 PM UTC 24
Peak memory 199600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676684054 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.676684054
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/25.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/26.aon_timer_intr_test.3177326047
Short name T389
Test name
Test status
Simulation time 402677989 ps
CPU time 0.73 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177326047 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3177326047
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/26.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/27.aon_timer_intr_test.3736679460
Short name T387
Test name
Test status
Simulation time 513402734 ps
CPU time 0.74 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736679460 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3736679460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/27.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/28.aon_timer_intr_test.2694999934
Short name T391
Test name
Test status
Simulation time 603605151 ps
CPU time 0.71 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694999934 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2694999934
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/28.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/29.aon_timer_intr_test.2922197799
Short name T398
Test name
Test status
Simulation time 324686201 ps
CPU time 1.11 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:47 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922197799 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2922197799
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/29.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3526629327
Short name T63
Test name
Test status
Simulation time 638852624 ps
CPU time 1.41 seconds
Started Oct 11 11:44:31 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526629327 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.3526629327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3989088101
Short name T66
Test name
Test status
Simulation time 6046320051 ps
CPU time 3.3 seconds
Started Oct 11 11:44:31 PM UTC 24
Finished Oct 11 11:44:35 PM UTC 24
Peak memory 201164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989088101 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.3989088101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4034956669
Short name T61
Test name
Test status
Simulation time 807236936 ps
CPU time 1.08 seconds
Started Oct 11 11:44:31 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034956669 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.4034956669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3750114245
Short name T312
Test name
Test status
Simulation time 369952773 ps
CPU time 1.38 seconds
Started Oct 11 11:44:32 PM UTC 24
Finished Oct 11 11:44:35 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3750114245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_csr_mem_rw_with_rand_reset.3750114245
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_csr_rw.118409085
Short name T74
Test name
Test status
Simulation time 440630157 ps
CPU time 0.95 seconds
Started Oct 11 11:44:31 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118409085 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.118409085
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_intr_test.3563622192
Short name T302
Test name
Test status
Simulation time 366757637 ps
CPU time 0.72 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:32 PM UTC 24
Peak memory 199544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563622192 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3563622192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2194309734
Short name T308
Test name
Test status
Simulation time 406501316 ps
CPU time 1.53 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194309734 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.2194309734
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_mem_walk.3702815790
Short name T304
Test name
Test status
Simulation time 282502447 ps
CPU time 0.94 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:32 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702815790 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.3702815790
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2507879139
Short name T77
Test name
Test status
Simulation time 2535052129 ps
CPU time 1.43 seconds
Started Oct 11 11:44:31 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 199756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507879139 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.2507879139
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_errors.2900679324
Short name T309
Test name
Test status
Simulation time 464154809 ps
CPU time 1.99 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:33 PM UTC 24
Peak memory 206044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900679324 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2900679324
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/3.aon_timer_tl_intg_err.781184419
Short name T41
Test name
Test status
Simulation time 4700433996 ps
CPU time 2.5 seconds
Started Oct 11 11:44:30 PM UTC 24
Finished Oct 11 11:44:34 PM UTC 24
Peak memory 205640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781184419 -assert nopostproc +UVM_TES
TNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.781184419
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/30.aon_timer_intr_test.2735583982
Short name T401
Test name
Test status
Simulation time 477188818 ps
CPU time 1.18 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:47 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735583982 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2735583982
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/30.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/31.aon_timer_intr_test.3316874240
Short name T402
Test name
Test status
Simulation time 449231554 ps
CPU time 1.22 seconds
Started Oct 11 11:44:44 PM UTC 24
Finished Oct 11 11:44:47 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316874240 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3316874240
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/31.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/32.aon_timer_intr_test.3361974256
Short name T397
Test name
Test status
Simulation time 517106276 ps
CPU time 0.95 seconds
Started Oct 11 11:44:45 PM UTC 24
Finished Oct 11 11:44:47 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361974256 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3361974256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/32.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/33.aon_timer_intr_test.844183941
Short name T400
Test name
Test status
Simulation time 441187683 ps
CPU time 1 seconds
Started Oct 11 11:44:45 PM UTC 24
Finished Oct 11 11:44:47 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844183941 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.844183941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/33.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/34.aon_timer_intr_test.3011711209
Short name T395
Test name
Test status
Simulation time 502870500 ps
CPU time 0.68 seconds
Started Oct 11 11:44:45 PM UTC 24
Finished Oct 11 11:44:46 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011711209 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3011711209
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/34.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/35.aon_timer_intr_test.1718935675
Short name T405
Test name
Test status
Simulation time 451122973 ps
CPU time 0.71 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:47 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718935675 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1718935675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/35.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/36.aon_timer_intr_test.3340913982
Short name T345
Test name
Test status
Simulation time 513092387 ps
CPU time 0.79 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340913982 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3340913982
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/36.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/37.aon_timer_intr_test.2471342028
Short name T408
Test name
Test status
Simulation time 285030020 ps
CPU time 0.91 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471342028 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2471342028
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/37.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/38.aon_timer_intr_test.3157701054
Short name T415
Test name
Test status
Simulation time 389144378 ps
CPU time 1.32 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157701054 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3157701054
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/38.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/39.aon_timer_intr_test.445247516
Short name T412
Test name
Test status
Simulation time 350749611 ps
CPU time 0.99 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445247516 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.445247516
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/39.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2526453744
Short name T73
Test name
Test status
Simulation time 672519246 ps
CPU time 1.55 seconds
Started Oct 11 11:44:33 PM UTC 24
Finished Oct 11 11:44:35 PM UTC 24
Peak memory 199624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526453744 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.2526453744
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1689384675
Short name T72
Test name
Test status
Simulation time 998750322 ps
CPU time 1.63 seconds
Started Oct 11 11:44:32 PM UTC 24
Finished Oct 11 11:44:35 PM UTC 24
Peak memory 199352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689384675 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.1689384675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3400810469
Short name T65
Test name
Test status
Simulation time 816677815 ps
CPU time 1.5 seconds
Started Oct 11 11:44:32 PM UTC 24
Finished Oct 11 11:44:35 PM UTC 24
Peak memory 199560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400810469 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.3400810469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.773251862
Short name T313
Test name
Test status
Simulation time 321935167 ps
CPU time 0.96 seconds
Started Oct 11 11:44:33 PM UTC 24
Finished Oct 11 11:44:35 PM UTC 24
Peak memory 199740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=773251862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_time
r_csr_mem_rw_with_rand_reset.773251862
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_csr_rw.2504693403
Short name T78
Test name
Test status
Simulation time 527414266 ps
CPU time 1.43 seconds
Started Oct 11 11:44:32 PM UTC 24
Finished Oct 11 11:44:35 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504693403 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2504693403
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_intr_test.3749052065
Short name T310
Test name
Test status
Simulation time 336625903 ps
CPU time 0.84 seconds
Started Oct 11 11:44:32 PM UTC 24
Finished Oct 11 11:44:34 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749052065 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3749052065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3716310758
Short name T314
Test name
Test status
Simulation time 468744259 ps
CPU time 1.32 seconds
Started Oct 11 11:44:32 PM UTC 24
Finished Oct 11 11:44:35 PM UTC 24
Peak memory 199752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716310758 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.3716310758
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_mem_walk.2844909965
Short name T311
Test name
Test status
Simulation time 424763756 ps
CPU time 0.83 seconds
Started Oct 11 11:44:32 PM UTC 24
Finished Oct 11 11:44:34 PM UTC 24
Peak memory 199568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844909965 -assert nopostproc +UVM_TESTN
AME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.2844909965
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2747980457
Short name T79
Test name
Test status
Simulation time 2662646399 ps
CPU time 1.89 seconds
Started Oct 11 11:44:33 PM UTC 24
Finished Oct 11 11:44:36 PM UTC 24
Peak memory 199756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747980457 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.2747980457
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/4.aon_timer_tl_errors.1522933372
Short name T317
Test name
Test status
Simulation time 403140271 ps
CPU time 2.66 seconds
Started Oct 11 11:44:32 PM UTC 24
Finished Oct 11 11:44:36 PM UTC 24
Peak memory 206736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522933372 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1522933372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/40.aon_timer_intr_test.2079945144
Short name T407
Test name
Test status
Simulation time 436498924 ps
CPU time 0.75 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079945144 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2079945144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/40.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/41.aon_timer_intr_test.4202111079
Short name T404
Test name
Test status
Simulation time 478247027 ps
CPU time 0.69 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202111079 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.4202111079
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/41.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/42.aon_timer_intr_test.73668513
Short name T416
Test name
Test status
Simulation time 420018727 ps
CPU time 1.25 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73668513 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.73668513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/42.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/43.aon_timer_intr_test.729997900
Short name T411
Test name
Test status
Simulation time 335249657 ps
CPU time 0.82 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729997900 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.729997900
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/43.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/44.aon_timer_intr_test.1695507228
Short name T410
Test name
Test status
Simulation time 327009921 ps
CPU time 0.72 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695507228 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1695507228
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/44.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/45.aon_timer_intr_test.1399186924
Short name T409
Test name
Test status
Simulation time 335171898 ps
CPU time 0.79 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399186924 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1399186924
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/45.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/46.aon_timer_intr_test.535121931
Short name T413
Test name
Test status
Simulation time 337822731 ps
CPU time 0.74 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535121931 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.535121931
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/46.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/47.aon_timer_intr_test.1578650513
Short name T418
Test name
Test status
Simulation time 457528865 ps
CPU time 1.41 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:49 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578650513 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1578650513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/47.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/48.aon_timer_intr_test.858496470
Short name T417
Test name
Test status
Simulation time 350150202 ps
CPU time 0.96 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:49 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858496470 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.858496470
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/48.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/49.aon_timer_intr_test.69616234
Short name T414
Test name
Test status
Simulation time 464040244 ps
CPU time 0.78 seconds
Started Oct 11 11:44:46 PM UTC 24
Finished Oct 11 11:44:48 PM UTC 24
Peak memory 199668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69616234 -assert nopostproc +UVM_TESTNAME=aon_tim
er_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.69616234
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/49.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1987653595
Short name T325
Test name
Test status
Simulation time 571384815 ps
CPU time 1.63 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:38 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1987653595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_tim
er_csr_mem_rw_with_rand_reset.1987653595
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_csr_rw.3569900378
Short name T316
Test name
Test status
Simulation time 352590550 ps
CPU time 0.68 seconds
Started Oct 11 11:44:34 PM UTC 24
Finished Oct 11 11:44:36 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569900378 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3569900378
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_intr_test.3227113989
Short name T315
Test name
Test status
Simulation time 459046906 ps
CPU time 0.7 seconds
Started Oct 11 11:44:34 PM UTC 24
Finished Oct 11 11:44:36 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227113989 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3227113989
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3609594151
Short name T81
Test name
Test status
Simulation time 2172935385 ps
CPU time 1.73 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:38 PM UTC 24
Peak memory 199460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609594151 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.3609594151
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_errors.3577887677
Short name T318
Test name
Test status
Simulation time 807420045 ps
CPU time 2.31 seconds
Started Oct 11 11:44:33 PM UTC 24
Finished Oct 11 11:44:36 PM UTC 24
Peak memory 201296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577887677 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3577887677
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3134499422
Short name T354
Test name
Test status
Simulation time 8554539445 ps
CPU time 7.94 seconds
Started Oct 11 11:44:33 PM UTC 24
Finished Oct 11 11:44:42 PM UTC 24
Peak memory 201232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134499422 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.3134499422
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1873657184
Short name T327
Test name
Test status
Simulation time 522925517 ps
CPU time 1.71 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:38 PM UTC 24
Peak memory 199720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1873657184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_tim
er_csr_mem_rw_with_rand_reset.1873657184
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_csr_rw.1674472094
Short name T323
Test name
Test status
Simulation time 477402700 ps
CPU time 1.47 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:38 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674472094 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1674472094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_intr_test.268261208
Short name T320
Test name
Test status
Simulation time 462780131 ps
CPU time 0.9 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:37 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268261208 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.268261208
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.60217869
Short name T82
Test name
Test status
Simulation time 2063894804 ps
CPU time 3.04 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:39 PM UTC 24
Peak memory 201072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60217869 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.60217869
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_errors.1973046593
Short name T331
Test name
Test status
Simulation time 395965947 ps
CPU time 2.48 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:39 PM UTC 24
Peak memory 203248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973046593 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1973046593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1374089206
Short name T206
Test name
Test status
Simulation time 8364913604 ps
CPU time 3.59 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:40 PM UTC 24
Peak memory 201228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374089206 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.1374089206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1164021559
Short name T322
Test name
Test status
Simulation time 447858388 ps
CPU time 0.91 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:37 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1164021559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_tim
er_csr_mem_rw_with_rand_reset.1164021559
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_csr_rw.3527081668
Short name T319
Test name
Test status
Simulation time 647014959 ps
CPU time 0.71 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:37 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527081668 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3527081668
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_intr_test.1762735490
Short name T321
Test name
Test status
Simulation time 485515256 ps
CPU time 0.84 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:37 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762735490 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1762735490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4065224666
Short name T83
Test name
Test status
Simulation time 1446237940 ps
CPU time 2.88 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:39 PM UTC 24
Peak memory 200876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065224666 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.4065224666
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_errors.3213404502
Short name T326
Test name
Test status
Simulation time 426640632 ps
CPU time 1.57 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:38 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213404502 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3213404502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3359342886
Short name T365
Test name
Test status
Simulation time 4407972111 ps
CPU time 6.84 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:43 PM UTC 24
Peak memory 205880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359342886 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.3359342886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3406678690
Short name T335
Test name
Test status
Simulation time 422660280 ps
CPU time 1.48 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:39 PM UTC 24
Peak memory 199736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3406678690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_tim
er_csr_mem_rw_with_rand_reset.3406678690
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_csr_rw.1349687127
Short name T329
Test name
Test status
Simulation time 566514970 ps
CPU time 0.77 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:38 PM UTC 24
Peak memory 201668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349687127 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1349687127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_intr_test.2439948589
Short name T324
Test name
Test status
Simulation time 454304476 ps
CPU time 1.1 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:38 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439948589 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2439948589
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.840899656
Short name T343
Test name
Test status
Simulation time 1341288923 ps
CPU time 2.4 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:40 PM UTC 24
Peak memory 200868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840899656 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.840899656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_errors.2060759765
Short name T328
Test name
Test status
Simulation time 484417491 ps
CPU time 1.7 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:38 PM UTC 24
Peak memory 199604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060759765 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2060759765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4160621231
Short name T209
Test name
Test status
Simulation time 4113767434 ps
CPU time 2.59 seconds
Started Oct 11 11:44:35 PM UTC 24
Finished Oct 11 11:44:39 PM UTC 24
Peak memory 201148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160621231 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.4160621231
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.613075360
Short name T342
Test name
Test status
Simulation time 575443561 ps
CPU time 1.96 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:40 PM UTC 24
Peak memory 199740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +e
n_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=613075360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_time
r_csr_mem_rw_with_rand_reset.613075360
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_csr_rw.3182486650
Short name T332
Test name
Test status
Simulation time 531386554 ps
CPU time 0.84 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:39 PM UTC 24
Peak memory 199620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182486650 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3182486650
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_intr_test.965527645
Short name T330
Test name
Test status
Simulation time 385831660 ps
CPU time 0.77 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:39 PM UTC 24
Peak memory 199608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965527645 -assert nopostproc +UVM_TESTNAME=aon_ti
mer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.965527645
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3927564555
Short name T356
Test name
Test status
Simulation time 1225746107 ps
CPU time 3.99 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:42 PM UTC 24
Peak memory 200948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927564555 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.3927564555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_errors.3973397909
Short name T338
Test name
Test status
Simulation time 407995126 ps
CPU time 1.91 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:40 PM UTC 24
Peak memory 199568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973397909 -assert nopostproc +UVM_TESTNAME=aon_t
imer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3973397909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3483602523
Short name T421
Test name
Test status
Simulation time 8554492513 ps
CPU time 14.57 seconds
Started Oct 11 11:44:37 PM UTC 24
Finished Oct 11 11:44:53 PM UTC 24
Peak memory 201148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483602523 -assert nopostproc +UVM_TE
STNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.3483602523
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/0.aon_timer_prescaler.251677083
Short name T220
Test name
Test status
Simulation time 52476649411 ps
CPU time 10.89 seconds
Started Oct 11 11:44:47 PM UTC 24
Finished Oct 11 11:45:00 PM UTC 24
Peak memory 203272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251677083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.251677083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/0.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/1.aon_timer_prescaler.20409147
Short name T219
Test name
Test status
Simulation time 45997371046 ps
CPU time 26.78 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:45:16 PM UTC 24
Peak memory 203344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20409147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.20409147
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/1.aon_timer_sec_cm.741761408
Short name T11
Test name
Test status
Simulation time 8044892084 ps
CPU time 2.06 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:51 PM UTC 24
Peak memory 233960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741761408 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.741761408
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/1.aon_timer_smoke.367177253
Short name T6
Test name
Test status
Simulation time 501271853 ps
CPU time 1.59 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:50 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367177253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.367177253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/1.aon_timer_stress_all.2584501768
Short name T266
Test name
Test status
Simulation time 294112419747 ps
CPU time 450.2 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:52:23 PM UTC 24
Peak memory 206636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584501768 -assert nopostproc +UVM_TESTNA
ME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.2584501768
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/1.aon_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/10.aon_timer_prescaler.2826285007
Short name T99
Test name
Test status
Simulation time 24011929344 ps
CPU time 10.97 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:45:05 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826285007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2826285007
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/10.aon_timer_smoke.1485525503
Short name T22
Test name
Test status
Simulation time 364219267 ps
CPU time 1.67 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:44:55 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485525503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1485525503
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/10.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/11.aon_timer_prescaler.1937541491
Short name T243
Test name
Test status
Simulation time 21169089197 ps
CPU time 42.57 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:45:37 PM UTC 24
Peak memory 203476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937541491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1937541491
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/11.aon_timer_smoke.3608304825
Short name T223
Test name
Test status
Simulation time 558239411 ps
CPU time 1.71 seconds
Started Oct 11 11:44:53 PM UTC 24
Finished Oct 11 11:44:56 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608304825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3608304825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/11.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/12.aon_timer_prescaler.2449975938
Short name T244
Test name
Test status
Simulation time 21652295714 ps
CPU time 42.31 seconds
Started Oct 11 11:44:54 PM UTC 24
Finished Oct 11 11:45:38 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449975938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2449975938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/12.aon_timer_smoke.1187669299
Short name T50
Test name
Test status
Simulation time 576662755 ps
CPU time 0.95 seconds
Started Oct 11 11:44:54 PM UTC 24
Finished Oct 11 11:44:56 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187669299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1187669299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/12.aon_timer_stress_all_with_rand_reset.2593473347
Short name T215
Test name
Test status
Simulation time 32857442651 ps
CPU time 21.13 seconds
Started Oct 11 11:44:55 PM UTC 24
Finished Oct 11 11:45:17 PM UTC 24
Peak memory 217400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2593473347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 12.aon_timer_stress_all_with_rand_reset.2593473347
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/13.aon_timer_prescaler.4129265122
Short name T280
Test name
Test status
Simulation time 58402415726 ps
CPU time 84.17 seconds
Started Oct 11 11:44:55 PM UTC 24
Finished Oct 11 11:46:21 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129265122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4129265122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/13.aon_timer_smoke.370873638
Short name T52
Test name
Test status
Simulation time 585601476 ps
CPU time 1.06 seconds
Started Oct 11 11:44:55 PM UTC 24
Finished Oct 11 11:44:57 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370873638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.370873638
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/13.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/14.aon_timer_jump.3829519522
Short name T36
Test name
Test status
Simulation time 378149680 ps
CPU time 0.98 seconds
Started Oct 11 11:44:56 PM UTC 24
Finished Oct 11 11:44:58 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829519522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3829519522
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/14.aon_timer_prescaler.513942758
Short name T55
Test name
Test status
Simulation time 4771844506 ps
CPU time 4.62 seconds
Started Oct 11 11:44:56 PM UTC 24
Finished Oct 11 11:45:02 PM UTC 24
Peak memory 203348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513942758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.513942758
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/14.aon_timer_smoke.2198555102
Short name T86
Test name
Test status
Simulation time 385973992 ps
CPU time 1.73 seconds
Started Oct 11 11:44:56 PM UTC 24
Finished Oct 11 11:44:59 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198555102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2198555102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/14.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/15.aon_timer_prescaler.91956480
Short name T218
Test name
Test status
Simulation time 28492213275 ps
CPU time 10.36 seconds
Started Oct 11 11:44:57 PM UTC 24
Finished Oct 11 11:45:10 PM UTC 24
Peak memory 203348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91956480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.91956480
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/15.aon_timer_smoke.1760461663
Short name T224
Test name
Test status
Simulation time 538420591 ps
CPU time 1.19 seconds
Started Oct 11 11:44:57 PM UTC 24
Finished Oct 11 11:45:00 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760461663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1760461663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/15.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/16.aon_timer_prescaler.3367300674
Short name T273
Test name
Test status
Simulation time 46478357277 ps
CPU time 66.5 seconds
Started Oct 11 11:45:00 PM UTC 24
Finished Oct 11 11:46:08 PM UTC 24
Peak memory 203412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367300674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3367300674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/16.aon_timer_smoke.3556897553
Short name T225
Test name
Test status
Simulation time 590909132 ps
CPU time 1.12 seconds
Started Oct 11 11:44:58 PM UTC 24
Finished Oct 11 11:45:00 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556897553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3556897553
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/16.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/17.aon_timer_jump.3466429712
Short name T100
Test name
Test status
Simulation time 550792882 ps
CPU time 1.72 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:45:05 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466429712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3466429712
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/17.aon_timer_prescaler.185782157
Short name T213
Test name
Test status
Simulation time 5041705164 ps
CPU time 4.92 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:45:08 PM UTC 24
Peak memory 203348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185782157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.185782157
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/17.aon_timer_smoke.3172133766
Short name T97
Test name
Test status
Simulation time 400246459 ps
CPU time 1.31 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:45:05 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172133766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3172133766
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/17.aon_timer_stress_all_with_rand_reset.935226742
Short name T47
Test name
Test status
Simulation time 1204949754 ps
CPU time 6.86 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:45:10 PM UTC 24
Peak memory 217520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=935226742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 17.aon_timer_stress_all_with_rand_reset.935226742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/18.aon_timer_prescaler.3484295854
Short name T217
Test name
Test status
Simulation time 23919040965 ps
CPU time 13.2 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:45:17 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484295854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3484295854
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/18.aon_timer_smoke.3052043030
Short name T96
Test name
Test status
Simulation time 603350300 ps
CPU time 0.99 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:45:04 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052043030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3052043030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/18.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/19.aon_timer_jump.3998776328
Short name T181
Test name
Test status
Simulation time 584767640 ps
CPU time 1.5 seconds
Started Oct 11 11:45:05 PM UTC 24
Finished Oct 11 11:45:08 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998776328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3998776328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/19.aon_timer_prescaler.1131319249
Short name T212
Test name
Test status
Simulation time 612471822 ps
CPU time 1.27 seconds
Started Oct 11 11:45:05 PM UTC 24
Finished Oct 11 11:45:07 PM UTC 24
Peak memory 201376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131319249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1131319249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/19.aon_timer_smoke.4278733648
Short name T98
Test name
Test status
Simulation time 527453987 ps
CPU time 1.03 seconds
Started Oct 11 11:45:02 PM UTC 24
Finished Oct 11 11:45:05 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278733648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.4278733648
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/19.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/2.aon_timer_prescaler.4160728237
Short name T44
Test name
Test status
Simulation time 60888637961 ps
CPU time 8.03 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:57 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160728237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.4160728237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/2.aon_timer_sec_cm.4144793314
Short name T12
Test name
Test status
Simulation time 4286073630 ps
CPU time 1.9 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:51 PM UTC 24
Peak memory 234016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144793314 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4144793314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/2.aon_timer_smoke.2262880396
Short name T7
Test name
Test status
Simulation time 480178017 ps
CPU time 1.43 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:50 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262880396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2262880396
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/2.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/20.aon_timer_prescaler.3587646030
Short name T260
Test name
Test status
Simulation time 29134518469 ps
CPU time 49.83 seconds
Started Oct 11 11:45:05 PM UTC 24
Finished Oct 11 11:45:57 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587646030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3587646030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/20.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/20.aon_timer_smoke.3183298311
Short name T226
Test name
Test status
Simulation time 342305878 ps
CPU time 1.37 seconds
Started Oct 11 11:45:05 PM UTC 24
Finished Oct 11 11:45:08 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183298311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3183298311
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/20.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/21.aon_timer_prescaler.1224443541
Short name T265
Test name
Test status
Simulation time 34228416233 ps
CPU time 49.77 seconds
Started Oct 11 11:45:07 PM UTC 24
Finished Oct 11 11:45:59 PM UTC 24
Peak memory 203348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224443541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1224443541
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/21.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/21.aon_timer_smoke.629885617
Short name T227
Test name
Test status
Simulation time 603447313 ps
CPU time 1.63 seconds
Started Oct 11 11:45:07 PM UTC 24
Finished Oct 11 11:45:10 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629885617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.629885617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/21.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/22.aon_timer_prescaler.70082560
Short name T267
Test name
Test status
Simulation time 25148751582 ps
CPU time 51.16 seconds
Started Oct 11 11:45:08 PM UTC 24
Finished Oct 11 11:46:01 PM UTC 24
Peak memory 203552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70082560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.70082560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/22.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/22.aon_timer_smoke.1484816942
Short name T228
Test name
Test status
Simulation time 496397096 ps
CPU time 1.66 seconds
Started Oct 11 11:45:08 PM UTC 24
Finished Oct 11 11:45:10 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484816942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1484816942
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/22.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/23.aon_timer_prescaler.3748427921
Short name T285
Test name
Test status
Simulation time 59865777503 ps
CPU time 89.29 seconds
Started Oct 11 11:45:10 PM UTC 24
Finished Oct 11 11:46:41 PM UTC 24
Peak memory 203412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748427921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3748427921
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/23.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/23.aon_timer_smoke.1898570322
Short name T229
Test name
Test status
Simulation time 416483703 ps
CPU time 1 seconds
Started Oct 11 11:45:10 PM UTC 24
Finished Oct 11 11:45:12 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898570322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1898570322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/23.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/24.aon_timer_prescaler.946429038
Short name T253
Test name
Test status
Simulation time 41030399132 ps
CPU time 33.47 seconds
Started Oct 11 11:45:12 PM UTC 24
Finished Oct 11 11:45:47 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946429038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.946429038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/24.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/24.aon_timer_smoke.2431262440
Short name T230
Test name
Test status
Simulation time 438445791 ps
CPU time 1.19 seconds
Started Oct 11 11:45:12 PM UTC 24
Finished Oct 11 11:45:14 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431262440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2431262440
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/24.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/25.aon_timer_prescaler.3615484318
Short name T235
Test name
Test status
Simulation time 5672416942 ps
CPU time 8.89 seconds
Started Oct 11 11:45:13 PM UTC 24
Finished Oct 11 11:45:23 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615484318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3615484318
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/25.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/25.aon_timer_smoke.2067022733
Short name T231
Test name
Test status
Simulation time 513134710 ps
CPU time 2.39 seconds
Started Oct 11 11:45:12 PM UTC 24
Finished Oct 11 11:45:16 PM UTC 24
Peak memory 203144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067022733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2067022733
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/25.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/26.aon_timer_prescaler.1061424932
Short name T246
Test name
Test status
Simulation time 9946962819 ps
CPU time 23.82 seconds
Started Oct 11 11:45:15 PM UTC 24
Finished Oct 11 11:45:40 PM UTC 24
Peak memory 203348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061424932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1061424932
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/26.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/26.aon_timer_smoke.2876846596
Short name T232
Test name
Test status
Simulation time 433104907 ps
CPU time 1.17 seconds
Started Oct 11 11:45:15 PM UTC 24
Finished Oct 11 11:45:18 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876846596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2876846596
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/26.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/27.aon_timer_prescaler.2253705314
Short name T216
Test name
Test status
Simulation time 14395482165 ps
CPU time 6.56 seconds
Started Oct 11 11:45:17 PM UTC 24
Finished Oct 11 11:45:25 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253705314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2253705314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/27.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/27.aon_timer_smoke.3741682883
Short name T233
Test name
Test status
Simulation time 440430248 ps
CPU time 1.21 seconds
Started Oct 11 11:45:17 PM UTC 24
Finished Oct 11 11:45:20 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741682883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3741682883
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/27.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/28.aon_timer_prescaler.3059198681
Short name T264
Test name
Test status
Simulation time 26852093181 ps
CPU time 37.08 seconds
Started Oct 11 11:45:20 PM UTC 24
Finished Oct 11 11:45:59 PM UTC 24
Peak memory 203412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059198681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3059198681
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/28.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/28.aon_timer_smoke.3394750197
Short name T234
Test name
Test status
Simulation time 512500494 ps
CPU time 1.26 seconds
Started Oct 11 11:45:20 PM UTC 24
Finished Oct 11 11:45:22 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394750197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3394750197
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/28.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/29.aon_timer_prescaler.461345294
Short name T252
Test name
Test status
Simulation time 26892575443 ps
CPU time 21.17 seconds
Started Oct 11 11:45:24 PM UTC 24
Finished Oct 11 11:45:47 PM UTC 24
Peak memory 203348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461345294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.461345294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/29.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/29.aon_timer_smoke.1161119597
Short name T236
Test name
Test status
Simulation time 624208084 ps
CPU time 1.2 seconds
Started Oct 11 11:45:22 PM UTC 24
Finished Oct 11 11:45:24 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161119597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1161119597
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/29.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/3.aon_timer_jump.4244568279
Short name T8
Test name
Test status
Simulation time 390275963 ps
CPU time 1.26 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:51 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244568279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.4244568279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/3.aon_timer_prescaler.3097676693
Short name T281
Test name
Test status
Simulation time 60460918627 ps
CPU time 97.03 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:46:27 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097676693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3097676693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/3.aon_timer_sec_cm.30711943
Short name T32
Test name
Test status
Simulation time 4257193462 ps
CPU time 4.06 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:54 PM UTC 24
Peak memory 233556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30711943 -assert nopostproc +UVM_TESTNAME=aon
_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.30711943
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/3.aon_timer_smoke.134008130
Short name T5
Test name
Test status
Simulation time 397388737 ps
CPU time 0.92 seconds
Started Oct 11 11:44:48 PM UTC 24
Finished Oct 11 11:44:50 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134008130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.134008130
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/3.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/30.aon_timer_prescaler.967172391
Short name T241
Test name
Test status
Simulation time 21193093757 ps
CPU time 7.25 seconds
Started Oct 11 11:45:27 PM UTC 24
Finished Oct 11 11:45:35 PM UTC 24
Peak memory 203260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967172391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.967172391
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/30.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/30.aon_timer_smoke.85274740
Short name T237
Test name
Test status
Simulation time 357392324 ps
CPU time 1.33 seconds
Started Oct 11 11:45:24 PM UTC 24
Finished Oct 11 11:45:27 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85274740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.85274740
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/30.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/31.aon_timer_prescaler.1322026883
Short name T240
Test name
Test status
Simulation time 6469077627 ps
CPU time 3.82 seconds
Started Oct 11 11:45:29 PM UTC 24
Finished Oct 11 11:45:34 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322026883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1322026883
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/31.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/31.aon_timer_smoke.3193516355
Short name T238
Test name
Test status
Simulation time 417537493 ps
CPU time 1.17 seconds
Started Oct 11 11:45:29 PM UTC 24
Finished Oct 11 11:45:31 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193516355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3193516355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/31.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/32.aon_timer_prescaler.1202255012
Short name T270
Test name
Test status
Simulation time 58031973856 ps
CPU time 31.87 seconds
Started Oct 11 11:45:30 PM UTC 24
Finished Oct 11 11:46:03 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202255012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1202255012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/32.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/32.aon_timer_smoke.3434265708
Short name T239
Test name
Test status
Simulation time 476673754 ps
CPU time 1.17 seconds
Started Oct 11 11:45:30 PM UTC 24
Finished Oct 11 11:45:32 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434265708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3434265708
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/32.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/32.aon_timer_stress_all_with_rand_reset.2842371005
Short name T90
Test name
Test status
Simulation time 2936849697 ps
CPU time 11.37 seconds
Started Oct 11 11:45:34 PM UTC 24
Finished Oct 11 11:45:46 PM UTC 24
Peak memory 218692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2842371005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 32.aon_timer_stress_all_with_rand_reset.2842371005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/33.aon_timer_prescaler.974123742
Short name T261
Test name
Test status
Simulation time 52304877327 ps
CPU time 21.67 seconds
Started Oct 11 11:45:34 PM UTC 24
Finished Oct 11 11:45:57 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974123742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.974123742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/33.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/33.aon_timer_smoke.2712746377
Short name T242
Test name
Test status
Simulation time 576370617 ps
CPU time 1.26 seconds
Started Oct 11 11:45:34 PM UTC 24
Finished Oct 11 11:45:36 PM UTC 24
Peak memory 201272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712746377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2712746377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/33.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/34.aon_timer_prescaler.188571990
Short name T249
Test name
Test status
Simulation time 11623654159 ps
CPU time 6.02 seconds
Started Oct 11 11:45:36 PM UTC 24
Finished Oct 11 11:45:43 PM UTC 24
Peak memory 203348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188571990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.188571990
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/34.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/34.aon_timer_smoke.1514589370
Short name T245
Test name
Test status
Simulation time 449012796 ps
CPU time 1.29 seconds
Started Oct 11 11:45:36 PM UTC 24
Finished Oct 11 11:45:38 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514589370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1514589370
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/34.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/35.aon_timer_prescaler.1687724988
Short name T250
Test name
Test status
Simulation time 4773379786 ps
CPU time 3.48 seconds
Started Oct 11 11:45:40 PM UTC 24
Finished Oct 11 11:45:45 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687724988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1687724988
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/35.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/35.aon_timer_smoke.3578038002
Short name T247
Test name
Test status
Simulation time 557037704 ps
CPU time 1.23 seconds
Started Oct 11 11:45:38 PM UTC 24
Finished Oct 11 11:45:41 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578038002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3578038002
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/35.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/36.aon_timer_prescaler.2932311277
Short name T269
Test name
Test status
Simulation time 38175988359 ps
CPU time 19.39 seconds
Started Oct 11 11:45:42 PM UTC 24
Finished Oct 11 11:46:02 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932311277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2932311277
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/36.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/36.aon_timer_smoke.3627220801
Short name T248
Test name
Test status
Simulation time 561466867 ps
CPU time 1.04 seconds
Started Oct 11 11:45:41 PM UTC 24
Finished Oct 11 11:45:43 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627220801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3627220801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/36.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/37.aon_timer_prescaler.3122805113
Short name T287
Test name
Test status
Simulation time 31298878512 ps
CPU time 60.78 seconds
Started Oct 11 11:45:45 PM UTC 24
Finished Oct 11 11:46:48 PM UTC 24
Peak memory 203284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122805113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3122805113
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/37.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/37.aon_timer_smoke.1724710339
Short name T251
Test name
Test status
Simulation time 466004630 ps
CPU time 1.7 seconds
Started Oct 11 11:45:43 PM UTC 24
Finished Oct 11 11:45:46 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724710339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1724710339
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/37.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/38.aon_timer_prescaler.969778781
Short name T290
Test name
Test status
Simulation time 55391324272 ps
CPU time 101.44 seconds
Started Oct 11 11:45:47 PM UTC 24
Finished Oct 11 11:47:31 PM UTC 24
Peak memory 203668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969778781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.969778781
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/38.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/38.aon_timer_smoke.258652576
Short name T254
Test name
Test status
Simulation time 591513093 ps
CPU time 1.94 seconds
Started Oct 11 11:45:45 PM UTC 24
Finished Oct 11 11:45:48 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258652576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.258652576
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/38.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/39.aon_timer_prescaler.3870825867
Short name T263
Test name
Test status
Simulation time 41039290202 ps
CPU time 9.72 seconds
Started Oct 11 11:45:48 PM UTC 24
Finished Oct 11 11:45:58 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870825867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3870825867
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/39.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/39.aon_timer_smoke.4034674846
Short name T255
Test name
Test status
Simulation time 457858823 ps
CPU time 1.9 seconds
Started Oct 11 11:45:48 PM UTC 24
Finished Oct 11 11:45:51 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034674846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4034674846
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/39.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/4.aon_timer_prescaler.1351219500
Short name T56
Test name
Test status
Simulation time 14771035628 ps
CPU time 13.54 seconds
Started Oct 11 11:44:49 PM UTC 24
Finished Oct 11 11:45:04 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351219500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1351219500
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/4.aon_timer_sec_cm.3239420735
Short name T33
Test name
Test status
Simulation time 4071362369 ps
CPU time 8.32 seconds
Started Oct 11 11:44:49 PM UTC 24
Finished Oct 11 11:44:59 PM UTC 24
Peak memory 233596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239420735 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3239420735
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/4.aon_timer_smoke.2103515137
Short name T10
Test name
Test status
Simulation time 635277314 ps
CPU time 0.99 seconds
Started Oct 11 11:44:49 PM UTC 24
Finished Oct 11 11:44:51 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103515137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2103515137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/4.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/40.aon_timer_jump.2844503572
Short name T198
Test name
Test status
Simulation time 555880462 ps
CPU time 1.96 seconds
Started Oct 11 11:45:50 PM UTC 24
Finished Oct 11 11:45:53 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844503572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2844503572
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/40.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/40.aon_timer_prescaler.1763543595
Short name T268
Test name
Test status
Simulation time 17054407690 ps
CPU time 10.86 seconds
Started Oct 11 11:45:49 PM UTC 24
Finished Oct 11 11:46:01 PM UTC 24
Peak memory 203600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763543595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1763543595
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/40.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/40.aon_timer_smoke.537090267
Short name T257
Test name
Test status
Simulation time 487759282 ps
CPU time 1.08 seconds
Started Oct 11 11:45:49 PM UTC 24
Finished Oct 11 11:45:51 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537090267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.537090267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/40.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/41.aon_timer_prescaler.2471840895
Short name T278
Test name
Test status
Simulation time 24832666602 ps
CPU time 22.98 seconds
Started Oct 11 11:45:51 PM UTC 24
Finished Oct 11 11:46:15 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471840895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2471840895
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/41.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/41.aon_timer_smoke.4034833829
Short name T258
Test name
Test status
Simulation time 374224809 ps
CPU time 1.72 seconds
Started Oct 11 11:45:51 PM UTC 24
Finished Oct 11 11:45:54 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034833829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.4034833829
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/41.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/41.aon_timer_stress_all_with_rand_reset.778166788
Short name T94
Test name
Test status
Simulation time 1350010773 ps
CPU time 5.64 seconds
Started Oct 11 11:45:51 PM UTC 24
Finished Oct 11 11:45:58 PM UTC 24
Peak memory 218184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=778166788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 41.aon_timer_stress_all_with_rand_reset.778166788
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/42.aon_timer_prescaler.527532593
Short name T283
Test name
Test status
Simulation time 45306520698 ps
CPU time 36.9 seconds
Started Oct 11 11:45:52 PM UTC 24
Finished Oct 11 11:46:31 PM UTC 24
Peak memory 203348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527532593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.527532593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/42.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/42.aon_timer_smoke.1103808168
Short name T259
Test name
Test status
Simulation time 387484454 ps
CPU time 1.39 seconds
Started Oct 11 11:45:52 PM UTC 24
Finished Oct 11 11:45:55 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103808168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1103808168
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/42.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/42.aon_timer_stress_all_with_rand_reset.2493288459
Short name T95
Test name
Test status
Simulation time 8181747725 ps
CPU time 18.8 seconds
Started Oct 11 11:45:55 PM UTC 24
Finished Oct 11 11:46:15 PM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2493288459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 42.aon_timer_stress_all_with_rand_reset.2493288459
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/43.aon_timer_prescaler.2376990568
Short name T288
Test name
Test status
Simulation time 42796373954 ps
CPU time 60.51 seconds
Started Oct 11 11:45:56 PM UTC 24
Finished Oct 11 11:46:58 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376990568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2376990568
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/43.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/43.aon_timer_smoke.1585399929
Short name T262
Test name
Test status
Simulation time 480102315 ps
CPU time 1.61 seconds
Started Oct 11 11:45:55 PM UTC 24
Finished Oct 11 11:45:57 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585399929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1585399929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/43.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/44.aon_timer_prescaler.2464581410
Short name T284
Test name
Test status
Simulation time 11466087890 ps
CPU time 30.01 seconds
Started Oct 11 11:45:58 PM UTC 24
Finished Oct 11 11:46:41 PM UTC 24
Peak memory 203348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464581410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2464581410
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/44.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/44.aon_timer_smoke.2995829142
Short name T272
Test name
Test status
Simulation time 437522308 ps
CPU time 0.91 seconds
Started Oct 11 11:45:57 PM UTC 24
Finished Oct 11 11:46:06 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995829142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2995829142
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/44.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/45.aon_timer_prescaler.2866680416
Short name T286
Test name
Test status
Simulation time 20862876602 ps
CPU time 32.15 seconds
Started Oct 11 11:45:59 PM UTC 24
Finished Oct 11 11:46:43 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866680416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2866680416
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/45.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/45.aon_timer_smoke.177626187
Short name T274
Test name
Test status
Simulation time 406871950 ps
CPU time 1.13 seconds
Started Oct 11 11:45:59 PM UTC 24
Finished Oct 11 11:46:11 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177626187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.177626187
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/45.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/46.aon_timer_prescaler.3268232143
Short name T279
Test name
Test status
Simulation time 31673083436 ps
CPU time 11.88 seconds
Started Oct 11 11:46:02 PM UTC 24
Finished Oct 11 11:46:18 PM UTC 24
Peak memory 203284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268232143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3268232143
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/46.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/46.aon_timer_smoke.2952021428
Short name T276
Test name
Test status
Simulation time 407999765 ps
CPU time 1.09 seconds
Started Oct 11 11:46:01 PM UTC 24
Finished Oct 11 11:46:13 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952021428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2952021428
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/46.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/47.aon_timer_prescaler.3668018714
Short name T291
Test name
Test status
Simulation time 49235087045 ps
CPU time 116.47 seconds
Started Oct 11 11:46:05 PM UTC 24
Finished Oct 11 11:48:04 PM UTC 24
Peak memory 203284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668018714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3668018714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/47.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/47.aon_timer_smoke.1020832119
Short name T271
Test name
Test status
Simulation time 458557454 ps
CPU time 0.73 seconds
Started Oct 11 11:46:04 PM UTC 24
Finished Oct 11 11:46:06 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020832119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1020832119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/47.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/48.aon_timer_prescaler.3307336230
Short name T289
Test name
Test status
Simulation time 37961880850 ps
CPU time 62.7 seconds
Started Oct 11 11:46:09 PM UTC 24
Finished Oct 11 11:47:14 PM UTC 24
Peak memory 203604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307336230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3307336230
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/48.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/48.aon_timer_smoke.535889661
Short name T275
Test name
Test status
Simulation time 400563587 ps
CPU time 1.69 seconds
Started Oct 11 11:46:08 PM UTC 24
Finished Oct 11 11:46:12 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535889661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.535889661
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/48.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/48.aon_timer_stress_all_with_rand_reset.3465652668
Short name T193
Test name
Test status
Simulation time 2921848663 ps
CPU time 13.91 seconds
Started Oct 11 11:46:12 PM UTC 24
Finished Oct 11 11:46:28 PM UTC 24
Peak memory 219660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3465652668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 48.aon_timer_stress_all_with_rand_reset.3465652668
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/49.aon_timer_prescaler.3917947960
Short name T282
Test name
Test status
Simulation time 21697681195 ps
CPU time 14.14 seconds
Started Oct 11 11:46:14 PM UTC 24
Finished Oct 11 11:46:30 PM UTC 24
Peak memory 203276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917947960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3917947960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/49.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/49.aon_timer_smoke.927409105
Short name T277
Test name
Test status
Simulation time 492625741 ps
CPU time 1.48 seconds
Started Oct 11 11:46:13 PM UTC 24
Finished Oct 11 11:46:15 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927409105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.927409105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/49.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/5.aon_timer_prescaler.2299135961
Short name T256
Test name
Test status
Simulation time 44554314228 ps
CPU time 66.97 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:45:58 PM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299135961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2299135961
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/5.aon_timer_smoke.73528363
Short name T9
Test name
Test status
Simulation time 607630748 ps
CPU time 0.75 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:44:51 PM UTC 24
Peak memory 201304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73528363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TES
T_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.73528363
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/5.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/6.aon_timer_jump.1636043009
Short name T14
Test name
Test status
Simulation time 479350062 ps
CPU time 0.91 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:44:52 PM UTC 24
Peak memory 201240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636043009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1636043009
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_jump/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/6.aon_timer_prescaler.4206716473
Short name T102
Test name
Test status
Simulation time 37624049036 ps
CPU time 14.91 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:45:06 PM UTC 24
Peak memory 203352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206716473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4206716473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/6.aon_timer_smoke.680804647
Short name T16
Test name
Test status
Simulation time 423394278 ps
CPU time 1.17 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:44:52 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680804647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.680804647
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/6.aon_timer_stress_all_with_rand_reset.1987932587
Short name T25
Test name
Test status
Simulation time 1820439335 ps
CPU time 9.92 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:45:01 PM UTC 24
Peak memory 219984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_
seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1987932587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 6.aon_timer_stress_all_with_rand_reset.1987932587
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/7.aon_timer_prescaler.1623874586
Short name T54
Test name
Test status
Simulation time 28642092390 ps
CPU time 7.85 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:44:59 PM UTC 24
Peak memory 203416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623874586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1623874586
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/7.aon_timer_smoke.3379757531
Short name T18
Test name
Test status
Simulation time 528696076 ps
CPU time 1.43 seconds
Started Oct 11 11:44:50 PM UTC 24
Finished Oct 11 11:44:52 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379757531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3379757531
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/7.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/8.aon_timer_prescaler.1164077806
Short name T53
Test name
Test status
Simulation time 10722902012 ps
CPU time 5.58 seconds
Started Oct 11 11:44:51 PM UTC 24
Finished Oct 11 11:44:58 PM UTC 24
Peak memory 203284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164077806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1164077806
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/8.aon_timer_smoke.482203959
Short name T19
Test name
Test status
Simulation time 480422444 ps
CPU time 1.08 seconds
Started Oct 11 11:44:51 PM UTC 24
Finished Oct 11 11:44:53 PM UTC 24
Peak memory 201308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482203959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.482203959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/8.aon_timer_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/9.aon_timer_prescaler.2814418875
Short name T214
Test name
Test status
Simulation time 9485998303 ps
CPU time 13.58 seconds
Started Oct 11 11:44:52 PM UTC 24
Finished Oct 11 11:45:06 PM UTC 24
Peak memory 203608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814418875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_T
EST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2814418875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_prescaler/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/coverage/default/9.aon_timer_smoke.949769250
Short name T222
Test name
Test status
Simulation time 479160567 ps
CPU time 1.37 seconds
Started Oct 11 11:44:51 PM UTC 24
Finished Oct 11 11:44:54 PM UTC 24
Peak memory 201300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949769250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TE
ST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.949769250
Directory /workspaces/repo/scratch/os_regression_2024_10_11/aon_timer-sim-vcs/9.aon_timer_smoke/latest
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