AON_TIMER Lint Results
Sunday May 19 2024 19:02:23 UTC
Branch: os_regression
Tool: ASCENTLINT
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Lint Infos
I FSM_DEFAULT_REQ: prim_sync_reqack.sv:253 Next state register 'gen_nrz_hs_protocol.src_fsm_ns' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: prim_sync_reqack.sv:297 Next state register 'gen_nrz_hs_protocol.dst_fsm_ns' has no assignment in the default branch of the case statement for this finite state machine New
I FSM_DEFAULT_REQ: prim_diff_decode.sv:158 Next state register 'gen_async.state_d' has no assignment in the default branch of the case statement for this finite state machine New
I NESTED_SUBPROG: tlul_pkg.sv:143 Function 'prim_mubi_pkg::mubi4_test_invalid' is called from within a function New
I CASE_INC: prim_alert_sender.sv:199 Case statement tag not specified for value 'b111 New
I CASE_INC: prim_diff_decode.sv:115 Case statement tag not specified for value 'b11 New
I CASE_INC: prim_reg_cdc_arb.sv:197 Case statement tag not specified for value 'b10 and 1 other value New
I CASE_INC: tlul_err.sv:62 Case statement tag not specified for value 'h3 New
I ONE_BIT_VEC: aon_timer.sv:10 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'AlertAsyncOn' has a length of one, instance 'aon_timer' of module 'aon_timer' (NumAlerts=1) New
I ONE_BIT_VEC: aon_timer.sv:22 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_rx_i' has a length of one, instance 'aon_timer' of module 'aon_timer' (NumAlerts=1) New
I ONE_BIT_VEC: aon_timer.sv:23 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_tx_o' has a length of one, instance 'aon_timer' of module 'aon_timer' (NumAlerts=1) New
I ONE_BIT_VEC: aon_timer.sv:65 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_test' has a length of one, instance 'aon_timer' of module 'aon_timer' (NumAlerts=1) New
I ONE_BIT_VEC: aon_timer_reg_top.sv:167 Declaration range '[0:0]' of 'wkup_cause_qs' has a length of one New
I ONE_BIT_VEC: aon_timer_reg_top.sv:538 Declaration range '[0:0]' of 'aon_wkup_cause_ds' has a length of one New
I ONE_BIT_VEC: aon_timer_reg_top.sv:540 Declaration range '[0:0]' of 'aon_wkup_cause_qs' has a length of one New
I ONE_BIT_VEC: aon_timer_reg_top.sv:541 Declaration range '[0:0]' of 'aon_wkup_cause_wdata' has a length of one New
I ONE_BIT_VEC: aon_timer_reg_top.sv:582 Declaration range '[0:0]' of 'alert_test_flds_we' has a length of one New
I ONE_BIT_VEC: aon_timer_reg_top.sv:713 Declaration range '[0:0]' of 'wkup_count_hi_flds_we' has a length of one New
I ONE_BIT_VEC: aon_timer_reg_top.sv:743 Declaration range '[0:0]' of 'wkup_count_lo_flds_we' has a length of one New
I ONE_BIT_VEC: aon_timer_reg_top.sv:922 Declaration range '[0:0]' of 'wdog_count_flds_we' has a length of one New
I ONE_BIT_VEC: aon_timer_reg_top.sv:1045 Declaration range '[0:0]' of 'wkup_cause_flds_we' has a length of one New
I ONE_BIT_VEC: prim_buf.sv:24 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'aon_timer.u_lc_sync_escalate_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_buf.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'aon_timer.u_lc_sync_escalate_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:22 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'aon_timer.u_sync_sleep_mode.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:27 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'aon_timer.u_sync_sleep_mode.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:28 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'aon_timer.u_sync_sleep_mode.u_sync_1' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'aon_timer.u_sync_sleep_mode' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:16 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'aon_timer.u_sync_sleep_mode' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:17 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'aon_timer.u_sync_sleep_mode' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:20 Declaration range '[Width - 1:0]' ([0:0]) of 'd_o' has a length of one, instance 'aon_timer.u_sync_sleep_mode' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:21 Declaration range '[Width - 1:0]' ([0:0]) of 'intq' has a length of one, instance 'aon_timer.u_sync_sleep_mode' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'aon_timer.u_lc_sync_escalate_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'aon_timer.u_lc_sync_escalate_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'inv' has a length of one, instance 'aon_timer.u_lc_sync_escalate_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'aon_timer.u_sync_sleep_mode.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:13 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'aon_timer.u_sync_sleep_mode.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'aon_timer.u_sync_sleep_mode.u_sync_1.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'aon_timer.u_lc_sync_escalate_en.gen_buffs[0].gen_bits[0].u_prim_buf' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'aon_timer.u_lc_sync_escalate_en.gen_buffs[0].gen_bits[0].u_prim_buf' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_reg_cdc.sv:30 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'ResetVal' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc' of module 'prim_reg_cdc' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc.sv:31 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'BitMask' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc' of module 'prim_reg_cdc' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc.sv:42 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'src_wd_i' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc' of module 'prim_reg_cdc' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc.sv:44 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'src_qs_o' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc' of module 'prim_reg_cdc' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc.sv:45 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_ds_i' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc' of module 'prim_reg_cdc' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc.sv:46 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_qs_i' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc' of module 'prim_reg_cdc' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc.sv:51 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_wd_o' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc' of module 'prim_reg_cdc' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc.sv:61 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'src_q' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc' of module 'prim_reg_cdc' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc.sv:112 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_qs' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc' of module 'prim_reg_cdc' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc_arb.sv:54 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'ResetVal' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc.u_arb' of module 'prim_reg_cdc_arb' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc_arb.sv:80 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_ds_i' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc.u_arb' of module 'prim_reg_cdc_arb' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc_arb.sv:81 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_qs_i' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc.u_arb' of module 'prim_reg_cdc_arb' (DataWidth=1) New
I ONE_BIT_VEC: prim_reg_cdc_arb.sv:82 Declaration range '[DataWidth - 1:0]' ([0:0]) of 'dst_qs_o' has a length of one, instance 'aon_timer.u_reg.u_wkup_cause_cdc.u_arb' of module 'prim_reg_cdc_arb' (DataWidth=1) New
I ONE_BIT_VEC: prim_subreg.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'RESVAL' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:25 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:29 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:34 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:35 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:39 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:17 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:24 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:28 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:36 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_w.unused_q' has a length of one, instance 'aon_timer.u_reg.u_wkup_ctrl_enable.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'aon_timer.u_reg.u_alert_test' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:14 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'aon_timer.u_reg.u_alert_test' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:19 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'aon_timer.u_reg.u_alert_test' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:20 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'aon_timer.u_reg.u_alert_test' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'aon_timer.u_reg.u_alert_test' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_pre' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_reg_d2h' has a length of one New
I EXPLICIT_BITLEN: prim_util_pkg.sv:85 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: tlul_err.sv:69 Bit length not specified for constant "'h1" New
I EXPLICIT_BITLEN: tlul_err.sv:77 Bit length not specified for constant "'h2" New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:20 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:26 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:29 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:34 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:38 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:42 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:46 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:51 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:54 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:59 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:63 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:67 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:72 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:75 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:81 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:85 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:91 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:95 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:100 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:105 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:111 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:115 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: aon_timer_reg_pkg.sv:121 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:85 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:111 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:217 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:243 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:349 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:375 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:481 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:507 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:25 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:29 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:21 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:24 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:14 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:19 Name 'q' is shorter than minimum length 2 New
I CONST_OUTPUT: prim_reg_cdc_arb.sv:287 Output 'src_update_o' is driven by constant zero New
I CONST_OUTPUT: prim_reg_cdc_arb.sv:287 Output 'src_update_o' is driven by constant zero in module 'prim_reg_cdc_arb' (DataWidth=13) New
I CONST_OUTPUT: tlul_adapter_reg.sv:91 Output 'addr_o[1:0]' is driven by constant zeros in module 'tlul_adapter_reg' (RegAw=6) New
I CONST_OUTPUT: tlul_adapter_reg.sv:195 Output 'intg_error_o' is driven by constant zero in module 'tlul_adapter_reg' (RegAw=6) New
Past Results