CLKMGR Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.110s	75.892us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.060s	126.604us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.980s	110.849us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	5.760s	1.059ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.760s	68.903us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.840s	260.629us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.980s	110.849us	20	20	100.00
		clkmgr_csr_aliasing	1.760s	68.903us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	0.920s	73.077us	49	50	98.00
V2	trans_enables	clkmgr_trans	1.720s	256.325us	50	50	100.00
V2	extclk	clkmgr_extclk	1.740s	328.629us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.010s	171.834us	50	50	100.00
V2	jitter	clkmgr_smoke	1.110s	75.892us	50	50	100.00
V2	frequency	clkmgr_frequency	17.330s	2.474ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.950s	2.296ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	17.330s	2.474ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.691m	14.765ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	1.000s	150.592us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.140s	107.757us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	8.110s	2.209ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	8.110s	2.209ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.060s	126.604us	5	5	100.00
		clkmgr_csr_rw	0.980s	110.849us	20	20	100.00
		clkmgr_csr_aliasing	1.760s	68.903us	5	5	100.00
		clkmgr_same_csr_outstanding	2.950s	777.369us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.060s	126.604us	5	5	100.00
		clkmgr_csr_rw	0.980s	110.849us	20	20	100.00
		clkmgr_csr_aliasing	1.760s	68.903us	5	5	100.00
		clkmgr_same_csr_outstanding	2.950s	777.369us	20	20	100.00
V2		TOTAL			489	490	99.80
V2S	tl_intg_err	clkmgr_sec_cm	10.030s	2.261ms	5	5	100.00
		clkmgr_tl_intg_err	3.270s	436.885us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.070s	451.467us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.070s	451.467us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.070s	451.467us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.070s	451.467us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	7.570s	1.880ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.270s	436.885us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	17.330s	2.474ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.950s	2.296ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.070s	451.467us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.880s	347.226us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.770s	370.481us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.190s	167.526us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	2.040s	447.016us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.130s	125.585us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.980s	110.849us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	10.030s	2.261ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.980s	110.849us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.980s	110.849us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	10.030s	2.261ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	34.995m	600.497ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			956	960	99.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	99.12	95.40	100.00	100.00	98.71	96.97	93.18

Failure Buckets

Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)' has 3 failures:

Test clkmgr_peri has 1 failures.

18.clkmgr_peri.3867219441
Line 216, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_peri/latest/run.log

      Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
  UVM_ERROR @   2292810 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
  UVM_INFO @   2292810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test clkmgr_stress_all_with_rand_reset has 2 failures.

19.clkmgr_stress_all_with_rand_reset.2708887919
Line 1289, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest/run.log

      Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
  UVM_ERROR @ 30788194610 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
  UVM_INFO @ 30788194610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.clkmgr_stress_all_with_rand_reset.2524907037
Line 1079, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest/run.log

      Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
  UVM_ERROR @ 39593297132 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
  UVM_INFO @ 39593297132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(meas_ctrl_en == MuBi4False)' has 1 failures:
- Test clkmgr_stress_all_with_rand_reset has 1 failures.
  - 40.clkmgr_stress_all_with_rand_reset.3219447660
    Line 645, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest/run.log
```
      Offending '(meas_ctrl_en == MuBi4False)'
  UVM_ERROR @ 18030965516 ps: (clkmgr_lost_calib_ctrl_en_sva_if.sv:18) [ASSERT FAILED] CtrlEnOn_A
  UVM_INFO @ 18030965516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```