26b0ee226
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | clkmgr_smoke | 1.520s | 263.689us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | clkmgr_csr_hw_reset | 0.900s | 52.752us | 5 | 5 | 100.00 |
V1 | csr_rw | clkmgr_csr_rw | 1.290s | 234.674us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | clkmgr_csr_bit_bash | 7.390s | 684.891us | 5 | 5 | 100.00 |
V1 | csr_aliasing | clkmgr_csr_aliasing | 1.980s | 215.292us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | clkmgr_csr_mem_rw_with_rand_reset | 1.480s | 50.581us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | clkmgr_csr_rw | 1.290s | 234.674us | 20 | 20 | 100.00 |
clkmgr_csr_aliasing | 1.980s | 215.292us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | peri_enables | clkmgr_peri | 1.170s | 188.650us | 50 | 50 | 100.00 |
V2 | trans_enables | clkmgr_trans | 1.590s | 307.514us | 50 | 50 | 100.00 |
V2 | extclk | clkmgr_extclk | 1.740s | 363.275us | 50 | 50 | 100.00 |
V2 | clk_status | clkmgr_clk_status | 1.120s | 195.667us | 50 | 50 | 100.00 |
V2 | jitter | clkmgr_smoke | 1.520s | 263.689us | 50 | 50 | 100.00 |
V2 | frequency | clkmgr_frequency | 17.290s | 2.358ms | 50 | 50 | 100.00 |
V2 | frequency_timeout | clkmgr_frequency_timeout | 16.870s | 2.422ms | 50 | 50 | 100.00 |
V2 | frequency_overflow | clkmgr_frequency | 17.290s | 2.358ms | 50 | 50 | 100.00 |
V2 | stress_all | clkmgr_stress_all | 1.198m | 11.457ms | 50 | 50 | 100.00 |
V2 | intr_test | clkmgr_intr_test | 0.950s | 149.167us | 50 | 50 | 100.00 |
V2 | alert_test | clkmgr_alert_test | 1.090s | 160.994us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | clkmgr_tl_errors | 4.420s | 639.484us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | clkmgr_tl_errors | 4.420s | 639.484us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | clkmgr_csr_hw_reset | 0.900s | 52.752us | 5 | 5 | 100.00 |
clkmgr_csr_rw | 1.290s | 234.674us | 20 | 20 | 100.00 | ||
clkmgr_csr_aliasing | 1.980s | 215.292us | 5 | 5 | 100.00 | ||
clkmgr_same_csr_outstanding | 1.790s | 299.930us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | clkmgr_csr_hw_reset | 0.900s | 52.752us | 5 | 5 | 100.00 |
clkmgr_csr_rw | 1.290s | 234.674us | 20 | 20 | 100.00 | ||
clkmgr_csr_aliasing | 1.980s | 215.292us | 5 | 5 | 100.00 | ||
clkmgr_same_csr_outstanding | 1.790s | 299.930us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 490 | 490 | 100.00 | |||
V2S | tl_intg_err | clkmgr_sec_cm | 5.850s | 1.172ms | 5 | 5 | 100.00 |
clkmgr_tl_intg_err | 4.160s | 639.092us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | clkmgr_shadow_reg_errors | 3.280s | 725.449us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | clkmgr_shadow_reg_errors | 3.280s | 725.449us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | clkmgr_shadow_reg_errors | 3.280s | 725.449us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | clkmgr_shadow_reg_errors | 3.280s | 725.449us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | clkmgr_shadow_reg_errors_with_csr_rw | 5.460s | 1.475ms | 20 | 20 | 100.00 |
V2S | sec_cm_bus_integrity | clkmgr_tl_intg_err | 4.160s | 639.092us | 20 | 20 | 100.00 |
V2S | sec_cm_meas_clk_bkgn_chk | clkmgr_frequency | 17.290s | 2.358ms | 50 | 50 | 100.00 |
V2S | sec_cm_timeout_clk_bkgn_chk | clkmgr_frequency_timeout | 16.870s | 2.422ms | 50 | 50 | 100.00 |
V2S | sec_cm_meas_config_shadow | clkmgr_shadow_reg_errors | 3.280s | 725.449us | 20 | 20 | 100.00 |
V2S | sec_cm_idle_intersig_mubi | clkmgr_idle_intersig_mubi | 1.840s | 384.150us | 50 | 50 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | clkmgr_lc_ctrl_intersig_mubi | 1.390s | 201.141us | 50 | 50 | 100.00 |
V2S | sec_cm_lc_ctrl_clk_handshake_intersig_mubi | clkmgr_lc_clk_byp_req_intersig_mubi | 1.580s | 313.129us | 50 | 50 | 100.00 |
V2S | sec_cm_clk_handshake_intersig_mubi | clkmgr_clk_handshake_intersig_mubi | 1.260s | 166.277us | 50 | 50 | 100.00 |
V2S | sec_cm_div_intersig_mubi | clkmgr_div_intersig_mubi | 1.300s | 184.043us | 50 | 50 | 100.00 |
V2S | sec_cm_jitter_config_mubi | clkmgr_csr_rw | 1.290s | 234.674us | 20 | 20 | 100.00 |
V2S | sec_cm_idle_ctr_redun | clkmgr_sec_cm | 5.850s | 1.172ms | 5 | 5 | 100.00 |
V2S | sec_cm_meas_config_regwen | clkmgr_csr_rw | 1.290s | 234.674us | 20 | 20 | 100.00 |
V2S | sec_cm_clk_ctrl_config_regwen | clkmgr_csr_rw | 1.290s | 234.674us | 20 | 20 | 100.00 |
V2S | prim_count_check | clkmgr_sec_cm | 5.850s | 1.172ms | 5 | 5 | 100.00 |
V2S | TOTAL | 315 | 315 | 100.00 | |||
V3 | stress_all_with_rand_reset | clkmgr_stress_all_with_rand_reset | 27.470m | 453.513ms | 47 | 50 | 94.00 |
V3 | TOTAL | 47 | 50 | 94.00 | |||
TOTAL | 957 | 960 | 99.69 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 11 | 11 | 11 | 100.00 |
V2S | 9 | 9 | 9 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.63 | 99.12 | 95.44 | 100.00 | 100.00 | 98.71 | 96.97 | 93.18 |
Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
has 2 failures:
19.clkmgr_stress_all_with_rand_reset.1369813082
Line 1363, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest/run.log
Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
UVM_ERROR @ 29044777324 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
UVM_INFO @ 29044777324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.clkmgr_stress_all_with_rand_reset.2523296324
Line 807, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest/run.log
Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
UVM_ERROR @ 13985796072 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
UVM_INFO @ 13985796072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(meas_ctrl_en == MuBi4False)'
has 1 failures:
12.clkmgr_stress_all_with_rand_reset.745488832
Line 474, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest/run.log
Offending '(meas_ctrl_en == MuBi4False)'
UVM_ERROR @ 14514849975 ps: (clkmgr_lost_calib_ctrl_en_sva_if.sv:18) [ASSERT FAILED] CtrlEnOn_A
UVM_INFO @ 14514849975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---