CLKMGR Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: 213e792ea

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.530s	285.880us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.910s	39.489us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.020s	63.266us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.480s	1.426ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	4.150s	1.107ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.690s	33.761us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.020s	63.266us	20	20	100.00
		clkmgr_csr_aliasing	4.150s	1.107ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.030s	99.407us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.720s	300.019us	50	50	100.00
V2	extclk	clkmgr_extclk	1.310s	213.059us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.860s	79.226us	50	50	100.00
V2	jitter	clkmgr_smoke	1.530s	285.880us	50	50	100.00
V2	frequency	clkmgr_frequency	18.400s	2.474ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.800s	2.303ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.400s	2.474ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.278m	12.168ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.810s	78.769us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.150s	138.295us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.090s	475.470us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.090s	475.470us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.910s	39.489us	5	5	100.00
		clkmgr_csr_rw	1.020s	63.266us	20	20	100.00
		clkmgr_csr_aliasing	4.150s	1.107ms	5	5	100.00
		clkmgr_same_csr_outstanding	1.610s	184.757us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.910s	39.489us	5	5	100.00
		clkmgr_csr_rw	1.020s	63.266us	20	20	100.00
		clkmgr_csr_aliasing	4.150s	1.107ms	5	5	100.00
		clkmgr_same_csr_outstanding	1.610s	184.757us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.830s	935.850us	5	5	100.00
		clkmgr_tl_intg_err	5.230s	1.216ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.490s	827.393us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.490s	827.393us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.490s	827.393us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.490s	827.393us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.990s	874.179us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.230s	1.216ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.400s	2.474ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.800s	2.303ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.490s	827.393us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.350s	235.337us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.190s	169.850us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.820s	366.166us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.550s	244.935us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.640s	310.857us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.020s	63.266us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.830s	935.850us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.020s	63.266us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.020s	63.266us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.830s	935.850us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	1.071h	1.079s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			960	960	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.63	99.12	95.44	100.00	100.00	98.71	96.97	93.18

Past Results

• Latest
• 2023.05.25_17.59.49
• 2023.05.24_17.23.22
• 2023.05.23_17.35.36
• 2023.05.22_19.28.47
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