V1 |
smoke |
clkmgr_smoke |
1.290s |
205.554us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
clkmgr_csr_hw_reset |
0.910s |
64.089us |
5 |
5 |
100.00 |
V1 |
csr_rw |
clkmgr_csr_rw |
1.210s |
178.883us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
clkmgr_csr_bit_bash |
6.210s |
398.643us |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
clkmgr_csr_aliasing |
2.510s |
457.645us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
clkmgr_csr_mem_rw_with_rand_reset |
1.710s |
85.765us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
clkmgr_csr_rw |
1.210s |
178.883us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.510s |
457.645us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
peri_enables |
clkmgr_peri |
1.040s |
138.050us |
50 |
50 |
100.00 |
V2 |
trans_enables |
clkmgr_trans |
1.500s |
287.384us |
50 |
50 |
100.00 |
V2 |
extclk |
clkmgr_extclk |
1.380s |
204.533us |
50 |
50 |
100.00 |
V2 |
clk_status |
clkmgr_clk_status |
1.040s |
123.005us |
50 |
50 |
100.00 |
V2 |
jitter |
clkmgr_smoke |
1.290s |
205.554us |
50 |
50 |
100.00 |
V2 |
frequency |
clkmgr_frequency |
18.140s |
2.474ms |
50 |
50 |
100.00 |
V2 |
frequency_timeout |
clkmgr_frequency_timeout |
16.250s |
2.422ms |
50 |
50 |
100.00 |
V2 |
frequency_overflow |
clkmgr_frequency |
18.140s |
2.474ms |
50 |
50 |
100.00 |
V2 |
stress_all |
clkmgr_stress_all |
1.616m |
13.668ms |
50 |
50 |
100.00 |
V2 |
intr_test |
clkmgr_intr_test |
0.920s |
139.973us |
50 |
50 |
100.00 |
V2 |
alert_test |
clkmgr_alert_test |
1.470s |
249.296us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
clkmgr_tl_errors |
4.190s |
994.638us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
clkmgr_tl_errors |
4.190s |
994.638us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
clkmgr_csr_hw_reset |
0.910s |
64.089us |
5 |
5 |
100.00 |
|
|
clkmgr_csr_rw |
1.210s |
178.883us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.510s |
457.645us |
5 |
5 |
100.00 |
|
|
clkmgr_same_csr_outstanding |
1.700s |
222.417us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
clkmgr_csr_hw_reset |
0.910s |
64.089us |
5 |
5 |
100.00 |
|
|
clkmgr_csr_rw |
1.210s |
178.883us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.510s |
457.645us |
5 |
5 |
100.00 |
|
|
clkmgr_same_csr_outstanding |
1.700s |
222.417us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
490 |
490 |
100.00 |
V2S |
tl_intg_err |
clkmgr_sec_cm |
5.320s |
1.316ms |
5 |
5 |
100.00 |
|
|
clkmgr_tl_intg_err |
3.520s |
424.052us |
20 |
20 |
100.00 |
V2S |
shadow_reg_update_error |
clkmgr_shadow_reg_errors |
3.680s |
620.692us |
20 |
20 |
100.00 |
V2S |
shadow_reg_read_clear_staged_value |
clkmgr_shadow_reg_errors |
3.680s |
620.692us |
20 |
20 |
100.00 |
V2S |
shadow_reg_storage_error |
clkmgr_shadow_reg_errors |
3.680s |
620.692us |
20 |
20 |
100.00 |
V2S |
shadowed_reset_glitch |
clkmgr_shadow_reg_errors |
3.680s |
620.692us |
20 |
20 |
100.00 |
V2S |
shadow_reg_update_error_with_csr_rw |
clkmgr_shadow_reg_errors_with_csr_rw |
4.980s |
741.332us |
20 |
20 |
100.00 |
V2S |
sec_cm_bus_integrity |
clkmgr_tl_intg_err |
3.520s |
424.052us |
20 |
20 |
100.00 |
V2S |
sec_cm_meas_clk_bkgn_chk |
clkmgr_frequency |
18.140s |
2.474ms |
50 |
50 |
100.00 |
V2S |
sec_cm_timeout_clk_bkgn_chk |
clkmgr_frequency_timeout |
16.250s |
2.422ms |
50 |
50 |
100.00 |
V2S |
sec_cm_meas_config_shadow |
clkmgr_shadow_reg_errors |
3.680s |
620.692us |
20 |
20 |
100.00 |
V2S |
sec_cm_idle_intersig_mubi |
clkmgr_idle_intersig_mubi |
1.930s |
392.506us |
50 |
50 |
100.00 |
V2S |
sec_cm_lc_ctrl_intersig_mubi |
clkmgr_lc_ctrl_intersig_mubi |
1.720s |
338.108us |
50 |
50 |
100.00 |
V2S |
sec_cm_lc_ctrl_clk_handshake_intersig_mubi |
clkmgr_lc_clk_byp_req_intersig_mubi |
1.240s |
184.099us |
50 |
50 |
100.00 |
V2S |
sec_cm_clk_handshake_intersig_mubi |
clkmgr_clk_handshake_intersig_mubi |
1.500s |
254.875us |
50 |
50 |
100.00 |
V2S |
sec_cm_div_intersig_mubi |
clkmgr_div_intersig_mubi |
1.570s |
278.153us |
50 |
50 |
100.00 |
V2S |
sec_cm_jitter_config_mubi |
clkmgr_csr_rw |
1.210s |
178.883us |
20 |
20 |
100.00 |
V2S |
sec_cm_idle_ctr_redun |
clkmgr_sec_cm |
5.320s |
1.316ms |
5 |
5 |
100.00 |
V2S |
sec_cm_meas_config_regwen |
clkmgr_csr_rw |
1.210s |
178.883us |
20 |
20 |
100.00 |
V2S |
sec_cm_clk_ctrl_config_regwen |
clkmgr_csr_rw |
1.210s |
178.883us |
20 |
20 |
100.00 |
V2S |
prim_count_check |
clkmgr_sec_cm |
5.320s |
1.316ms |
5 |
5 |
100.00 |
V2S |
|
TOTAL |
|
|
315 |
315 |
100.00 |
V3 |
stress_all_with_rand_reset |
clkmgr_stress_all_with_rand_reset |
36.986m |
608.436ms |
49 |
50 |
98.00 |
V3 |
|
TOTAL |
|
|
49 |
50 |
98.00 |
|
|
TOTAL |
|
|
959 |
960 |
99.90 |