c06cc3921
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | clkmgr_smoke | 1.500s | 247.908us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | clkmgr_csr_hw_reset | 1.030s | 140.186us | 5 | 5 | 100.00 |
V1 | csr_rw | clkmgr_csr_rw | 0.990s | 141.476us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | clkmgr_csr_bit_bash | 9.720s | 1.376ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | clkmgr_csr_aliasing | 3.550s | 850.841us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | clkmgr_csr_mem_rw_with_rand_reset | 1.760s | 115.670us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | clkmgr_csr_rw | 0.990s | 141.476us | 20 | 20 | 100.00 |
clkmgr_csr_aliasing | 3.550s | 850.841us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | peri_enables | clkmgr_peri | 0.980s | 102.631us | 49 | 50 | 98.00 |
V2 | trans_enables | clkmgr_trans | 2.710s | 647.245us | 50 | 50 | 100.00 |
V2 | extclk | clkmgr_extclk | 1.240s | 176.495us | 50 | 50 | 100.00 |
V2 | clk_status | clkmgr_clk_status | 0.910s | 15.665us | 50 | 50 | 100.00 |
V2 | jitter | clkmgr_smoke | 1.500s | 247.908us | 50 | 50 | 100.00 |
V2 | frequency | clkmgr_frequency | 18.050s | 2.361ms | 50 | 50 | 100.00 |
V2 | frequency_timeout | clkmgr_frequency_timeout | 14.500s | 2.055ms | 50 | 50 | 100.00 |
V2 | frequency_overflow | clkmgr_frequency | 18.050s | 2.361ms | 50 | 50 | 100.00 |
V2 | stress_all | clkmgr_stress_all | 1.497m | 17.955ms | 49 | 50 | 98.00 |
V2 | intr_test | clkmgr_intr_test | 0.760s | 66.476us | 50 | 50 | 100.00 |
V2 | alert_test | clkmgr_alert_test | 1.230s | 179.146us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | clkmgr_tl_errors | 4.150s | 469.146us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | clkmgr_tl_errors | 4.150s | 469.146us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | clkmgr_csr_hw_reset | 1.030s | 140.186us | 5 | 5 | 100.00 |
clkmgr_csr_rw | 0.990s | 141.476us | 20 | 20 | 100.00 | ||
clkmgr_csr_aliasing | 3.550s | 850.841us | 5 | 5 | 100.00 | ||
clkmgr_same_csr_outstanding | 1.630s | 167.617us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | clkmgr_csr_hw_reset | 1.030s | 140.186us | 5 | 5 | 100.00 |
clkmgr_csr_rw | 0.990s | 141.476us | 20 | 20 | 100.00 | ||
clkmgr_csr_aliasing | 3.550s | 850.841us | 5 | 5 | 100.00 | ||
clkmgr_same_csr_outstanding | 1.630s | 167.617us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 488 | 490 | 99.59 | |||
V2S | tl_intg_err | clkmgr_sec_cm | 14.800s | 3.579ms | 5 | 5 | 100.00 |
clkmgr_tl_intg_err | 5.290s | 1.245ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | clkmgr_shadow_reg_errors | 2.510s | 162.571us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | clkmgr_shadow_reg_errors | 2.510s | 162.571us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | clkmgr_shadow_reg_errors | 2.510s | 162.571us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | clkmgr_shadow_reg_errors | 2.510s | 162.571us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | clkmgr_shadow_reg_errors_with_csr_rw | 4.640s | 782.733us | 20 | 20 | 100.00 |
V2S | sec_cm_bus_integrity | clkmgr_tl_intg_err | 5.290s | 1.245ms | 20 | 20 | 100.00 |
V2S | sec_cm_meas_clk_bkgn_chk | clkmgr_frequency | 18.050s | 2.361ms | 50 | 50 | 100.00 |
V2S | sec_cm_timeout_clk_bkgn_chk | clkmgr_frequency_timeout | 14.500s | 2.055ms | 50 | 50 | 100.00 |
V2S | sec_cm_meas_config_shadow | clkmgr_shadow_reg_errors | 2.510s | 162.571us | 20 | 20 | 100.00 |
V2S | sec_cm_idle_intersig_mubi | clkmgr_idle_intersig_mubi | 1.700s | 288.684us | 50 | 50 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | clkmgr_lc_ctrl_intersig_mubi | 1.510s | 251.369us | 50 | 50 | 100.00 |
V2S | sec_cm_lc_ctrl_clk_handshake_intersig_mubi | clkmgr_lc_clk_byp_req_intersig_mubi | 1.340s | 222.840us | 50 | 50 | 100.00 |
V2S | sec_cm_clk_handshake_intersig_mubi | clkmgr_clk_handshake_intersig_mubi | 1.510s | 221.344us | 50 | 50 | 100.00 |
V2S | sec_cm_div_intersig_mubi | clkmgr_div_intersig_mubi | 1.170s | 103.328us | 50 | 50 | 100.00 |
V2S | sec_cm_jitter_config_mubi | clkmgr_csr_rw | 0.990s | 141.476us | 20 | 20 | 100.00 |
V2S | sec_cm_idle_ctr_redun | clkmgr_sec_cm | 14.800s | 3.579ms | 5 | 5 | 100.00 |
V2S | sec_cm_meas_config_regwen | clkmgr_csr_rw | 0.990s | 141.476us | 20 | 20 | 100.00 |
V2S | sec_cm_clk_ctrl_config_regwen | clkmgr_csr_rw | 0.990s | 141.476us | 20 | 20 | 100.00 |
V2S | prim_count_check | clkmgr_sec_cm | 14.800s | 3.579ms | 5 | 5 | 100.00 |
V2S | TOTAL | 315 | 315 | 100.00 | |||
V3 | stress_all_with_rand_reset | clkmgr_stress_all_with_rand_reset | 28.430m | 508.449ms | 50 | 50 | 100.00 |
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 958 | 960 | 99.79 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 11 | 11 | 9 | 81.82 |
V2S | 9 | 9 | 9 | 100.00 |
V3 | 1 | 1 | 1 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.63 | 99.12 | 95.44 | 100.00 | 100.00 | 98.71 | 96.97 | 93.18 |
Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
has 2 failures:
Test clkmgr_peri has 1 failures.
22.clkmgr_peri.2786340430
Line 216, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_peri/latest/run.log
Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
UVM_ERROR @ 2544733 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
UVM_INFO @ 2544733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test clkmgr_stress_all has 1 failures.
41.clkmgr_stress_all.2850232309
Line 280, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_stress_all/latest/run.log
Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
UVM_ERROR @ 50129328 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
UVM_INFO @ 50129328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---