75560c7848| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | clkmgr_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | clkmgr_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | clkmgr_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | peri_enables | clkmgr_peri | 0 | 50 | 0.00 | ||
| V2 | trans_enables | clkmgr_trans | 0 | 50 | 0.00 | ||
| V2 | extclk | clkmgr_extclk | 0 | 50 | 0.00 | ||
| V2 | clk_status | clkmgr_clk_status | 0 | 50 | 0.00 | ||
| V2 | jitter | clkmgr_smoke | 0 | 50 | 0.00 | ||
| V2 | frequency | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2 | frequency_timeout | clkmgr_frequency_timeout | 0 | 50 | 0.00 | ||
| V2 | frequency_overflow | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2 | stress_all | clkmgr_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | clkmgr_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | clkmgr_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | clkmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | clkmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| clkmgr_csr_rw | 0 | 20 | 0.00 | ||||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| clkmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | clkmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| clkmgr_csr_rw | 0 | 20 | 0.00 | ||||
| clkmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| clkmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 490 | 0.00 | |||
| V2S | tl_intg_err | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| clkmgr_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | shadow_reg_update_error | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | clkmgr_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bus_integrity | clkmgr_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_meas_clk_bkgn_chk | clkmgr_frequency | 0 | 50 | 0.00 | ||
| V2S | sec_cm_timeout_clk_bkgn_chk | clkmgr_frequency_timeout | 0 | 50 | 0.00 | ||
| V2S | sec_cm_meas_config_shadow | clkmgr_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_idle_intersig_mubi | clkmgr_idle_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | clkmgr_lc_ctrl_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_clk_handshake_intersig_mubi | clkmgr_lc_clk_byp_req_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_clk_handshake_intersig_mubi | clkmgr_clk_handshake_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_div_intersig_mubi | clkmgr_div_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_jitter_config_mubi | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_idle_ctr_redun | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_meas_config_regwen | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_clk_ctrl_config_regwen | clkmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | prim_count_check | clkmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 315 | 0.00 | |||
| V3 | regwen | clkmgr_regwen | 0 | 50 | 0.00 | ||
| V3 | stress_all_with_rand_reset | clkmgr_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| TOTAL | 0 | 1010 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 9 | 9 | 0 | 0.00 |
| V3 | 2 | 2 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1012 failures:
0.clkmgr_smoke.67692632903988149310070993377500799262641295339678506528710359654107998608989
Log /usr/local/google/home/miguelosorio/o/live/ot2/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_smoke/latest/run.log
1.clkmgr_smoke.67763285886075915676502844515875802373259962770834051396453176588123968881824
Log /usr/local/google/home/miguelosorio/o/live/ot2/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_smoke/latest/run.log
... and 48 more failures.
0.clkmgr_extclk.38312423466630573583761795101722045852292720234174067950867470531698546607166
Log /usr/local/google/home/miguelosorio/o/live/ot2/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_extclk/latest/run.log
1.clkmgr_extclk.112942028449878206788811532110736737050830529913760283609390379155272740735667
Log /usr/local/google/home/miguelosorio/o/live/ot2/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_extclk/latest/run.log
... and 48 more failures.
0.clkmgr_frequency.87263638482814578124990689013100224031560896742902331921852328287698006902406
Log /usr/local/google/home/miguelosorio/o/live/ot2/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log
1.clkmgr_frequency.68926384419824684455375952339055889720744315518414098025233722318118233693211
Log /usr/local/google/home/miguelosorio/o/live/ot2/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_frequency/latest/run.log
... and 48 more failures.
0.clkmgr_frequency_timeout.71298979747579336964945933285348176690586861440931223193406492375159449927131
Log /usr/local/google/home/miguelosorio/o/live/ot2/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log
1.clkmgr_frequency_timeout.41312312506569300900116043465722485802711789238382138438286153380873977114941
Log /usr/local/google/home/miguelosorio/o/live/ot2/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest/run.log
... and 48 more failures.
0.clkmgr_peri.109642611849317610086642959063374483517974635168468464176035475670767186237313
Log /usr/local/google/home/miguelosorio/o/live/ot2/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_peri/latest/run.log
1.clkmgr_peri.109564783734210619917111492773678813117621694901532332558365923271263458437216
Log /usr/local/google/home/miguelosorio/o/live/ot2/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_peri/latest/run.log
... and 48 more failures.
User terminated with CTRL-C has 2 failures:
Test default has 1 failures.
Test cover_reg_top has 1 failures.