Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	587032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3291988

1

T7

11

T8

2

T5

174

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	953272	1			T7	20		T8	5		T5	16
values[0x0]	1343146	1			T7	7		T8	3		T5	170
values[0x1]	1582602	1			T7	8		T8	2		T5	167

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	326545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3552475

1

T7

13

T8

4

T5

226

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14359	1			T5	1		T35	3		T37	2
valid_sources[0x01]	14232	1			T5	1		T32	3		T37	4
valid_sources[0x02]	14746	1			T5	2		T35	1		T46	2
valid_sources[0x03]	16315	1			T5	1		T35	6		T44	2
valid_sources[0x04]	14311	1			T5	1		T35	5		T44	7
valid_sources[0x05]	16462	1			T7	1		T34	1		T35	4
valid_sources[0x06]	13434	1			T5	2		T44	2		T45	8
valid_sources[0x07]	14284	1			T35	1		T44	6		T66	2
valid_sources[0x08]	15154	1			T7	1		T5	2		T34	3
valid_sources[0x09]	14589	1			T34	1		T35	8		T46	3
valid_sources[0x0a]	15633	1			T7	4		T34	1		T35	4
valid_sources[0x0b]	15762	1			T5	1		T34	3		T35	4
valid_sources[0x0c]	16967	1			T5	3		T35	2		T44	2
valid_sources[0x0d]	13573	1			T5	2		T34	1		T35	18
valid_sources[0x0e]	14896	1			T5	1		T32	18		T34	2
valid_sources[0x0f]	14681	1			T5	2		T34	3		T35	6
valid_sources[0x10]	15035	1			T5	1		T34	2		T37	3
valid_sources[0x11]	14940	1			T5	3		T33	1		T35	3
valid_sources[0x12]	14564	1			T5	1		T34	2		T35	9
valid_sources[0x13]	15009	1			T5	1		T35	17		T37	1
valid_sources[0x14]	16847	1			T7	1		T5	2		T34	1
valid_sources[0x15]	14897	1			T5	3		T34	2		T35	3
valid_sources[0x16]	15116	1			T34	1		T35	3		T37	2
valid_sources[0x17]	15057	1			T5	1		T34	1		T35	3
valid_sources[0x18]	14694	1			T34	1		T35	5		T44	1
valid_sources[0x19]	16460	1			T34	2		T44	1		T46	1
valid_sources[0x1a]	13456	1			T7	2		T5	1		T34	1
valid_sources[0x1b]	15551	1			T5	2		T32	8		T37	1
valid_sources[0x1c]	15669	1			T5	3		T34	2		T35	2
valid_sources[0x1d]	14454	1			T5	1		T34	1		T35	10
valid_sources[0x1e]	14900	1			T5	2		T34	1		T35	2
valid_sources[0x1f]	15769	1			T5	1		T34	1		T35	5
valid_sources[0x20]	15003	1			T5	2		T34	1		T35	6
valid_sources[0x21]	16374	1			T44	3		T66	2		T73	1
valid_sources[0x22]	14864	1			T5	1		T37	2		T44	1
valid_sources[0x23]	14140	1			T5	1		T34	1		T35	9
valid_sources[0x24]	14757	1			T35	5		T67	1		T68	3
valid_sources[0x25]	14993	1			T7	1		T5	2		T32	9
valid_sources[0x26]	17159	1			T5	1		T35	2		T44	2
valid_sources[0x27]	15223	1			T7	1		T34	1		T35	8
valid_sources[0x28]	16760	1			T5	1		T37	1		T44	1
valid_sources[0x29]	15173	1			T5	2		T34	1		T35	3
valid_sources[0x2a]	18052	1			T5	3		T34	1		T35	5
valid_sources[0x2b]	14928	1			T34	2		T35	1		T37	1
valid_sources[0x2c]	14949	1			T34	2		T35	3		T37	1
valid_sources[0x2d]	14830	1			T5	3		T34	2		T35	7
valid_sources[0x2e]	15022	1			T5	6		T35	1		T44	4
valid_sources[0x2f]	13965	1			T5	2		T35	4		T44	1
valid_sources[0x30]	13525	1			T33	1		T34	2		T44	7
valid_sources[0x31]	15650	1			T5	3		T34	1		T35	5
valid_sources[0x32]	14364	1			T5	2		T35	5		T44	1
valid_sources[0x33]	13321	1			T5	2		T35	7		T37	4
valid_sources[0x34]	16208	1			T5	4		T33	1		T35	7
valid_sources[0x35]	14423	1			T32	7		T33	2		T34	2
valid_sources[0x36]	14655	1			T34	1		T35	14		T44	2
valid_sources[0x37]	14189	1			T5	1		T34	1		T35	2
valid_sources[0x38]	15658	1			T5	1		T33	1		T35	3
valid_sources[0x39]	15657	1			T34	1		T35	4		T44	2
valid_sources[0x3a]	15159	1			T5	3		T34	3		T35	2
valid_sources[0x3b]	15607	1			T5	1		T34	1		T35	2
valid_sources[0x3c]	15368	1			T5	1		T34	2		T35	4
valid_sources[0x3d]	13557	1			T5	1		T32	2		T34	1
valid_sources[0x3e]	16403	1			T34	2		T35	3		T44	2
valid_sources[0x3f]	13670	1			T5	2		T44	1		T46	1
valid_sources[0x40]	14564	1			T35	1		T44	3		T46	1
valid_sources[0x41]	14771	1			T7	1		T5	2		T34	2
valid_sources[0x42]	13752	1			T7	1		T5	2		T34	1
valid_sources[0x43]	16225	1			T5	1		T33	1		T35	7
valid_sources[0x44]	14165	1			T5	1		T32	21		T34	1
valid_sources[0x45]	13536	1			T5	3		T33	1		T35	1
valid_sources[0x46]	14986	1			T5	2		T32	2		T35	3
valid_sources[0x47]	13650	1			T5	2		T33	1		T35	2
valid_sources[0x48]	14978	1			T5	2		T35	7		T37	1
valid_sources[0x49]	15098	1			T33	1		T35	10		T44	3
valid_sources[0x4a]	15651	1			T7	3		T5	1		T33	1
valid_sources[0x4b]	15586	1			T5	4		T34	1		T35	1
valid_sources[0x4c]	14794	1			T7	2		T5	3		T34	1
valid_sources[0x4d]	15693	1			T5	2		T34	4		T35	2
valid_sources[0x4e]	15754	1			T5	3		T34	1		T37	1
valid_sources[0x4f]	14388	1			T5	2		T32	1		T33	1
valid_sources[0x50]	15123	1			T5	2		T34	2		T35	1
valid_sources[0x51]	14789	1			T5	2		T35	3		T37	3
valid_sources[0x52]	15734	1			T5	2		T34	2		T44	2
valid_sources[0x53]	14260	1			T5	1		T35	2		T44	5
valid_sources[0x54]	14951	1			T5	1		T67	1		T47	2
valid_sources[0x55]	15288	1			T34	2		T35	2		T37	1
valid_sources[0x56]	16369	1			T34	1		T35	7		T37	3
valid_sources[0x57]	14713	1			T5	1		T34	1		T35	13
valid_sources[0x58]	15889	1			T34	1		T35	7		T37	1
valid_sources[0x59]	16031	1			T34	1		T35	1		T37	2
valid_sources[0x5a]	14124	1			T5	2		T32	4		T35	3
valid_sources[0x5b]	15925	1			T5	2		T35	2		T44	2
valid_sources[0x5c]	14769	1			T5	2		T33	1		T34	2
valid_sources[0x5d]	15648	1			T5	1		T35	4		T44	2
valid_sources[0x5e]	15761	1			T5	1		T34	1		T44	1
valid_sources[0x5f]	15860	1			T5	1		T35	3		T37	3
valid_sources[0x60]	14092	1			T5	3		T34	2		T35	4
valid_sources[0x61]	16003	1			T5	1		T34	1		T35	5
valid_sources[0x62]	15302	1			T5	1		T35	11		T44	1
valid_sources[0x63]	15672	1			T5	2		T35	6		T37	1
valid_sources[0x64]	14933	1			T5	1		T32	8		T35	5
valid_sources[0x65]	14629	1			T5	3		T35	1		T37	1
valid_sources[0x66]	15181	1			T5	3		T34	1		T35	1
valid_sources[0x67]	15064	1			T7	2		T35	1		T66	3
valid_sources[0x68]	15946	1			T5	1		T35	8		T44	3
valid_sources[0x69]	14940	1			T5	3		T35	5		T46	2
valid_sources[0x6a]	15199	1			T34	1		T35	1		T46	2
valid_sources[0x6b]	14712	1			T7	1		T5	2		T34	1
valid_sources[0x6c]	14590	1			T5	1		T33	2		T35	5
valid_sources[0x6d]	15501	1			T5	1		T35	11		T37	1
valid_sources[0x6e]	16145	1			T5	1		T33	1		T34	3
valid_sources[0x6f]	14371	1			T5	2		T32	1		T35	2
valid_sources[0x70]	14439	1			T5	3		T34	2		T35	6
valid_sources[0x71]	14031	1			T7	1		T8	5		T5	1
valid_sources[0x72]	16957	1			T5	1		T35	1		T44	1
valid_sources[0x73]	14767	1			T5	1		T34	2		T35	10
valid_sources[0x74]	14826	1			T34	1		T35	5		T37	2
valid_sources[0x75]	17007	1			T5	1		T32	21		T35	2
valid_sources[0x76]	16499	1			T5	1		T35	5		T37	6
valid_sources[0x77]	16578	1			T35	4		T67	2		T47	2
valid_sources[0x78]	15118	1			T5	1		T34	1		T35	6
valid_sources[0x79]	16950	1			T34	1		T35	4		T66	2
valid_sources[0x7a]	14210	1			T5	6		T35	7		T46	1
valid_sources[0x7b]	15044	1			T33	1		T34	1		T35	6
valid_sources[0x7c]	15970	1			T5	3		T46	1		T66	1
valid_sources[0x7d]	14871	1			T5	2		T35	2		T37	5
valid_sources[0x7e]	14133	1			T34	1		T35	5		T44	1
valid_sources[0x7f]	14468	1			T7	1		T5	1		T32	7
valid_sources[0x80]	15830	1			T33	1		T35	10		T37	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

831774

1

T7

10

T8

2

T5

12

values[0x0]

all_enables

biggest_size

1251615

1

T7

1

T5

102

T32

25

values[0x1]

all_enables

biggest_size

1208599

1

T5

60

T32

10

T33

1