Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 300062416 1 T7 2530 T8 1536 T5 387656
auto[1] 426948 1 T8 164 T26 424 T1 1178


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 300103214 1 T7 2530 T8 1492 T5 387656
auto[1] 386150 1 T8 208 T26 424 T1 852


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 299972780 1 T7 2530 T8 1492 T5 387656
auto[1] 516584 1 T8 208 T26 358 T1 1078


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 281225322 1 T7 2530 T8 56 T5 387656
auto[1] 19264042 1 T8 1644 T26 2500 T1 4040


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 156644060 1 T7 516 T8 1472 T5 387636
auto[1] 143845304 1 T7 2014 T8 228 T5 20


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 140023238 1 T7 516 T8 56 T5 387636
auto[0] auto[0] auto[0] auto[0] auto[1] 140868448 1 T7 2014 T5 20 T32 40
auto[0] auto[0] auto[0] auto[1] auto[0] 32022 1 T26 118 T1 172 T27 210
auto[0] auto[0] auto[0] auto[1] auto[1] 6406 1 T1 14 T27 22 T2 58
auto[0] auto[0] auto[1] auto[0] auto[0] 16029894 1 T8 1310 T26 1988 T1 1766
auto[0] auto[0] auto[1] auto[0] auto[1] 2859308 1 T8 126 T1 1582 T27 2920
auto[0] auto[0] auto[1] auto[1] auto[0] 52728 1 T26 122 T1 64 T27 142
auto[0] auto[0] auto[1] auto[1] auto[1] 14242 1 T1 34 T27 72 T2 188
auto[0] auto[1] auto[0] auto[0] auto[0] 28808 1 T26 22 T1 58 T27 30
auto[0] auto[1] auto[0] auto[0] auto[1] 1144 1 T27 2 T2 8 T161 6
auto[0] auto[1] auto[0] auto[1] auto[0] 13002 1 T26 56 T1 142 T27 146
auto[0] auto[1] auto[0] auto[1] auto[1] 2956 1 T27 54 T161 60 T14 114
auto[0] auto[1] auto[1] auto[0] auto[0] 10926 1 T26 32 T27 36 T2 16
auto[0] auto[1] auto[1] auto[0] auto[1] 3164 1 T27 8 T2 64 T156 16
auto[0] auto[1] auto[1] auto[1] auto[0] 20576 1 T27 132 T2 162 T29 44
auto[0] auto[1] auto[1] auto[1] auto[1] 5918 1 T2 158 T162 44 T163 48
auto[1] auto[0] auto[0] auto[0] auto[0] 63134 1 T1 48 T27 14 T2 80
auto[1] auto[0] auto[0] auto[0] auto[1] 3362 1 T1 8 T27 8 T105 24
auto[1] auto[0] auto[0] auto[1] auto[0] 34656 1 T1 140 T27 154 T2 366
auto[1] auto[0] auto[0] auto[1] auto[1] 7022 1 T1 92 T2 162 T161 54
auto[1] auto[0] auto[1] auto[0] auto[0] 29810 1 T26 44 T1 58 T27 100
auto[1] auto[0] auto[1] auto[0] auto[1] 7542 1 T1 20 T27 14 T105 22
auto[1] auto[0] auto[1] auto[1] auto[0] 56818 1 T27 376 T105 224 T2 1260
auto[1] auto[0] auto[1] auto[1] auto[1] 14584 1 T1 60 T27 164 T105 64
auto[1] auto[1] auto[0] auto[0] auto[0] 73302 1 T1 44 T27 62 T2 212
auto[1] auto[1] auto[0] auto[0] auto[1] 5654 1 T27 34 T2 16 T164 12
auto[1] auto[1] auto[0] auto[1] auto[0] 49578 1 T1 152 T27 236 T2 710
auto[1] auto[1] auto[0] auto[1] auto[1] 12590 1 T27 42 T2 178 T164 36
auto[1] auto[1] auto[1] auto[0] auto[0] 43812 1 T8 20 T26 186 T1 100
auto[1] auto[1] auto[1] auto[0] auto[1] 10870 1 T8 24 T1 48 T27 86
auto[1] auto[1] auto[1] auto[1] auto[0] 81756 1 T8 86 T26 128 T1 308
auto[1] auto[1] auto[1] auto[1] auto[1] 22094 1 T8 78 T27 162 T105 36

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