Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	758520230	75389	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758520230	75389	0	0
T1	2819910	1247	0	0
T2	0	2075	0	0
T3	0	188	0	0
T6	105390	0	0	0
T10	0	76	0	0
T11	0	141	0	0
T12	0	361	0	0
T13	0	318	0	0
T14	0	311	0	0
T15	0	396	0	0
T16	0	1254	0	0
T17	5370	0	0	0
T18	6630	0	0	0
T19	4265	0	0	0
T20	19690	0	0	0
T21	9000	0	0	0
T22	10025	0	0	0
T23	7335	0	0	0
T24	7910	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151704046	11175	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	11175	0	0
T1	563982	183	0	0
T2	0	300	0	0
T3	0	27	0	0
T6	21078	0	0	0
T10	0	11	0	0
T11	0	23	0	0
T12	0	66	0	0
T13	0	62	0	0
T14	0	52	0	0
T15	0	52	0	0
T16	0	205	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T24	1582	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151704046	15134	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	15134	0	0
T1	563982	253	0	0
T2	0	419	0	0
T3	0	38	0	0
T6	21078	0	0	0
T10	0	15	0	0
T11	0	29	0	0
T12	0	70	0	0
T13	0	62	0	0
T14	0	66	0	0
T15	0	81	0	0
T16	0	259	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T24	1582	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151704046	22973	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	22973	0	0
T1	563982	411	0	0
T2	0	642	0	0
T3	0	59	0	0
T6	21078	0	0	0
T10	0	22	0	0
T11	0	38	0	0
T12	0	89	0	0
T13	0	70	0	0
T14	0	85	0	0
T15	0	132	0	0
T16	0	350	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T24	1582	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151704046	10986	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	10986	0	0
T1	563982	156	0	0
T2	0	297	0	0
T3	0	28	0	0
T6	21078	0	0	0
T10	0	11	0	0
T11	0	22	0	0
T12	0	66	0	0
T13	0	62	0	0
T14	0	47	0	0
T15	0	52	0	0
T16	0	192	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T24	1582	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151704046	15121	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	15121	0	0
T1	563982	244	0	0
T2	0	417	0	0
T3	0	36	0	0
T6	21078	0	0	0
T10	0	17	0	0
T11	0	29	0	0
T12	0	70	0	0
T13	0	62	0	0
T14	0	61	0	0
T15	0	79	0	0
T16	0	248	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T24	1582	0	0	0