Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T1,T27,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	151704046	149308187	0	0
AllClkBypReqTrue_A	151704046	133640	0	0
IoClkBypReqFalse_A	151704046	149223865	0	2409
IoClkBypReqTrue_A	151704046	213462	0	0
LcClkBypAckFalse_A	151704046	149316122	0	0
LcClkBypAckTrue_A	151704046	125705	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	149308187	0	0
T1	563982	562477	0	0
T5	193926	193827	0	0
T7	1306	1264	0	0
T8	876	745	0	0
T17	1074	1032	0	0
T18	1326	1250	0	0
T19	853	835	0	0
T20	3938	3697	0	0
T21	1800	1761	0	0
T26	1505	1279	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	133640	0	0
T1	563982	297	0	0
T2	0	1736	0	0
T5	193926	0	0	0
T6	21078	0	0	0
T8	876	104	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T26	1505	179	0	0
T27	0	759	0	0
T29	0	132	0	0
T105	0	253	0	0
T106	0	47	0	0
T107	0	119	0	0
T108	0	229	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	149223865	0	2409
T1	563982	562169	0	3
T5	193926	193825	0	3
T7	1306	1262	0	3
T8	876	765	0	3
T17	1074	1030	0	3
T18	1326	1248	0	3
T19	853	833	0	3
T20	3938	3695	0	3
T21	1800	1759	0	3
T26	1505	1244	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	213462	0	0
T1	563982	589	0	0
T2	0	2727	0	0
T5	193926	0	0	0
T6	21078	0	0	0
T8	876	82	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T26	1505	212	0	0
T27	0	1229	0	0
T29	0	317	0	0
T105	0	193	0	0
T107	0	41	0	0
T108	0	290	0	0
T109	0	227	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	149316122	0	0
T1	563982	562409	0	0
T5	193926	193827	0	0
T7	1306	1264	0	0
T8	876	812	0	0
T17	1074	1032	0	0
T18	1326	1250	0	0
T19	853	835	0	0
T20	3938	3697	0	0
T21	1800	1761	0	0
T26	1505	1350	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151704046	125705	0	0
T1	563982	365	0	0
T2	0	1734	0	0
T5	193926	0	0	0
T6	21078	0	0	0
T8	876	37	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T26	1505	108	0	0
T27	0	708	0	0
T29	0	220	0	0
T105	0	120	0	0
T107	0	6	0	0
T108	0	174	0	0
T109	0	110	0	0