Module Definition
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Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TransStart_A 2147483647 15592 0 0
TransStop_A 2147483647 8032 0 0


TransStart_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 15592 0 0
T1 2302000 61 0 0
T2 0 237 0 0
T5 607708 0 0 0
T6 327316 0 0 0
T7 21776 8 0 0
T8 14624 0 0 0
T17 18688 0 0 0
T18 13968 0 0 0
T19 34140 0 0 0
T20 15756 44 0 0
T21 28812 31 0 0
T22 0 20 0 0
T27 0 33 0 0
T29 0 63 0 0
T110 0 23 0 0
T111 0 26 0 0

TransStop_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 8032 0 0
T1 2302000 36 0 0
T2 0 114 0 0
T5 455781 0 0 0
T6 327316 0 0 0
T7 16332 4 0 0
T8 10968 0 0 0
T17 18688 0 0 0
T18 13968 0 0 0
T19 34140 0 0 0
T20 15756 18 0 0
T21 28812 14 0 0
T22 4013 11 0 0
T23 3123 0 0 0
T24 1614 0 0 0
T27 0 25 0 0
T29 0 29 0 0
T110 0 14 0 0
T111 0 13 0 0
T112 0 1 0 0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TransStart_A 595694752 3854 0 0
TransStop_A 595694752 2001 0 0


TransStart_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595694752 3854 0 0
T1 575500 14 0 0
T2 0 57 0 0
T5 151927 0 0 0
T6 81829 0 0 0
T7 5444 1 0 0
T8 3656 0 0 0
T17 4672 0 0 0
T18 3492 0 0 0
T19 8535 0 0 0
T20 3939 11 0 0
T21 7203 8 0 0
T22 0 7 0 0
T27 0 11 0 0
T29 0 11 0 0
T110 0 6 0 0
T111 0 8 0 0

TransStop_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595694752 2001 0 0
T1 575500 10 0 0
T2 0 30 0 0
T5 151927 0 0 0
T6 81829 0 0 0
T7 5444 1 0 0
T8 3656 0 0 0
T17 4672 0 0 0
T18 3492 0 0 0
T19 8535 0 0 0
T20 3939 4 0 0
T21 7203 4 0 0
T22 0 4 0 0
T27 0 8 0 0
T29 0 4 0 0
T110 0 4 0 0
T111 0 4 0 0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TransStart_A 595694752 3918 0 0
TransStop_A 595694752 2002 0 0


TransStart_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595694752 3918 0 0
T1 575500 18 0 0
T2 0 61 0 0
T5 151927 0 0 0
T6 81829 0 0 0
T7 5444 3 0 0
T8 3656 0 0 0
T17 4672 0 0 0
T18 3492 0 0 0
T19 8535 0 0 0
T20 3939 9 0 0
T21 7203 7 0 0
T22 0 4 0 0
T27 0 8 0 0
T29 0 14 0 0
T110 0 5 0 0
T111 0 4 0 0

TransStop_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595694752 2002 0 0
T1 575500 11 0 0
T2 0 27 0 0
T5 151927 0 0 0
T6 81829 0 0 0
T7 5444 2 0 0
T8 3656 0 0 0
T17 4672 0 0 0
T18 3492 0 0 0
T19 8535 0 0 0
T20 3939 4 0 0
T21 7203 3 0 0
T22 0 2 0 0
T27 0 5 0 0
T29 0 6 0 0
T110 0 4 0 0
T111 0 3 0 0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TransStart_A 595694752 3948 0 0
TransStop_A 595694752 2012 0 0


TransStart_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595694752 3948 0 0
T1 575500 15 0 0
T2 0 57 0 0
T5 151927 0 0 0
T6 81829 0 0 0
T7 5444 3 0 0
T8 3656 0 0 0
T17 4672 0 0 0
T18 3492 0 0 0
T19 8535 0 0 0
T20 3939 12 0 0
T21 7203 7 0 0
T22 0 5 0 0
T27 0 7 0 0
T29 0 19 0 0
T110 0 6 0 0
T111 0 6 0 0

TransStop_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595694752 2012 0 0
T1 575500 9 0 0
T2 0 26 0 0
T5 151927 0 0 0
T6 81829 0 0 0
T7 5444 1 0 0
T8 3656 0 0 0
T17 4672 0 0 0
T18 3492 0 0 0
T19 8535 0 0 0
T20 3939 5 0 0
T21 7203 2 0 0
T22 0 3 0 0
T27 0 6 0 0
T29 0 10 0 0
T110 0 3 0 0
T111 0 1 0 0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TransStart_A 595694752 3872 0 0
TransStop_A 595694752 2017 0 0


TransStart_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595694752 3872 0 0
T1 575500 14 0 0
T2 0 62 0 0
T5 151927 0 0 0
T6 81829 0 0 0
T7 5444 1 0 0
T8 3656 0 0 0
T17 4672 0 0 0
T18 3492 0 0 0
T19 8535 0 0 0
T20 3939 12 0 0
T21 7203 9 0 0
T22 0 4 0 0
T27 0 7 0 0
T29 0 19 0 0
T110 0 6 0 0
T111 0 8 0 0

TransStop_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 595694752 2017 0 0
T1 575500 6 0 0
T2 0 31 0 0
T6 81829 0 0 0
T17 4672 0 0 0
T18 3492 0 0 0
T19 8535 0 0 0
T20 3939 5 0 0
T21 7203 5 0 0
T22 4013 2 0 0
T23 3123 0 0 0
T24 1614 0 0 0
T27 0 6 0 0
T29 0 9 0 0
T110 0 3 0 0
T111 0 5 0 0
T112 0 1 0 0

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