Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	931330	0	0
SrcPulseCheck_M	2147483647	930007	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	931330
T1	1792313	1212
T2	0	8613
T3	0	458
T4	0	30
T5	730972	712
T6	206685	278
T10	0	264
T11	0	1016
T17	14607	0
T18	10898	0
T19	26905	0
T20	12329	0
T21	22611	0
T22	12562	0
T23	9749	0
T25	0	16
T27	0	1042
T28	0	614
T29	0	1478
T32	9469	26
T33	2518	3
T35	18279	64
T44	7527	35
T45	3525	3
T46	3210	8
T66	26644	41
T67	12742	20
T68	12133	36
T71	4945	0
T120	727	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	930007
T1	573270	1212
T2	0	8616
T3	0	458
T4	0	30
T5	459078	712
T6	21630	278
T10	0	264
T11	0	1016
T17	2378	0
T18	2302	0
T19	3241	0
T20	5038	0
T21	3816	0
T22	3125	0
T23	2343	0
T25	0	16
T27	0	1042
T28	0	614
T29	0	1478
T32	7844	26
T33	2518	3
T35	18279	65
T44	7527	35
T45	3525	3
T46	3210	8
T66	34070	41
T67	9590	20
T68	12133	36
T71	2272	0
T120	1450	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	564075522	24628	0	0
SrcPulseCheck_M	152611123	24628	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	564075522	24628
T1	540943	96
T2	0	531
T3	0	42
T4	0	30
T5	140085	32
T6	55513	14
T17	4483	0
T18	3352	0
T19	8193	0
T20	3781	0
T21	6915	0
T22	3852	0
T23	2997	0
T25	0	16
T27	0	46
T28	0	24
T29	0	70

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152611123	24628
T1	563982	96
T2	0	531
T3	0	42
T4	0	30
T5	193926	32
T6	21078	14
T17	1074	0
T18	1326	0
T19	853	0
T20	3938	0
T21	1800	0
T22	2005	0
T23	1467	0
T25	0	16
T27	0	46
T28	0	24
T29	0	70

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	564075522	30058	0	0
SrcPulseCheck_M	152611123	30074	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	564075522	30058
T5	140085	32
T32	4798	18
T33	1719	3
T35	18630	71
T44	5315	35
T45	5266	1
T46	2113	20
T66	29281	23
T67	5137	17
T68	12067	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152611123	30074
T5	193926	32
T32	3698	19
T33	1719	3
T35	9897	71
T44	5315	36
T45	986	1
T46	2200	20
T66	6406	23
T67	5298	18
T68	6160	36

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	30046	0	0
SrcPulseCheck_M	564075522	30060	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	30046
T5	193926	32
T32	3698	18
T33	1719	3
T35	9897	70
T44	5315	34
T45	986	1
T46	2200	20
T66	6406	23
T67	5298	17
T68	6160	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	564075522	30060
T5	140085	32
T32	4798	18
T33	1719	3
T35	18630	71
T44	5315	35
T45	5266	1
T46	2113	20
T66	29281	23
T67	5137	17
T68	12067	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	281363680	24627	0	0
SrcPulseCheck_M	152611123	24627	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	281363680	24627
T1	270348	96
T2	0	531
T3	0	42
T4	0	30
T5	70010	32
T6	27737	14
T17	2181	0
T18	1622	0
T19	4071	0
T20	1844	0
T21	3397	0
T22	1879	0
T23	1452	0
T25	0	16
T27	0	46
T28	0	24
T29	0	70

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152611123	24627
T1	563982	96
T2	0	531
T3	0	42
T4	0	30
T5	193926	32
T6	21078	14
T17	1074	0
T18	1326	0
T19	853	0
T20	3938	0
T21	1800	0
T22	2005	0
T23	1467	0
T25	0	16
T27	0	46
T28	0	24
T29	0	70

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	281363680	30054	0	0
SrcPulseCheck_M	152611123	30083	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	281363680	30054
T5	70010	32
T32	2073	26
T33	799	3
T35	8382	64
T44	2212	35
T45	2539	3
T46	1010	8
T66	13832	41
T67	2146	20
T68	5973	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152611123	30083
T5	193926	32
T32	3698	26
T33	1719	3
T35	9897	68
T44	5315	35
T45	986	3
T46	2200	8
T66	6406	42
T67	5298	21
T68	6160	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	30048	0	0
SrcPulseCheck_M	281363680	30057	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	30048
T5	193926	32
T32	3698	26
T33	1719	3
T35	9897	64
T44	5315	35
T45	986	3
T46	2200	8
T66	6406	41
T67	5298	20
T68	6160	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	281363680	30057
T5	70010	32
T32	2073	26
T33	799	3
T35	8382	65
T44	2212	35
T45	2539	3
T46	1010	8
T66	13832	41
T67	2146	20
T68	5973	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	140681263	24625	0	0
SrcPulseCheck_M	152611123	24625	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	140681263	24625
T1	135174	96
T2	0	531
T3	0	42
T4	0	30
T5	35005	32
T6	13869	14
T17	1091	0
T18	811	0
T19	2035	0
T20	922	0
T21	1699	0
T22	940	0
T23	726	0
T25	0	16
T27	0	46
T28	0	24
T29	0	70

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152611123	24625
T1	563982	96
T2	0	531
T3	0	42
T4	0	30
T5	193926	32
T6	21078	14
T17	1074	0
T18	1326	0
T19	853	0
T20	3938	0
T21	1800	0
T22	2005	0
T23	1467	0
T25	0	16
T27	0	46
T28	0	24
T29	0	70

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T33,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T33,T35
1	1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	140681263	30054	0	0
SrcPulseCheck_M	152611123	30088	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	140681263	30054
T5	35005	32
T32	1036	5
T33	400	3
T35	4190	70
T44	1105	33
T45	1270	1
T46	505	5
T66	6914	37
T67	1076	7
T68	2987	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152611123	30088
T5	193926	32
T32	3698	5
T33	1719	3
T35	9897	70
T44	5315	34
T45	986	1
T46	2200	5
T66	6406	39
T67	5298	7
T68	6160	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T33,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T33,T35
1	1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	30047	0	0
SrcPulseCheck_M	140681263	30055	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	30047
T5	193926	32
T32	3698	5
T33	1719	3
T35	9897	70
T44	5315	33
T45	986	1
T46	2200	5
T66	6406	37
T67	5298	7
T68	6160	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	140681263	30055
T5	35005	32
T32	1036	5
T33	400	3
T35	4190	70
T44	1105	34
T45	1270	1
T46	505	5
T66	6914	37
T67	1076	7
T68	2987	36

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	598285493	24624	0	0
SrcPulseCheck_M	152611123	24624	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	598285493	24624
T1	575500	96
T2	0	531
T3	0	42
T4	0	30
T5	151926	32
T6	81829	14
T17	4671	0
T18	3491	0
T19	8535	0
T20	3938	0
T21	7203	0
T22	4012	0
T23	3122	0
T25	0	16
T27	0	46
T28	0	24
T29	0	70

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152611123	24624
T1	563982	96
T2	0	531
T3	0	42
T4	0	30
T5	193926	32
T6	21078	14
T17	1074	0
T18	1326	0
T19	853	0
T20	3938	0
T21	1800	0
T22	2005	0
T23	1467	0
T25	0	16
T27	0	46
T28	0	24
T29	0	70

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	598285493	30268	0	0
SrcPulseCheck_M	152611123	30282	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	598285493	30268
T5	151926	32
T32	4999	24
T33	1792	3
T35	19407	65
T44	5537	35
T45	5485	1
T46	2200	15
T66	30503	52
T67	5351	22
T68	12570	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152611123	30282
T5	193926	32
T32	3698	24
T33	1719	3
T35	9897	65
T44	5315	35
T45	986	1
T46	2200	15
T66	6406	52
T67	5298	22
T68	6160	36

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	30259	0	0
SrcPulseCheck_M	598285493	30271	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	30259
T5	193926	32
T32	3698	24
T33	1719	3
T35	9897	65
T44	5315	35
T45	986	1
T46	2200	15
T66	6406	52
T67	5298	22
T68	6160	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	598285493	30271
T5	151926	32
T32	4999	24
T33	1792	3
T35	19407	65
T44	5537	35
T45	5485	1
T46	2200	15
T66	30503	52
T67	5351	22
T68	12570	36

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	286931354	24257	0	0
SrcPulseCheck_M	152611123	24622	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	286931354	24257
T1	270485	96
T2	0	531
T3	0	42
T4	0	17
T5	90206	32
T6	42158	14
T17	2241	0
T18	1675	0
T19	4097	0
T20	1890	0
T21	3458	0
T22	1925	0
T23	1498	0
T25	0	11
T27	0	46
T28	0	24
T29	0	70

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152611123	24622
T1	563982	96
T2	0	531
T3	0	42
T4	0	30
T5	193926	32
T6	21078	14
T17	1074	0
T18	1326	0
T19	853	0
T20	3938	0
T21	1800	0
T22	2005	0
T23	1467	0
T25	0	16
T27	0	46
T28	0	24
T29	0	70

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	286931354	29970	0	0
SrcPulseCheck_M	152611123	30137	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	286931354	29970
T5	90206	32
T32	2399	18
T33	860	3
T35	9315	67
T44	2658	34
T45	2632	1
T46	1056	10
T66	14641	31
T67	2569	17
T68	6033	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152611123	30137
T5	193926	32
T32	3698	18
T33	1719	3
T35	9897	69
T44	5315	34
T45	986	1
T46	2200	10
T66	6406	31
T67	5298	18
T68	6160	36

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T32,T33
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	29849	0	0
SrcPulseCheck_M	286931354	30008	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	29849
T5	193926	32
T32	3698	18
T33	1719	3
T35	9897	67
T44	5315	34
T45	986	1
T46	2200	10
T66	6406	31
T67	5298	17
T68	6160	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	286931354	30008
T5	90206	32
T32	2399	18
T33	860	3
T35	9315	67
T44	2658	34
T45	2632	1
T46	1056	10
T66	14641	31
T67	2569	17
T68	6033	36

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T67
1	0	Covered	T32,T66,T67
1	1	Covered	T66,T67,T72

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T67
1	0	Covered	T66,T67,T72
1	1	Covered	T32,T66,T67

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	44	0	0
SrcPulseCheck_M	564075522	44	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	44
T32	3698	2
T66	6406	2
T67	5298	2
T70	8822	2
T72	3119	2
T90	1627	0
T91	15549	0
T121	0	1
T122	0	1
T123	0	3
T124	0	1
T125	0	4
T126	8807	0
T127	1347	0
T128	5916	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	564075522	44
T32	4798	2
T66	29281	2
T67	5137	2
T70	16937	2
T72	17618	2
T90	3253	0
T91	14926	0
T121	0	1
T122	0	1
T123	0	3
T124	0	1
T125	0	4
T126	33823	0
T127	4788	0
T128	5916	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T67
1	0	Covered	T32,T66,T67
1	1	Covered	T66,T67,T129

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T67
1	0	Covered	T66,T67,T129
1	1	Covered	T32,T66,T67

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	36	0	0
SrcPulseCheck_M	564075522	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	36
T32	3698	1
T66	6406	2
T67	5298	2
T70	8822	1
T72	3119	1
T90	1627	0
T91	15549	0
T121	0	1
T122	0	1
T126	8807	0
T127	1347	0
T128	5916	1
T130	0	1
T131	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	564075522	36
T32	4798	1
T66	29281	2
T67	5137	2
T70	16937	1
T72	17618	1
T90	3253	0
T91	14926	0
T121	0	1
T122	0	1
T126	33823	0
T127	4788	0
T128	5916	1
T130	0	1
T131	0	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T67
1	0	Covered	T32,T66,T67
1	1	Covered	T32,T71,T132

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T67
1	0	Covered	T32,T71,T132
1	1	Covered	T32,T66,T67

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	36	0	0
SrcPulseCheck_M	281363680	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	36
T32	3698	2
T66	6406	2
T67	5298	1
T69	0	2
T70	0	2
T71	4945	2
T74	14499	0
T75	5852	0
T77	2597	0
T81	1755	0
T91	0	1
T120	727	0
T122	0	1
T128	0	1
T133	0	1
T134	1335	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	281363680	36
T32	2073	2
T66	13832	2
T67	2146	1
T69	0	2
T70	0	2
T71	2272	2
T74	5994	0
T75	2355	0
T77	24466	0
T81	824	0
T91	0	1
T120	1450	0
T122	0	1
T128	0	1
T133	0	1
T134	2451	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T71
1	0	Covered	T32,T66,T71
1	1	Covered	T32,T66,T71

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T71
1	0	Covered	T32,T66,T71
1	1	Covered	T32,T66,T71

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	34	0	0
SrcPulseCheck_M	281363680	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	34
T32	3698	2
T66	6406	3
T69	0	1
T71	4945	2
T72	3119	0
T74	14499	0
T75	5852	0
T77	2597	0
T81	1755	0
T91	0	1
T120	727	0
T123	0	2
T125	0	2
T128	0	1
T133	0	1
T134	1335	0
T135	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	281363680	34
T32	2073	2
T66	13832	3
T69	0	1
T71	2272	2
T72	8245	0
T74	5994	0
T75	2355	0
T77	24466	0
T81	824	0
T91	0	1
T120	1450	0
T123	0	2
T125	0	2
T128	0	1
T133	0	1
T134	2451	0
T135	0	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T66,T71,T69
1	0	Covered	T66,T71,T69
1	1	Covered	T71,T69,T136

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T66,T71,T69
1	0	Covered	T71,T69,T136
1	1	Covered	T66,T71,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	35	0	0
SrcPulseCheck_M	140681263	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	35
T66	6406	2
T69	0	2
T71	4945	2
T72	3119	0
T74	14499	0
T75	5852	0
T77	2597	0
T81	1755	0
T120	727	0
T121	0	2
T123	0	2
T125	0	1
T126	8807	0
T129	0	1
T131	0	1
T133	0	2
T134	1335	0
T137	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	140681263	35
T66	6914	2
T69	0	2
T71	1136	2
T72	4124	0
T74	2997	0
T75	1175	0
T77	12234	0
T81	412	0
T120	725	0
T121	0	2
T123	0	2
T125	0	1
T126	8422	0
T129	0	1
T131	0	1
T133	0	2
T134	1226	0
T137	0	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T66,T71,T72
1	0	Covered	T66,T71,T72
1	1	Covered	T71,T69,T137

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T66,T71,T72
1	0	Covered	T71,T69,T137
1	1	Covered	T66,T71,T72

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	40	0	0
SrcPulseCheck_M	140681263	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	40
T66	6406	2
T69	0	2
T70	0	1
T71	4945	2
T72	3119	1
T74	14499	0
T75	5852	0
T77	2597	0
T81	1755	0
T120	727	0
T123	0	2
T124	0	1
T126	8807	0
T131	0	1
T133	0	1
T134	1335	0
T137	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	140681263	40
T66	6914	2
T69	0	2
T70	0	1
T71	1136	2
T72	4124	1
T74	2997	0
T75	1175	0
T77	12234	0
T81	412	0
T120	725	0
T123	0	2
T124	0	1
T126	8422	0
T131	0	1
T133	0	1
T134	1226	0
T137	0	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T66,T67,T69
1	0	Covered	T66,T67,T69
1	1	Covered	T67,T135,T138

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T66,T67,T69
1	0	Covered	T67,T135,T138
1	1	Covered	T66,T67,T69

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	35	0	0
SrcPulseCheck_M	598285493	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	35
T66	6406	1
T67	5298	3
T69	5699	2
T70	8822	2
T76	6451	0
T90	1627	0
T91	15549	2
T121	0	2
T122	0	1
T127	1347	0
T128	5916	1
T130	0	1
T137	0	2
T139	582	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	598285493	35
T66	30503	1
T67	5351	3
T69	23748	2
T70	17644	2
T76	12902	0
T90	3390	0
T91	15549	2
T121	0	2
T122	0	1
T127	4988	0
T128	6163	1
T130	0	1
T137	0	2
T139	2532	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T67
1	0	Covered	T32,T66,T67
1	1	Covered	T138

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T67
1	0	Covered	T138
1	1	Covered	T32,T66,T67

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	26	0	0
SrcPulseCheck_M	598285493	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	26
T32	3698	1
T66	6406	1
T67	5298	2
T69	0	1
T70	0	2
T71	4945	1
T74	14499	0
T75	5852	0
T77	2597	0
T81	1755	0
T91	0	2
T120	727	0
T130	0	1
T134	1335	0
T135	0	1
T137	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	598285493	26
T32	4999	1
T66	30503	1
T67	5351	2
T69	0	1
T70	0	2
T71	5317	1
T74	14645	0
T75	5852	0
T77	51965	0
T81	1829	0
T91	0	2
T120	3161	0
T130	0	1
T134	5343	0
T135	0	1
T137	0	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T67
1	0	Covered	T32,T66,T67
1	1	Covered	T121,T125,T140

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T66,T67
1	0	Covered	T121,T125,T140
1	1	Covered	T32,T66,T67

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	41	0	0
SrcPulseCheck_M	286931354	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	41
T32	3698	1
T66	6406	1
T67	5298	1
T69	5699	1
T70	8822	2
T76	6451	0
T90	1627	0
T91	0	2
T121	0	5
T127	1347	0
T128	5916	2
T133	0	1
T137	0	1
T139	582	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	286931354	41
T32	2399	1
T66	14641	1
T67	2569	1
T69	11399	1
T70	8469	2
T76	6193	0
T90	1627	0
T91	0	2
T121	0	5
T127	2394	0
T128	2958	2
T133	0	1
T137	0	1
T139	1215	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T67,T69,T70
1	0	Covered	T67,T69,T70
1	1	Covered	T121,T129,T141

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T67,T69,T70
1	0	Covered	T121,T129,T141
1	1	Covered	T67,T69,T70

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152611123	36	0	0
SrcPulseCheck_M	286931354	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152611123	36
T67	5298	2
T69	5699	1
T70	8822	1
T76	6451	0
T78	3835	0
T90	1627	0
T91	15549	0
T121	0	4
T122	0	1
T127	1347	0
T128	5916	1
T130	0	1
T133	0	2
T137	0	1
T139	582	0
T142	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	286931354	36
T67	2569	2
T69	11399	1
T70	8469	1
T76	6193	0
T78	26298	0
T90	1627	0
T91	7463	0
T121	0	4
T122	0	1
T127	2394	0
T128	2958	1
T130	0	1
T133	0	2
T137	0	1
T139	1215	0
T142	0	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	561588074	96016	0	0
SrcPulseCheck_M	21544390	95781	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	561588074	96016
T1	540943	273
T2	0	1916
T3	0	104
T5	140085	159
T6	55513	54
T10	0	66
T11	0	245
T17	4483	0
T18	3352	0
T19	8193	0
T20	3781	0
T21	6915	0
T22	3852	0
T23	2997	0
T27	0	231
T28	0	134
T29	0	304

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	21544390	95781
T1	2316	273
T2	0	1917
T3	0	104
T5	301	159
T6	126	54
T10	0	66
T11	0	245
T17	326	0
T18	244	0
T19	597	0
T20	275	0
T21	504	0
T22	280	0
T23	219	0
T27	0	231
T28	0	134
T29	0	304

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	280164740	94937	0	0
SrcPulseCheck_M	21544390	94703	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	280164740	94937
T1	270348	273
T2	0	1916
T3	0	104
T5	70010	159
T6	27737	54
T10	0	66
T11	0	245
T17	2181	0
T18	1622	0
T19	4071	0
T20	1844	0
T21	3397	0
T22	1879	0
T23	1452	0
T27	0	231
T28	0	134
T29	0	304

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	21544390	94703
T1	2316	273
T2	0	1917
T3	0	104
T5	301	159
T6	126	54
T10	0	66
T11	0	245
T17	326	0
T18	244	0
T19	597	0
T20	275	0
T21	504	0
T22	280	0
T23	219	0
T27	0	231
T28	0	134
T29	0	304

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	140081788	93450	0	0
SrcPulseCheck_M	21544390	93215	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	140081788	93450
T1	135174	273
T2	0	1916
T3	0	104
T5	35005	159
T6	13869	54
T10	0	66
T11	0	245
T17	1091	0
T18	811	0
T19	2035	0
T20	922	0
T21	1699	0
T22	940	0
T23	726	0
T27	0	231
T28	0	133
T29	0	304

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	21544390	93215
T1	2316	273
T2	0	1917
T3	0	104
T5	301	159
T6	126	54
T10	0	66
T11	0	245
T17	326	0
T18	244	0
T19	597	0
T20	275	0
T21	504	0
T22	280	0
T23	219	0
T27	0	231
T28	0	133
T29	0	304

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	595694301	113029	0	0
SrcPulseCheck_M	20887343	111696	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	595694301	113029
T1	575500	297
T2	0	2334
T3	0	104
T5	151926	171
T6	81829	102
T10	0	66
T11	0	281
T17	4671	0
T18	3491	0
T19	8535	0
T20	3938	0
T21	7203	0
T22	4012	0
T23	3122	0
T27	0	303
T28	0	189
T29	0	496

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	20887343	111696
T1	2340	297
T2	0	2334
T3	0	104
T5	313	171
T6	174	102
T10	0	66
T11	0	281
T17	326	0
T18	244	0
T19	597	0
T20	275	0
T21	504	0
T22	280	0
T23	219	0
T27	0	303
T28	0	189
T29	0	496

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	285687614	110121	0	0
SrcPulseCheck_M	21710879	110008	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	285687614	110121
T1	270485	273
T2	0	2418
T3	0	104
T5	90206	243
T6	42158	114
T10	0	66
T11	0	269
T17	2241	0
T18	1675	0
T19	4097	0
T20	1890	0
T21	3458	0
T22	1925	0
T23	1498	0
T27	0	327
T28	0	158
T29	0	496

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	21710879	110008
T1	2316	273
T2	0	2418
T3	0	104
T5	385	243
T6	186	114
T10	0	66
T11	0	269
T17	326	0
T18	244	0
T19	597	0
T20	275	0
T21	504	0
T22	280	0
T23	219	0
T27	0	327
T28	0	158
T29	0	496

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb