Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	152611123	4830685	0	0
clk_enables_rd_A	152611123	41759	0	0
clk_hints_rd_A	152611123	37560	0	0
extclk_ctrl_rd_A	152611123	49942	0	0
extclk_ctrl_regwen_rd_A	152611123	36122	0	0
jitter_enable_rd_A	152611123	55963	0	0
jitter_regwen_rd_A	152611123	41039	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	4830685	0	0
T34	12637	695	0	0
T35	9897	9	0	0
T36	6341	199	0	0
T37	7440	409	0	0
T44	5315	3	0	0
T45	986	5	0	0
T73	9951	712	0	0
T74	0	7	0	0
T77	0	6	0	0
T143	924	5	0	0
T144	695	0	0	0
T145	1201	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	41759	0	0
T33	1719	2	0	0
T34	12637	26	0	0
T36	6341	9	0	0
T45	986	7	0	0
T48	5700	56	0	0
T68	6160	48	0	0
T71	4945	0	0	0
T74	0	121	0	0
T78	0	14	0	0
T86	4102	0	0	0
T89	903	0	0	0
T91	0	425	0	0
T120	727	0	0	0
T146	0	2	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	37560	0	0
T33	1719	7	0	0
T34	12637	33	0	0
T36	6341	16	0	0
T37	7440	2	0	0
T45	986	9	0	0
T48	5700	81	0	0
T68	6160	63	0	0
T71	4945	0	0	0
T74	0	155	0	0
T86	4102	0	0	0
T89	903	0	0	0
T91	0	482	0	0
T146	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	49942	0	0
T5	193926	0	0	0
T8	876	11	0	0
T33	1719	2	0	0
T34	12637	19	0	0
T36	6341	11	0	0
T37	7440	4	0	0
T45	986	1	0	0
T48	5700	31	0	0
T68	6160	61	0	0
T78	0	4	0	0
T89	903	0	0	0
T91	0	53	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	36122	0	0
T33	1719	1	0	0
T34	12637	26	0	0
T36	6341	17	0	0
T37	7440	3	0	0
T45	986	6	0	0
T48	5700	18	0	0
T68	6160	63	0	0
T71	4945	0	0	0
T74	0	76	0	0
T78	0	2	0	0
T86	4102	0	0	0
T89	903	0	0	0
T91	0	188	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	55963	0	0
T33	1719	8	0	0
T34	12637	21	0	0
T36	6341	17	0	0
T37	7440	9	0	0
T45	986	3	0	0
T48	5700	49	0	0
T68	6160	59	0	0
T71	4945	0	0	0
T74	0	63	0	0
T78	0	9	0	0
T86	4102	0	0	0
T89	903	0	0	0
T91	0	206	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	41039	0	0
T33	1719	1	0	0
T34	12637	22	0	0
T36	6341	14	0	0
T37	7440	5	0	0
T45	986	2	0	0
T48	5700	39	0	0
T68	6160	46	0	0
T71	4945	0	0	0
T74	0	90	0	0
T78	0	3	0	0
T86	4102	0	0	0
T89	903	0	0	0
T91	0	239	0	0