Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T33,T35
1	0	Covered	T5,T32,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1526111230	1381947	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1526111230	272998	0	0
SrcBusyKnown_A	1526111230	1502446820	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526111230	1381947	0	0
T1	2819910	4000	0	0
T2	0	13487	0	0
T3	0	1005	0	0
T4	0	1259	0	0
T5	1939260	2797	0	0
T6	105390	244	0	0
T17	5370	0	0	0
T18	6630	0	0	0
T19	4265	0	0	0
T20	19690	0	0	0
T21	9000	0	0	0
T22	10025	0	0	0
T23	7335	0	0	0
T25	0	200	0	0
T27	0	1976	0	0
T28	0	420	0	0
T29	0	1698	0	0
T32	18490	551	0	0
T33	8595	129	0	0
T35	49485	1821	0	0
T44	26575	1431	0	0
T45	4930	18	0	0
T46	11000	424	0	0
T66	32030	587	0	0
T67	26490	655	0	0
T68	30800	895	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T5	974464	973946	0	0
T7	34242	33334	0	0
T8	23286	22700	0	0
T31	30408	29558	0	0
T32	30610	23564	0	0
T33	11140	9440	0	0
T34	79830	79434	0	0
T35	119848	99274	0	0
T36	41686	40588	0	0
T37	188038	186940	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526111230	272998	0	0
T1	2819910	480	0	0
T2	0	2655	0	0
T3	0	210	0	0
T4	0	137	0	0
T5	1939260	320	0	0
T6	105390	70	0	0
T17	5370	0	0	0
T18	6630	0	0	0
T19	4265	0	0	0
T20	19690	0	0	0
T21	9000	0	0	0
T22	10025	0	0	0
T23	7335	0	0	0
T25	0	72	0	0
T27	0	230	0	0
T28	0	120	0	0
T29	0	350	0	0
T32	18490	91	0	0
T33	8595	15	0	0
T35	49485	336	0	0
T44	26575	172	0	0
T45	4930	7	0	0
T46	11000	58	0	0
T66	32030	184	0	0
T67	26490	83	0	0
T68	30800	180	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526111230	1502446820	0	0
T5	1939260	1938280	0	0
T7	13060	12650	0	0
T8	8760	8500	0	0
T31	7700	7480	0	0
T32	36980	27620	0	0
T33	17190	14340	0	0
T34	126370	125680	0	0
T35	98970	80230	0	0
T36	63410	61650	0	0
T37	74400	73940	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152611123	86416	0	0
DstReqKnown_A	564075522	560040216	0	0
SrcAckBusyChk_A	152611123	24628	0	0
SrcBusyKnown_A	152611123	150244682	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	86416	0	0
T1	563982	570	0	0
T2	0	1882	0	0
T3	0	143	0	0
T4	0	186	0	0
T5	193926	170	0	0
T6	21078	36	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T25	0	38	0	0
T27	0	242	0	0
T28	0	62	0	0
T29	0	243	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564075522	560040216	0	0
T5	140085	139992	0	0
T7	5225	5063	0	0
T8	3509	3402	0	0
T31	4625	4490	0	0
T32	4798	3580	0	0
T33	1719	1434	0	0
T34	12132	12066	0	0
T35	18630	15079	0	0
T36	6341	6165	0	0
T37	28571	28396	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	24628	0	0
T1	563982	96	0	0
T2	0	531	0	0
T3	0	42	0	0
T4	0	30	0	0
T5	193926	32	0	0
T6	21078	14	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T25	0	16	0	0
T27	0	46	0	0
T28	0	24	0	0
T29	0	70	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	150244682	0	0
T5	193926	193828	0	0
T7	1306	1265	0	0
T8	876	850	0	0
T31	770	748	0	0
T32	3698	2762	0	0
T33	1719	1434	0	0
T34	12637	12568	0	0
T35	9897	8023	0	0
T36	6341	6165	0	0
T37	7440	7394	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152611123	122845	0	0
DstReqKnown_A	281363680	280352646	0	0
SrcAckBusyChk_A	152611123	24627	0	0
SrcBusyKnown_A	152611123	150244682	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	122845	0	0
T1	563982	819	0	0
T2	0	2711	0	0
T3	0	201	0	0
T4	0	258	0	0
T5	193926	271	0	0
T6	21078	50	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T25	0	41	0	0
T27	0	389	0	0
T28	0	86	0	0
T29	0	339	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281363680	280352646	0	0
T5	70010	69996	0	0
T7	2559	2531	0	0
T8	1817	1803	0	0
T31	2300	2245	0	0
T32	2073	1790	0	0
T33	799	716	0	0
T34	6054	6033	0	0
T35	8382	7540	0	0
T36	3151	3082	0	0
T37	14267	14198	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	24627	0	0
T1	563982	96	0	0
T2	0	531	0	0
T3	0	42	0	0
T4	0	30	0	0
T5	193926	32	0	0
T6	21078	14	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T25	0	16	0	0
T27	0	46	0	0
T28	0	24	0	0
T29	0	70	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	150244682	0	0
T5	193926	193828	0	0
T7	1306	1265	0	0
T8	876	850	0	0
T31	770	748	0	0
T32	3698	2762	0	0
T33	1719	1434	0	0
T34	12637	12568	0	0
T35	9897	8023	0	0
T36	6341	6165	0	0
T37	7440	7394	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152611123	194932	0	0
DstReqKnown_A	140681263	140175861	0	0
SrcAckBusyChk_A	152611123	24625	0	0
SrcBusyKnown_A	152611123	150244682	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	194932	0	0
T1	563982	1379	0	0
T2	0	4347	0	0
T3	0	318	0	0
T4	0	461	0	0
T5	193926	475	0	0
T6	21078	72	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T25	0	56	0	0
T27	0	675	0	0
T28	0	124	0	0
T29	0	543	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140681263	140175861	0	0
T5	35005	34998	0	0
T7	1280	1266	0	0
T8	908	901	0	0
T31	1150	1122	0	0
T32	1036	894	0	0
T33	400	359	0	0
T34	3027	3017	0	0
T35	4190	3769	0	0
T36	1576	1542	0	0
T37	7133	7099	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	24625	0	0
T1	563982	96	0	0
T2	0	531	0	0
T3	0	42	0	0
T4	0	30	0	0
T5	193926	32	0	0
T6	21078	14	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T25	0	16	0	0
T27	0	46	0	0
T28	0	24	0	0
T29	0	70	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	150244682	0	0
T5	193926	193828	0	0
T7	1306	1265	0	0
T8	876	850	0	0
T31	770	748	0	0
T32	3698	2762	0	0
T33	1719	1434	0	0
T34	12637	12568	0	0
T35	9897	8023	0	0
T36	6341	6165	0	0
T37	7440	7394	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152611123	85567	0	0
DstReqKnown_A	598285493	594036173	0	0
SrcAckBusyChk_A	152611123	24623	0	0
SrcBusyKnown_A	152611123	150244682	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	85567	0	0
T1	563982	468	0	0
T2	0	1846	0	0
T3	0	142	0	0
T4	0	156	0	0
T5	193926	198	0	0
T6	21078	36	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T25	0	38	0	0
T27	0	280	0	0
T28	0	62	0	0
T29	0	235	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598285493	594036173	0	0
T5	151926	151828	0	0
T7	5444	5275	0	0
T8	3655	3543	0	0
T31	4817	4677	0	0
T32	4999	3729	0	0
T33	1792	1494	0	0
T34	12637	12568	0	0
T35	19407	15709	0	0
T36	6605	6422	0	0
T37	29762	29579	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	24623	0	0
T1	563982	96	0	0
T2	0	531	0	0
T3	0	42	0	0
T4	0	30	0	0
T5	193926	32	0	0
T6	21078	14	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T25	0	16	0	0
T27	0	46	0	0
T28	0	24	0	0
T29	0	70	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	150244682	0	0
T5	193926	193828	0	0
T7	1306	1265	0	0
T8	876	850	0	0
T31	770	748	0	0
T32	3698	2762	0	0
T33	1719	1434	0	0
T34	12637	12568	0	0
T35	9897	8023	0	0
T36	6341	6165	0	0
T37	7440	7394	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152611123	121055	0	0
DstReqKnown_A	286931354	284892377	0	0
SrcAckBusyChk_A	152611123	24208	0	0
SrcBusyKnown_A	152611123	150244682	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	121055	0	0
T1	563982	764	0	0
T2	0	2701	0	0
T3	0	201	0	0
T4	0	198	0	0
T5	193926	274	0	0
T6	21078	50	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T25	0	27	0	0
T27	0	390	0	0
T28	0	86	0	0
T29	0	338	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286931354	284892377	0	0
T5	90206	90159	0	0
T7	2613	2532	0	0
T8	1754	1701	0	0
T31	2312	2245	0	0
T32	2399	1789	0	0
T33	860	717	0	0
T34	6065	6033	0	0
T35	9315	7540	0	0
T36	3170	3083	0	0
T37	14286	14198	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	24208	0	0
T1	563982	96	0	0
T2	0	531	0	0
T3	0	42	0	0
T4	0	17	0	0
T5	193926	32	0	0
T6	21078	14	0	0
T17	1074	0	0	0
T18	1326	0	0	0
T19	853	0	0	0
T20	3938	0	0	0
T21	1800	0	0	0
T22	2005	0	0	0
T23	1467	0	0	0
T25	0	8	0	0
T27	0	46	0	0
T28	0	24	0	0
T29	0	70	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	150244682	0	0
T5	193926	193828	0	0
T7	1306	1265	0	0
T8	876	850	0	0
T31	770	748	0	0
T32	3698	2762	0	0
T33	1719	1434	0	0
T34	12637	12568	0	0
T35	9897	8023	0	0
T36	6341	6165	0	0
T37	7440	7394	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T33,T35
1	0	Covered	T5,T32,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152611123	107762	0	0
DstReqKnown_A	564075522	560040216	0	0
SrcAckBusyChk_A	152611123	30048	0	0
SrcBusyKnown_A	152611123	150244682	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	107762	0	0
T5	193926	173	0	0
T32	3698	82	0	0
T33	1719	19	0	0
T35	9897	265	0	0
T44	5315	210	0	0
T45	986	2	0	0
T46	2200	106	0	0
T66	6406	54	0	0
T67	5298	94	0	0
T68	6160	127	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564075522	560040216	0	0
T5	140085	139992	0	0
T7	5225	5063	0	0
T8	3509	3402	0	0
T31	4625	4490	0	0
T32	4798	3580	0	0
T33	1719	1434	0	0
T34	12132	12066	0	0
T35	18630	15079	0	0
T36	6341	6165	0	0
T37	28571	28396	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	30048	0	0
T5	193926	32	0	0
T32	3698	18	0	0
T33	1719	3	0	0
T35	9897	70	0	0
T44	5315	34	0	0
T45	986	1	0	0
T46	2200	20	0	0
T66	6406	23	0	0
T67	5298	17	0	0
T68	6160	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	150244682	0	0
T5	193926	193828	0	0
T7	1306	1265	0	0
T8	876	850	0	0
T31	770	748	0	0
T32	3698	2762	0	0
T33	1719	1434	0	0
T34	12637	12568	0	0
T35	9897	8023	0	0
T36	6341	6165	0	0
T37	7440	7394	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T33,T35
1	0	Covered	T5,T32,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152611123	154200	0	0
DstReqKnown_A	281363680	280352646	0	0
SrcAckBusyChk_A	152611123	30051	0	0
SrcBusyKnown_A	152611123	150244682	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	154200	0	0
T5	193926	274	0	0
T32	3698	180	0	0
T33	1719	27	0	0
T35	9897	358	0	0
T44	5315	290	0	0
T45	986	8	0	0
T46	2200	69	0	0
T66	6406	131	0	0
T67	5298	177	0	0
T68	6160	180	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281363680	280352646	0	0
T5	70010	69996	0	0
T7	2559	2531	0	0
T8	1817	1803	0	0
T31	2300	2245	0	0
T32	2073	1790	0	0
T33	799	716	0	0
T34	6054	6033	0	0
T35	8382	7540	0	0
T36	3151	3082	0	0
T37	14267	14198	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	30051	0	0
T5	193926	32	0	0
T32	3698	26	0	0
T33	1719	3	0	0
T35	9897	64	0	0
T44	5315	35	0	0
T45	986	3	0	0
T46	2200	8	0	0
T66	6406	41	0	0
T67	5298	20	0	0
T68	6160	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	150244682	0	0
T5	193926	193828	0	0
T7	1306	1265	0	0
T8	876	850	0	0
T31	770	748	0	0
T32	3698	2762	0	0
T33	1719	1434	0	0
T34	12637	12568	0	0
T35	9897	8023	0	0
T36	6341	6165	0	0
T37	7440	7394	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T33,T35
1	0	Covered	T5,T33,T35

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152611123	247259	0	0
DstReqKnown_A	140681263	140175861	0	0
SrcAckBusyChk_A	152611123	30051	0	0
SrcBusyKnown_A	152611123	150244682	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	247259	0	0
T5	193926	485	0	0
T32	3698	62	0	0
T33	1719	43	0	0
T35	9897	608	0	0
T44	5315	495	0	0
T45	986	3	0	0
T46	2200	68	0	0
T66	6406	176	0	0
T67	5298	110	0	0
T68	6160	283	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140681263	140175861	0	0
T5	35005	34998	0	0
T7	1280	1266	0	0
T8	908	901	0	0
T31	1150	1122	0	0
T32	1036	894	0	0
T33	400	359	0	0
T34	3027	3017	0	0
T35	4190	3769	0	0
T36	1576	1542	0	0
T37	7133	7099	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	30051	0	0
T5	193926	32	0	0
T32	3698	5	0	0
T33	1719	3	0	0
T35	9897	70	0	0
T44	5315	34	0	0
T45	986	1	0	0
T46	2200	5	0	0
T66	6406	37	0	0
T67	5298	7	0	0
T68	6160	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	150244682	0	0
T5	193926	193828	0	0
T7	1306	1265	0	0
T8	876	850	0	0
T31	770	748	0	0
T32	3698	2762	0	0
T33	1719	1434	0	0
T34	12637	12568	0	0
T35	9897	8023	0	0
T36	6341	6165	0	0
T37	7440	7394	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T33,T35
1	0	Covered	T5,T32,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152611123	107579	0	0
DstReqKnown_A	598285493	594036173	0	0
SrcAckBusyChk_A	152611123	30262	0	0
SrcBusyKnown_A	152611123	150244682	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	107579	0	0
T5	193926	198	0	0
T32	3698	103	0	0
T33	1719	15	0	0
T35	9897	235	0	0
T44	5315	168	0	0
T45	986	2	0	0
T46	2200	95	0	0
T66	6406	123	0	0
T67	5298	117	0	0
T68	6160	125	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598285493	594036173	0	0
T5	151926	151828	0	0
T7	5444	5275	0	0
T8	3655	3543	0	0
T31	4817	4677	0	0
T32	4999	3729	0	0
T33	1792	1494	0	0
T34	12637	12568	0	0
T35	19407	15709	0	0
T36	6605	6422	0	0
T37	29762	29579	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	30262	0	0
T5	193926	32	0	0
T32	3698	24	0	0
T33	1719	3	0	0
T35	9897	65	0	0
T44	5315	35	0	0
T45	986	1	0	0
T46	2200	15	0	0
T66	6406	52	0	0
T67	5298	22	0	0
T68	6160	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	150244682	0	0
T5	193926	193828	0	0
T7	1306	1265	0	0
T8	876	850	0	0
T31	770	748	0	0
T32	3698	2762	0	0
T33	1719	1434	0	0
T34	12637	12568	0	0
T35	9897	8023	0	0
T36	6341	6165	0	0
T37	7440	7394	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T32,T33,T35
1	0	Covered	T5,T32,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T32,T33
1	1	Covered	T5,T32,T33

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T32,T33
0	0	1	Covered	T5,T32,T33
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152611123	154332	0	0
DstReqKnown_A	286931354	284892377	0	0
SrcAckBusyChk_A	152611123	29875	0	0
SrcBusyKnown_A	152611123	150244682	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	154332	0	0
T5	193926	279	0	0
T32	3698	124	0	0
T33	1719	25	0	0
T35	9897	355	0	0
T44	5315	268	0	0
T45	986	3	0	0
T46	2200	86	0	0
T66	6406	103	0	0
T67	5298	157	0	0
T68	6160	180	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286931354	284892377	0	0
T5	90206	90159	0	0
T7	2613	2532	0	0
T8	1754	1701	0	0
T31	2312	2245	0	0
T32	2399	1789	0	0
T33	860	717	0	0
T34	6065	6033	0	0
T35	9315	7540	0	0
T36	3170	3083	0	0
T37	14286	14198	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	29875	0	0
T5	193926	32	0	0
T32	3698	18	0	0
T33	1719	3	0	0
T35	9897	67	0	0
T44	5315	34	0	0
T45	986	1	0	0
T46	2200	10	0	0
T66	6406	31	0	0
T67	5298	17	0	0
T68	6160	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152611123	150244682	0	0
T5	193926	193828	0	0
T7	1306	1265	0	0
T8	876	850	0	0
T31	770	748	0	0
T32	3698	2762	0	0
T33	1719	1434	0	0
T34	12637	12568	0	0
T35	9897	8023	0	0
T36	6341	6165	0	0
T37	7440	7394	0	0