Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	45952	0	0
CgEnOn_A	2147483647	36973	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45952	0	0
T1	1521965	87	0	0
T2	2201995	0	0	0
T5	397026	3	0	0
T6	81829	0	0	0
T7	14508	4	0	0
T8	9889	3	0	0
T17	12426	3	0	0
T18	9276	46	0	0
T19	22834	3	0	0
T20	10485	14	0	0
T21	19214	11	0	0
T22	0	7	0	0
T26	12809	3	0	0
T41	8055	31	0	0
T42	3597	15	0	0
T43	0	10	0	0
T107	22885	0	0	0
T108	5693	0	0	0
T109	13464	0	0	0
T112	4894	0	0	0
T147	0	25	0	0
T148	0	5	0	0
T149	0	25	0	0
T150	0	25	0	0
T151	0	5	0	0
T152	0	10	0	0
T153	0	25	0	0
T154	10444	0	0	0
T155	23090	0	0	0
T156	9635	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36973	0	0
T1	1521965	63	0	0
T2	2201995	238	0	0
T6	178948	0	0	0
T7	5444	1	0	0
T17	12426	0	0	0
T18	9276	43	0	0
T19	22834	0	0	0
T20	10485	11	0	0
T21	19214	8	0	0
T22	6671	0	0	0
T23	5175	0	0	0
T24	2682	32	0	0
T27	0	43	0	0
T29	0	47	0	0
T41	8055	46	0	0
T42	3597	24	0	0
T43	0	12	0	0
T107	22885	0	0	0
T108	5693	0	0	0
T109	13464	0	0	0
T112	4894	2	0	0
T147	0	25	0	0
T148	0	5	0	0
T149	0	25	0	0
T150	0	25	0	0
T151	0	5	0	0
T152	0	10	0	0
T153	0	25	0	0
T154	10444	0	0	0
T155	23090	0	0	0
T156	9635	0	0	0
T158	0	28	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	280164740	158	0	0
CgEnOn_A	280164740	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280164740	158	0	0
T2	489191	0	0	0
T41	1760	5	0	0
T42	794	3	0	0
T43	0	2	0	0
T107	5202	0	0	0
T108	1293	0	0	0
T109	3088	0	0	0
T112	1070	0	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	2309	0	0	0
T155	5117	0	0	0
T156	2170	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280164740	158	0	0
T2	489191	0	0	0
T41	1760	5	0	0
T42	794	3	0	0
T43	0	2	0	0
T107	5202	0	0	0
T108	1293	0	0	0
T109	3088	0	0	0
T112	1070	0	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	2309	0	0	0
T155	5117	0	0	0
T156	2170	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140081788	158	0	0
CgEnOn_A	140081788	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140081788	158	0	0
T2	244595	0	0	0
T41	880	5	0	0
T42	397	3	0	0
T43	0	2	0	0
T107	2599	0	0	0
T108	645	0	0	0
T109	1544	0	0	0
T112	535	0	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	1155	0	0	0
T155	2558	0	0	0
T156	1084	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140081788	158	0	0
T2	244595	0	0	0
T41	880	5	0	0
T42	397	3	0	0
T43	0	2	0	0
T107	2599	0	0	0
T108	645	0	0	0
T109	1544	0	0	0
T112	535	0	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	1155	0	0	0
T155	2558	0	0	0
T156	1084	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	561588074	158	0	0
CgEnOn_A	561588074	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561588074	158	0	0
T2	979019	0	0	0
T41	3655	5	0	0
T42	1612	3	0	0
T43	0	2	0	0
T107	9886	0	0	0
T108	2465	0	0	0
T109	5744	0	0	0
T112	2219	0	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	4670	0	0	0
T155	10299	0	0	0
T156	4213	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561588074	152	0	0
T2	979019	0	0	0
T41	3655	5	0	0
T42	1612	3	0	0
T43	0	2	0	0
T107	9886	0	0	0
T108	2465	0	0	0
T109	5744	0	0	0
T112	2219	0	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	4670	0	0	0
T155	10299	0	0	0
T156	4213	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595694301	160	0	0
CgEnOn_A	595694301	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	160	0	0
T2	104084	0	0	0
T41	3673	6	0	0
T42	1686	2	0	0
T43	0	3	0	0
T107	10297	0	0	0
T108	2567	0	0	0
T109	5984	0	0	0
T112	2311	0	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	6	0	0
T154	4866	0	0	0
T155	10728	0	0	0
T156	4388	0	0	0
T157	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	159	0	0
T2	104084	0	0	0
T41	3673	6	0	0
T42	1686	2	0	0
T43	0	3	0	0
T107	10297	0	0	0
T108	2567	0	0	0
T109	5984	0	0	0
T112	2311	0	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	6	0	0
T154	4866	0	0	0
T155	10728	0	0	0
T156	4388	0	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140081788	158	0	0
CgEnOn_A	140081788	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140081788	158	0	0
T2	244595	0	0	0
T41	880	5	0	0
T42	397	3	0	0
T43	0	2	0	0
T107	2599	0	0	0
T108	645	0	0	0
T109	1544	0	0	0
T112	535	0	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	1155	0	0	0
T155	2558	0	0	0
T156	1084	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140081788	158	0	0
T2	244595	0	0	0
T41	880	5	0	0
T42	397	3	0	0
T43	0	2	0	0
T107	2599	0	0	0
T108	645	0	0	0
T109	1544	0	0	0
T112	535	0	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	1155	0	0	0
T155	2558	0	0	0
T156	1084	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595694301	160	0	0
CgEnOn_A	595694301	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	160	0	0
T2	104084	0	0	0
T41	3673	6	0	0
T42	1686	2	0	0
T43	0	3	0	0
T107	10297	0	0	0
T108	2567	0	0	0
T109	5984	0	0	0
T112	2311	0	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	6	0	0
T154	4866	0	0	0
T155	10728	0	0	0
T156	4388	0	0	0
T157	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	159	0	0
T2	104084	0	0	0
T41	3673	6	0	0
T42	1686	2	0	0
T43	0	3	0	0
T107	10297	0	0	0
T108	2567	0	0	0
T109	5984	0	0	0
T112	2311	0	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	3	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	6	0	0
T154	4866	0	0	0
T155	10728	0	0	0
T156	4388	0	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140081788	158	0	0
CgEnOn_A	140081788	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140081788	158	0	0
T2	244595	0	0	0
T41	880	5	0	0
T42	397	3	0	0
T43	0	2	0	0
T107	2599	0	0	0
T108	645	0	0	0
T109	1544	0	0	0
T112	535	0	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	1155	0	0	0
T155	2558	0	0	0
T156	1084	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140081788	158	0	0
T2	244595	0	0	0
T41	880	5	0	0
T42	397	3	0	0
T43	0	2	0	0
T107	2599	0	0	0
T108	645	0	0	0
T109	1544	0	0	0
T112	535	0	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	1155	0	0	0
T155	2558	0	0	0
T156	1084	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	280164740	7200	0	0
CgEnOn_A	280164740	4959	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280164740	7200	0	0
T1	270348	25	0	0
T5	70010	1	0	0
T7	2559	1	0	0
T8	1817	1	0	0
T17	2181	1	0	0
T18	1622	16	0	0
T19	4071	1	0	0
T20	1844	1	0	0
T21	3397	1	0	0
T26	4686	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280164740	4959	0	0
T1	270348	17	0	0
T2	0	67	0	0
T6	27737	0	0	0
T17	2181	0	0	0
T18	1622	15	0	0
T19	4071	0	0	0
T20	1844	0	0	0
T21	3397	0	0	0
T22	1879	0	0	0
T23	1452	0	0	0
T24	755	11	0	0
T27	0	9	0	0
T29	0	19	0	0
T41	0	5	0	0
T42	0	3	0	0
T112	0	1	0	0
T158	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140081788	6854	0	0
CgEnOn_A	140081788	4615	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140081788	6854	0	0
T1	135174	23	0	0
T5	35005	1	0	0
T7	1280	1	0	0
T8	908	1	0	0
T17	1091	1	0	0
T18	811	15	0	0
T19	2035	1	0	0
T20	922	1	0	0
T21	1699	1	0	0
T26	2342	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140081788	4615	0	0
T1	135174	15	0	0
T2	0	47	0	0
T6	13869	0	0	0
T17	1091	0	0	0
T18	811	14	0	0
T19	2035	0	0	0
T20	922	0	0	0
T21	1699	0	0	0
T22	940	0	0	0
T23	726	0	0	0
T24	378	11	0	0
T27	0	5	0	0
T29	0	10	0	0
T41	0	5	0	0
T42	0	3	0	0
T43	0	2	0	0
T158	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	561588074	7382	0	0
CgEnOn_A	561588074	5137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561588074	7382	0	0
T1	540943	25	0	0
T5	140085	1	0	0
T7	5225	1	0	0
T8	3509	1	0	0
T17	4483	1	0	0
T18	3352	15	0	0
T19	8193	1	0	0
T20	3781	1	0	0
T21	6915	1	0	0
T26	5781	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561588074	5137	0	0
T1	540943	17	0	0
T2	0	67	0	0
T6	55513	0	0	0
T17	4483	0	0	0
T18	3352	14	0	0
T19	8193	0	0	0
T20	3781	0	0	0
T21	6915	0	0	0
T22	3852	0	0	0
T23	2997	0	0	0
T24	1549	10	0	0
T27	0	18	0	0
T29	0	18	0	0
T41	0	5	0	0
T42	0	3	0	0
T112	0	1	0	0
T158	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	285687614	7174	0	0
CgEnOn_A	285687614	4926	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285687614	7174	0	0
T1	270485	24	0	0
T5	90206	1	0	0
T7	2613	1	0	0
T8	1754	1	0	0
T17	2241	1	0	0
T18	1675	14	0	0
T19	4097	1	0	0
T20	1890	1	0	0
T21	3458	1	0	0
T26	2890	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285687614	4926	0	0
T1	270485	16	0	0
T2	0	65	0	0
T6	42158	0	0	0
T17	2241	0	0	0
T18	1675	13	0	0
T19	4097	0	0	0
T20	1890	0	0	0
T21	3458	0	0	0
T22	1925	0	0	0
T23	1498	0	0	0
T24	774	11	0	0
T27	0	11	0	0
T29	0	19	0	0
T41	0	5	0	0
T42	0	1	0	0
T112	0	1	0	0
T158	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Covered	T7,T1,T20
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595694301	4014	0	0
CgEnOn_A	595694301	4013	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	4014	0	0
T1	575500	14	0	0
T2	0	57	0	0
T5	151926	0	0	0
T6	81829	0	0	0
T7	5444	1	0	0
T8	3655	0	0	0
T17	4671	0	0	0
T18	3491	0	0	0
T19	8535	0	0	0
T20	3938	11	0	0
T21	7203	8	0	0
T22	0	7	0	0
T27	0	11	0	0
T41	0	6	0	0
T110	0	6	0	0
T111	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	4013	0	0
T1	575500	14	0	0
T2	0	57	0	0
T5	151926	0	0	0
T6	81829	0	0	0
T7	5444	1	0	0
T8	3655	0	0	0
T17	4671	0	0	0
T18	3491	0	0	0
T19	8535	0	0	0
T20	3938	11	0	0
T21	7203	8	0	0
T22	0	7	0	0
T27	0	11	0	0
T41	0	6	0	0
T110	0	6	0	0
T111	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Covered	T7,T1,T20
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595694301	4078	0	0
CgEnOn_A	595694301	4080	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	4078	0	0
T1	575500	18	0	0
T2	0	61	0	0
T5	151926	0	0	0
T6	81829	0	0	0
T7	5444	3	0	0
T8	3655	0	0	0
T17	4671	0	0	0
T18	3491	0	0	0
T19	8535	0	0	0
T20	3938	9	0	0
T21	7203	7	0	0
T22	0	4	0	0
T27	0	8	0	0
T41	0	6	0	0
T110	0	5	0	0
T111	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	4080	0	0
T1	575500	18	0	0
T2	0	61	0	0
T5	151926	0	0	0
T6	81829	0	0	0
T7	5444	3	0	0
T8	3655	0	0	0
T17	4671	0	0	0
T18	3491	0	0	0
T19	8535	0	0	0
T20	3938	9	0	0
T21	7203	7	0	0
T22	0	4	0	0
T27	0	8	0	0
T41	0	6	0	0
T110	0	5	0	0
T111	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Covered	T7,T1,T20
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595694301	4108	0	0
CgEnOn_A	595694301	4108	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	4108	0	0
T1	575500	15	0	0
T2	0	57	0	0
T5	151926	0	0	0
T6	81829	0	0	0
T7	5444	3	0	0
T8	3655	0	0	0
T17	4671	0	0	0
T18	3491	0	0	0
T19	8535	0	0	0
T20	3938	12	0	0
T21	7203	7	0	0
T22	0	5	0	0
T27	0	7	0	0
T41	0	6	0	0
T110	0	6	0	0
T111	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	4108	0	0
T1	575500	15	0	0
T2	0	57	0	0
T5	151926	0	0	0
T6	81829	0	0	0
T7	5444	3	0	0
T8	3655	0	0	0
T17	4671	0	0	0
T18	3491	0	0	0
T19	8535	0	0	0
T20	3938	12	0	0
T21	7203	7	0	0
T22	0	5	0	0
T27	0	7	0	0
T41	0	6	0	0
T110	0	6	0	0
T111	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T41
1	0	Covered	T7,T1,T20
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	595694301	4032	0	0
CgEnOn_A	595694301	4033	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	4032	0	0
T1	575500	14	0	0
T2	0	62	0	0
T5	151926	0	0	0
T6	81829	0	0	0
T7	5444	1	0	0
T8	3655	0	0	0
T17	4671	0	0	0
T18	3491	0	0	0
T19	8535	0	0	0
T20	3938	12	0	0
T21	7203	9	0	0
T22	0	4	0	0
T27	0	7	0	0
T41	0	6	0	0
T110	0	6	0	0
T111	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595694301	4033	0	0
T1	575500	14	0	0
T2	0	62	0	0
T5	151926	0	0	0
T6	81829	0	0	0
T7	5444	1	0	0
T8	3655	0	0	0
T17	4671	0	0	0
T18	3491	0	0	0
T19	8535	0	0	0
T20	3938	12	0	0
T21	7203	9	0	0
T22	0	4	0	0
T27	0	7	0	0
T41	0	6	0	0
T110	0	6	0	0
T111	0	8	0	0