Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T24
0	1	Covered	T1,T18,T24
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Covered	T41,T42,T43
1	1	Covered	T7,T8,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1267523831	13045	0	0
GateOpen_A	1267523831	13041	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1267523831	13045	0	0
T1	1216952	28	0	0
T2	0	183	0	0
T6	139279	0	0	0
T17	9999	0	0	0
T18	7463	49	0	0
T19	18399	0	0	0
T20	8439	0	0	0
T21	15470	0	0	0
T22	8598	0	0	0
T23	6677	0	0	0
T24	3458	36	0	0
T27	0	39	0	0
T29	0	54	0	0
T41	0	20	0	0
T42	0	10	0	0
T112	0	4	0	0
T158	0	27	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1267523831	13041	0	0
T1	1216952	28	0	0
T2	0	183	0	0
T6	139279	0	0	0
T17	9999	0	0	0
T18	7463	49	0	0
T19	18399	0	0	0
T20	8439	0	0	0
T21	15470	0	0	0
T22	8598	0	0	0
T23	6677	0	0	0
T24	3458	36	0	0
T27	0	39	0	0
T29	0	54	0	0
T41	0	20	0	0
T42	0	10	0	0
T112	0	4	0	0
T158	0	27	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T24
0	1	Covered	T1,T18,T24
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Covered	T41,T42,T43
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	140082177	3193	0	0
GateOpen_A	140082177	3192	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140082177	3193	0	0
T1	135174	7	0	0
T2	0	41	0	0
T6	13869	0	0	0
T17	1091	0	0	0
T18	812	12	0	0
T19	2036	0	0	0
T20	922	0	0	0
T21	1699	0	0	0
T22	940	0	0	0
T23	727	0	0	0
T24	378	9	0	0
T27	0	8	0	0
T29	0	12	0	0
T41	0	5	0	0
T42	0	3	0	0
T112	0	1	0	0
T158	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140082177	3192	0	0
T1	135174	7	0	0
T2	0	41	0	0
T6	13869	0	0	0
T17	1091	0	0	0
T18	812	12	0	0
T19	2036	0	0	0
T20	922	0	0	0
T21	1699	0	0	0
T22	940	0	0	0
T23	727	0	0	0
T24	378	9	0	0
T27	0	8	0	0
T29	0	12	0	0
T41	0	5	0	0
T42	0	3	0	0
T112	0	1	0	0
T158	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T24
0	1	Covered	T1,T18,T24
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Covered	T41,T42,T43
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	280165139	3283	0	0
GateOpen_A	280165139	3283	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280165139	3283	0	0
T1	270349	7	0	0
T2	0	46	0	0
T6	27738	0	0	0
T17	2182	0	0	0
T18	1623	14	0	0
T19	4071	0	0	0
T20	1844	0	0	0
T21	3398	0	0	0
T22	1880	0	0	0
T23	1453	0	0	0
T24	756	11	0	0
T27	0	10	0	0
T29	0	15	0	0
T41	0	5	0	0
T42	0	3	0	0
T112	0	1	0	0
T158	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280165139	3283	0	0
T1	270349	7	0	0
T2	0	46	0	0
T6	27738	0	0	0
T17	2182	0	0	0
T18	1623	14	0	0
T19	4071	0	0	0
T20	1844	0	0	0
T21	3398	0	0	0
T22	1880	0	0	0
T23	1453	0	0	0
T24	756	11	0	0
T27	0	10	0	0
T29	0	15	0	0
T41	0	5	0	0
T42	0	3	0	0
T112	0	1	0	0
T158	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T24
0	1	Covered	T1,T18,T24
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Covered	T41,T42,T43
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	561588481	3309	0	0
GateOpen_A	561588481	3307	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561588481	3309	0	0
T1	540944	6	0	0
T2	0	47	0	0
T6	55513	0	0	0
T17	4484	0	0	0
T18	3352	12	0	0
T19	8194	0	0	0
T20	3782	0	0	0
T21	6915	0	0	0
T22	3852	0	0	0
T23	2998	0	0	0
T24	1549	8	0	0
T27	0	11	0	0
T29	0	13	0	0
T41	0	5	0	0
T42	0	3	0	0
T112	0	1	0	0
T158	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561588481	3307	0	0
T1	540944	6	0	0
T2	0	47	0	0
T6	55513	0	0	0
T17	4484	0	0	0
T18	3352	12	0	0
T19	8194	0	0	0
T20	3782	0	0	0
T21	6915	0	0	0
T22	3852	0	0	0
T23	2998	0	0	0
T24	1549	8	0	0
T27	0	11	0	0
T29	0	13	0	0
T41	0	5	0	0
T42	0	3	0	0
T112	0	1	0	0
T158	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T24
0	1	Covered	T1,T18,T24
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Covered	T41,T42,T43
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	285688034	3260	0	0
GateOpen_A	285688034	3259	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285688034	3260	0	0
T1	270485	8	0	0
T2	0	49	0	0
T6	42159	0	0	0
T17	2242	0	0	0
T18	1676	11	0	0
T19	4098	0	0	0
T20	1891	0	0	0
T21	3458	0	0	0
T22	1926	0	0	0
T23	1499	0	0	0
T24	775	8	0	0
T27	0	10	0	0
T29	0	14	0	0
T41	0	5	0	0
T42	0	1	0	0
T112	0	1	0	0
T158	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	285688034	3259	0	0
T1	270485	8	0	0
T2	0	49	0	0
T6	42159	0	0	0
T17	2242	0	0	0
T18	1676	11	0	0
T19	4098	0	0	0
T20	1891	0	0	0
T21	3458	0	0	0
T22	1926	0	0	0
T23	1499	0	0	0
T24	775	8	0	0
T27	0	10	0	0
T29	0	14	0	0
T41	0	5	0	0
T42	0	1	0	0
T112	0	1	0	0
T158	0	6	0	0