CLKMGR Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: 0c759b93ab

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.330s	195.152us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.920s	47.703us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.930s	57.216us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	12.530s	2.092ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.820s	125.725us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.660s	53.426us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.930s	57.216us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	125.725us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.170s	157.104us	49	50	98.00
V2	trans_enables	clkmgr_trans	1.470s	195.604us	50	50	100.00
V2	extclk	clkmgr_extclk	1.440s	235.100us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.860s	94.981us	50	50	100.00
V2	jitter	clkmgr_smoke	1.330s	195.152us	50	50	100.00
V2	frequency	clkmgr_frequency	18.720s	2.480ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.530s	2.180ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.720s	2.480ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.138m	9.337ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.740s	48.106us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.210s	178.449us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	8.110s	2.030ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	8.110s	2.030ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.920s	47.703us	5	5	100.00
		clkmgr_csr_rw	0.930s	57.216us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	125.725us	5	5	100.00
		clkmgr_same_csr_outstanding	1.580s	166.137us	19	20	95.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.920s	47.703us	5	5	100.00
		clkmgr_csr_rw	0.930s	57.216us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	125.725us	5	5	100.00
		clkmgr_same_csr_outstanding	1.580s	166.137us	19	20	95.00
V2		TOTAL			488	490	99.59
V2S	tl_intg_err	clkmgr_sec_cm	3.420s	583.980us	5	5	100.00
		clkmgr_tl_intg_err	6.550s	1.387ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.210s	766.494us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.210s	766.494us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.210s	766.494us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.210s	766.494us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.250s	1.221ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	6.550s	1.387ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.720s	2.480ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.530s	2.180ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.210s	766.494us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.650s	275.408us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.260s	172.852us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.300s	175.265us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.650s	272.470us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.230s	156.981us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.930s	57.216us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.420s	583.980us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.930s	57.216us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.930s	57.216us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.420s	583.980us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.240s	1.247ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	53.147m	918.378ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1007	1010	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.54	99.15	95.84	100.00	100.00	98.81	97.01	98.97

Failure Buckets

• Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 2 failures:

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 13.clkmgr_stress_all_with_rand_reset.12165855488863125840278506759009139725880613591233763885506281476043729697950
      Line 913, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @ 18700735203 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @ 18700735203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_same_csr_outstanding has 1 failures.

    • 13.clkmgr_same_csr_outstanding.26463647315750755441475515471815386655344737897721349987093761897154570020879
      Line 250, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @   7696171 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @   7696171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)' has 1 failures:

  • Test clkmgr_peri has 1 failures.

    • 39.clkmgr_peri.79551249034211324876610511349153318921902415325320329183886232002967849579555
      Line 249, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_peri/latest/run.log

            Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
        UVM_ERROR @   2006838 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
        UVM_INFO @   2006838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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