Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 319739756 1 T6 1836 T4 142342 T7 1946
auto[1] 458820 1 T1 6762 T18 1226 T19 1008


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 319780478 1 T6 1836 T4 142342 T7 1946
auto[1] 418098 1 T1 4418 T18 580 T19 476


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 319688772 1 T6 1836 T4 142342 T7 1946
auto[1] 509804 1 T1 6544 T18 994 T19 764


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 298994452 1 T6 1836 T4 142342 T7 1946
auto[1] 21204124 1 T1 23642 T18 4422 T19 4382


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 178006858 1 T6 1784 T4 142342 T7 92
auto[1] 142191718 1 T6 52 T7 1854 T24 18


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 163322574 1 T6 1784 T4 142342 T7 92
auto[0] auto[0] auto[0] auto[0] auto[1] 135350286 1 T6 52 T7 1854 T24 18
auto[0] auto[0] auto[0] auto[1] auto[0] 34216 1 T1 138 T18 118 T20 44
auto[0] auto[0] auto[0] auto[1] auto[1] 8526 1 T1 98 T19 50 T106 4
auto[0] auto[0] auto[1] auto[0] auto[0] 14077772 1 T1 8870 T18 3178 T19 3024
auto[0] auto[0] auto[1] auto[0] auto[1] 6711716 1 T1 7408 T18 146 T19 266
auto[0] auto[0] auto[1] auto[1] auto[0] 61304 1 T1 1050 T18 178 T19 260
auto[0] auto[0] auto[1] auto[1] auto[1] 15666 1 T1 450 T18 26 T19 74
auto[0] auto[1] auto[0] auto[0] auto[0] 46322 1 T106 68 T27 778 T148 2
auto[0] auto[1] auto[0] auto[0] auto[1] 1434 1 T20 20 T106 58 T151 10
auto[0] auto[1] auto[0] auto[1] auto[0] 13436 1 T106 224 T148 58 T10 392
auto[0] auto[1] auto[0] auto[1] auto[1] 2426 1 T20 100 T151 40 T152 134
auto[0] auto[1] auto[1] auto[0] auto[0] 12968 1 T1 166 T18 28 T19 44
auto[0] auto[1] auto[1] auto[0] auto[1] 3136 1 T1 144 T19 22 T107 22
auto[0] auto[1] auto[1] auto[1] auto[0] 21572 1 T1 394 T18 98 T3 44
auto[0] auto[1] auto[1] auto[1] auto[1] 5418 1 T1 140 T19 78 T10 128
auto[1] auto[0] auto[0] auto[0] auto[0] 30272 1 T1 132 T18 10 T19 32
auto[1] auto[0] auto[0] auto[0] auto[1] 4012 1 T1 56 T106 38 T10 30
auto[1] auto[0] auto[0] auto[1] auto[0] 34464 1 T1 262 T18 56 T20 88
auto[1] auto[0] auto[0] auto[1] auto[1] 8286 1 T1 210 T106 164 T10 98
auto[1] auto[0] auto[1] auto[0] auto[0] 34582 1 T1 554 T18 60 T19 52
auto[1] auto[0] auto[1] auto[0] auto[1] 9366 1 T1 164 T18 10 T19 12
auto[1] auto[0] auto[1] auto[1] auto[0] 61002 1 T1 1506 T18 320 T19 286
auto[1] auto[0] auto[1] auto[1] auto[1] 16434 1 T1 86 T18 84 T19 50
auto[1] auto[1] auto[0] auto[0] auto[0] 65910 1 T1 216 T18 56 T19 46
auto[1] auto[1] auto[0] auto[0] auto[1] 7336 1 T1 32 T19 12 T106 38
auto[1] auto[1] auto[0] auto[1] auto[0] 50814 1 T1 418 T18 104 T20 142
auto[1] auto[1] auto[0] auto[1] auto[1] 14138 1 T1 198 T19 60 T106 98
auto[1] auto[1] auto[1] auto[0] auto[0] 50188 1 T1 742 T18 44 T19 58
auto[1] auto[1] auto[1] auto[0] auto[1] 11882 1 T1 156 T18 8 T19 6
auto[1] auto[1] auto[1] auto[1] auto[0] 89462 1 T1 1266 T18 198 T19 76
auto[1] auto[1] auto[1] auto[1] auto[1] 21656 1 T1 546 T18 44 T19 74

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