Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	807399185	74008	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807399185	74008	0	0
T1	994070	930	0	0
T2	0	426	0	0
T3	0	110	0	0
T5	968895	0	0	0
T9	0	53	0	0
T10	0	1844	0	0
T11	0	143	0	0
T12	0	2852	0	0
T13	0	454	0	0
T14	0	119	0	0
T15	0	407	0	0
T16	7715	0	0	0
T17	182835	0	0	0
T18	13715	0	0	0
T19	12710	0	0	0
T20	11210	0	0	0
T21	6980	0	0	0
T22	7095	0	0	0
T23	1161880	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161479837	10904	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	10904	0	0
T1	198814	142	0	0
T2	0	56	0	0
T3	0	14	0	0
T5	193779	0	0	0
T9	0	8	0	0
T10	0	239	0	0
T11	0	22	0	0
T12	0	376	0	0
T13	0	67	0	0
T14	0	23	0	0
T15	0	54	0	0
T16	1543	0	0	0
T17	36567	0	0	0
T18	2743	0	0	0
T19	2542	0	0	0
T20	2242	0	0	0
T21	1396	0	0	0
T22	1419	0	0	0
T23	232376	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161479837	14834	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	14834	0	0
T1	198814	186	0	0
T2	0	86	0	0
T3	0	22	0	0
T5	193779	0	0	0
T9	0	11	0	0
T10	0	373	0	0
T11	0	28	0	0
T12	0	578	0	0
T13	0	93	0	0
T14	0	23	0	0
T15	0	83	0	0
T16	1543	0	0	0
T17	36567	0	0	0
T18	2743	0	0	0
T19	2542	0	0	0
T20	2242	0	0	0
T21	1396	0	0	0
T22	1419	0	0	0
T23	232376	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161479837	22587	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	22587	0	0
T1	198814	276	0	0
T2	0	140	0	0
T3	0	38	0	0
T5	193779	0	0	0
T9	0	15	0	0
T10	0	626	0	0
T11	0	44	0	0
T12	0	956	0	0
T13	0	142	0	0
T14	0	27	0	0
T15	0	134	0	0
T16	1543	0	0	0
T17	36567	0	0	0
T18	2743	0	0	0
T19	2542	0	0	0
T20	2242	0	0	0
T21	1396	0	0	0
T22	1419	0	0	0
T23	232376	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161479837	10777	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	10777	0	0
T1	198814	140	0	0
T2	0	60	0	0
T3	0	14	0	0
T5	193779	0	0	0
T9	0	8	0	0
T10	0	236	0	0
T11	0	21	0	0
T12	0	368	0	0
T13	0	62	0	0
T14	0	23	0	0
T15	0	53	0	0
T16	1543	0	0	0
T17	36567	0	0	0
T18	2743	0	0	0
T19	2542	0	0	0
T20	2242	0	0	0
T21	1396	0	0	0
T22	1419	0	0	0
T23	232376	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161479837	14906	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161479837	14906	0	0
T1	198814	186	0	0
T2	0	84	0	0
T3	0	22	0	0
T5	193779	0	0	0
T9	0	11	0	0
T10	0	370	0	0
T11	0	28	0	0
T12	0	574	0	0
T13	0	90	0	0
T14	0	23	0	0
T15	0	83	0	0
T16	1543	0	0	0
T17	36567	0	0	0
T18	2743	0	0	0
T19	2542	0	0	0
T20	2242	0	0	0
T21	1396	0	0	0
T22	1419	0	0	0
T23	232376	0	0	0