Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T24

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T7,T24

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1050212695	13913	0	0
GateOpen_A	1050212695	13910	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050212695	13913	0	0
T1	1056244	379	0	0
T3	0	92	0	0
T4	115574	0	0	0
T5	326371	0	0	0
T6	4210	4	0	0
T7	4749	16	0	0
T16	3446	0	0	0
T17	130933	0	0	0
T18	6483	0	0	0
T19	5833	0	0	0
T24	7537	0	0	0
T38	0	70	0	0
T39	0	8	0	0
T40	0	16	0	0
T111	0	4	0	0
T114	0	4	0	0
T147	0	28	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050212695	13910	0	0
T1	1056244	379	0	0
T3	0	92	0	0
T4	115574	0	0	0
T5	326371	0	0	0
T6	4210	4	0	0
T7	4749	16	0	0
T16	3446	0	0	0
T17	130933	0	0	0
T18	6483	0	0	0
T19	5833	0	0	0
T24	7537	0	0	0
T38	0	70	0	0
T39	0	8	0	0
T40	0	16	0	0
T111	0	4	0	0
T114	0	4	0	0
T147	0	28	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T24

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T7,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	115888861	3411	0	0
GateOpen_A	115888861	3410	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115888861	3411	0	0
T1	116021	93	0	0
T3	0	23	0	0
T4	11866	0	0	0
T5	34977	0	0	0
T6	457	1	0	0
T7	515	3	0	0
T16	377	0	0	0
T17	13584	0	0	0
T18	789	0	0	0
T19	685	0	0	0
T24	815	0	0	0
T38	0	17	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115888861	3410	0	0
T1	116021	93	0	0
T3	0	23	0	0
T4	11866	0	0	0
T5	34977	0	0	0
T6	457	1	0	0
T7	515	3	0	0
T16	377	0	0	0
T17	13584	0	0	0
T18	789	0	0	0
T19	685	0	0	0
T24	815	0	0	0
T38	0	17	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T24

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T7,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	231778698	3483	0	0
GateOpen_A	231778698	3483	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231778698	3483	0	0
T1	232044	91	0	0
T3	0	23	0	0
T4	23732	0	0	0
T5	69953	0	0	0
T6	913	1	0	0
T7	1029	4	0	0
T16	753	0	0	0
T17	27168	0	0	0
T18	1579	0	0	0
T19	1374	0	0	0
T24	1630	0	0	0
T38	0	18	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231778698	3483	0	0
T1	232044	91	0	0
T3	0	23	0	0
T4	23732	0	0	0
T5	69953	0	0	0
T6	913	1	0	0
T7	1029	4	0	0
T16	753	0	0	0
T17	27168	0	0	0
T18	1579	0	0	0
T19	1374	0	0	0
T24	1630	0	0	0
T38	0	18	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T24

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T7,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	464906063	3514	0	0
GateOpen_A	464906063	3513	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464906063	3514	0	0
T1	463664	97	0	0
T3	0	23	0	0
T4	47556	0	0	0
T5	139945	0	0	0
T6	1893	1	0	0
T7	2137	4	0	0
T16	1544	0	0	0
T17	54360	0	0	0
T18	2744	0	0	0
T19	2516	0	0	0
T24	3394	0	0	0
T38	0	18	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464906063	3513	0	0
T1	463664	97	0	0
T3	0	23	0	0
T4	47556	0	0	0
T5	139945	0	0	0
T6	1893	1	0	0
T7	2137	4	0	0
T16	1544	0	0	0
T17	54360	0	0	0
T18	2744	0	0	0
T19	2516	0	0	0
T24	3394	0	0	0
T38	0	18	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T1
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T24

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T1
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T7,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	237639073	3505	0	0
GateOpen_A	237639073	3504	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237639073	3505	0	0
T1	244515	98	0	0
T3	0	23	0	0
T4	32420	0	0	0
T5	81496	0	0	0
T6	947	1	0	0
T7	1068	5	0	0
T16	772	0	0	0
T17	35821	0	0	0
T18	1371	0	0	0
T19	1258	0	0	0
T24	1698	0	0	0
T38	0	17	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237639073	3504	0	0
T1	244515	98	0	0
T3	0	23	0	0
T4	32420	0	0	0
T5	81496	0	0	0
T6	947	1	0	0
T7	1068	5	0	0
T16	772	0	0	0
T17	35821	0	0	0
T18	1371	0	0	0
T19	1258	0	0	0
T24	1698	0	0	0
T38	0	17	0	0
T39	0	2	0	0
T40	0	4	0	0
T111	0	1	0	0
T114	0	1	0	0
T147	0	6	0	0