Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324179256

1

T5

4358

T6

9966

T7

1466

auto[1]

419836

1

T2

7794

T19

138

T20

716

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324186172

1

T5

4358

T6

9966

T7

1466

auto[1]

412920

1

T2

5662

T19

288

T20

564

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324096128

1

T5

4358

T6

9966

T7

1466

auto[1]

502964

1

T2

7762

T19

294

T20

808

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

307523086

1

T5

4358

T6

9966

T7

1466

auto[1]

17076006

1

T2

324714

T19

790

T20

1330

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

184407852

1

T5

4358

T6

9936

T7

1466

auto[1]

140191240

1

T6

30

T32

34

T35

28

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

174492992

1

T5

4358

T6

9936

T7

1466

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

132680758

1

T6

30

T32

34

T35

28

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

31676

1

T2

276

T20

42

T23

36

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7782

1

T2

188

T23

34

T12

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

9318172

1

T2

15758

T19

406

T20

204

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7391256

1

T2

302724

T19

114

T20

556

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

53290

1

T2

512

T19

24

T20

48

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13834

1

T2

332

T20

22

T11

24

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

51094

1

T2

78

T73

12

T12

32

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1916

1

T2

30

T16

56

T147

38

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12002

1

T2

214

T73

76

T12

84

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2472

1

T2

52

T16

98

T156

56

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

11118

1

T2

148

T19

70

T20

44

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2770

1

T2

26

T20

70

T16

78

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20092

1

T2

280

T11

64

T12

132

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4904

1

T2

52

T16

114

T157

58

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44894

1

T2

74

T19

52

T20

24

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4550

1

T2

68

T19

24

T20

20

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33776

1

T2

390

T20

156

T11

174

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8136

1

T2

188

T20

68

T16

132

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

29120

1

T2

312

T20

2

T21

34

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7714

1

T2

86

T21

42

T73

26

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

54138

1

T2

1396

T20

88

T111

142

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14084

1

T2

466

T11

96

T12

130

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

82716

1

T2

316

T20

68

T21

78

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5708

1

T2

128

T19

42

T21

42

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

50078

1

T2

1318

T20

86

T23

126

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12536

1

T2

398

T23

72

T11

64

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

42686

1

T2

784

T19

62

T20

30

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11792

1

T2

106

T20

60

T21

56

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

80008

1

T2

1412

T19

114

T20

74

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

21028

1

T2

320

T20

132

T143

42