Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80


Total test records in report: 996
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T761 /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3257512476 Jan 03 01:04:13 PM PST 24 Jan 03 01:05:24 PM PST 24 12918855 ps
T762 /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.2414980837 Jan 03 01:02:51 PM PST 24 Jan 03 01:03:57 PM PST 24 22389481 ps
T763 /workspace/coverage/default/8.clkmgr_trans.638511875 Jan 03 01:03:06 PM PST 24 Jan 03 01:04:12 PM PST 24 101187173 ps
T764 /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3340593632 Jan 03 01:04:05 PM PST 24 Jan 03 01:05:12 PM PST 24 75213077 ps
T765 /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.1769484323 Jan 03 01:02:46 PM PST 24 Jan 03 01:20:03 PM PST 24 172353095116 ps
T766 /workspace/coverage/default/45.clkmgr_smoke.953896281 Jan 03 01:04:06 PM PST 24 Jan 03 01:05:13 PM PST 24 47245050 ps
T767 /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.3384731974 Jan 03 01:03:48 PM PST 24 Jan 03 01:04:44 PM PST 24 43341936 ps
T768 /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.4062073803 Jan 03 01:03:44 PM PST 24 Jan 03 01:04:39 PM PST 24 21166037 ps
T769 /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.1487167615 Jan 03 01:02:36 PM PST 24 Jan 03 01:03:44 PM PST 24 31373012 ps
T770 /workspace/coverage/default/32.clkmgr_regwen.4014162663 Jan 03 01:04:13 PM PST 24 Jan 03 01:05:26 PM PST 24 110489454 ps
T771 /workspace/coverage/default/15.clkmgr_regwen.1669068768 Jan 03 01:03:26 PM PST 24 Jan 03 01:04:27 PM PST 24 724733393 ps
T772 /workspace/coverage/default/46.clkmgr_stress_all.1879346836 Jan 03 01:04:40 PM PST 24 Jan 03 01:07:39 PM PST 24 13155470068 ps
T773 /workspace/coverage/default/13.clkmgr_div_intersig_mubi.3118474073 Jan 03 01:03:04 PM PST 24 Jan 03 01:04:11 PM PST 24 25909575 ps
T774 /workspace/coverage/default/31.clkmgr_regwen.1634488234 Jan 03 01:03:52 PM PST 24 Jan 03 01:04:53 PM PST 24 308531925 ps
T775 /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.1956460023 Jan 03 01:02:45 PM PST 24 Jan 03 01:03:52 PM PST 24 39397604 ps
T776 /workspace/coverage/default/48.clkmgr_div_intersig_mubi.1006269055 Jan 03 01:04:16 PM PST 24 Jan 03 01:05:30 PM PST 24 30386450 ps
T777 /workspace/coverage/default/40.clkmgr_peri.2308105809 Jan 03 01:04:01 PM PST 24 Jan 03 01:05:04 PM PST 24 11491038 ps
T778 /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.708144931 Jan 03 01:02:33 PM PST 24 Jan 03 01:03:45 PM PST 24 56716559 ps
T779 /workspace/coverage/default/39.clkmgr_peri.912320910 Jan 03 01:04:49 PM PST 24 Jan 03 01:06:08 PM PST 24 21307655 ps
T780 /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.1449959944 Jan 03 01:04:21 PM PST 24 Jan 03 01:05:39 PM PST 24 35623738 ps
T781 /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.3197156739 Jan 03 01:04:08 PM PST 24 Jan 03 01:05:15 PM PST 24 15742468 ps
T782 /workspace/coverage/default/19.clkmgr_frequency.1617058583 Jan 03 01:04:10 PM PST 24 Jan 03 01:05:20 PM PST 24 226960825 ps
T783 /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1594142980 Jan 03 01:03:04 PM PST 24 Jan 03 01:04:11 PM PST 24 25707535 ps
T784 /workspace/coverage/default/6.clkmgr_alert_test.117726403 Jan 03 01:02:47 PM PST 24 Jan 03 01:03:53 PM PST 24 15832635 ps
T785 /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.1450590448 Jan 03 01:04:03 PM PST 24 Jan 03 01:05:09 PM PST 24 19808822 ps
T786 /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3085838866 Jan 03 01:02:54 PM PST 24 Jan 03 01:03:59 PM PST 24 24497353 ps
T787 /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.1519765435 Jan 03 01:02:54 PM PST 24 Jan 03 01:03:59 PM PST 24 28324317 ps
T788 /workspace/coverage/default/23.clkmgr_stress_all.1754755262 Jan 03 01:03:28 PM PST 24 Jan 03 01:05:00 PM PST 24 4881208356 ps
T789 /workspace/coverage/default/7.clkmgr_frequency_timeout.2946830418 Jan 03 01:02:55 PM PST 24 Jan 03 01:04:09 PM PST 24 1461042276 ps
T790 /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1134066439 Jan 03 01:04:22 PM PST 24 Jan 03 01:05:40 PM PST 24 30442067 ps
T791 /workspace/coverage/default/6.clkmgr_frequency.2881963024 Jan 03 01:03:07 PM PST 24 Jan 03 01:04:27 PM PST 24 1761796836 ps
T792 /workspace/coverage/default/14.clkmgr_frequency.1208043312 Jan 03 01:03:06 PM PST 24 Jan 03 01:04:16 PM PST 24 679623819 ps
T793 /workspace/coverage/default/22.clkmgr_alert_test.3164396188 Jan 03 01:03:46 PM PST 24 Jan 03 01:04:42 PM PST 24 112414321 ps
T794 /workspace/coverage/default/1.clkmgr_smoke.3454172 Jan 03 01:02:29 PM PST 24 Jan 03 01:03:37 PM PST 24 40155657 ps
T795 /workspace/coverage/default/2.clkmgr_trans.2345562565 Jan 03 01:02:36 PM PST 24 Jan 03 01:03:43 PM PST 24 32334536 ps
T796 /workspace/coverage/default/37.clkmgr_stress_all.567553053 Jan 03 01:03:46 PM PST 24 Jan 03 01:05:13 PM PST 24 5113782782 ps
T797 /workspace/coverage/default/37.clkmgr_frequency_timeout.3125196564 Jan 03 01:03:51 PM PST 24 Jan 03 01:04:49 PM PST 24 157010507 ps
T798 /workspace/coverage/default/11.clkmgr_clk_status.3952528128 Jan 03 01:03:20 PM PST 24 Jan 03 01:04:22 PM PST 24 38725735 ps
T10 /workspace/coverage/default/2.clkmgr_regwen.3156613216 Jan 03 01:02:36 PM PST 24 Jan 03 01:03:47 PM PST 24 746122524 ps
T799 /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.1404919816 Jan 03 01:03:57 PM PST 24 Jan 03 01:14:18 PM PST 24 36626740162 ps
T800 /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3760643193 Jan 03 01:04:14 PM PST 24 Jan 03 01:05:28 PM PST 24 46696530 ps
T801 /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.631267246 Jan 03 01:03:10 PM PST 24 Jan 03 01:04:16 PM PST 24 94197611 ps
T802 /workspace/coverage/default/24.clkmgr_peri.3260557784 Jan 03 01:03:42 PM PST 24 Jan 03 01:04:35 PM PST 24 13189587 ps
T803 /workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.4259757697 Jan 03 01:02:48 PM PST 24 Jan 03 01:08:16 PM PST 24 14145087011 ps
T804 /workspace/coverage/default/6.clkmgr_regwen.4188222372 Jan 03 01:02:55 PM PST 24 Jan 03 01:04:02 PM PST 24 649133200 ps
T805 /workspace/coverage/default/44.clkmgr_peri.1361901103 Jan 03 01:04:22 PM PST 24 Jan 03 01:05:39 PM PST 24 22393582 ps
T806 /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3504372755 Jan 03 01:04:11 PM PST 24 Jan 03 01:05:21 PM PST 24 38314411 ps
T807 /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.2292815689 Jan 03 01:03:49 PM PST 24 Jan 03 01:08:50 PM PST 24 25630423625 ps
T808 /workspace/coverage/default/33.clkmgr_div_intersig_mubi.3955917738 Jan 03 01:03:51 PM PST 24 Jan 03 01:04:49 PM PST 24 53700493 ps
T809 /workspace/coverage/default/10.clkmgr_peri.3562189828 Jan 03 01:02:50 PM PST 24 Jan 03 01:03:56 PM PST 24 23658365 ps
T810 /workspace/coverage/default/24.clkmgr_clk_status.3966594203 Jan 03 01:03:46 PM PST 24 Jan 03 01:04:40 PM PST 24 46464844 ps
T811 /workspace/coverage/default/3.clkmgr_alert_test.536880952 Jan 03 01:02:29 PM PST 24 Jan 03 01:03:37 PM PST 24 27401589 ps
T812 /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1896464515 Jan 03 01:03:06 PM PST 24 Jan 03 01:04:12 PM PST 24 77218366 ps
T813 /workspace/coverage/default/32.clkmgr_peri.3447334702 Jan 03 01:04:09 PM PST 24 Jan 03 01:05:18 PM PST 24 15323656 ps
T814 /workspace/coverage/default/5.clkmgr_div_intersig_mubi.1003944501 Jan 03 01:02:44 PM PST 24 Jan 03 01:03:51 PM PST 24 172301143 ps
T815 /workspace/coverage/default/18.clkmgr_peri.2390688748 Jan 03 01:03:48 PM PST 24 Jan 03 01:04:46 PM PST 24 31082821 ps
T816 /workspace/coverage/default/49.clkmgr_extclk.3328196577 Jan 03 01:04:15 PM PST 24 Jan 03 01:05:29 PM PST 24 51082923 ps
T817 /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1450065579 Jan 03 01:04:45 PM PST 24 Jan 03 01:06:04 PM PST 24 25825973 ps
T818 /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.108291416 Jan 03 01:03:46 PM PST 24 Jan 03 01:04:40 PM PST 24 48981769 ps
T819 /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.286123237 Jan 03 01:04:08 PM PST 24 Jan 03 01:05:17 PM PST 24 20736257 ps
T820 /workspace/coverage/default/30.clkmgr_div_intersig_mubi.392036454 Jan 03 01:03:52 PM PST 24 Jan 03 01:04:52 PM PST 24 66287045 ps
T821 /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.2392262392 Jan 03 01:04:19 PM PST 24 Jan 03 01:05:36 PM PST 24 22645858 ps
T822 /workspace/coverage/default/18.clkmgr_trans.3439783556 Jan 03 01:03:44 PM PST 24 Jan 03 01:04:39 PM PST 24 146668471 ps
T823 /workspace/coverage/default/13.clkmgr_trans.3509415861 Jan 03 01:02:46 PM PST 24 Jan 03 01:03:53 PM PST 24 110090005 ps
T824 /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.3211232912 Jan 03 01:04:22 PM PST 24 Jan 03 01:09:33 PM PST 24 16398571060 ps
T825 /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.3566840394 Jan 03 01:02:32 PM PST 24 Jan 03 01:03:40 PM PST 24 21667475 ps
T826 /workspace/coverage/default/34.clkmgr_smoke.1389477548 Jan 03 01:03:41 PM PST 24 Jan 03 01:04:37 PM PST 24 309893789 ps
T827 /workspace/coverage/default/7.clkmgr_smoke.3123560943 Jan 03 01:02:52 PM PST 24 Jan 03 01:03:57 PM PST 24 126889640 ps
T828 /workspace/coverage/default/8.clkmgr_clk_status.33365712 Jan 03 01:03:23 PM PST 24 Jan 03 01:04:23 PM PST 24 46474768 ps
T829 /workspace/coverage/default/11.clkmgr_peri.2424866472 Jan 03 01:03:08 PM PST 24 Jan 03 01:04:14 PM PST 24 37735734 ps
T58 /workspace/coverage/default/0.clkmgr_sec_cm.2772202392 Jan 03 01:02:20 PM PST 24 Jan 03 01:03:29 PM PST 24 178935780 ps
T59 /workspace/coverage/default/25.clkmgr_extclk.181776444 Jan 03 01:03:39 PM PST 24 Jan 03 01:04:33 PM PST 24 45493681 ps
T60 /workspace/coverage/default/8.clkmgr_frequency_timeout.3760129022 Jan 03 01:03:04 PM PST 24 Jan 03 01:04:17 PM PST 24 1711876250 ps
T61 /workspace/coverage/default/21.clkmgr_stress_all.1051590576 Jan 03 01:04:15 PM PST 24 Jan 03 01:05:48 PM PST 24 4941741336 ps
T62 /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.1870052653 Jan 03 01:04:21 PM PST 24 Jan 03 01:05:38 PM PST 24 114122181 ps
T43 /workspace/coverage/default/42.clkmgr_stress_all.2591615632 Jan 03 01:04:23 PM PST 24 Jan 03 01:06:27 PM PST 24 9089224411 ps
T63 /workspace/coverage/default/38.clkmgr_peri.348287097 Jan 03 01:04:18 PM PST 24 Jan 03 01:05:34 PM PST 24 13413531 ps
T64 /workspace/coverage/default/25.clkmgr_div_intersig_mubi.646608166 Jan 03 01:03:46 PM PST 24 Jan 03 01:04:40 PM PST 24 45427573 ps
T65 /workspace/coverage/default/8.clkmgr_frequency.906388670 Jan 03 01:02:56 PM PST 24 Jan 03 01:04:16 PM PST 24 2240794885 ps
T830 /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.3833579058 Jan 03 01:04:03 PM PST 24 Jan 03 01:13:18 PM PST 24 32202894086 ps
T831 /workspace/coverage/default/19.clkmgr_div_intersig_mubi.787243388 Jan 03 01:03:40 PM PST 24 Jan 03 01:04:35 PM PST 24 22387965 ps
T832 /workspace/coverage/default/31.clkmgr_div_intersig_mubi.2470419367 Jan 03 01:04:08 PM PST 24 Jan 03 01:05:17 PM PST 24 35493549 ps
T833 /workspace/coverage/default/41.clkmgr_peri.529798177 Jan 03 01:04:26 PM PST 24 Jan 03 01:05:46 PM PST 24 14430556 ps
T834 /workspace/coverage/default/19.clkmgr_frequency_timeout.3398577231 Jan 03 01:04:16 PM PST 24 Jan 03 01:05:43 PM PST 24 2058245247 ps
T835 /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.4291407983 Jan 03 01:04:17 PM PST 24 Jan 03 01:15:22 PM PST 24 40559619726 ps
T836 /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.491887873 Jan 03 01:02:48 PM PST 24 Jan 03 01:03:55 PM PST 24 21491400 ps
T837 /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.516602436 Jan 03 01:03:55 PM PST 24 Jan 03 01:04:55 PM PST 24 24252422 ps
T838 /workspace/coverage/default/25.clkmgr_clk_status.933398119 Jan 03 01:03:43 PM PST 24 Jan 03 01:04:37 PM PST 24 31223109 ps
T839 /workspace/coverage/default/9.clkmgr_clk_status.836376775 Jan 03 01:03:57 PM PST 24 Jan 03 01:04:58 PM PST 24 55623458 ps
T840 /workspace/coverage/default/35.clkmgr_stress_all.835529801 Jan 03 01:04:05 PM PST 24 Jan 03 01:05:31 PM PST 24 2563495151 ps
T841 /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1845244159 Jan 03 01:03:12 PM PST 24 Jan 03 01:04:17 PM PST 24 18555084 ps
T842 /workspace/coverage/default/3.clkmgr_extclk.3353653793 Jan 03 01:02:27 PM PST 24 Jan 03 01:03:36 PM PST 24 30216551 ps
T843 /workspace/coverage/default/4.clkmgr_extclk.1739341276 Jan 03 01:02:38 PM PST 24 Jan 03 01:03:45 PM PST 24 28227997 ps
T844 /workspace/coverage/default/47.clkmgr_frequency.428101521 Jan 03 01:04:31 PM PST 24 Jan 03 01:06:17 PM PST 24 2241588910 ps
T845 /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.1488783069 Jan 03 01:04:21 PM PST 24 Jan 03 01:05:39 PM PST 24 18686724 ps
T846 /workspace/coverage/default/16.clkmgr_regwen.2340462437 Jan 03 01:03:39 PM PST 24 Jan 03 01:04:36 PM PST 24 1110244015 ps
T847 /workspace/coverage/default/19.clkmgr_clk_status.1648749048 Jan 03 01:04:21 PM PST 24 Jan 03 01:05:39 PM PST 24 45070321 ps
T848 /workspace/coverage/default/23.clkmgr_extclk.1821695740 Jan 03 01:03:48 PM PST 24 Jan 03 01:04:44 PM PST 24 17980051 ps
T849 /workspace/coverage/default/18.clkmgr_extclk.2601095354 Jan 03 01:03:28 PM PST 24 Jan 03 01:04:25 PM PST 24 24733693 ps
T850 /workspace/coverage/default/42.clkmgr_div_intersig_mubi.3878809104 Jan 03 01:04:22 PM PST 24 Jan 03 01:05:39 PM PST 24 14929158 ps
T851 /workspace/coverage/default/21.clkmgr_div_intersig_mubi.3091107858 Jan 03 01:04:07 PM PST 24 Jan 03 01:05:15 PM PST 24 21619170 ps
T852 /workspace/coverage/default/0.clkmgr_trans.2284963863 Jan 03 01:02:47 PM PST 24 Jan 03 01:03:54 PM PST 24 34464426 ps
T853 /workspace/coverage/default/30.clkmgr_trans.2750831142 Jan 03 01:04:39 PM PST 24 Jan 03 01:06:03 PM PST 24 87234944 ps
T854 /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1029899730 Jan 03 01:04:28 PM PST 24 Jan 03 01:05:59 PM PST 24 30346851 ps
T855 /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.3805903441 Jan 03 01:04:24 PM PST 24 Jan 03 01:14:19 PM PST 24 43278808653 ps
T856 /workspace/coverage/default/49.clkmgr_clk_status.2915380352 Jan 03 01:04:28 PM PST 24 Jan 03 01:05:51 PM PST 24 15781913 ps
T857 /workspace/coverage/default/16.clkmgr_stress_all.1911943038 Jan 03 01:03:28 PM PST 24 Jan 03 01:04:37 PM PST 24 2320488191 ps
T858 /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.2150955515 Jan 03 01:04:24 PM PST 24 Jan 03 01:05:45 PM PST 24 162765151 ps
T859 /workspace/coverage/default/49.clkmgr_frequency_timeout.2637746454 Jan 03 01:04:24 PM PST 24 Jan 03 01:05:47 PM PST 24 613332897 ps
T860 /workspace/coverage/default/40.clkmgr_div_intersig_mubi.2333117606 Jan 03 01:04:09 PM PST 24 Jan 03 01:05:19 PM PST 24 49393140 ps
T861 /workspace/coverage/default/13.clkmgr_regwen.1978825060 Jan 03 01:02:54 PM PST 24 Jan 03 01:04:01 PM PST 24 375048245 ps
T862 /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.2997594799 Jan 03 01:04:14 PM PST 24 Jan 03 01:08:11 PM PST 24 10985026967 ps
T863 /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.722958190 Jan 03 01:04:00 PM PST 24 Jan 03 01:05:04 PM PST 24 257592361 ps
T864 /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.1477045503 Jan 03 01:03:41 PM PST 24 Jan 03 01:04:35 PM PST 24 118958266 ps
T865 /workspace/coverage/default/8.clkmgr_stress_all.2060701976 Jan 03 01:03:39 PM PST 24 Jan 03 01:04:40 PM PST 24 1479731130 ps
T866 /workspace/coverage/default/43.clkmgr_div_intersig_mubi.4217246471 Jan 03 01:04:14 PM PST 24 Jan 03 01:05:27 PM PST 24 21920794 ps
T867 /workspace/coverage/default/37.clkmgr_clk_status.2559468350 Jan 03 01:04:11 PM PST 24 Jan 03 01:05:22 PM PST 24 87559286 ps
T868 /workspace/coverage/default/30.clkmgr_stress_all.461366707 Jan 03 01:04:01 PM PST 24 Jan 03 01:05:58 PM PST 24 11206971638 ps
T869 /workspace/coverage/default/34.clkmgr_div_intersig_mubi.654055990 Jan 03 01:03:54 PM PST 24 Jan 03 01:04:53 PM PST 24 48247339 ps
T870 /workspace/coverage/default/20.clkmgr_extclk.353207669 Jan 03 01:03:27 PM PST 24 Jan 03 01:04:25 PM PST 24 46814349 ps
T871 /workspace/coverage/default/7.clkmgr_peri.1374621551 Jan 03 01:02:56 PM PST 24 Jan 03 01:04:01 PM PST 24 12540655 ps
T872 /workspace/coverage/default/35.clkmgr_frequency_timeout.782807280 Jan 03 01:04:00 PM PST 24 Jan 03 01:05:06 PM PST 24 377841043 ps
T873 /workspace/coverage/default/15.clkmgr_frequency.2811650477 Jan 03 01:03:11 PM PST 24 Jan 03 01:04:21 PM PST 24 678450237 ps
T874 /workspace/coverage/default/18.clkmgr_regwen.3416771625 Jan 03 01:04:08 PM PST 24 Jan 03 01:05:17 PM PST 24 535286160 ps
T875 /workspace/coverage/default/49.clkmgr_trans.2512702372 Jan 03 01:04:17 PM PST 24 Jan 03 01:05:35 PM PST 24 22413719 ps
T876 /workspace/coverage/default/27.clkmgr_clk_status.1160683430 Jan 03 01:04:02 PM PST 24 Jan 03 01:05:06 PM PST 24 16160989 ps
T877 /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.1312776411 Jan 03 01:03:51 PM PST 24 Jan 03 01:04:49 PM PST 24 48433237 ps
T878 /workspace/coverage/default/26.clkmgr_div_intersig_mubi.2409046771 Jan 03 01:04:06 PM PST 24 Jan 03 01:05:13 PM PST 24 37035945 ps
T879 /workspace/coverage/default/13.clkmgr_stress_all.1564724991 Jan 03 01:02:46 PM PST 24 Jan 03 01:04:10 PM PST 24 4103296809 ps
T880 /workspace/coverage/default/7.clkmgr_alert_test.1788009956 Jan 03 01:02:52 PM PST 24 Jan 03 01:03:58 PM PST 24 108262637 ps
T881 /workspace/coverage/default/18.clkmgr_frequency_timeout.2242615301 Jan 03 01:04:19 PM PST 24 Jan 03 01:05:39 PM PST 24 616774513 ps
T882 /workspace/coverage/default/49.clkmgr_peri.2203000185 Jan 03 01:04:20 PM PST 24 Jan 03 01:05:37 PM PST 24 44502139 ps
T883 /workspace/coverage/default/12.clkmgr_smoke.2546524933 Jan 03 01:03:02 PM PST 24 Jan 03 01:04:09 PM PST 24 68892052 ps
T884 /workspace/coverage/default/10.clkmgr_alert_test.2290388628 Jan 03 01:03:05 PM PST 24 Jan 03 01:04:11 PM PST 24 64039121 ps
T885 /workspace/coverage/default/3.clkmgr_smoke.2320970336 Jan 03 01:02:28 PM PST 24 Jan 03 01:03:37 PM PST 24 43916074 ps
T886 /workspace/coverage/default/21.clkmgr_regwen.3146424345 Jan 03 01:04:09 PM PST 24 Jan 03 01:05:21 PM PST 24 480566857 ps
T887 /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1298586408 Jan 03 01:03:06 PM PST 24 Jan 03 01:04:13 PM PST 24 12478734 ps
T888 /workspace/coverage/default/24.clkmgr_div_intersig_mubi.653261931 Jan 03 01:03:42 PM PST 24 Jan 03 01:04:36 PM PST 24 21646639 ps
T889 /workspace/coverage/default/41.clkmgr_frequency.3953845240 Jan 03 01:04:22 PM PST 24 Jan 03 01:05:57 PM PST 24 2242390572 ps
T890 /workspace/coverage/default/38.clkmgr_smoke.915806935 Jan 03 01:04:14 PM PST 24 Jan 03 01:05:28 PM PST 24 31044602 ps
T891 /workspace/coverage/default/43.clkmgr_regwen.2636419212 Jan 03 01:04:20 PM PST 24 Jan 03 01:05:38 PM PST 24 162576943 ps
T892 /workspace/coverage/default/28.clkmgr_regwen.2713037505 Jan 03 01:04:17 PM PST 24 Jan 03 01:05:40 PM PST 24 1228844555 ps
T893 /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.3844095182 Jan 03 01:03:56 PM PST 24 Jan 03 01:19:46 PM PST 24 228840235246 ps
T894 /workspace/coverage/default/17.clkmgr_alert_test.1579430925 Jan 03 01:04:06 PM PST 24 Jan 03 01:05:12 PM PST 24 20617632 ps
T895 /workspace/coverage/default/32.clkmgr_div_intersig_mubi.1517488643 Jan 03 01:04:23 PM PST 24 Jan 03 01:05:41 PM PST 24 59634807 ps
T896 /workspace/coverage/default/18.clkmgr_frequency.1373334748 Jan 03 01:03:56 PM PST 24 Jan 03 01:05:05 PM PST 24 1880974814 ps
T897 /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.2163772634 Jan 03 01:02:27 PM PST 24 Jan 03 01:03:35 PM PST 24 42316098 ps
T898 /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2308948535 Jan 03 01:04:25 PM PST 24 Jan 03 01:05:45 PM PST 24 81573784 ps
T899 /workspace/coverage/default/7.clkmgr_trans.440242260 Jan 03 01:03:00 PM PST 24 Jan 03 01:04:07 PM PST 24 28766024 ps
T900 /workspace/coverage/default/1.clkmgr_extclk.3424281744 Jan 03 01:02:18 PM PST 24 Jan 03 01:03:26 PM PST 24 63910982 ps
T901 /workspace/coverage/default/37.clkmgr_smoke.3232130405 Jan 03 01:04:06 PM PST 24 Jan 03 01:05:13 PM PST 24 23373019 ps
T902 /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.2156566886 Jan 03 01:03:45 PM PST 24 Jan 03 01:04:39 PM PST 24 29985392 ps
T903 /workspace/coverage/default/36.clkmgr_smoke.353607576 Jan 03 01:04:06 PM PST 24 Jan 03 01:05:13 PM PST 24 94153964 ps
T904 /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.3893197669 Jan 03 01:04:09 PM PST 24 Jan 03 01:05:17 PM PST 24 22310300 ps
T905 /workspace/coverage/default/48.clkmgr_stress_all.456060967 Jan 03 01:04:22 PM PST 24 Jan 03 01:06:00 PM PST 24 5832879768 ps
T906 /workspace/coverage/default/20.clkmgr_regwen.1237823762 Jan 03 01:03:48 PM PST 24 Jan 03 01:04:46 PM PST 24 681199986 ps
T907 /workspace/coverage/default/18.clkmgr_smoke.2323727790 Jan 03 01:04:00 PM PST 24 Jan 03 01:05:04 PM PST 24 17173135 ps
T908 /workspace/coverage/default/30.clkmgr_clk_status.2819255346 Jan 03 01:04:35 PM PST 24 Jan 03 01:05:55 PM PST 24 17308710 ps
T909 /workspace/coverage/default/4.clkmgr_div_intersig_mubi.1549065627 Jan 03 01:02:44 PM PST 24 Jan 03 01:03:51 PM PST 24 19139276 ps
T910 /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.2660383581 Jan 03 01:04:18 PM PST 24 Jan 03 01:05:34 PM PST 24 27464189 ps
T911 /workspace/coverage/default/35.clkmgr_trans.1355662941 Jan 03 01:03:58 PM PST 24 Jan 03 01:05:00 PM PST 24 26094919 ps
T912 /workspace/coverage/default/47.clkmgr_peri.2537638700 Jan 03 01:04:27 PM PST 24 Jan 03 01:05:47 PM PST 24 14246540 ps
T913 /workspace/coverage/default/30.clkmgr_extclk.793260038 Jan 03 01:04:34 PM PST 24 Jan 03 01:05:57 PM PST 24 55365666 ps
T914 /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2177051913 Jan 03 01:02:45 PM PST 24 Jan 03 01:03:52 PM PST 24 124295872 ps
T915 /workspace/coverage/default/25.clkmgr_smoke.491950076 Jan 03 01:03:36 PM PST 24 Jan 03 01:04:31 PM PST 24 76293326 ps
T916 /workspace/coverage/default/6.clkmgr_clk_status.860194664 Jan 03 01:02:49 PM PST 24 Jan 03 01:03:55 PM PST 24 51680443 ps
T917 /workspace/coverage/default/10.clkmgr_frequency.1501881393 Jan 03 01:02:53 PM PST 24 Jan 03 01:04:07 PM PST 24 2140265108 ps
T918 /workspace/coverage/default/42.clkmgr_smoke.2750234827 Jan 03 01:04:22 PM PST 24 Jan 03 01:05:40 PM PST 24 44528035 ps
T919 /workspace/coverage/default/33.clkmgr_smoke.4064651944 Jan 03 01:04:39 PM PST 24 Jan 03 01:06:04 PM PST 24 71768514 ps
T920 /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1334213972 Jan 03 01:03:28 PM PST 24 Jan 03 01:04:25 PM PST 24 47458104 ps
T921 /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.129901817 Jan 03 01:03:06 PM PST 24 Jan 03 01:04:12 PM PST 24 35128950 ps
T922 /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.2391361608 Jan 03 01:03:50 PM PST 24 Jan 03 01:04:47 PM PST 24 22619571 ps
T923 /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.3526685762 Jan 03 01:02:49 PM PST 24 Jan 03 01:03:55 PM PST 24 31735988 ps
T924 /workspace/coverage/default/15.clkmgr_smoke.2038642832 Jan 03 01:03:08 PM PST 24 Jan 03 01:04:14 PM PST 24 67145548 ps
T925 /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.3914809077 Jan 03 01:02:45 PM PST 24 Jan 03 01:03:52 PM PST 24 27965244 ps
T926 /workspace/coverage/default/47.clkmgr_stress_all.187583438 Jan 03 01:04:43 PM PST 24 Jan 03 01:06:15 PM PST 24 2006070922 ps
T927 /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.2379430790 Jan 03 01:03:41 PM PST 24 Jan 03 01:04:42 PM PST 24 39214770 ps
T928 /workspace/coverage/default/0.clkmgr_smoke.2232325354 Jan 03 01:02:55 PM PST 24 Jan 03 01:04:00 PM PST 24 19984419 ps
T929 /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.4202618914 Jan 03 01:03:28 PM PST 24 Jan 03 01:04:25 PM PST 24 35013678 ps
T930 /workspace/coverage/default/35.clkmgr_regwen.1754657600 Jan 03 01:04:00 PM PST 24 Jan 03 01:05:08 PM PST 24 1157417107 ps
T931 /workspace/coverage/default/34.clkmgr_trans.2888550295 Jan 03 01:04:04 PM PST 24 Jan 03 01:05:09 PM PST 24 40522603 ps
T932 /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.3914309116 Jan 03 01:03:01 PM PST 24 Jan 03 01:04:08 PM PST 24 25064424 ps
T933 /workspace/coverage/default/24.clkmgr_stress_all.1437920168 Jan 03 01:03:55 PM PST 24 Jan 03 01:05:30 PM PST 24 8654202421 ps
T934 /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3567827283 Jan 03 01:02:43 PM PST 24 Jan 03 01:03:50 PM PST 24 51446780 ps
T935 /workspace/coverage/default/36.clkmgr_peri.1342669506 Jan 03 01:04:02 PM PST 24 Jan 03 01:05:06 PM PST 24 22394114 ps
T936 /workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.1115094469 Jan 03 01:04:12 PM PST 24 Jan 03 01:16:56 PM PST 24 44088622785 ps
T937 /workspace/coverage/default/36.clkmgr_frequency.1789230060 Jan 03 01:04:06 PM PST 24 Jan 03 01:05:21 PM PST 24 1926277899 ps
T938 /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.3154474603 Jan 03 01:03:43 PM PST 24 Jan 03 01:04:37 PM PST 24 58722373 ps
T939 /workspace/coverage/default/47.clkmgr_frequency_timeout.3653643635 Jan 03 01:04:19 PM PST 24 Jan 03 01:05:37 PM PST 24 266992105 ps
T940 /workspace/coverage/default/28.clkmgr_peri.1023864860 Jan 03 01:03:50 PM PST 24 Jan 03 01:04:47 PM PST 24 26066305 ps
T941 /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.542084433 Jan 03 01:04:05 PM PST 24 Jan 03 01:05:13 PM PST 24 117185946 ps
T942 /workspace/coverage/default/32.clkmgr_smoke.2074233226 Jan 03 01:03:57 PM PST 24 Jan 03 01:04:58 PM PST 24 48595426 ps
T943 /workspace/coverage/default/22.clkmgr_frequency.3424121494 Jan 03 01:04:24 PM PST 24 Jan 03 01:05:45 PM PST 24 318654353 ps
T944 /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.3027378703 Jan 03 01:04:11 PM PST 24 Jan 03 01:05:22 PM PST 24 24967686 ps
T945 /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.2015988831 Jan 03 01:03:33 PM PST 24 Jan 03 01:04:28 PM PST 24 14493051 ps
T946 /workspace/coverage/default/10.clkmgr_clk_status.4179787932 Jan 03 01:03:01 PM PST 24 Jan 03 01:04:08 PM PST 24 40701199 ps
T947 /workspace/coverage/default/12.clkmgr_peri.2882847821 Jan 03 01:03:12 PM PST 24 Jan 03 01:04:17 PM PST 24 20675815 ps
T948 /workspace/coverage/default/22.clkmgr_frequency_timeout.1923045538 Jan 03 01:04:08 PM PST 24 Jan 03 01:05:26 PM PST 24 1700429786 ps
T949 /workspace/coverage/default/9.clkmgr_extclk.1899506495 Jan 03 01:03:56 PM PST 24 Jan 03 01:04:57 PM PST 24 47780645 ps
T950 /workspace/coverage/default/46.clkmgr_clk_status.2751805424 Jan 03 01:04:16 PM PST 24 Jan 03 01:05:31 PM PST 24 25131519 ps
T951 /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.206348765 Jan 03 01:04:05 PM PST 24 Jan 03 01:05:12 PM PST 24 55595157 ps
T952 /workspace/coverage/default/16.clkmgr_frequency.2271662631 Jan 03 01:03:49 PM PST 24 Jan 03 01:04:47 PM PST 24 252729822 ps
T953 /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1388040303 Jan 03 01:04:16 PM PST 24 Jan 03 01:05:30 PM PST 24 47373629 ps
T954 /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.232393476 Jan 03 01:04:27 PM PST 24 Jan 03 01:12:10 PM PST 24 27641277883 ps
T955 /workspace/coverage/default/49.clkmgr_smoke.2822563376 Jan 03 01:04:22 PM PST 24 Jan 03 01:05:41 PM PST 24 87071177 ps
T956 /workspace/coverage/default/28.clkmgr_div_intersig_mubi.1955038984 Jan 03 01:04:22 PM PST 24 Jan 03 01:05:39 PM PST 24 81922310 ps
T957 /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.719097383 Jan 03 01:04:05 PM PST 24 Jan 03 01:05:12 PM PST 24 27738864 ps
T958 /workspace/coverage/default/41.clkmgr_clk_status.687590912 Jan 03 01:04:14 PM PST 24 Jan 03 01:05:28 PM PST 24 88410143 ps
T959 /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.2930301072 Jan 03 01:02:29 PM PST 24 Jan 03 01:03:38 PM PST 24 32122742 ps
T960 /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.1672524271 Jan 03 01:03:56 PM PST 24 Jan 03 01:04:56 PM PST 24 31300363 ps
T961 /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.1369904701 Jan 03 01:04:28 PM PST 24 Jan 03 01:05:51 PM PST 24 34706149 ps
T962 /workspace/coverage/default/25.clkmgr_alert_test.3763204196 Jan 03 01:03:41 PM PST 24 Jan 03 01:04:35 PM PST 24 49981741 ps
T963 /workspace/coverage/default/46.clkmgr_peri.3620067057 Jan 03 01:04:17 PM PST 24 Jan 03 01:05:35 PM PST 24 18254120 ps
T964 /workspace/coverage/default/10.clkmgr_stress_all.1191536952 Jan 03 01:02:58 PM PST 24 Jan 03 01:04:47 PM PST 24 8522738412 ps
T965 /workspace/coverage/default/45.clkmgr_stress_all.1763788833 Jan 03 01:04:17 PM PST 24 Jan 03 01:05:52 PM PST 24 4745974326 ps
T966 /workspace/coverage/default/42.clkmgr_alert_test.1545785862 Jan 03 01:04:16 PM PST 24 Jan 03 01:05:31 PM PST 24 58750302 ps
T967 /workspace/coverage/default/0.clkmgr_frequency.2953251934 Jan 03 01:02:51 PM PST 24 Jan 03 01:04:01 PM PST 24 682251550 ps
T968 /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.3208521124 Jan 03 01:04:11 PM PST 24 Jan 03 01:05:21 PM PST 24 21107133 ps
T969 /workspace/coverage/default/25.clkmgr_trans.2654561541 Jan 03 01:03:45 PM PST 24 Jan 03 01:04:39 PM PST 24 109186303 ps
T970 /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.3192799484 Jan 03 01:04:24 PM PST 24 Jan 03 01:14:01 PM PST 24 33470955461 ps
T971 /workspace/coverage/default/9.clkmgr_regwen.3670633488 Jan 03 01:02:54 PM PST 24 Jan 03 01:04:00 PM PST 24 138142300 ps
T972 /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.1588551139 Jan 03 01:02:49 PM PST 24 Jan 03 01:12:15 PM PST 24 36337839218 ps
T973 /workspace/coverage/default/39.clkmgr_extclk.229817360 Jan 03 01:04:27 PM PST 24 Jan 03 01:05:48 PM PST 24 25848018 ps
T974 /workspace/coverage/default/48.clkmgr_extclk.110570217 Jan 03 01:03:59 PM PST 24 Jan 03 01:05:01 PM PST 24 24958020 ps
T975 /workspace/coverage/default/31.clkmgr_frequency.2646272456 Jan 03 01:03:45 PM PST 24 Jan 03 01:04:47 PM PST 24 1521548532 ps
T976 /workspace/coverage/default/20.clkmgr_clk_status.678894146 Jan 03 01:03:48 PM PST 24 Jan 03 01:04:44 PM PST 24 37115301 ps
T977 /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1625155231 Jan 03 01:04:16 PM PST 24 Jan 03 01:05:32 PM PST 24 19207865 ps
T978 /workspace/coverage/default/29.clkmgr_alert_test.60390452 Jan 03 01:04:20 PM PST 24 Jan 03 01:05:38 PM PST 24 14620942 ps
T979 /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.335633572 Jan 03 01:04:04 PM PST 24 Jan 03 01:05:10 PM PST 24 30446214 ps
T980 /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3018218121 Jan 03 01:04:22 PM PST 24 Jan 03 01:05:41 PM PST 24 90452344 ps
T981 /workspace/coverage/default/10.clkmgr_div_intersig_mubi.3930051155 Jan 03 01:03:01 PM PST 24 Jan 03 01:04:09 PM PST 24 40082525 ps
T982 /workspace/coverage/default/44.clkmgr_clk_status.3598275171 Jan 03 01:04:20 PM PST 24 Jan 03 01:05:38 PM PST 24 52878635 ps
T983 /workspace/coverage/default/15.clkmgr_peri.4095085808 Jan 03 01:03:36 PM PST 24 Jan 03 01:04:31 PM PST 24 17102309 ps
T984 /workspace/coverage/default/13.clkmgr_frequency.3472982347 Jan 03 01:03:43 PM PST 24 Jan 03 01:04:46 PM PST 24 1523134647 ps
T985 /workspace/coverage/default/2.clkmgr_frequency_timeout.2470110107 Jan 03 01:02:41 PM PST 24 Jan 03 01:03:52 PM PST 24 1474286540 ps
T986 /workspace/coverage/default/11.clkmgr_div_intersig_mubi.4076470488 Jan 03 01:03:23 PM PST 24 Jan 03 01:04:23 PM PST 24 24662881 ps
T987 /workspace/coverage/default/48.clkmgr_alert_test.4115141537 Jan 03 01:04:03 PM PST 24 Jan 03 01:05:07 PM PST 24 28921508 ps
T988 /workspace/coverage/default/33.clkmgr_clk_status.1575186090 Jan 03 01:04:28 PM PST 24 Jan 03 01:05:57 PM PST 24 76003314 ps
T989 /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.1205461024 Jan 03 01:04:16 PM PST 24 Jan 03 01:05:31 PM PST 24 87358051 ps
T990 /workspace/coverage/default/36.clkmgr_trans.2074494806 Jan 03 01:04:25 PM PST 24 Jan 03 01:05:45 PM PST 24 100986460 ps
T991 /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.1017432840 Jan 03 01:04:44 PM PST 24 Jan 03 01:06:15 PM PST 24 106871343 ps
T992 /workspace/coverage/default/0.clkmgr_stress_all.2566773771 Jan 03 01:02:26 PM PST 24 Jan 03 01:04:01 PM PST 24 3596344013 ps
T993 /workspace/coverage/default/17.clkmgr_clk_status.1297606832 Jan 03 01:03:33 PM PST 24 Jan 03 01:04:28 PM PST 24 28106493 ps
T994 /workspace/coverage/default/9.clkmgr_div_intersig_mubi.2543539219 Jan 03 01:03:58 PM PST 24 Jan 03 01:04:59 PM PST 24 106123808 ps
T995 /workspace/coverage/default/23.clkmgr_trans.850235526 Jan 03 01:03:57 PM PST 24 Jan 03 01:04:58 PM PST 24 17361668 ps
T996 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2178280857 Jan 03 12:37:44 PM PST 24 Jan 03 12:38:59 PM PST 24 68001353 ps

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1395179042
Short name T5
Test name
Test status
Simulation time 22937936 ps
CPU time 1.46 seconds
Started Jan 03 12:37:54 PM PST 24
Finished Jan 03 12:39:18 PM PST 24
Peak memory 200900 kb
Host smart-e3f6e981-9caa-4b71-87a4-f787ef430799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395179042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.1395179042
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.1663577261
Short name T2
Test name
Test status
Simulation time 180755129305 ps
CPU time 1221.84 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:25:05 PM PST 24
Peak memory 217508 kb
Host smart-6786a35d-5e17-45a9-b510-5744bf161a2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1663577261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.1663577261
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.400640898
Short name T47
Test name
Test status
Simulation time 125022911 ps
CPU time 2.54 seconds
Started Jan 03 12:38:27 PM PST 24
Finished Jan 03 12:39:52 PM PST 24
Peak memory 200920 kb
Host smart-7d8c6d3d-132b-4d19-bb65-294200c85968
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400640898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.clkmgr_tl_intg_err.400640898
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.1457675774
Short name T74
Test name
Test status
Simulation time 295959931 ps
CPU time 2.16 seconds
Started Jan 03 12:38:13 PM PST 24
Finished Jan 03 12:39:33 PM PST 24
Peak memory 201200 kb
Host smart-aa38192d-4470-4987-b165-a86bb8e3d0d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457675774 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.1457675774
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.1737310179
Short name T12
Test name
Test status
Simulation time 9725909326 ps
CPU time 30.34 seconds
Started Jan 03 01:03:25 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 201088 kb
Host smart-a28853c7-9882-47dc-898f-fd8186aa3721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737310179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.1737310179
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1804247076
Short name T97
Test name
Test status
Simulation time 136606515 ps
CPU time 2.6 seconds
Started Jan 03 12:37:17 PM PST 24
Finished Jan 03 12:38:28 PM PST 24
Peak memory 209396 kb
Host smart-90a6af09-21d2-490a-bc97-4a01b9927b99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804247076 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1804247076
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.3206445856
Short name T138
Test name
Test status
Simulation time 15682646 ps
CPU time 0.74 seconds
Started Jan 03 01:02:29 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 200572 kb
Host smart-1925710c-4b47-4acc-95da-e423db266b19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206445856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3206445856
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.2772202392
Short name T58
Test name
Test status
Simulation time 178935780 ps
CPU time 2.06 seconds
Started Jan 03 01:02:20 PM PST 24
Finished Jan 03 01:03:29 PM PST 24
Peak memory 215224 kb
Host smart-8d35f30c-3263-4560-89d8-9898cc2302dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772202392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.2772202392
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.2499006249
Short name T70
Test name
Test status
Simulation time 34423594 ps
CPU time 0.84 seconds
Started Jan 03 01:02:52 PM PST 24
Finished Jan 03 01:03:58 PM PST 24
Peak memory 200712 kb
Host smart-882493ce-9110-4d98-b1af-db2af8194189
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499006249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.2499006249
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.3241126457
Short name T387
Test name
Test status
Simulation time 959156905 ps
CPU time 5.52 seconds
Started Jan 03 01:03:13 PM PST 24
Finished Jan 03 01:04:22 PM PST 24
Peak memory 201000 kb
Host smart-6fd08462-3e09-400b-97fd-5bcc6e86a65c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241126457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3241126457
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.301865158
Short name T49
Test name
Test status
Simulation time 79961858 ps
CPU time 1.49 seconds
Started Jan 03 12:37:50 PM PST 24
Finished Jan 03 12:39:07 PM PST 24
Peak memory 200924 kb
Host smart-01cf3140-2e68-4cd5-b524-4f2918f23ca8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301865158 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.301865158
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3659234901
Short name T93
Test name
Test status
Simulation time 164991288 ps
CPU time 2.17 seconds
Started Jan 03 12:37:45 PM PST 24
Finished Jan 03 12:39:12 PM PST 24
Peak memory 201228 kb
Host smart-5249db50-6bd4-4cf2-9c79-0b1fd926de21
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659234901 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.3659234901
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.3388673379
Short name T73
Test name
Test status
Simulation time 22669887 ps
CPU time 0.85 seconds
Started Jan 03 01:02:54 PM PST 24
Finished Jan 03 01:03:59 PM PST 24
Peak memory 200640 kb
Host smart-6f29fac8-a8ab-4e92-8f13-4a71a855e173
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388673379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.3388673379
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.4009308803
Short name T38
Test name
Test status
Simulation time 15591108 ps
CPU time 0.81 seconds
Started Jan 03 01:03:33 PM PST 24
Finished Jan 03 01:04:28 PM PST 24
Peak memory 200708 kb
Host smart-3232145d-0e2b-4d4b-a925-a12d69d1a09b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009308803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.4009308803
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.3156613216
Short name T10
Test name
Test status
Simulation time 746122524 ps
CPU time 4.35 seconds
Started Jan 03 01:02:36 PM PST 24
Finished Jan 03 01:03:47 PM PST 24
Peak memory 200948 kb
Host smart-8a9f0750-ecd3-40ad-a2fa-b0724e9d1749
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156613216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.3156613216
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1412934393
Short name T107
Test name
Test status
Simulation time 61589045 ps
CPU time 1.52 seconds
Started Jan 03 12:37:31 PM PST 24
Finished Jan 03 12:38:58 PM PST 24
Peak memory 200868 kb
Host smart-387898c8-2eba-466c-ad68-bb6c59561882
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412934393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.1412934393
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3075843847
Short name T35
Test name
Test status
Simulation time 96117797 ps
CPU time 1.15 seconds
Started Jan 03 12:37:33 PM PST 24
Finished Jan 03 12:38:45 PM PST 24
Peak memory 200696 kb
Host smart-530f7ce7-8a83-4842-8b37-cd91e83941cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075843847 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.3075843847
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.657870807
Short name T125
Test name
Test status
Simulation time 188239948 ps
CPU time 1.88 seconds
Started Jan 03 12:37:38 PM PST 24
Finished Jan 03 12:38:54 PM PST 24
Peak memory 201244 kb
Host smart-7cf0c8fa-74a7-43a1-9b38-0dc8d9e73a35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657870807 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.clkmgr_shadow_reg_errors.657870807
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3676391171
Short name T36
Test name
Test status
Simulation time 75293731 ps
CPU time 2.21 seconds
Started Jan 03 12:37:52 PM PST 24
Finished Jan 03 12:39:16 PM PST 24
Peak memory 200976 kb
Host smart-e8eeba70-5b0e-448f-bedb-3d0d6d054f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676391171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.3676391171
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.3833579058
Short name T830
Test name
Test status
Simulation time 32202894086 ps
CPU time 492.1 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:13:18 PM PST 24
Peak memory 217436 kb
Host smart-eb5d09ee-375b-4c5e-b4a9-247b098fb80d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3833579058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.3833579058
Directory /workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2079968477
Short name T106
Test name
Test status
Simulation time 81070923 ps
CPU time 1.74 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:35 PM PST 24
Peak memory 200876 kb
Host smart-e241d191-c7ec-444e-93bc-8a25869f538b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079968477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.2079968477
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1671734816
Short name T31
Test name
Test status
Simulation time 1786958300 ps
CPU time 6.45 seconds
Started Jan 03 12:37:32 PM PST 24
Finished Jan 03 12:39:16 PM PST 24
Peak memory 201020 kb
Host smart-9a621ed9-671c-4255-a0e7-d0f847cfc194
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671734816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.1671734816
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3310132339
Short name T101
Test name
Test status
Simulation time 28856585 ps
CPU time 1.39 seconds
Started Jan 03 12:37:24 PM PST 24
Finished Jan 03 12:38:37 PM PST 24
Peak memory 200884 kb
Host smart-8db2cc98-6257-4574-9fae-fd6d026e95bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310132339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.3310132339
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.689661848
Short name T183
Test name
Test status
Simulation time 3598556154 ps
CPU time 14.11 seconds
Started Jan 03 12:38:46 PM PST 24
Finished Jan 03 12:40:18 PM PST 24
Peak memory 199992 kb
Host smart-1f64fefb-99e4-483f-bb81-4f8db1b4cf5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689661848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_bit_bash.689661848
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.3157129298
Short name T37
Test name
Test status
Simulation time 43405524 ps
CPU time 0.82 seconds
Started Jan 03 12:40:24 PM PST 24
Finished Jan 03 12:41:52 PM PST 24
Peak memory 200388 kb
Host smart-97c18bfc-0052-4481-9b8f-964589d3f0f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157129298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.3157129298
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.953298522
Short name T197
Test name
Test status
Simulation time 94453667 ps
CPU time 1.16 seconds
Started Jan 03 12:39:02 PM PST 24
Finished Jan 03 12:40:15 PM PST 24
Peak memory 199572 kb
Host smart-1bc0c006-b61d-495b-92fa-dde3c4836a5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953298522 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.953298522
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2098321073
Short name T277
Test name
Test status
Simulation time 24856323 ps
CPU time 0.87 seconds
Started Jan 03 12:37:29 PM PST 24
Finished Jan 03 12:38:51 PM PST 24
Peak memory 200620 kb
Host smart-8985b6e5-8fc8-444a-a469-6e0920344356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098321073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.2098321073
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1100870566
Short name T241
Test name
Test status
Simulation time 20284672 ps
CPU time 0.66 seconds
Started Jan 03 12:37:28 PM PST 24
Finished Jan 03 12:38:37 PM PST 24
Peak memory 199016 kb
Host smart-cc32fc7b-8810-41e0-9f4c-b28f84b966d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100870566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.1100870566
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.502068245
Short name T201
Test name
Test status
Simulation time 24107668 ps
CPU time 0.94 seconds
Started Jan 03 12:39:40 PM PST 24
Finished Jan 03 12:41:13 PM PST 24
Peak memory 200344 kb
Host smart-6ae9eb44-61f8-40e5-8543-208ede94ed18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502068245 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.clkmgr_same_csr_outstanding.502068245
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.2913544082
Short name T123
Test name
Test status
Simulation time 109095427 ps
CPU time 1.38 seconds
Started Jan 03 12:37:16 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 200920 kb
Host smart-47b630db-76e0-4c3e-ab84-7933cd48ca84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913544082 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.2913544082
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3118023871
Short name T76
Test name
Test status
Simulation time 538502768 ps
CPU time 3.62 seconds
Started Jan 03 12:37:10 PM PST 24
Finished Jan 03 12:38:20 PM PST 24
Peak memory 209356 kb
Host smart-7d007a73-e077-4e5c-8c5a-24e9e179814e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118023871 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.3118023871
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1879964451
Short name T235
Test name
Test status
Simulation time 43748794 ps
CPU time 2.5 seconds
Started Jan 03 12:37:13 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 200984 kb
Host smart-9c7858cb-c600-4801-b440-2e83ba55482e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879964451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.1879964451
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.2950565079
Short name T279
Test name
Test status
Simulation time 141524649 ps
CPU time 2.75 seconds
Started Jan 03 12:37:29 PM PST 24
Finished Jan 03 12:38:53 PM PST 24
Peak memory 200968 kb
Host smart-8fbcb66d-43d6-4359-b425-a4f413c9e85c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950565079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.2950565079
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1514434219
Short name T262
Test name
Test status
Simulation time 124581302 ps
CPU time 1.37 seconds
Started Jan 03 12:37:23 PM PST 24
Finished Jan 03 12:38:41 PM PST 24
Peak memory 200616 kb
Host smart-b08417ae-56d0-4c56-9f57-b82a70209bec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514434219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.1514434219
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.4135187270
Short name T263
Test name
Test status
Simulation time 215065935 ps
CPU time 4 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:38 PM PST 24
Peak memory 200748 kb
Host smart-3c3fb320-6b25-4dc4-b98d-99c2139e7fc4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135187270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.4135187270
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2265143088
Short name T188
Test name
Test status
Simulation time 170543094 ps
CPU time 1.12 seconds
Started Jan 03 12:37:10 PM PST 24
Finished Jan 03 12:38:18 PM PST 24
Peak memory 200588 kb
Host smart-be9585f5-bb53-4ba4-acde-ff967d4625e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265143088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.2265143088
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.456001136
Short name T286
Test name
Test status
Simulation time 25072399 ps
CPU time 1.03 seconds
Started Jan 03 12:37:06 PM PST 24
Finished Jan 03 12:38:13 PM PST 24
Peak memory 200736 kb
Host smart-2ccd289c-9ff1-4d21-a8f3-463b2ddfa654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456001136 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.456001136
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2363673543
Short name T203
Test name
Test status
Simulation time 25416424 ps
CPU time 0.76 seconds
Started Jan 03 12:37:37 PM PST 24
Finished Jan 03 12:38:47 PM PST 24
Peak memory 200600 kb
Host smart-0ac1a4d6-9084-4d32-8636-1079a8d8ba1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363673543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.2363673543
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.1831615025
Short name T247
Test name
Test status
Simulation time 49682869 ps
CPU time 0.71 seconds
Started Jan 03 12:37:44 PM PST 24
Finished Jan 03 12:38:58 PM PST 24
Peak memory 198956 kb
Host smart-a6f9437c-0c85-4d36-8b0c-48d160a1c9d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831615025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.1831615025
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3682154971
Short name T52
Test name
Test status
Simulation time 28326334 ps
CPU time 0.97 seconds
Started Jan 03 12:37:37 PM PST 24
Finished Jan 03 12:38:53 PM PST 24
Peak memory 200744 kb
Host smart-cf8ff32f-9876-4a2a-ad05-c2e116234409
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682154971 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.3682154971
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3419845602
Short name T126
Test name
Test status
Simulation time 263076080 ps
CPU time 2.2 seconds
Started Jan 03 12:39:20 PM PST 24
Finished Jan 03 12:40:46 PM PST 24
Peak memory 200804 kb
Host smart-c3c0ee63-cd0e-4289-8016-6fc8a26936bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419845602 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.3419845602
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.494001924
Short name T119
Test name
Test status
Simulation time 86807611 ps
CPU time 2.25 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:40 PM PST 24
Peak memory 201144 kb
Host smart-114c54d8-2950-4a00-9301-2e462ba060b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494001924 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.494001924
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3127962219
Short name T196
Test name
Test status
Simulation time 22989332 ps
CPU time 1.31 seconds
Started Jan 03 12:37:19 PM PST 24
Finished Jan 03 12:38:51 PM PST 24
Peak memory 200836 kb
Host smart-cc07ecc6-fb44-4ba5-ab0a-2361cb1ad5da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127962219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.3127962219
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3370808197
Short name T155
Test name
Test status
Simulation time 193673635 ps
CPU time 2.55 seconds
Started Jan 03 12:37:21 PM PST 24
Finished Jan 03 12:38:36 PM PST 24
Peak memory 201028 kb
Host smart-43aae203-e367-42fd-a93e-f78abc8aa589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370808197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.3370808197
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2391917093
Short name T193
Test name
Test status
Simulation time 70035568 ps
CPU time 1.33 seconds
Started Jan 03 12:37:36 PM PST 24
Finished Jan 03 12:39:06 PM PST 24
Peak memory 200744 kb
Host smart-c3d40792-912c-4451-ba03-8ce7c6535f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391917093 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.2391917093
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3280673947
Short name T232
Test name
Test status
Simulation time 20553669 ps
CPU time 0.86 seconds
Started Jan 03 12:37:50 PM PST 24
Finished Jan 03 12:39:02 PM PST 24
Peak memory 200588 kb
Host smart-6f84ded8-8e14-4f09-b647-c9b2d0f25892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280673947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.3280673947
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1041513152
Short name T173
Test name
Test status
Simulation time 39713503 ps
CPU time 0.71 seconds
Started Jan 03 12:37:55 PM PST 24
Finished Jan 03 12:39:11 PM PST 24
Peak memory 199112 kb
Host smart-ade6c736-ad46-4637-9f05-dc8607e8cd2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041513152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.1041513152
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.235423117
Short name T206
Test name
Test status
Simulation time 146875490 ps
CPU time 1.53 seconds
Started Jan 03 12:38:10 PM PST 24
Finished Jan 03 12:39:46 PM PST 24
Peak memory 200836 kb
Host smart-bc248599-1a9e-41bb-af5c-e070c6b1218e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235423117 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 10.clkmgr_same_csr_outstanding.235423117
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1455975904
Short name T33
Test name
Test status
Simulation time 126552214 ps
CPU time 1.6 seconds
Started Jan 03 12:37:39 PM PST 24
Finished Jan 03 12:38:52 PM PST 24
Peak memory 200940 kb
Host smart-20bd1010-b473-4618-b3ad-06f7e670ebfa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455975904 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.1455975904
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.329786910
Short name T229
Test name
Test status
Simulation time 245176315 ps
CPU time 2.15 seconds
Started Jan 03 12:37:45 PM PST 24
Finished Jan 03 12:39:12 PM PST 24
Peak memory 201216 kb
Host smart-4d289a92-58dd-40f7-9737-d6564739d053
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329786910 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.329786910
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2135715044
Short name T250
Test name
Test status
Simulation time 376590102 ps
CPU time 2.76 seconds
Started Jan 03 12:37:30 PM PST 24
Finished Jan 03 12:39:00 PM PST 24
Peak memory 200876 kb
Host smart-8964d58d-9de4-48ed-aad2-3ee25b4eb3bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135715044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.2135715044
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1771401648
Short name T280
Test name
Test status
Simulation time 16377704 ps
CPU time 0.8 seconds
Started Jan 03 12:37:32 PM PST 24
Finished Jan 03 12:38:46 PM PST 24
Peak memory 200676 kb
Host smart-41169b82-50ef-49d8-8cad-310f7359211a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771401648 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.1771401648
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3779201779
Short name T221
Test name
Test status
Simulation time 52491058 ps
CPU time 0.79 seconds
Started Jan 03 12:37:39 PM PST 24
Finished Jan 03 12:38:50 PM PST 24
Peak memory 200588 kb
Host smart-19179afd-8ef5-430a-beba-a9ac04387375
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779201779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.3779201779
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1538127153
Short name T186
Test name
Test status
Simulation time 12825089 ps
CPU time 0.66 seconds
Started Jan 03 12:37:30 PM PST 24
Finished Jan 03 12:38:49 PM PST 24
Peak memory 198984 kb
Host smart-9f00a7e2-2aea-48cd-a86e-c775cd84889b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538127153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.1538127153
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.65075686
Short name T268
Test name
Test status
Simulation time 394506825 ps
CPU time 3.17 seconds
Started Jan 03 12:37:41 PM PST 24
Finished Jan 03 12:38:58 PM PST 24
Peak memory 217404 kb
Host smart-ffbe70eb-fe1e-424a-a4b7-090a90585ba9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65075686 -assert nopostproc +UVM_TESTNAME=
clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.65075686
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3440536005
Short name T218
Test name
Test status
Simulation time 1091850737 ps
CPU time 4.51 seconds
Started Jan 03 12:37:31 PM PST 24
Finished Jan 03 12:38:44 PM PST 24
Peak memory 200944 kb
Host smart-80744b9c-8dcd-466a-a208-58ac35de3089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440536005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.3440536005
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1230431472
Short name T105
Test name
Test status
Simulation time 70279069 ps
CPU time 1.55 seconds
Started Jan 03 12:38:00 PM PST 24
Finished Jan 03 12:39:14 PM PST 24
Peak memory 200820 kb
Host smart-a93f9ce9-8499-4b39-9eb9-b4c9af925b31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230431472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.1230431472
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3549983082
Short name T252
Test name
Test status
Simulation time 29852349 ps
CPU time 0.87 seconds
Started Jan 03 12:37:29 PM PST 24
Finished Jan 03 12:38:51 PM PST 24
Peak memory 200400 kb
Host smart-0f023dff-b3fb-4734-a71a-5898221ad294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549983082 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.3549983082
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.530924206
Short name T287
Test name
Test status
Simulation time 21115959 ps
CPU time 0.8 seconds
Started Jan 03 12:37:34 PM PST 24
Finished Jan 03 12:38:45 PM PST 24
Peak memory 200572 kb
Host smart-710e7a87-3ee8-4f1f-9444-44add910f997
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530924206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
clkmgr_csr_rw.530924206
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3329581783
Short name T211
Test name
Test status
Simulation time 37633937 ps
CPU time 0.67 seconds
Started Jan 03 12:37:32 PM PST 24
Finished Jan 03 12:38:46 PM PST 24
Peak memory 199036 kb
Host smart-126a70e5-afc2-4dda-84e5-247b1c73c92e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329581783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.3329581783
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1588286292
Short name T230
Test name
Test status
Simulation time 27644713 ps
CPU time 0.92 seconds
Started Jan 03 12:37:19 PM PST 24
Finished Jan 03 12:38:50 PM PST 24
Peak memory 200644 kb
Host smart-15b1bc80-77d6-4d8d-b64b-aed8f0df48e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588286292 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.1588286292
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1870870116
Short name T75
Test name
Test status
Simulation time 52085769 ps
CPU time 1.21 seconds
Started Jan 03 12:37:36 PM PST 24
Finished Jan 03 12:39:01 PM PST 24
Peak memory 201056 kb
Host smart-3d271505-1005-4657-bb0b-346532ef5e03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870870116 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.1870870116
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1067903183
Short name T77
Test name
Test status
Simulation time 141394170 ps
CPU time 2.69 seconds
Started Jan 03 12:37:24 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 217484 kb
Host smart-df405808-0af9-4a7c-81eb-1d17410b4fbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067903183 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.1067903183
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.2096067447
Short name T283
Test name
Test status
Simulation time 25565414 ps
CPU time 1.35 seconds
Started Jan 03 12:37:24 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 200876 kb
Host smart-a480a489-6300-4dee-863a-3b71af4720e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096067447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.2096067447
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1165390321
Short name T110
Test name
Test status
Simulation time 565635504 ps
CPU time 3.45 seconds
Started Jan 03 12:37:46 PM PST 24
Finished Jan 03 12:39:00 PM PST 24
Peak memory 200988 kb
Host smart-5aad2a91-ecc2-49b2-956b-03bd6c656ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165390321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.1165390321
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.623099058
Short name T87
Test name
Test status
Simulation time 30467935 ps
CPU time 0.74 seconds
Started Jan 03 12:37:31 PM PST 24
Finished Jan 03 12:38:57 PM PST 24
Peak memory 200680 kb
Host smart-2060b7da-57f3-42c4-9cd3-e8dc6e285fb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623099058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
clkmgr_csr_rw.623099058
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2036475722
Short name T34
Test name
Test status
Simulation time 14709620 ps
CPU time 0.66 seconds
Started Jan 03 12:37:26 PM PST 24
Finished Jan 03 12:38:47 PM PST 24
Peak memory 199032 kb
Host smart-349dc3e7-2238-404d-b4ad-30f71c6c3204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036475722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.2036475722
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.1430242917
Short name T182
Test name
Test status
Simulation time 112190445 ps
CPU time 1.21 seconds
Started Jan 03 12:38:08 PM PST 24
Finished Jan 03 12:39:26 PM PST 24
Peak memory 200768 kb
Host smart-d9cee0ef-b783-42fd-b261-855927b0bc5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430242917 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.1430242917
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3951155777
Short name T122
Test name
Test status
Simulation time 101251503 ps
CPU time 1.6 seconds
Started Jan 03 12:38:08 PM PST 24
Finished Jan 03 12:39:37 PM PST 24
Peak memory 201264 kb
Host smart-161e54a6-3724-455c-9e16-9d54c8640a45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951155777 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.3951155777
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.199507815
Short name T244
Test name
Test status
Simulation time 139077630 ps
CPU time 1.76 seconds
Started Jan 03 12:37:40 PM PST 24
Finished Jan 03 12:38:56 PM PST 24
Peak memory 200916 kb
Host smart-36a1feaa-f93c-4a62-bfab-cf4c8d61d3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199507815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk
mgr_tl_errors.199507815
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2166765254
Short name T90
Test name
Test status
Simulation time 152332962 ps
CPU time 2.8 seconds
Started Jan 03 12:37:55 PM PST 24
Finished Jan 03 12:39:13 PM PST 24
Peak memory 200980 kb
Host smart-7b27511a-10e3-4f88-aa41-5bf3302dd60f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166765254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.2166765254
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3808700797
Short name T217
Test name
Test status
Simulation time 38937085 ps
CPU time 1.3 seconds
Started Jan 03 12:37:42 PM PST 24
Finished Jan 03 12:39:08 PM PST 24
Peak memory 200760 kb
Host smart-51fd5d35-c91f-4a38-9699-d52a5b8ce954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808700797 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.3808700797
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1191483559
Short name T88
Test name
Test status
Simulation time 57375241 ps
CPU time 0.94 seconds
Started Jan 03 12:37:17 PM PST 24
Finished Jan 03 12:38:28 PM PST 24
Peak memory 200580 kb
Host smart-83ec9993-c253-439a-a4d2-ac9bccf8c6e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191483559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.1191483559
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2322125506
Short name T274
Test name
Test status
Simulation time 14954825 ps
CPU time 0.67 seconds
Started Jan 03 12:37:47 PM PST 24
Finished Jan 03 12:39:11 PM PST 24
Peak memory 198976 kb
Host smart-d4b377b8-9c66-4a5f-b695-1354b954260e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322125506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.2322125506
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3051800941
Short name T55
Test name
Test status
Simulation time 257477136 ps
CPU time 1.78 seconds
Started Jan 03 12:37:51 PM PST 24
Finished Jan 03 12:39:03 PM PST 24
Peak memory 200856 kb
Host smart-8a76441c-0c75-450a-8569-d20213fb4a17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051800941 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.3051800941
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2948447808
Short name T127
Test name
Test status
Simulation time 52961290 ps
CPU time 1.2 seconds
Started Jan 03 12:38:00 PM PST 24
Finished Jan 03 12:39:14 PM PST 24
Peak memory 200996 kb
Host smart-8b2968cc-a6c4-4fe3-a073-7af683e4cedf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948447808 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.2948447808
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.678295776
Short name T223
Test name
Test status
Simulation time 484748758 ps
CPU time 3.24 seconds
Started Jan 03 12:37:28 PM PST 24
Finished Jan 03 12:38:40 PM PST 24
Peak memory 217576 kb
Host smart-26809014-14b8-409e-993b-6e4b4cf44589
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678295776 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.678295776
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2204596703
Short name T265
Test name
Test status
Simulation time 73438608 ps
CPU time 1.68 seconds
Started Jan 03 12:37:49 PM PST 24
Finished Jan 03 12:39:08 PM PST 24
Peak memory 201072 kb
Host smart-02cab7ba-6f64-4834-8b14-90d89db80970
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204596703 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.2204596703
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.232369668
Short name T184
Test name
Test status
Simulation time 51868857 ps
CPU time 0.81 seconds
Started Jan 03 12:37:27 PM PST 24
Finished Jan 03 12:38:42 PM PST 24
Peak memory 200676 kb
Host smart-fb9155eb-7ef9-4997-83df-a641a09c688e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232369668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
clkmgr_csr_rw.232369668
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3153471294
Short name T239
Test name
Test status
Simulation time 18162977 ps
CPU time 0.65 seconds
Started Jan 03 12:37:49 PM PST 24
Finished Jan 03 12:39:04 PM PST 24
Peak memory 199056 kb
Host smart-35b9e34d-2df5-4807-97d4-21e200639b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153471294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.3153471294
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.4182821319
Short name T212
Test name
Test status
Simulation time 114239367 ps
CPU time 1.22 seconds
Started Jan 03 12:37:21 PM PST 24
Finished Jan 03 12:38:35 PM PST 24
Peak memory 200732 kb
Host smart-db553e2b-b158-4b80-979a-6b886545ce1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182821319 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.4182821319
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.2758507484
Short name T80
Test name
Test status
Simulation time 153059583 ps
CPU time 2.53 seconds
Started Jan 03 12:37:42 PM PST 24
Finished Jan 03 12:39:06 PM PST 24
Peak memory 201140 kb
Host smart-ffe1cf00-8b32-4a3e-ba03-27414e0eb394
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758507484 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.2758507484
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.4245831199
Short name T278
Test name
Test status
Simulation time 94633459 ps
CPU time 1.87 seconds
Started Jan 03 12:37:32 PM PST 24
Finished Jan 03 12:39:12 PM PST 24
Peak memory 200976 kb
Host smart-0f00618f-8be3-4dbc-acea-6402dfa35c34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245831199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.4245831199
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2402315871
Short name T264
Test name
Test status
Simulation time 632772710 ps
CPU time 3.86 seconds
Started Jan 03 12:38:00 PM PST 24
Finished Jan 03 12:39:17 PM PST 24
Peak memory 200868 kb
Host smart-41f60bf1-e3ab-408e-9975-0ca527240204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402315871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.2402315871
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.546838996
Short name T237
Test name
Test status
Simulation time 19615895 ps
CPU time 0.8 seconds
Started Jan 03 12:38:10 PM PST 24
Finished Jan 03 12:39:28 PM PST 24
Peak memory 200564 kb
Host smart-9c7ab914-1296-4cb9-91f5-feeac225744d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546838996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
clkmgr_csr_rw.546838996
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3779689069
Short name T226
Test name
Test status
Simulation time 25010908 ps
CPU time 0.67 seconds
Started Jan 03 12:38:10 PM PST 24
Finished Jan 03 12:39:28 PM PST 24
Peak memory 198980 kb
Host smart-723a35cc-3cab-472a-be23-e7c207ca7855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779689069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.3779689069
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.480887513
Short name T134
Test name
Test status
Simulation time 228624053 ps
CPU time 1.44 seconds
Started Jan 03 12:38:03 PM PST 24
Finished Jan 03 12:39:21 PM PST 24
Peak memory 200712 kb
Host smart-b853c438-9012-4ed0-a1cf-2e8562d7fd1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480887513 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 16.clkmgr_same_csr_outstanding.480887513
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2392223969
Short name T240
Test name
Test status
Simulation time 181048997 ps
CPU time 2 seconds
Started Jan 03 12:37:17 PM PST 24
Finished Jan 03 12:38:33 PM PST 24
Peak memory 201092 kb
Host smart-23eeea37-2a95-444e-bff8-6876811e27a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392223969 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.2392223969
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1959378762
Short name T85
Test name
Test status
Simulation time 122643936 ps
CPU time 2.31 seconds
Started Jan 03 12:38:03 PM PST 24
Finished Jan 03 12:39:18 PM PST 24
Peak memory 201004 kb
Host smart-9adc0c29-4431-4ba4-93cb-e6eed26351ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959378762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.1959378762
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1985612672
Short name T6
Test name
Test status
Simulation time 209542097 ps
CPU time 2.38 seconds
Started Jan 03 12:37:42 PM PST 24
Finished Jan 03 12:39:06 PM PST 24
Peak memory 200976 kb
Host smart-cf3c70e6-c31c-455f-918b-1e26314a89ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985612672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.1985612672
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.989222470
Short name T224
Test name
Test status
Simulation time 86990218 ps
CPU time 1.18 seconds
Started Jan 03 12:37:45 PM PST 24
Finished Jan 03 12:38:57 PM PST 24
Peak memory 200824 kb
Host smart-4ccb302f-e0c5-4a39-a216-25e45a7ec079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989222470 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.989222470
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2874475921
Short name T207
Test name
Test status
Simulation time 132150264 ps
CPU time 1.05 seconds
Started Jan 03 12:37:34 PM PST 24
Finished Jan 03 12:38:45 PM PST 24
Peak memory 200644 kb
Host smart-2faef3f4-84b4-45c7-8462-c9bd71cfb853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874475921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.2874475921
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2591271868
Short name T256
Test name
Test status
Simulation time 13754976 ps
CPU time 0.64 seconds
Started Jan 03 12:37:35 PM PST 24
Finished Jan 03 12:38:57 PM PST 24
Peak memory 198996 kb
Host smart-132fc9f1-1c9b-4280-ab40-06ec5eb78675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591271868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.2591271868
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2919378099
Short name T53
Test name
Test status
Simulation time 187661619 ps
CPU time 1.6 seconds
Started Jan 03 12:39:56 PM PST 24
Finished Jan 03 12:41:35 PM PST 24
Peak memory 200500 kb
Host smart-621064bc-e070-47fe-9369-d5ad0e0c96df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919378099 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.2919378099
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3062289605
Short name T267
Test name
Test status
Simulation time 224728275 ps
CPU time 1.74 seconds
Started Jan 03 12:37:50 PM PST 24
Finished Jan 03 12:39:03 PM PST 24
Peak memory 201204 kb
Host smart-a889cad3-06f5-41b5-a9d2-db4f48ff31ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062289605 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.3062289605
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2465890198
Short name T121
Test name
Test status
Simulation time 313200177 ps
CPU time 3.33 seconds
Started Jan 03 12:37:46 PM PST 24
Finished Jan 03 12:39:04 PM PST 24
Peak memory 209284 kb
Host smart-2611673b-4ebd-4c1b-82b9-bcfc962c50bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465890198 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.2465890198
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3206120216
Short name T82
Test name
Test status
Simulation time 213367156 ps
CPU time 2.23 seconds
Started Jan 03 12:37:40 PM PST 24
Finished Jan 03 12:39:06 PM PST 24
Peak memory 200836 kb
Host smart-60aada36-206d-4056-8ae0-ecd61cffca97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206120216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.3206120216
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.436459441
Short name T48
Test name
Test status
Simulation time 29185114 ps
CPU time 1.05 seconds
Started Jan 03 12:38:02 PM PST 24
Finished Jan 03 12:39:20 PM PST 24
Peak memory 200724 kb
Host smart-1ad0119d-4df5-4226-ab44-754c4bc64f33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436459441 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.436459441
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2955164391
Short name T208
Test name
Test status
Simulation time 25012451 ps
CPU time 0.65 seconds
Started Jan 03 12:38:03 PM PST 24
Finished Jan 03 12:39:19 PM PST 24
Peak memory 199092 kb
Host smart-ef483c5d-1959-4e22-896e-457afd5899b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955164391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.2955164391
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1722718535
Short name T234
Test name
Test status
Simulation time 123413534 ps
CPU time 1.22 seconds
Started Jan 03 12:38:12 PM PST 24
Finished Jan 03 12:39:30 PM PST 24
Peak memory 200632 kb
Host smart-912d125f-1e41-4d34-a86f-dd865fe617ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722718535 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.1722718535
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.93673992
Short name T285
Test name
Test status
Simulation time 48979233 ps
CPU time 1.15 seconds
Started Jan 03 12:37:45 PM PST 24
Finished Jan 03 12:38:57 PM PST 24
Peak memory 200896 kb
Host smart-88ba1d13-d944-4e87-a785-7cb614018283
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93673992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_
test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.clkmgr_shadow_reg_errors.93673992
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1961409729
Short name T219
Test name
Test status
Simulation time 283828626 ps
CPU time 3.31 seconds
Started Jan 03 12:39:31 PM PST 24
Finished Jan 03 12:41:16 PM PST 24
Peak memory 200956 kb
Host smart-6d3be01d-eee7-4dce-8150-f893edf55a15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961409729 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.1961409729
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3750691581
Short name T190
Test name
Test status
Simulation time 87727963 ps
CPU time 2.58 seconds
Started Jan 03 12:38:12 PM PST 24
Finished Jan 03 12:39:28 PM PST 24
Peak memory 201012 kb
Host smart-d68620c5-7d0c-48ef-8ff4-c0364bb3a4d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750691581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.3750691581
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3917532898
Short name T91
Test name
Test status
Simulation time 103748536 ps
CPU time 1.81 seconds
Started Jan 03 12:38:12 PM PST 24
Finished Jan 03 12:39:27 PM PST 24
Peak memory 200872 kb
Host smart-bc24c402-3273-4f48-87b6-557dd8a7dd33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917532898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.3917532898
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3849344101
Short name T166
Test name
Test status
Simulation time 22503753 ps
CPU time 1.05 seconds
Started Jan 03 12:37:35 PM PST 24
Finished Jan 03 12:38:50 PM PST 24
Peak memory 200756 kb
Host smart-cf4ca73f-b397-4238-bb22-6c1708fb4501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849344101 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3849344101
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.432649809
Short name T205
Test name
Test status
Simulation time 61014269 ps
CPU time 0.97 seconds
Started Jan 03 12:39:54 PM PST 24
Finished Jan 03 12:41:52 PM PST 24
Peak memory 200620 kb
Host smart-f3d980bc-8ea4-4b57-83da-1d9f6323da18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432649809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
clkmgr_csr_rw.432649809
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.205743353
Short name T281
Test name
Test status
Simulation time 45016121 ps
CPU time 0.68 seconds
Started Jan 03 12:37:55 PM PST 24
Finished Jan 03 12:39:09 PM PST 24
Peak memory 199124 kb
Host smart-d663cbe4-da1f-4dda-b4e9-24ae0fffd6f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205743353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk
mgr_intr_test.205743353
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3944692797
Short name T288
Test name
Test status
Simulation time 56654461 ps
CPU time 1.29 seconds
Started Jan 03 12:37:34 PM PST 24
Finished Jan 03 12:38:46 PM PST 24
Peak memory 200820 kb
Host smart-888a0f11-f278-476e-994e-14b1f64f027c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944692797 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.3944692797
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.549386795
Short name T233
Test name
Test status
Simulation time 68298214 ps
CPU time 1.31 seconds
Started Jan 03 12:37:51 PM PST 24
Finished Jan 03 12:39:03 PM PST 24
Peak memory 200848 kb
Host smart-c2bf1930-6596-4931-b8da-563931e87761
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549386795 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.clkmgr_shadow_reg_errors.549386795
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2662088511
Short name T131
Test name
Test status
Simulation time 124180496 ps
CPU time 1.77 seconds
Started Jan 03 12:37:57 PM PST 24
Finished Jan 03 12:39:15 PM PST 24
Peak memory 209432 kb
Host smart-4ceca49b-39b7-4478-9e9d-9b58abdfe7f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662088511 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2662088511
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.3440320837
Short name T243
Test name
Test status
Simulation time 409587585 ps
CPU time 3.75 seconds
Started Jan 03 12:38:01 PM PST 24
Finished Jan 03 12:39:20 PM PST 24
Peak memory 200948 kb
Host smart-780ea481-7bab-4433-9198-276914acfc45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440320837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.3440320837
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.4109902786
Short name T83
Test name
Test status
Simulation time 265977069 ps
CPU time 2.13 seconds
Started Jan 03 12:37:58 PM PST 24
Finished Jan 03 12:39:15 PM PST 24
Peak memory 200988 kb
Host smart-59f2058c-d196-4857-98bf-4a7d8be42304
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109902786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.4109902786
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3408252281
Short name T98
Test name
Test status
Simulation time 20747584 ps
CPU time 1.06 seconds
Started Jan 03 12:38:07 PM PST 24
Finished Jan 03 12:39:25 PM PST 24
Peak memory 200584 kb
Host smart-e2cadb4b-b916-435a-9d03-97811ec739d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408252281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.3408252281
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3854747275
Short name T180
Test name
Test status
Simulation time 6794732417 ps
CPU time 22.11 seconds
Started Jan 03 12:37:09 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 200936 kb
Host smart-59a1b892-f599-4249-bf35-9f2b5ef02935
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854747275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.3854747275
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1769347581
Short name T187
Test name
Test status
Simulation time 42577712 ps
CPU time 0.82 seconds
Started Jan 03 12:37:43 PM PST 24
Finished Jan 03 12:38:58 PM PST 24
Peak memory 200588 kb
Host smart-9bbbf8dc-3a03-41f6-81d2-bc876d48fd16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769347581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.1769347581
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2282855743
Short name T99
Test name
Test status
Simulation time 17132760 ps
CPU time 0.76 seconds
Started Jan 03 12:37:18 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 200692 kb
Host smart-346c2722-86d0-4357-a9dd-1cd6ae0b9174
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282855743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.2282855743
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3249271145
Short name T185
Test name
Test status
Simulation time 23719450 ps
CPU time 0.65 seconds
Started Jan 03 12:37:27 PM PST 24
Finished Jan 03 12:38:37 PM PST 24
Peak memory 199048 kb
Host smart-a3347fc2-3dc2-4f10-acc4-f5537080e977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249271145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.3249271145
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1041554472
Short name T120
Test name
Test status
Simulation time 122850784 ps
CPU time 1.33 seconds
Started Jan 03 12:37:32 PM PST 24
Finished Jan 03 12:38:47 PM PST 24
Peak memory 200972 kb
Host smart-52c4543a-d510-4d23-b21f-9f3335a7d25e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041554472 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.1041554472
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3276667926
Short name T231
Test name
Test status
Simulation time 84038028 ps
CPU time 1.68 seconds
Started Jan 03 12:37:27 PM PST 24
Finished Jan 03 12:38:38 PM PST 24
Peak memory 201272 kb
Host smart-30ac5247-777b-48b7-9aa4-a4c2afc66f44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276667926 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.3276667926
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.518778494
Short name T215
Test name
Test status
Simulation time 99560155 ps
CPU time 2.8 seconds
Started Jan 03 12:37:21 PM PST 24
Finished Jan 03 12:38:37 PM PST 24
Peak memory 200924 kb
Host smart-f0d5e50a-20ce-43c7-89ea-f6f7ab221f60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518778494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_tl_errors.518778494
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3405081197
Short name T104
Test name
Test status
Simulation time 120734021 ps
CPU time 2.38 seconds
Started Jan 03 12:39:34 PM PST 24
Finished Jan 03 12:41:07 PM PST 24
Peak memory 200528 kb
Host smart-a2b8eadf-dc7d-4ed3-98ba-30560a68bfed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405081197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.3405081197
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.3168661793
Short name T191
Test name
Test status
Simulation time 29812917 ps
CPU time 0.69 seconds
Started Jan 03 12:38:11 PM PST 24
Finished Jan 03 12:39:30 PM PST 24
Peak memory 199028 kb
Host smart-23fb4f62-880d-4842-b1b0-6aa39e97a631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168661793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.3168661793
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3861192428
Short name T169
Test name
Test status
Simulation time 12305278 ps
CPU time 0.68 seconds
Started Jan 03 12:37:45 PM PST 24
Finished Jan 03 12:38:57 PM PST 24
Peak memory 199056 kb
Host smart-ecbb664a-8ade-45ff-a6b6-84159ffe58df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861192428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.3861192428
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.2344810240
Short name T170
Test name
Test status
Simulation time 26266352 ps
CPU time 0.72 seconds
Started Jan 03 12:37:42 PM PST 24
Finished Jan 03 12:39:08 PM PST 24
Peak memory 198984 kb
Host smart-69a3e305-e84d-49f9-b731-816edf95b7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344810240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.2344810240
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3969332274
Short name T168
Test name
Test status
Simulation time 13019883 ps
CPU time 0.66 seconds
Started Jan 03 12:38:05 PM PST 24
Finished Jan 03 12:39:22 PM PST 24
Peak memory 199092 kb
Host smart-a88dbc9d-9d75-42f2-905f-e444a3763521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969332274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.3969332274
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.680411293
Short name T276
Test name
Test status
Simulation time 25722762 ps
CPU time 0.65 seconds
Started Jan 03 12:37:54 PM PST 24
Finished Jan 03 12:39:11 PM PST 24
Peak memory 199028 kb
Host smart-8b0155f8-9a73-42e0-8f85-047357ba1266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680411293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clk
mgr_intr_test.680411293
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.3154921639
Short name T7
Test name
Test status
Simulation time 16800778 ps
CPU time 0.64 seconds
Started Jan 03 12:37:39 PM PST 24
Finished Jan 03 12:39:03 PM PST 24
Peak memory 199068 kb
Host smart-1a771697-8b8d-4a71-9f12-85fb28ee7c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154921639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.3154921639
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3762983639
Short name T181
Test name
Test status
Simulation time 13870279 ps
CPU time 0.68 seconds
Started Jan 03 12:38:13 PM PST 24
Finished Jan 03 12:39:36 PM PST 24
Peak memory 198976 kb
Host smart-6936483a-1b9b-4169-bcc7-546059895044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762983639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.3762983639
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1826327424
Short name T270
Test name
Test status
Simulation time 12212631 ps
CPU time 0.63 seconds
Started Jan 03 12:37:48 PM PST 24
Finished Jan 03 12:39:06 PM PST 24
Peak memory 199048 kb
Host smart-1ff48150-270e-4d04-9aaf-b0e3f68a3d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826327424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.1826327424
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1900216504
Short name T167
Test name
Test status
Simulation time 41142005 ps
CPU time 0.71 seconds
Started Jan 03 12:38:07 PM PST 24
Finished Jan 03 12:39:25 PM PST 24
Peak memory 199056 kb
Host smart-791124ea-df98-4f63-abd9-c4261fde249d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900216504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.1900216504
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2772762219
Short name T176
Test name
Test status
Simulation time 13286156 ps
CPU time 0.65 seconds
Started Jan 03 12:38:03 PM PST 24
Finished Jan 03 12:39:16 PM PST 24
Peak memory 199096 kb
Host smart-88576fff-783a-4be5-988e-d31a633d427f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772762219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.2772762219
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3019773956
Short name T100
Test name
Test status
Simulation time 294736325 ps
CPU time 2.26 seconds
Started Jan 03 12:38:52 PM PST 24
Finished Jan 03 12:40:01 PM PST 24
Peak memory 199080 kb
Host smart-a5136e60-f509-42ec-9247-94e9db7471e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019773956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.3019773956
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2886066278
Short name T96
Test name
Test status
Simulation time 263218812 ps
CPU time 6.46 seconds
Started Jan 03 12:37:26 PM PST 24
Finished Jan 03 12:38:53 PM PST 24
Peak memory 200736 kb
Host smart-ed642793-5928-402f-b111-d5c754f880cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886066278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.2886066278
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.851842447
Short name T50
Test name
Test status
Simulation time 140277375 ps
CPU time 1.37 seconds
Started Jan 03 12:37:21 PM PST 24
Finished Jan 03 12:38:31 PM PST 24
Peak memory 200796 kb
Host smart-e7b72595-1457-4884-b68c-9e8b6c046167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851842447 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.851842447
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1741181953
Short name T210
Test name
Test status
Simulation time 21720104 ps
CPU time 0.81 seconds
Started Jan 03 12:37:24 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 200596 kb
Host smart-bb85f8c8-6828-4f08-823d-4a3792e6d565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741181953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.1741181953
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.278594100
Short name T179
Test name
Test status
Simulation time 24195830 ps
CPU time 0.68 seconds
Started Jan 03 12:37:47 PM PST 24
Finished Jan 03 12:39:07 PM PST 24
Peak memory 199088 kb
Host smart-ce82006a-953b-4146-b657-b7964c6c969e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278594100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkm
gr_intr_test.278594100
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3535797656
Short name T51
Test name
Test status
Simulation time 36381936 ps
CPU time 1.04 seconds
Started Jan 03 12:37:20 PM PST 24
Finished Jan 03 12:38:31 PM PST 24
Peak memory 200624 kb
Host smart-1d8f480a-8213-4537-aae9-11c8d60f1869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535797656 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.3535797656
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3640978584
Short name T94
Test name
Test status
Simulation time 210245313 ps
CPU time 1.72 seconds
Started Jan 03 12:37:21 PM PST 24
Finished Jan 03 12:38:36 PM PST 24
Peak memory 201004 kb
Host smart-31c21d4b-dd3c-48b4-b333-8aff197738d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640978584 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.3640978584
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.536576729
Short name T79
Test name
Test status
Simulation time 152364002 ps
CPU time 1.72 seconds
Started Jan 03 12:37:50 PM PST 24
Finished Jan 03 12:39:03 PM PST 24
Peak memory 217576 kb
Host smart-d57327c6-7438-4eee-9b89-8c7a303d9741
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536576729 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.536576729
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1627129975
Short name T202
Test name
Test status
Simulation time 188437814 ps
CPU time 1.87 seconds
Started Jan 03 12:39:45 PM PST 24
Finished Jan 03 12:41:18 PM PST 24
Peak memory 200500 kb
Host smart-b25d2cca-bc04-4ff6-9ccc-cc303ce10e34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627129975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.1627129975
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.152533347
Short name T227
Test name
Test status
Simulation time 102207022 ps
CPU time 2.19 seconds
Started Jan 03 12:37:14 PM PST 24
Finished Jan 03 12:38:25 PM PST 24
Peak memory 200880 kb
Host smart-3c3b2380-8e86-4940-a2d3-060bcd2e4745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152533347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.clkmgr_tl_intg_err.152533347
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.1168699534
Short name T275
Test name
Test status
Simulation time 26005184 ps
CPU time 0.65 seconds
Started Jan 03 12:37:37 PM PST 24
Finished Jan 03 12:38:52 PM PST 24
Peak memory 199044 kb
Host smart-e3bd3214-f4fb-4159-bd2a-6d0d1d1dc9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168699534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.1168699534
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3095476618
Short name T129
Test name
Test status
Simulation time 23862074 ps
CPU time 0.64 seconds
Started Jan 03 12:40:09 PM PST 24
Finished Jan 03 12:41:34 PM PST 24
Peak memory 198716 kb
Host smart-23448f15-d67a-4110-89d5-af5719286af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095476618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.3095476618
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.369659880
Short name T269
Test name
Test status
Simulation time 37782847 ps
CPU time 0.67 seconds
Started Jan 03 12:39:49 PM PST 24
Finished Jan 03 12:41:16 PM PST 24
Peak memory 198628 kb
Host smart-4e246e6e-05cd-40f1-bebc-14c1d771eb0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369659880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clk
mgr_intr_test.369659880
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1721786034
Short name T189
Test name
Test status
Simulation time 22979620 ps
CPU time 0.67 seconds
Started Jan 03 12:37:45 PM PST 24
Finished Jan 03 12:39:08 PM PST 24
Peak memory 199036 kb
Host smart-9570eb8d-fe65-47c4-8bed-e07f81ef490e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721786034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.1721786034
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.3689466025
Short name T271
Test name
Test status
Simulation time 13883432 ps
CPU time 0.69 seconds
Started Jan 03 12:39:02 PM PST 24
Finished Jan 03 12:40:14 PM PST 24
Peak memory 197664 kb
Host smart-8758a4eb-6273-4a21-a4c5-9bb89d1f60fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689466025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.3689466025
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2555599649
Short name T174
Test name
Test status
Simulation time 23361004 ps
CPU time 0.65 seconds
Started Jan 03 12:39:04 PM PST 24
Finished Jan 03 12:40:39 PM PST 24
Peak memory 198460 kb
Host smart-1af3ac26-2a22-4dcb-9e4a-e889615fd586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555599649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.2555599649
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.2205127076
Short name T273
Test name
Test status
Simulation time 12348375 ps
CPU time 0.68 seconds
Started Jan 03 12:37:55 PM PST 24
Finished Jan 03 12:39:08 PM PST 24
Peak memory 199068 kb
Host smart-5f8b81c0-24a7-4099-9273-d620075c474a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205127076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.2205127076
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1223521006
Short name T222
Test name
Test status
Simulation time 19818060 ps
CPU time 0.66 seconds
Started Jan 03 12:39:51 PM PST 24
Finished Jan 03 12:41:56 PM PST 24
Peak memory 198652 kb
Host smart-4f524b16-56d9-4eed-a7f9-6f5ea6880e25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223521006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.1223521006
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.3201806063
Short name T209
Test name
Test status
Simulation time 27814889 ps
CPU time 0.67 seconds
Started Jan 03 12:37:37 PM PST 24
Finished Jan 03 12:38:49 PM PST 24
Peak memory 198972 kb
Host smart-5792f1e4-6098-42d1-b879-41e174fe6efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201806063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.3201806063
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.579879014
Short name T259
Test name
Test status
Simulation time 78134499 ps
CPU time 0.77 seconds
Started Jan 03 12:39:44 PM PST 24
Finished Jan 03 12:41:11 PM PST 24
Peak memory 198644 kb
Host smart-94ed0a4f-be6c-433b-864a-de0c8b2062f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579879014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clk
mgr_intr_test.579879014
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3468806082
Short name T214
Test name
Test status
Simulation time 50736610 ps
CPU time 1.15 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:55 PM PST 24
Peak memory 200608 kb
Host smart-614bbac3-72a1-48c5-b1ea-1fef15a8f891
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468806082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.3468806082
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1226930315
Short name T194
Test name
Test status
Simulation time 491661180 ps
CPU time 4.73 seconds
Started Jan 03 12:38:52 PM PST 24
Finished Jan 03 12:40:03 PM PST 24
Peak memory 199132 kb
Host smart-072e648e-c4bb-4680-a01a-723faac93c05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226930315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.1226930315
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1956204693
Short name T258
Test name
Test status
Simulation time 32667910 ps
CPU time 0.76 seconds
Started Jan 03 12:37:25 PM PST 24
Finished Jan 03 12:38:38 PM PST 24
Peak memory 200680 kb
Host smart-a82f4919-aef8-4203-92f3-b80af21f376a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956204693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.1956204693
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2184955417
Short name T266
Test name
Test status
Simulation time 97860945 ps
CPU time 1.15 seconds
Started Jan 03 12:37:06 PM PST 24
Finished Jan 03 12:38:13 PM PST 24
Peak memory 200812 kb
Host smart-690311df-6abb-440d-b13e-0669d8d7f55b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184955417 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.2184955417
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1415109345
Short name T284
Test name
Test status
Simulation time 21623081 ps
CPU time 0.84 seconds
Started Jan 03 12:37:13 PM PST 24
Finished Jan 03 12:38:25 PM PST 24
Peak memory 200580 kb
Host smart-4c88de03-b72e-48dc-a196-ff3e142771b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415109345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.1415109345
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1563654766
Short name T198
Test name
Test status
Simulation time 40908694 ps
CPU time 0.71 seconds
Started Jan 03 12:37:28 PM PST 24
Finished Jan 03 12:38:55 PM PST 24
Peak memory 199076 kb
Host smart-85a07919-e2fa-4303-a9a6-f937c315ed94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563654766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.1563654766
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2749790197
Short name T95
Test name
Test status
Simulation time 367315351 ps
CPU time 2.45 seconds
Started Jan 03 12:39:22 PM PST 24
Finished Jan 03 12:40:51 PM PST 24
Peak memory 200824 kb
Host smart-3f75d9bb-75c5-402c-bbbf-aae23c966348
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749790197 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.2749790197
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2246568122
Short name T251
Test name
Test status
Simulation time 744644076 ps
CPU time 3.34 seconds
Started Jan 03 12:37:26 PM PST 24
Finished Jan 03 12:39:03 PM PST 24
Peak memory 209316 kb
Host smart-5303bb5f-f5b9-4e42-ac57-7aa376a37772
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246568122 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.2246568122
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3408639688
Short name T86
Test name
Test status
Simulation time 54306229 ps
CPU time 1.49 seconds
Started Jan 03 12:39:24 PM PST 24
Finished Jan 03 12:41:05 PM PST 24
Peak memory 200596 kb
Host smart-29675bd4-f7e7-42eb-8c06-a97e7bbfe0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408639688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.3408639688
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.688626848
Short name T109
Test name
Test status
Simulation time 74751215 ps
CPU time 1.45 seconds
Started Jan 03 12:39:17 PM PST 24
Finished Jan 03 12:40:43 PM PST 24
Peak memory 200512 kb
Host smart-30018712-b306-4a9b-b4aa-f8ade8f62ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688626848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.clkmgr_tl_intg_err.688626848
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3297553476
Short name T172
Test name
Test status
Simulation time 14226156 ps
CPU time 0.77 seconds
Started Jan 03 12:39:04 PM PST 24
Finished Jan 03 12:40:39 PM PST 24
Peak memory 198360 kb
Host smart-1af998c0-3e4e-416e-bda0-6bbced416d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297553476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.3297553476
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.1435033502
Short name T236
Test name
Test status
Simulation time 12781637 ps
CPU time 0.65 seconds
Started Jan 03 12:37:48 PM PST 24
Finished Jan 03 12:39:00 PM PST 24
Peak memory 199000 kb
Host smart-44605f6e-6d71-48b6-b6aa-286e613f489c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435033502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.1435033502
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2989513237
Short name T213
Test name
Test status
Simulation time 20312042 ps
CPU time 0.63 seconds
Started Jan 03 12:38:14 PM PST 24
Finished Jan 03 12:39:36 PM PST 24
Peak memory 199152 kb
Host smart-61bf60ad-356a-47f0-81a8-8e80f14b1392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989513237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.2989513237
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1749335634
Short name T282
Test name
Test status
Simulation time 12327036 ps
CPU time 0.64 seconds
Started Jan 03 12:37:44 PM PST 24
Finished Jan 03 12:39:03 PM PST 24
Peak memory 198968 kb
Host smart-73cfbe37-3e13-4490-b362-6014de20318a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749335634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.1749335634
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1532539253
Short name T175
Test name
Test status
Simulation time 44840070 ps
CPU time 0.72 seconds
Started Jan 03 12:37:42 PM PST 24
Finished Jan 03 12:38:59 PM PST 24
Peak memory 199120 kb
Host smart-79f77e32-e04b-4838-9b7b-9ef26900a1e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532539253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.1532539253
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2057290753
Short name T177
Test name
Test status
Simulation time 39311395 ps
CPU time 0.74 seconds
Started Jan 03 12:37:39 PM PST 24
Finished Jan 03 12:39:03 PM PST 24
Peak memory 199068 kb
Host smart-982d1f91-ff90-4eca-9f4d-a5af9c47fc17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057290753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.2057290753
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.562019623
Short name T178
Test name
Test status
Simulation time 38915524 ps
CPU time 0.77 seconds
Started Jan 03 12:38:52 PM PST 24
Finished Jan 03 12:40:00 PM PST 24
Peak memory 198104 kb
Host smart-2e9add76-595b-496b-b68f-2c1041edad3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562019623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clk
mgr_intr_test.562019623
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.985660000
Short name T260
Test name
Test status
Simulation time 12914574 ps
CPU time 0.74 seconds
Started Jan 03 12:38:52 PM PST 24
Finished Jan 03 12:40:00 PM PST 24
Peak memory 197816 kb
Host smart-1830c6d3-1059-44b0-b7e7-003286685389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985660000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clk
mgr_intr_test.985660000
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.3000547115
Short name T225
Test name
Test status
Simulation time 25247025 ps
CPU time 0.66 seconds
Started Jan 03 12:38:09 PM PST 24
Finished Jan 03 12:39:28 PM PST 24
Peak memory 199048 kb
Host smart-30222f54-8b1d-43ad-9ec1-3601d62fbb6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000547115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.3000547115
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2139539286
Short name T162
Test name
Test status
Simulation time 23371865 ps
CPU time 0.9 seconds
Started Jan 03 12:37:13 PM PST 24
Finished Jan 03 12:38:43 PM PST 24
Peak memory 200756 kb
Host smart-c6369854-7d74-43af-9656-3bb5a80544ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139539286 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.2139539286
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3101866930
Short name T192
Test name
Test status
Simulation time 16274347 ps
CPU time 0.75 seconds
Started Jan 03 12:37:29 PM PST 24
Finished Jan 03 12:38:42 PM PST 24
Peak memory 200596 kb
Host smart-5d90c4de-1a87-4d87-81af-938911549d3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101866930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.3101866930
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.622155883
Short name T171
Test name
Test status
Simulation time 14205622 ps
CPU time 0.62 seconds
Started Jan 03 12:40:08 PM PST 24
Finished Jan 03 12:41:31 PM PST 24
Peak memory 198696 kb
Host smart-563fd482-733b-4f86-a961-6ceceb327748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622155883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm
gr_intr_test.622155883
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.4122917181
Short name T242
Test name
Test status
Simulation time 307801818 ps
CPU time 1.84 seconds
Started Jan 03 12:37:28 PM PST 24
Finished Jan 03 12:38:38 PM PST 24
Peak memory 200848 kb
Host smart-ed12d157-168c-49bf-8b5c-c94572e500e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122917181 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.4122917181
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1203321407
Short name T32
Test name
Test status
Simulation time 69550868 ps
CPU time 1.41 seconds
Started Jan 03 12:39:33 PM PST 24
Finished Jan 03 12:41:06 PM PST 24
Peak memory 200540 kb
Host smart-3b89ff73-2fa0-470f-98bf-7dbb090e3ce3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203321407 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.1203321407
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.735241826
Short name T228
Test name
Test status
Simulation time 236965376 ps
CPU time 2.1 seconds
Started Jan 03 12:39:44 PM PST 24
Finished Jan 03 12:41:07 PM PST 24
Peak memory 200868 kb
Host smart-2b172fd9-df9a-4856-9452-5668d188c096
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735241826 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.735241826
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1445957798
Short name T84
Test name
Test status
Simulation time 207630785 ps
CPU time 2.16 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:37 PM PST 24
Peak memory 200828 kb
Host smart-fdc24332-72be-42ca-8ac6-411e39cc3a81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445957798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.1445957798
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.450355308
Short name T89
Test name
Test status
Simulation time 57224601 ps
CPU time 1.55 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:36 PM PST 24
Peak memory 200948 kb
Host smart-62033584-4a6c-445f-87b7-77f5e6c430cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450355308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.clkmgr_tl_intg_err.450355308
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2903053427
Short name T255
Test name
Test status
Simulation time 17421768 ps
CPU time 0.81 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:39:08 PM PST 24
Peak memory 200800 kb
Host smart-b689f3e0-d000-43c9-9ce1-3a7d7bc3f88f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903053427 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.2903053427
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2708052903
Short name T200
Test name
Test status
Simulation time 33017679 ps
CPU time 0.77 seconds
Started Jan 03 12:37:51 PM PST 24
Finished Jan 03 12:39:06 PM PST 24
Peak memory 200556 kb
Host smart-ed1eb9ba-0ff5-4f31-a768-5fb4aaf32358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708052903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.2708052903
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3048186450
Short name T272
Test name
Test status
Simulation time 20803612 ps
CPU time 0.65 seconds
Started Jan 03 12:37:45 PM PST 24
Finished Jan 03 12:39:10 PM PST 24
Peak memory 199060 kb
Host smart-53020e21-4739-46b7-96d3-25dcc3cdd94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048186450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.3048186450
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1642193854
Short name T54
Test name
Test status
Simulation time 218310428 ps
CPU time 1.71 seconds
Started Jan 03 12:37:47 PM PST 24
Finished Jan 03 12:39:07 PM PST 24
Peak memory 200912 kb
Host smart-305a719e-2e34-4ea1-a221-8560eef35c2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642193854 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.1642193854
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2792631990
Short name T128
Test name
Test status
Simulation time 221097499 ps
CPU time 1.87 seconds
Started Jan 03 12:37:11 PM PST 24
Finished Jan 03 12:38:26 PM PST 24
Peak memory 201128 kb
Host smart-942d029a-bd96-4f3f-a25c-3ee719260f82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792631990 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.2792631990
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.904980673
Short name T204
Test name
Test status
Simulation time 50794075 ps
CPU time 1.47 seconds
Started Jan 03 12:37:32 PM PST 24
Finished Jan 03 12:39:04 PM PST 24
Peak memory 201232 kb
Host smart-8b31f11a-6c34-4bd4-9f09-9b62d721eafd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904980673 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.904980673
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2949568427
Short name T248
Test name
Test status
Simulation time 50981594 ps
CPU time 1.46 seconds
Started Jan 03 12:37:24 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 200860 kb
Host smart-74893eb4-ed69-4481-a8e9-6a0cd8784f17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949568427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.2949568427
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.4107123653
Short name T132
Test name
Test status
Simulation time 75546015 ps
CPU time 1.05 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:36 PM PST 24
Peak memory 200720 kb
Host smart-e6ca548d-b795-4b9d-9138-7b7e14653cb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107123653 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.4107123653
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.4233986731
Short name T216
Test name
Test status
Simulation time 49883070 ps
CPU time 0.85 seconds
Started Jan 03 12:37:25 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 200600 kb
Host smart-6eeea39b-c32e-49e5-bef2-56f125a05cf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233986731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.4233986731
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3236323219
Short name T253
Test name
Test status
Simulation time 23458830 ps
CPU time 0.66 seconds
Started Jan 03 12:37:21 PM PST 24
Finished Jan 03 12:38:30 PM PST 24
Peak memory 199084 kb
Host smart-ad59467f-1e0b-45ab-b879-f258850f398b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236323219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.3236323219
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2122950873
Short name T246
Test name
Test status
Simulation time 42747639 ps
CPU time 0.98 seconds
Started Jan 03 12:37:48 PM PST 24
Finished Jan 03 12:39:04 PM PST 24
Peak memory 200664 kb
Host smart-cab1e321-7221-432b-af6a-142a33ed530e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122950873 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.2122950873
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1071200309
Short name T254
Test name
Test status
Simulation time 54428980 ps
CPU time 1.33 seconds
Started Jan 03 12:37:36 PM PST 24
Finished Jan 03 12:38:49 PM PST 24
Peak memory 200952 kb
Host smart-abc85a10-afd8-4169-98c3-021788d3666d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071200309 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.1071200309
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2376122908
Short name T220
Test name
Test status
Simulation time 124607701 ps
CPU time 1.95 seconds
Started Jan 03 12:37:23 PM PST 24
Finished Jan 03 12:38:41 PM PST 24
Peak memory 201224 kb
Host smart-d9b556cf-7ac8-4dbc-b31d-f5f55f1577f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376122908 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.2376122908
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1127618416
Short name T245
Test name
Test status
Simulation time 64362538 ps
CPU time 2.03 seconds
Started Jan 03 12:37:47 PM PST 24
Finished Jan 03 12:39:12 PM PST 24
Peak memory 200876 kb
Host smart-6334f4fc-68a7-477e-8d7d-75ce80e83a98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127618416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.1127618416
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.290309377
Short name T92
Test name
Test status
Simulation time 385902528 ps
CPU time 2.27 seconds
Started Jan 03 12:37:51 PM PST 24
Finished Jan 03 12:39:07 PM PST 24
Peak memory 200896 kb
Host smart-74907567-7ffe-4797-b44e-f2cb72fb2edc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290309377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.clkmgr_tl_intg_err.290309377
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.4254519766
Short name T159
Test name
Test status
Simulation time 162690190 ps
CPU time 1.41 seconds
Started Jan 03 12:37:33 PM PST 24
Finished Jan 03 12:38:50 PM PST 24
Peak memory 200840 kb
Host smart-8f756eb4-8766-48f0-adcc-6b4e43d6408f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254519766 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.4254519766
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3006707464
Short name T238
Test name
Test status
Simulation time 26782606 ps
CPU time 0.8 seconds
Started Jan 03 12:37:45 PM PST 24
Finished Jan 03 12:39:17 PM PST 24
Peak memory 200676 kb
Host smart-39353c44-2a66-4058-bccd-7c36d9003d01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006707464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.3006707464
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1518689787
Short name T195
Test name
Test status
Simulation time 14434081 ps
CPU time 0.67 seconds
Started Jan 03 12:37:30 PM PST 24
Finished Jan 03 12:38:57 PM PST 24
Peak memory 199040 kb
Host smart-5ed4dc1a-f09c-4087-99a5-795330960674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518689787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.1518689787
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.4154147520
Short name T257
Test name
Test status
Simulation time 199273824 ps
CPU time 1.7 seconds
Started Jan 03 12:37:41 PM PST 24
Finished Jan 03 12:39:06 PM PST 24
Peak memory 200792 kb
Host smart-536d1c7b-9e8e-4089-891e-0353c841c540
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154147520 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.4154147520
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1671787739
Short name T78
Test name
Test status
Simulation time 114866254 ps
CPU time 1.85 seconds
Started Jan 03 12:37:37 PM PST 24
Finished Jan 03 12:38:49 PM PST 24
Peak memory 209364 kb
Host smart-d6ef3ce3-1fcf-44e5-97b9-fc7dd585fb92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671787739 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.1671787739
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3883186260
Short name T130
Test name
Test status
Simulation time 241707959 ps
CPU time 3.07 seconds
Started Jan 03 12:38:05 PM PST 24
Finished Jan 03 12:39:20 PM PST 24
Peak memory 217544 kb
Host smart-a09fc8c2-6456-4e69-bd0b-afc78ed655e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883186260 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3883186260
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1179728400
Short name T81
Test name
Test status
Simulation time 120289425 ps
CPU time 2.11 seconds
Started Jan 03 12:37:45 PM PST 24
Finished Jan 03 12:39:12 PM PST 24
Peak memory 200796 kb
Host smart-d668e4c4-30ff-4765-9bf4-10e26e6eafcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179728400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.1179728400
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.403150946
Short name T108
Test name
Test status
Simulation time 108164191 ps
CPU time 2.34 seconds
Started Jan 03 12:37:32 PM PST 24
Finished Jan 03 12:38:48 PM PST 24
Peak memory 200968 kb
Host smart-d268b28b-5634-4931-8d31-51bd399fa829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403150946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_tl_intg_err.403150946
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.2202979958
Short name T133
Test name
Test status
Simulation time 31532641 ps
CPU time 0.99 seconds
Started Jan 03 12:37:51 PM PST 24
Finished Jan 03 12:39:04 PM PST 24
Peak memory 200824 kb
Host smart-c9ed8442-90aa-4a41-b5f1-9c62c5807e98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202979958 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.2202979958
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2178280857
Short name T996
Test name
Test status
Simulation time 68001353 ps
CPU time 0.91 seconds
Started Jan 03 12:37:44 PM PST 24
Finished Jan 03 12:38:59 PM PST 24
Peak memory 200580 kb
Host smart-b6398dab-700f-44a7-892d-6b356f1e9034
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178280857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.2178280857
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.76407122
Short name T249
Test name
Test status
Simulation time 42684112 ps
CPU time 0.73 seconds
Started Jan 03 12:37:51 PM PST 24
Finished Jan 03 12:39:13 PM PST 24
Peak memory 198956 kb
Host smart-11384205-2eea-45d4-98d9-34bd0c0132fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76407122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmg
r_intr_test.76407122
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1470174503
Short name T261
Test name
Test status
Simulation time 149085442 ps
CPU time 1.42 seconds
Started Jan 03 12:37:25 PM PST 24
Finished Jan 03 12:38:35 PM PST 24
Peak memory 200856 kb
Host smart-dc972472-9e59-48d9-a179-50e9a2be57d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470174503 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.1470174503
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.532019536
Short name T124
Test name
Test status
Simulation time 143295188 ps
CPU time 1.65 seconds
Started Jan 03 12:37:42 PM PST 24
Finished Jan 03 12:39:01 PM PST 24
Peak memory 201088 kb
Host smart-ad09e506-6bc8-494c-a96b-71a9949c8a50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532019536 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.532019536
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2853556701
Short name T199
Test name
Test status
Simulation time 650726972 ps
CPU time 3.32 seconds
Started Jan 03 12:38:07 PM PST 24
Finished Jan 03 12:39:31 PM PST 24
Peak memory 200956 kb
Host smart-23f30ca8-6b80-45b3-82f7-a2d65e6c97fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853556701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.2853556701
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.3328264198
Short name T647
Test name
Test status
Simulation time 30261183 ps
CPU time 0.74 seconds
Started Jan 03 01:02:20 PM PST 24
Finished Jan 03 01:03:28 PM PST 24
Peak memory 200692 kb
Host smart-c3fdeb47-d936-48f5-bea7-5a4647eaf95e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328264198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.3328264198
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.2485816563
Short name T411
Test name
Test status
Simulation time 20978125 ps
CPU time 0.8 seconds
Started Jan 03 01:02:28 PM PST 24
Finished Jan 03 01:03:36 PM PST 24
Peak memory 200776 kb
Host smart-38689749-d22d-4f65-97d9-3cd9d9c5c1e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485816563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.2485816563
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.1372096641
Short name T531
Test name
Test status
Simulation time 21988004 ps
CPU time 0.71 seconds
Started Jan 03 01:02:53 PM PST 24
Finished Jan 03 01:03:58 PM PST 24
Peak memory 200608 kb
Host smart-9213c17a-aae0-4fef-9e81-9b7f00960920
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372096641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.1372096641
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.1350324944
Short name T592
Test name
Test status
Simulation time 37274024 ps
CPU time 0.88 seconds
Started Jan 03 01:03:03 PM PST 24
Finished Jan 03 01:04:10 PM PST 24
Peak memory 200720 kb
Host smart-cfdb9f7a-1791-4293-83b9-0028fa9aa48b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350324944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.1350324944
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.298219810
Short name T547
Test name
Test status
Simulation time 20980850 ps
CPU time 0.79 seconds
Started Jan 03 01:03:01 PM PST 24
Finished Jan 03 01:04:07 PM PST 24
Peak memory 200712 kb
Host smart-ce67ff8a-1e82-4c49-be2a-4d370eb958c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298219810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.298219810
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.2953251934
Short name T967
Test name
Test status
Simulation time 682251550 ps
CPU time 4.55 seconds
Started Jan 03 01:02:51 PM PST 24
Finished Jan 03 01:04:01 PM PST 24
Peak memory 200752 kb
Host smart-b85b5f83-e1da-4087-9029-31f2bda036fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953251934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.2953251934
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.929174155
Short name T596
Test name
Test status
Simulation time 863374621 ps
CPU time 6.54 seconds
Started Jan 03 01:02:46 PM PST 24
Finished Jan 03 01:03:59 PM PST 24
Peak memory 200768 kb
Host smart-9528397e-66f6-4dba-b9e4-5f038e67be7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929174155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_tim
eout.929174155
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.167616660
Short name T374
Test name
Test status
Simulation time 34098090 ps
CPU time 0.74 seconds
Started Jan 03 01:03:05 PM PST 24
Finished Jan 03 01:04:12 PM PST 24
Peak memory 200748 kb
Host smart-00c2f8a7-2541-41ca-b1c9-a4df25d3bf74
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167616660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_idle_intersig_mubi.167616660
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.491887873
Short name T836
Test name
Test status
Simulation time 21491400 ps
CPU time 0.79 seconds
Started Jan 03 01:02:48 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 200700 kb
Host smart-acf97704-f74a-43fb-827f-06a4daf829e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491887873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_lc_clk_byp_req_intersig_mubi.491887873
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.2817474626
Short name T631
Test name
Test status
Simulation time 73033548 ps
CPU time 0.94 seconds
Started Jan 03 01:03:01 PM PST 24
Finished Jan 03 01:04:08 PM PST 24
Peak memory 200704 kb
Host smart-009bca9b-681c-4d10-91dd-39843f9a43b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817474626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_ctrl_intersig_mubi.2817474626
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.1888530401
Short name T737
Test name
Test status
Simulation time 47161475 ps
CPU time 0.84 seconds
Started Jan 03 01:02:44 PM PST 24
Finished Jan 03 01:03:51 PM PST 24
Peak memory 200640 kb
Host smart-03a71da2-0047-4a6d-952a-bc9f45d7b01a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888530401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.1888530401
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.3131439953
Short name T659
Test name
Test status
Simulation time 942068109 ps
CPU time 5.34 seconds
Started Jan 03 01:02:28 PM PST 24
Finished Jan 03 01:03:41 PM PST 24
Peak memory 200884 kb
Host smart-8582fa98-f17a-4e55-83ee-e44879f139a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131439953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3131439953
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.2232325354
Short name T928
Test name
Test status
Simulation time 19984419 ps
CPU time 0.81 seconds
Started Jan 03 01:02:55 PM PST 24
Finished Jan 03 01:04:00 PM PST 24
Peak memory 200752 kb
Host smart-ac847904-1924-4154-ba39-e49e318df18d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232325354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.2232325354
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.2566773771
Short name T992
Test name
Test status
Simulation time 3596344013 ps
CPU time 27.5 seconds
Started Jan 03 01:02:26 PM PST 24
Finished Jan 03 01:04:01 PM PST 24
Peak memory 201024 kb
Host smart-10b4127b-3d55-47e0-9247-ae56e70e042a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566773771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.2566773771
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.223368374
Short name T158
Test name
Test status
Simulation time 82077403968 ps
CPU time 598.42 seconds
Started Jan 03 01:02:30 PM PST 24
Finished Jan 03 01:13:36 PM PST 24
Peak memory 209300 kb
Host smart-53bf552e-33dd-49d8-96ec-f286eca5a341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=223368374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.223368374
Directory /workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.clkmgr_trans.2284963863
Short name T852
Test name
Test status
Simulation time 34464426 ps
CPU time 1.03 seconds
Started Jan 03 01:02:47 PM PST 24
Finished Jan 03 01:03:54 PM PST 24
Peak memory 200780 kb
Host smart-43246e7a-8dac-4f81-96c5-87a06b16b881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284963863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.2284963863
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.1365480534
Short name T558
Test name
Test status
Simulation time 26570125 ps
CPU time 0.8 seconds
Started Jan 03 01:02:29 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 200616 kb
Host smart-2758a902-83e2-43de-9b0e-f079e097f925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365480534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.1365480534
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.2163772634
Short name T897
Test name
Test status
Simulation time 42316098 ps
CPU time 0.8 seconds
Started Jan 03 01:02:27 PM PST 24
Finished Jan 03 01:03:35 PM PST 24
Peak memory 200800 kb
Host smart-da31d1cf-b3f6-4616-b470-78a92a9a955c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163772634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.2163772634
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.3051750173
Short name T453
Test name
Test status
Simulation time 36403993 ps
CPU time 0.85 seconds
Started Jan 03 01:02:17 PM PST 24
Finished Jan 03 01:03:26 PM PST 24
Peak memory 200808 kb
Host smart-9ccba8d8-180a-42f4-b4b2-35ba91c3a67f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051750173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.3051750173
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.3424281744
Short name T900
Test name
Test status
Simulation time 63910982 ps
CPU time 0.93 seconds
Started Jan 03 01:02:18 PM PST 24
Finished Jan 03 01:03:26 PM PST 24
Peak memory 200644 kb
Host smart-c4ad2325-c60a-4dc2-8a87-51fd58dcb1da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424281744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.3424281744
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.3569483187
Short name T500
Test name
Test status
Simulation time 2492421590 ps
CPU time 11.83 seconds
Started Jan 03 01:02:22 PM PST 24
Finished Jan 03 01:03:42 PM PST 24
Peak memory 200936 kb
Host smart-933b87cf-7047-4871-bfde-11afe9abd84d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569483187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3569483187
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.3062906128
Short name T373
Test name
Test status
Simulation time 1704597870 ps
CPU time 5.84 seconds
Started Jan 03 01:02:26 PM PST 24
Finished Jan 03 01:03:39 PM PST 24
Peak memory 200892 kb
Host smart-5b5b0c8a-977c-427b-8f0d-d3402498b9f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062906128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.3062906128
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.2269630354
Short name T608
Test name
Test status
Simulation time 32488517 ps
CPU time 0.8 seconds
Started Jan 03 01:02:26 PM PST 24
Finished Jan 03 01:03:34 PM PST 24
Peak memory 200724 kb
Host smart-f7fbf06b-e739-460f-90c3-2813862481a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269630354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.2269630354
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.1829445294
Short name T519
Test name
Test status
Simulation time 24037149 ps
CPU time 0.88 seconds
Started Jan 03 01:02:21 PM PST 24
Finished Jan 03 01:03:30 PM PST 24
Peak memory 200808 kb
Host smart-8017866f-5b08-4e0a-b131-0be55db00a4e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829445294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.1829445294
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.708144931
Short name T778
Test name
Test status
Simulation time 56716559 ps
CPU time 0.84 seconds
Started Jan 03 01:02:33 PM PST 24
Finished Jan 03 01:03:45 PM PST 24
Peak memory 200644 kb
Host smart-caf5b17c-921f-4659-a5e7-478c89e0b366
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708144931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.clkmgr_lc_ctrl_intersig_mubi.708144931
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.1524425455
Short name T491
Test name
Test status
Simulation time 23838828 ps
CPU time 0.75 seconds
Started Jan 03 01:02:26 PM PST 24
Finished Jan 03 01:03:34 PM PST 24
Peak memory 200592 kb
Host smart-f2d92858-e370-4875-883e-2dabd1e3ce44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524425455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.1524425455
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.500155937
Short name T615
Test name
Test status
Simulation time 1524446995 ps
CPU time 4.88 seconds
Started Jan 03 01:02:25 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 201008 kb
Host smart-ab4c3e1b-e7d2-47df-976b-96e1700aad77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500155937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.500155937
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.898037633
Short name T57
Test name
Test status
Simulation time 226187993 ps
CPU time 2.04 seconds
Started Jan 03 01:02:30 PM PST 24
Finished Jan 03 01:03:40 PM PST 24
Peak memory 215124 kb
Host smart-3331fdd7-56ec-4dba-ae14-087aba6bdd71
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898037633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr
_sec_cm.898037633
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.3454172
Short name T794
Test name
Test status
Simulation time 40155657 ps
CPU time 0.84 seconds
Started Jan 03 01:02:29 PM PST 24
Finished Jan 03 01:03:37 PM PST 24
Peak memory 200672 kb
Host smart-ee437e44-bba1-4a5c-9362-b1153ad7040f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.3454172
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.2900848068
Short name T650
Test name
Test status
Simulation time 6160396515 ps
CPU time 42.7 seconds
Started Jan 03 01:02:31 PM PST 24
Finished Jan 03 01:04:20 PM PST 24
Peak memory 201064 kb
Host smart-94dec177-6f61-4192-860f-d44fcd504c04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900848068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.2900848068
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.16085653
Short name T634
Test name
Test status
Simulation time 409684598036 ps
CPU time 1865.9 seconds
Started Jan 03 01:02:28 PM PST 24
Finished Jan 03 01:34:42 PM PST 24
Peak memory 216116 kb
Host smart-e9d8b967-041b-4210-a826-4983f44b7391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=16085653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.16085653
Directory /workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.clkmgr_trans.1732442371
Short name T698
Test name
Test status
Simulation time 35926331 ps
CPU time 0.86 seconds
Started Jan 03 01:02:25 PM PST 24
Finished Jan 03 01:03:34 PM PST 24
Peak memory 200788 kb
Host smart-3d4995e4-bc31-406d-9888-a5cb0464de63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732442371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.1732442371
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.2290388628
Short name T884
Test name
Test status
Simulation time 64039121 ps
CPU time 0.84 seconds
Started Jan 03 01:03:05 PM PST 24
Finished Jan 03 01:04:11 PM PST 24
Peak memory 200784 kb
Host smart-27e912ab-e872-4bf0-bf8e-f349d3ee0e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290388628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.2290388628
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.706582146
Short name T745
Test name
Test status
Simulation time 18230155 ps
CPU time 0.72 seconds
Started Jan 03 01:03:08 PM PST 24
Finished Jan 03 01:04:14 PM PST 24
Peak memory 200792 kb
Host smart-12517144-95a9-4b19-8005-aa4063954401
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706582146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.706582146
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.4179787932
Short name T946
Test name
Test status
Simulation time 40701199 ps
CPU time 0.75 seconds
Started Jan 03 01:03:01 PM PST 24
Finished Jan 03 01:04:08 PM PST 24
Peak memory 199620 kb
Host smart-162aa94b-956d-4280-bd98-7d66243f1845
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179787932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.4179787932
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.3930051155
Short name T981
Test name
Test status
Simulation time 40082525 ps
CPU time 0.9 seconds
Started Jan 03 01:03:01 PM PST 24
Finished Jan 03 01:04:09 PM PST 24
Peak memory 200736 kb
Host smart-74e5fb65-005a-4706-8efb-5f88f0bc0b86
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930051155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.3930051155
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.2634581755
Short name T748
Test name
Test status
Simulation time 57290023 ps
CPU time 0.88 seconds
Started Jan 03 01:02:54 PM PST 24
Finished Jan 03 01:03:59 PM PST 24
Peak memory 200704 kb
Host smart-a24d156e-6b36-4481-8ccd-98afbb6d3a67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634581755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.2634581755
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.1501881393
Short name T917
Test name
Test status
Simulation time 2140265108 ps
CPU time 9.54 seconds
Started Jan 03 01:02:53 PM PST 24
Finished Jan 03 01:04:07 PM PST 24
Peak memory 200844 kb
Host smart-30dbd2f3-e682-439b-b9e7-2406f0c8bb74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501881393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.1501881393
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.1650243953
Short name T469
Test name
Test status
Simulation time 2190346122 ps
CPU time 11.85 seconds
Started Jan 03 01:02:45 PM PST 24
Finished Jan 03 01:04:03 PM PST 24
Peak memory 200948 kb
Host smart-0344be2f-e09d-4608-80f2-4f6a37271217
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650243953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.1650243953
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.3914309116
Short name T932
Test name
Test status
Simulation time 25064424 ps
CPU time 0.85 seconds
Started Jan 03 01:03:01 PM PST 24
Finished Jan 03 01:04:08 PM PST 24
Peak memory 200700 kb
Host smart-3939a8c6-01f3-4184-bbb8-9d21005b6f70
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914309116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.3914309116
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.631267246
Short name T801
Test name
Test status
Simulation time 94197611 ps
CPU time 0.96 seconds
Started Jan 03 01:03:10 PM PST 24
Finished Jan 03 01:04:16 PM PST 24
Peak memory 200696 kb
Host smart-af9c3820-43dc-48bd-9fb8-2c32630dfd01
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631267246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_ctrl_intersig_mubi.631267246
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.3562189828
Short name T809
Test name
Test status
Simulation time 23658365 ps
CPU time 0.75 seconds
Started Jan 03 01:02:50 PM PST 24
Finished Jan 03 01:03:56 PM PST 24
Peak memory 200728 kb
Host smart-20bc59e8-9cc5-4168-a199-79921e9f01b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562189828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.3562189828
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.4281149755
Short name T759
Test name
Test status
Simulation time 678184857 ps
CPU time 2.79 seconds
Started Jan 03 01:02:56 PM PST 24
Finished Jan 03 01:04:02 PM PST 24
Peak memory 200804 kb
Host smart-41199553-fb13-413b-8e63-f885d0977b7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281149755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.4281149755
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.2239437535
Short name T720
Test name
Test status
Simulation time 23488875 ps
CPU time 0.83 seconds
Started Jan 03 01:02:56 PM PST 24
Finished Jan 03 01:04:01 PM PST 24
Peak memory 200744 kb
Host smart-5a26449a-9f98-47bd-b61a-97f14337c2cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239437535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.2239437535
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.1191536952
Short name T964
Test name
Test status
Simulation time 8522738412 ps
CPU time 44.21 seconds
Started Jan 03 01:02:58 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 201080 kb
Host smart-53d40415-f4f4-4f69-aab3-440f72e39b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191536952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.1191536952
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.3433930413
Short name T149
Test name
Test status
Simulation time 35349526114 ps
CPU time 509.07 seconds
Started Jan 03 01:02:59 PM PST 24
Finished Jan 03 01:12:33 PM PST 24
Peak memory 209704 kb
Host smart-4f8d0af8-94b9-4eca-a458-aae54ac8d165
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3433930413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.3433930413
Directory /workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.clkmgr_trans.2776154
Short name T550
Test name
Test status
Simulation time 50647104 ps
CPU time 0.85 seconds
Started Jan 03 01:02:49 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 200800 kb
Host smart-994938ee-548a-4e20-beb9-90c2885a2c0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2776154
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.2778449634
Short name T591
Test name
Test status
Simulation time 27060269 ps
CPU time 0.81 seconds
Started Jan 03 01:02:55 PM PST 24
Finished Jan 03 01:04:00 PM PST 24
Peak memory 200668 kb
Host smart-f268ede9-95ba-4549-b940-b0e554a485c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778449634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.2778449634
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2201765968
Short name T417
Test name
Test status
Simulation time 69514118 ps
CPU time 0.98 seconds
Started Jan 03 01:03:14 PM PST 24
Finished Jan 03 01:04:18 PM PST 24
Peak memory 200784 kb
Host smart-9e8d9dbd-4086-4ac9-b1c2-916e97cd748e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201765968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.2201765968
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.3952528128
Short name T798
Test name
Test status
Simulation time 38725735 ps
CPU time 0.85 seconds
Started Jan 03 01:03:20 PM PST 24
Finished Jan 03 01:04:22 PM PST 24
Peak memory 199700 kb
Host smart-51e8ab6b-2acd-4a3a-9391-23d68b823530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952528128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3952528128
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.4076470488
Short name T986
Test name
Test status
Simulation time 24662881 ps
CPU time 0.81 seconds
Started Jan 03 01:03:23 PM PST 24
Finished Jan 03 01:04:23 PM PST 24
Peak memory 200712 kb
Host smart-66f948b5-aa88-444e-8093-7fc242e13424
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076470488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.4076470488
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.299954149
Short name T606
Test name
Test status
Simulation time 44641000 ps
CPU time 0.83 seconds
Started Jan 03 01:02:54 PM PST 24
Finished Jan 03 01:03:59 PM PST 24
Peak memory 200700 kb
Host smart-4926113c-5a14-4bf1-b185-4d5d6fc497a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299954149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.299954149
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.3690396100
Short name T25
Test name
Test status
Simulation time 478119189 ps
CPU time 2.49 seconds
Started Jan 03 01:03:06 PM PST 24
Finished Jan 03 01:04:13 PM PST 24
Peak memory 200788 kb
Host smart-b319bfe2-2156-4ce6-a44d-a723249f9f84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690396100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.3690396100
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.599641676
Short name T544
Test name
Test status
Simulation time 813606016 ps
CPU time 3.35 seconds
Started Jan 03 01:02:56 PM PST 24
Finished Jan 03 01:04:04 PM PST 24
Peak memory 200852 kb
Host smart-5ef2ce99-680b-43de-bf63-329c30c22414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599641676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_ti
meout.599641676
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.335379107
Short name T327
Test name
Test status
Simulation time 35196330 ps
CPU time 0.83 seconds
Started Jan 03 01:03:06 PM PST 24
Finished Jan 03 01:04:12 PM PST 24
Peak memory 200824 kb
Host smart-358e688a-eb9c-4a20-867b-e8594f25da5e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335379107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.clkmgr_idle_intersig_mubi.335379107
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1298586408
Short name T887
Test name
Test status
Simulation time 12478734 ps
CPU time 0.7 seconds
Started Jan 03 01:03:06 PM PST 24
Finished Jan 03 01:04:13 PM PST 24
Peak memory 200776 kb
Host smart-d47ea05d-30a5-4819-aa09-d4999e3cbc9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298586408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1298586408
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.4188917225
Short name T682
Test name
Test status
Simulation time 23904117 ps
CPU time 0.93 seconds
Started Jan 03 01:03:21 PM PST 24
Finished Jan 03 01:04:22 PM PST 24
Peak memory 200700 kb
Host smart-7876cd19-9ffd-42c5-9968-7755715c75b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188917225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.4188917225
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.2424866472
Short name T829
Test name
Test status
Simulation time 37735734 ps
CPU time 0.76 seconds
Started Jan 03 01:03:08 PM PST 24
Finished Jan 03 01:04:14 PM PST 24
Peak memory 200640 kb
Host smart-4f2e3f93-429d-4b3f-8b29-4af50672cdf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424866472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.2424866472
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.2770874183
Short name T507
Test name
Test status
Simulation time 1092971876 ps
CPU time 4.8 seconds
Started Jan 03 01:03:07 PM PST 24
Finished Jan 03 01:04:17 PM PST 24
Peak memory 200952 kb
Host smart-4e287497-5a74-4af0-a183-8fce7a0904c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770874183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.2770874183
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.1144504651
Short name T154
Test name
Test status
Simulation time 21099823 ps
CPU time 0.82 seconds
Started Jan 03 01:02:56 PM PST 24
Finished Jan 03 01:04:01 PM PST 24
Peak memory 200784 kb
Host smart-ae5c98e9-e6d4-4f82-a353-ae066bd9e9fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144504651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.1144504651
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.3347171439
Short name T622
Test name
Test status
Simulation time 2532495683 ps
CPU time 9.64 seconds
Started Jan 03 01:02:54 PM PST 24
Finished Jan 03 01:04:08 PM PST 24
Peak memory 201068 kb
Host smart-8ef4c3e5-73a9-4964-9fc1-e071f2e6f621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347171439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.3347171439
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.1448001001
Short name T625
Test name
Test status
Simulation time 46408972462 ps
CPU time 673.29 seconds
Started Jan 03 01:03:03 PM PST 24
Finished Jan 03 01:15:23 PM PST 24
Peak memory 217504 kb
Host smart-455a2851-c2f6-4f2f-8134-988a36bd9662
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1448001001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.1448001001
Directory /workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.clkmgr_trans.403266266
Short name T372
Test name
Test status
Simulation time 97668660 ps
CPU time 1.15 seconds
Started Jan 03 01:03:03 PM PST 24
Finished Jan 03 01:04:10 PM PST 24
Peak memory 200832 kb
Host smart-ce34ea07-f152-4b1d-94fe-bc14a9fb4f1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403266266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.403266266
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.2279450560
Short name T576
Test name
Test status
Simulation time 13901392 ps
CPU time 0.73 seconds
Started Jan 03 01:03:37 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 200780 kb
Host smart-8f8ff5f7-2dc7-4be5-aa96-458ea38074cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279450560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.2279450560
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3155218377
Short name T618
Test name
Test status
Simulation time 79026305 ps
CPU time 1.06 seconds
Started Jan 03 01:03:39 PM PST 24
Finished Jan 03 01:04:33 PM PST 24
Peak memory 200824 kb
Host smart-5ed3b62e-d4f1-4d2d-aa61-bede02d5414f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155218377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3155218377
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.713180312
Short name T135
Test name
Test status
Simulation time 17011393 ps
CPU time 0.7 seconds
Started Jan 03 01:03:39 PM PST 24
Finished Jan 03 01:04:33 PM PST 24
Peak memory 200664 kb
Host smart-5637473f-116e-404c-bd71-0d151f4ea4e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713180312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.713180312
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.2235090777
Short name T510
Test name
Test status
Simulation time 91296941 ps
CPU time 1.09 seconds
Started Jan 03 01:03:27 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200776 kb
Host smart-d37ac3b2-19a7-4bfa-8f15-abdf3dba3f53
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235090777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.2235090777
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.3268096641
Short name T535
Test name
Test status
Simulation time 50222391 ps
CPU time 0.96 seconds
Started Jan 03 01:03:21 PM PST 24
Finished Jan 03 01:04:22 PM PST 24
Peak memory 200760 kb
Host smart-aba0cea0-0e21-4c0f-b654-7a6a29d3f6ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268096641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.3268096641
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.1229293605
Short name T557
Test name
Test status
Simulation time 203820838 ps
CPU time 1.64 seconds
Started Jan 03 01:03:23 PM PST 24
Finished Jan 03 01:04:24 PM PST 24
Peak memory 200756 kb
Host smart-0c2116f0-af15-4211-af3d-6349e3d48c1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229293605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.1229293605
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.1269949865
Short name T29
Test name
Test status
Simulation time 731921324 ps
CPU time 2.88 seconds
Started Jan 03 01:03:35 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 200780 kb
Host smart-990d521f-f6bd-4fa4-99f2-93783508dcae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269949865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.1269949865
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.32826378
Short name T570
Test name
Test status
Simulation time 31437157 ps
CPU time 1 seconds
Started Jan 03 01:03:27 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200668 kb
Host smart-ebec92a6-074d-4773-a7f8-62565e484854
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32826378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.clkmgr_idle_intersig_mubi.32826378
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.2015988831
Short name T945
Test name
Test status
Simulation time 14493051 ps
CPU time 0.73 seconds
Started Jan 03 01:03:33 PM PST 24
Finished Jan 03 01:04:28 PM PST 24
Peak memory 200752 kb
Host smart-1d162573-b565-4c2b-9dbe-f683bcb41d4f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015988831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_clk_byp_req_intersig_mubi.2015988831
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1896464515
Short name T812
Test name
Test status
Simulation time 77218366 ps
CPU time 0.98 seconds
Started Jan 03 01:03:06 PM PST 24
Finished Jan 03 01:04:12 PM PST 24
Peak memory 200764 kb
Host smart-9d2571a6-9d2b-4b77-b4c8-63428a113af4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896464515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.1896464515
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.2882847821
Short name T947
Test name
Test status
Simulation time 20675815 ps
CPU time 0.75 seconds
Started Jan 03 01:03:12 PM PST 24
Finished Jan 03 01:04:17 PM PST 24
Peak memory 200660 kb
Host smart-f3359000-754d-4560-97dd-08736d5015bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882847821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.2882847821
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.2138125664
Short name T711
Test name
Test status
Simulation time 599804581 ps
CPU time 2.67 seconds
Started Jan 03 01:03:32 PM PST 24
Finished Jan 03 01:04:29 PM PST 24
Peak memory 200752 kb
Host smart-3bce3894-40db-471b-aeda-af50c2a0c837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138125664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.2138125664
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.2546524933
Short name T883
Test name
Test status
Simulation time 68892052 ps
CPU time 0.96 seconds
Started Jan 03 01:03:02 PM PST 24
Finished Jan 03 01:04:09 PM PST 24
Peak memory 200676 kb
Host smart-f9e4854e-5bbf-4da8-8110-0fd07382fd67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546524933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2546524933
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.951467496
Short name T363
Test name
Test status
Simulation time 1048152618 ps
CPU time 4.24 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:48 PM PST 24
Peak memory 200788 kb
Host smart-755862ed-a793-42e4-b89f-8fc8a5bbe66e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951467496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.951467496
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.232816278
Short name T450
Test name
Test status
Simulation time 89924320508 ps
CPU time 442.82 seconds
Started Jan 03 01:03:32 PM PST 24
Finished Jan 03 01:11:50 PM PST 24
Peak memory 217536 kb
Host smart-00dca907-9e97-4972-9a4a-ffe87ad90ac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=232816278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.232816278
Directory /workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.clkmgr_trans.511089168
Short name T580
Test name
Test status
Simulation time 27705863 ps
CPU time 0.78 seconds
Started Jan 03 01:03:08 PM PST 24
Finished Jan 03 01:04:14 PM PST 24
Peak memory 200784 kb
Host smart-782577ba-08c4-47f9-9b60-e46917b22e03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511089168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.511089168
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.554714
Short name T354
Test name
Test status
Simulation time 54302935 ps
CPU time 0.87 seconds
Started Jan 03 01:03:01 PM PST 24
Finished Jan 03 01:04:08 PM PST 24
Peak memory 200660 kb
Host smart-44c718cc-d972-41b0-9f63-863c2fba16da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_
alert_test.554714
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.3498478237
Short name T528
Test name
Test status
Simulation time 124005845 ps
CPU time 1.13 seconds
Started Jan 03 01:02:59 PM PST 24
Finished Jan 03 01:04:05 PM PST 24
Peak memory 200808 kb
Host smart-466387ab-0440-43ae-a44f-6f9bcebd5e4a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498478237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.3498478237
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.3931028119
Short name T46
Test name
Test status
Simulation time 29850251 ps
CPU time 0.73 seconds
Started Jan 03 01:03:44 PM PST 24
Finished Jan 03 01:04:38 PM PST 24
Peak memory 199576 kb
Host smart-a4093cf7-6f7b-41b1-b7a3-212c911033d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931028119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3931028119
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.3118474073
Short name T773
Test name
Test status
Simulation time 25909575 ps
CPU time 0.9 seconds
Started Jan 03 01:03:04 PM PST 24
Finished Jan 03 01:04:11 PM PST 24
Peak memory 200668 kb
Host smart-9124df21-3ce9-482a-ae90-6bfebc443d62
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118474073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.3118474073
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.1847457624
Short name T424
Test name
Test status
Simulation time 23629453 ps
CPU time 0.81 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:04 PM PST 24
Peak memory 200696 kb
Host smart-7d3aea19-e85b-43b4-8263-c2b41520eec8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847457624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.1847457624
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.3472982347
Short name T984
Test name
Test status
Simulation time 1523134647 ps
CPU time 10.85 seconds
Started Jan 03 01:03:43 PM PST 24
Finished Jan 03 01:04:46 PM PST 24
Peak memory 200788 kb
Host smart-8abd7b62-b90f-40f5-a592-ee680432fd79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472982347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3472982347
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.4187428641
Short name T395
Test name
Test status
Simulation time 1822059745 ps
CPU time 13.24 seconds
Started Jan 03 01:02:47 PM PST 24
Finished Jan 03 01:04:06 PM PST 24
Peak memory 200788 kb
Host smart-25036af3-e5e1-4f6b-ac5a-949d8b92baf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187428641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.4187428641
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.3765940826
Short name T602
Test name
Test status
Simulation time 15317849 ps
CPU time 0.76 seconds
Started Jan 03 01:02:50 PM PST 24
Finished Jan 03 01:03:56 PM PST 24
Peak memory 200640 kb
Host smart-e102fd9d-1b88-4a2e-abfb-5f1c68771949
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765940826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.3765940826
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.3526685762
Short name T923
Test name
Test status
Simulation time 31735988 ps
CPU time 0.81 seconds
Started Jan 03 01:02:49 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 200808 kb
Host smart-b7dfeabd-93e5-4075-b6f9-297d31f137a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526685762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.3526685762
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.360498349
Short name T478
Test name
Test status
Simulation time 18782600 ps
CPU time 0.75 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200636 kb
Host smart-a55e52bb-eb17-4f20-b16c-aeab2793e7a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360498349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.360498349
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.1978825060
Short name T861
Test name
Test status
Simulation time 375048245 ps
CPU time 2.08 seconds
Started Jan 03 01:02:54 PM PST 24
Finished Jan 03 01:04:01 PM PST 24
Peak memory 200748 kb
Host smart-29c4c610-a012-457f-8265-f5f093d2ace2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978825060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.1978825060
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.547661894
Short name T556
Test name
Test status
Simulation time 22609949 ps
CPU time 0.87 seconds
Started Jan 03 01:03:36 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 200700 kb
Host smart-61ac04a6-2ef2-4d40-a4fc-e286c79807ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547661894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.547661894
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.1564724991
Short name T879
Test name
Test status
Simulation time 4103296809 ps
CPU time 17.89 seconds
Started Jan 03 01:02:46 PM PST 24
Finished Jan 03 01:04:10 PM PST 24
Peak memory 201004 kb
Host smart-5f69a29e-7dbc-4b19-92f8-c557a460fc77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564724991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.1564724991
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.1588551139
Short name T972
Test name
Test status
Simulation time 36337839218 ps
CPU time 500.53 seconds
Started Jan 03 01:02:49 PM PST 24
Finished Jan 03 01:12:15 PM PST 24
Peak memory 217408 kb
Host smart-41f0c91f-3e55-4061-883e-216c09ec9978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1588551139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.1588551139
Directory /workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.clkmgr_trans.3509415861
Short name T823
Test name
Test status
Simulation time 110090005 ps
CPU time 1.09 seconds
Started Jan 03 01:02:46 PM PST 24
Finished Jan 03 01:03:53 PM PST 24
Peak memory 200776 kb
Host smart-389da7c7-a22d-4707-8d0a-cef792c1833c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509415861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.3509415861
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.1671878581
Short name T537
Test name
Test status
Simulation time 29336695 ps
CPU time 0.83 seconds
Started Jan 03 01:03:05 PM PST 24
Finished Jan 03 01:04:12 PM PST 24
Peak memory 200696 kb
Host smart-d31c11ea-8bd9-454b-9f7f-823bb25f3b9e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671878581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.1671878581
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.1773447299
Short name T681
Test name
Test status
Simulation time 47686861 ps
CPU time 0.77 seconds
Started Jan 03 01:03:04 PM PST 24
Finished Jan 03 01:04:11 PM PST 24
Peak memory 200664 kb
Host smart-2f0e618f-d2ae-487b-8b88-1413f2ab56ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773447299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.1773447299
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.822264666
Short name T441
Test name
Test status
Simulation time 46700027 ps
CPU time 0.96 seconds
Started Jan 03 01:03:03 PM PST 24
Finished Jan 03 01:04:11 PM PST 24
Peak memory 200764 kb
Host smart-66862139-cb91-4ad1-b5be-7e5c08b84f0f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822264666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.clkmgr_div_intersig_mubi.822264666
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.3176455489
Short name T536
Test name
Test status
Simulation time 114527138 ps
CPU time 1.02 seconds
Started Jan 03 01:03:03 PM PST 24
Finished Jan 03 01:04:11 PM PST 24
Peak memory 200696 kb
Host smart-125cc76f-7729-4aa9-860f-67fbec5512d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176455489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3176455489
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.1208043312
Short name T792
Test name
Test status
Simulation time 679623819 ps
CPU time 5.56 seconds
Started Jan 03 01:03:06 PM PST 24
Finished Jan 03 01:04:16 PM PST 24
Peak memory 200724 kb
Host smart-323859b3-a3e8-4a56-948f-0f7d17305a4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208043312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.1208043312
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.3129973901
Short name T494
Test name
Test status
Simulation time 499350422 ps
CPU time 3 seconds
Started Jan 03 01:02:58 PM PST 24
Finished Jan 03 01:04:06 PM PST 24
Peak memory 200800 kb
Host smart-55b59636-0c82-485f-81a7-07df2ca76af1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129973901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.3129973901
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.1396674611
Short name T633
Test name
Test status
Simulation time 125651118 ps
CPU time 1.19 seconds
Started Jan 03 01:02:57 PM PST 24
Finished Jan 03 01:04:04 PM PST 24
Peak memory 200776 kb
Host smart-87aa2085-05c4-4e9b-93c6-061a44916447
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396674611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.1396674611
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.4115562916
Short name T21
Test name
Test status
Simulation time 23114453 ps
CPU time 0.77 seconds
Started Jan 03 01:03:03 PM PST 24
Finished Jan 03 01:04:10 PM PST 24
Peak memory 200716 kb
Host smart-5a4e1425-cdcd-4fe6-af8c-20648bfb36ce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115562916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.4115562916
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.801173502
Short name T352
Test name
Test status
Simulation time 47597333 ps
CPU time 0.95 seconds
Started Jan 03 01:03:05 PM PST 24
Finished Jan 03 01:04:11 PM PST 24
Peak memory 200756 kb
Host smart-5e298318-24df-4acf-ae61-fc8e876e53f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801173502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_ctrl_intersig_mubi.801173502
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.3310664746
Short name T586
Test name
Test status
Simulation time 28854167 ps
CPU time 0.79 seconds
Started Jan 03 01:02:55 PM PST 24
Finished Jan 03 01:03:59 PM PST 24
Peak memory 200556 kb
Host smart-efdddc6c-7d0e-483d-974e-c7d01fecb983
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310664746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.3310664746
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.2364124386
Short name T668
Test name
Test status
Simulation time 41192146 ps
CPU time 0.85 seconds
Started Jan 03 01:02:56 PM PST 24
Finished Jan 03 01:04:02 PM PST 24
Peak memory 200792 kb
Host smart-a313a68e-1ea5-4ea3-aa9d-9d126c7142a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364124386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2364124386
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.420957974
Short name T705
Test name
Test status
Simulation time 249443525328 ps
CPU time 1166.51 seconds
Started Jan 03 01:03:09 PM PST 24
Finished Jan 03 01:23:40 PM PST 24
Peak memory 217432 kb
Host smart-70e15cce-8cd8-4507-8773-9cfa3abbd612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=420957974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.420957974
Directory /workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.clkmgr_trans.2404950550
Short name T601
Test name
Test status
Simulation time 32813541 ps
CPU time 0.82 seconds
Started Jan 03 01:03:07 PM PST 24
Finished Jan 03 01:04:14 PM PST 24
Peak memory 200792 kb
Host smart-2f0655db-2df2-4d50-90a6-7d4e8bbefb9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404950550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.2404950550
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.269291609
Short name T648
Test name
Test status
Simulation time 17058661 ps
CPU time 0.75 seconds
Started Jan 03 01:03:30 PM PST 24
Finished Jan 03 01:04:27 PM PST 24
Peak memory 200808 kb
Host smart-344b2fa3-b5d3-4712-b540-d4ae54f1e22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269291609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkm
gr_alert_test.269291609
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.641978735
Short name T699
Test name
Test status
Simulation time 68988670 ps
CPU time 1.01 seconds
Started Jan 03 01:03:31 PM PST 24
Finished Jan 03 01:04:33 PM PST 24
Peak memory 200804 kb
Host smart-2c313f83-5460-4925-877d-9b55efee21db
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641978735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.641978735
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.1690102156
Short name T136
Test name
Test status
Simulation time 14991012 ps
CPU time 0.69 seconds
Started Jan 03 01:03:27 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200580 kb
Host smart-0f76d3ae-0d9f-4fae-aca5-f7687580d910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690102156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1690102156
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.2458378560
Short name T655
Test name
Test status
Simulation time 84547074 ps
CPU time 0.98 seconds
Started Jan 03 01:03:27 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200688 kb
Host smart-9ef770cc-5d2b-4640-8a14-0c64182e0fe2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458378560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.2458378560
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.664256199
Short name T291
Test name
Test status
Simulation time 55049546 ps
CPU time 0.89 seconds
Started Jan 03 01:03:38 PM PST 24
Finished Jan 03 01:04:33 PM PST 24
Peak memory 200684 kb
Host smart-6fa0511a-e989-45f2-a02b-76cde4e4c9d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664256199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.664256199
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.2811650477
Short name T873
Test name
Test status
Simulation time 678450237 ps
CPU time 5.56 seconds
Started Jan 03 01:03:11 PM PST 24
Finished Jan 03 01:04:21 PM PST 24
Peak memory 200684 kb
Host smart-22860c43-d773-4e50-8ed1-6296ba4c4ce6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811650477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.2811650477
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.784073595
Short name T432
Test name
Test status
Simulation time 1060583734 ps
CPU time 4.38 seconds
Started Jan 03 01:03:07 PM PST 24
Finished Jan 03 01:04:17 PM PST 24
Peak memory 200864 kb
Host smart-1bfb61e1-ddf2-43d6-a280-899560288286
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784073595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_ti
meout.784073595
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.2570912131
Short name T503
Test name
Test status
Simulation time 51331361 ps
CPU time 0.83 seconds
Started Jan 03 01:03:47 PM PST 24
Finished Jan 03 01:04:43 PM PST 24
Peak memory 200664 kb
Host smart-df1468ce-5273-4e7b-80d1-763d894b9595
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570912131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.2570912131
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.858448782
Short name T706
Test name
Test status
Simulation time 41661756 ps
CPU time 0.9 seconds
Started Jan 03 01:03:50 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 200688 kb
Host smart-7a183c5e-b201-4dc9-9343-0d0788bf9fc4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858448782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.clkmgr_lc_clk_byp_req_intersig_mubi.858448782
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3501784794
Short name T147
Test name
Test status
Simulation time 43512687 ps
CPU time 0.91 seconds
Started Jan 03 01:03:30 PM PST 24
Finished Jan 03 01:04:27 PM PST 24
Peak memory 200796 kb
Host smart-435715fb-902c-4792-9267-a2af574e6839
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501784794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.3501784794
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.4095085808
Short name T983
Test name
Test status
Simulation time 17102309 ps
CPU time 0.78 seconds
Started Jan 03 01:03:36 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 200520 kb
Host smart-52e42ab0-810d-4025-9ef5-3cc03650b83b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095085808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.4095085808
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.1669068768
Short name T771
Test name
Test status
Simulation time 724733393 ps
CPU time 2.99 seconds
Started Jan 03 01:03:26 PM PST 24
Finished Jan 03 01:04:27 PM PST 24
Peak memory 201008 kb
Host smart-76fbf204-2d7b-4fa6-a821-a26b649192dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669068768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.1669068768
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.2038642832
Short name T924
Test name
Test status
Simulation time 67145548 ps
CPU time 0.96 seconds
Started Jan 03 01:03:08 PM PST 24
Finished Jan 03 01:04:14 PM PST 24
Peak memory 200804 kb
Host smart-23d89322-dc5b-478f-8c96-919034f7c42c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038642832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.2038642832
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.3345391207
Short name T396
Test name
Test status
Simulation time 1938202981 ps
CPU time 14.87 seconds
Started Jan 03 01:03:49 PM PST 24
Finished Jan 03 01:05:00 PM PST 24
Peak memory 200896 kb
Host smart-5d330ffa-29f4-49aa-a21f-08fd04ccf2c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345391207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.3345391207
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.1913895193
Short name T692
Test name
Test status
Simulation time 98358252098 ps
CPU time 777.66 seconds
Started Jan 03 01:03:35 PM PST 24
Finished Jan 03 01:17:26 PM PST 24
Peak memory 209280 kb
Host smart-366ffc0c-07e4-47ed-af31-c3edcb44f543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1913895193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.1913895193
Directory /workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.clkmgr_trans.2407375853
Short name T22
Test name
Test status
Simulation time 82717857 ps
CPU time 1.04 seconds
Started Jan 03 01:03:36 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 200808 kb
Host smart-ccca3906-8ef6-46be-be2e-1ea715d3c71f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407375853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.2407375853
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.2110109167
Short name T342
Test name
Test status
Simulation time 42938873 ps
CPU time 0.81 seconds
Started Jan 03 01:03:29 PM PST 24
Finished Jan 03 01:04:26 PM PST 24
Peak memory 200780 kb
Host smart-57c1d375-4453-4a11-ba97-ef2bf910ef25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110109167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.2110109167
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3385547150
Short name T688
Test name
Test status
Simulation time 184357147 ps
CPU time 1.22 seconds
Started Jan 03 01:03:47 PM PST 24
Finished Jan 03 01:04:43 PM PST 24
Peak memory 200768 kb
Host smart-2a883d57-8d73-4b2d-87e8-27b0baca55a8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385547150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.3385547150
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.864385532
Short name T148
Test name
Test status
Simulation time 19093957 ps
CPU time 0.72 seconds
Started Jan 03 01:03:44 PM PST 24
Finished Jan 03 01:04:38 PM PST 24
Peak memory 200580 kb
Host smart-70f58def-cc6a-45e0-8727-9e58b34b3e8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864385532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.864385532
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.2719523477
Short name T467
Test name
Test status
Simulation time 26930672 ps
CPU time 0.83 seconds
Started Jan 03 01:04:02 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 200704 kb
Host smart-94c52f7b-b9d0-4c17-a9d0-445b00d2de97
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719523477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.2719523477
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.1613496680
Short name T430
Test name
Test status
Simulation time 46767009 ps
CPU time 0.93 seconds
Started Jan 03 01:03:27 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200648 kb
Host smart-69de7ae9-7a6a-40b2-a379-006822250305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613496680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.1613496680
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.2271662631
Short name T952
Test name
Test status
Simulation time 252729822 ps
CPU time 1.57 seconds
Started Jan 03 01:03:49 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 200660 kb
Host smart-3d7eed28-3e64-4332-a8b7-3ccd6126a353
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271662631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.2271662631
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.2103992603
Short name T383
Test name
Test status
Simulation time 255298529 ps
CPU time 2.51 seconds
Started Jan 03 01:03:38 PM PST 24
Finished Jan 03 01:04:34 PM PST 24
Peak memory 200788 kb
Host smart-1f8bdf60-3af1-4c19-aa3e-6cc503f60b44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103992603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.2103992603
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.850459834
Short name T675
Test name
Test status
Simulation time 227484928 ps
CPU time 1.48 seconds
Started Jan 03 01:03:30 PM PST 24
Finished Jan 03 01:04:27 PM PST 24
Peak memory 200776 kb
Host smart-92d1a162-3a58-4c53-a1fb-6f75ca230831
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850459834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.clkmgr_idle_intersig_mubi.850459834
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1334213972
Short name T920
Test name
Test status
Simulation time 47458104 ps
CPU time 0.85 seconds
Started Jan 03 01:03:28 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200720 kb
Host smart-d5afae8f-cb16-4ff2-9768-52ea604051e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334213972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.1334213972
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.4076738955
Short name T382
Test name
Test status
Simulation time 23039231 ps
CPU time 0.86 seconds
Started Jan 03 01:03:28 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200848 kb
Host smart-a9634345-82f7-495b-85cd-7af1be45b55f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076738955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.4076738955
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.1421679129
Short name T428
Test name
Test status
Simulation time 16558963 ps
CPU time 0.74 seconds
Started Jan 03 01:03:42 PM PST 24
Finished Jan 03 01:04:36 PM PST 24
Peak memory 200660 kb
Host smart-4864e784-d779-4fda-a004-797fe043fc0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421679129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.1421679129
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.2340462437
Short name T846
Test name
Test status
Simulation time 1110244015 ps
CPU time 4.11 seconds
Started Jan 03 01:03:39 PM PST 24
Finished Jan 03 01:04:36 PM PST 24
Peak memory 201004 kb
Host smart-71b843a3-c237-490c-8cca-83696b5c3ece
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340462437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.2340462437
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.1435413453
Short name T436
Test name
Test status
Simulation time 48436795 ps
CPU time 0.89 seconds
Started Jan 03 01:03:27 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200720 kb
Host smart-eee766c5-b358-46c3-b42f-3fb47ca1c6fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435413453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.1435413453
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.1911943038
Short name T857
Test name
Test status
Simulation time 2320488191 ps
CPU time 12.38 seconds
Started Jan 03 01:03:28 PM PST 24
Finished Jan 03 01:04:37 PM PST 24
Peak memory 200960 kb
Host smart-389c0beb-1495-42b5-90d4-5f143f792de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911943038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.1911943038
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.1228592844
Short name T466
Test name
Test status
Simulation time 32825951894 ps
CPU time 525.85 seconds
Started Jan 03 01:03:30 PM PST 24
Finished Jan 03 01:13:12 PM PST 24
Peak memory 217276 kb
Host smart-49080f7e-bd3e-48c3-8a16-e2c3dd0a4bf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1228592844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.1228592844
Directory /workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.clkmgr_trans.3529089134
Short name T339
Test name
Test status
Simulation time 19698021 ps
CPU time 0.81 seconds
Started Jan 03 01:03:43 PM PST 24
Finished Jan 03 01:04:37 PM PST 24
Peak memory 200784 kb
Host smart-1b6ea412-87df-4bf5-a030-79e76286fb8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529089134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3529089134
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.1579430925
Short name T894
Test name
Test status
Simulation time 20617632 ps
CPU time 0.8 seconds
Started Jan 03 01:04:06 PM PST 24
Finished Jan 03 01:05:12 PM PST 24
Peak memory 200804 kb
Host smart-4822a42a-6d77-4a17-a9f2-cfc64e4799fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579430925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.1579430925
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1775073422
Short name T113
Test name
Test status
Simulation time 61228390 ps
CPU time 0.92 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200780 kb
Host smart-51859d14-be04-47d8-9baa-2d8158e98520
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775073422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.1775073422
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.1297606832
Short name T993
Test name
Test status
Simulation time 28106493 ps
CPU time 0.71 seconds
Started Jan 03 01:03:33 PM PST 24
Finished Jan 03 01:04:28 PM PST 24
Peak memory 200636 kb
Host smart-b78023e5-d20a-4086-ab37-c88bc681573a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297606832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1297606832
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.1246744348
Short name T747
Test name
Test status
Simulation time 30026668 ps
CPU time 0.94 seconds
Started Jan 03 01:03:30 PM PST 24
Finished Jan 03 01:04:27 PM PST 24
Peak memory 200644 kb
Host smart-c630311c-6c2d-48ff-aef3-19e56ced36a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246744348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.1246744348
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.326886574
Short name T549
Test name
Test status
Simulation time 75171733 ps
CPU time 0.97 seconds
Started Jan 03 01:03:59 PM PST 24
Finished Jan 03 01:05:01 PM PST 24
Peak memory 200644 kb
Host smart-0e6ac881-4da4-4df0-93e6-b65c3b27d014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326886574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.326886574
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.1381727569
Short name T415
Test name
Test status
Simulation time 1638468739 ps
CPU time 12.55 seconds
Started Jan 03 01:03:34 PM PST 24
Finished Jan 03 01:04:40 PM PST 24
Peak memory 200712 kb
Host smart-3a4c1ce7-21d8-4304-89ab-8ceb8b08b65c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381727569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1381727569
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.3530702073
Short name T757
Test name
Test status
Simulation time 1490607906 ps
CPU time 6.49 seconds
Started Jan 03 01:03:46 PM PST 24
Finished Jan 03 01:04:46 PM PST 24
Peak memory 200712 kb
Host smart-59442c04-c203-40d3-bea8-e8e2d3fcf717
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530702073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.3530702073
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.2652323859
Short name T663
Test name
Test status
Simulation time 124161642 ps
CPU time 1.23 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:36 PM PST 24
Peak memory 200812 kb
Host smart-71c4eda1-c0ed-44f8-b270-019ea2ee6988
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652323859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.2652323859
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.2379430790
Short name T927
Test name
Test status
Simulation time 39214770 ps
CPU time 0.8 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:42 PM PST 24
Peak memory 200788 kb
Host smart-2ca94fd7-0fc5-468a-8d7b-186463ec7368
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379430790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.2379430790
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.108291416
Short name T818
Test name
Test status
Simulation time 48981769 ps
CPU time 0.93 seconds
Started Jan 03 01:03:46 PM PST 24
Finished Jan 03 01:04:40 PM PST 24
Peak memory 200652 kb
Host smart-5c1258d6-764b-42fc-ab3e-c64f1b01aae9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108291416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.clkmgr_lc_ctrl_intersig_mubi.108291416
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.3400375885
Short name T294
Test name
Test status
Simulation time 79634249 ps
CPU time 0.9 seconds
Started Jan 03 01:03:46 PM PST 24
Finished Jan 03 01:04:40 PM PST 24
Peak memory 200648 kb
Host smart-0a7870cf-6737-476c-89ff-2fd68ab21c7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400375885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.3400375885
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.2713875755
Short name T714
Test name
Test status
Simulation time 834856813 ps
CPU time 3.89 seconds
Started Jan 03 01:03:27 PM PST 24
Finished Jan 03 01:04:28 PM PST 24
Peak memory 200892 kb
Host smart-5cfa84a8-33fb-4b39-be9d-b88b5bdb40fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713875755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.2713875755
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.3286102989
Short name T68
Test name
Test status
Simulation time 27630139 ps
CPU time 0.91 seconds
Started Jan 03 01:03:39 PM PST 24
Finished Jan 03 01:04:33 PM PST 24
Peak memory 200780 kb
Host smart-db9b0ddb-e1f0-40b6-bdc0-c4700ad24779
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286102989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3286102989
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.2098046738
Short name T708
Test name
Test status
Simulation time 2013706835 ps
CPU time 8.92 seconds
Started Jan 03 01:03:32 PM PST 24
Finished Jan 03 01:04:36 PM PST 24
Peak memory 201012 kb
Host smart-f35e99cb-f12e-4525-9e88-28509b8fafab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098046738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.2098046738
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.386518446
Short name T362
Test name
Test status
Simulation time 39454938929 ps
CPU time 353.59 seconds
Started Jan 03 01:03:40 PM PST 24
Finished Jan 03 01:10:27 PM PST 24
Peak memory 217544 kb
Host smart-cba84ec4-8b20-4398-817e-1512a9f32634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=386518446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.386518446
Directory /workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.clkmgr_trans.494786454
Short name T630
Test name
Test status
Simulation time 19977234 ps
CPU time 0.78 seconds
Started Jan 03 01:03:29 PM PST 24
Finished Jan 03 01:04:26 PM PST 24
Peak memory 200732 kb
Host smart-503a3a0e-0e1d-494a-8827-7f80b3f86c43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494786454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.494786454
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.1006137272
Short name T312
Test name
Test status
Simulation time 15077385 ps
CPU time 0.72 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:31 PM PST 24
Peak memory 200720 kb
Host smart-ca0ea309-0a63-4110-8065-3ee96c79993c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006137272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.1006137272
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.2720290198
Short name T111
Test name
Test status
Simulation time 116258223 ps
CPU time 1.21 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:05:07 PM PST 24
Peak memory 200792 kb
Host smart-d8bc02dd-3d70-4cb5-8814-22dfab4f28a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720290198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.2720290198
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.3800803412
Short name T484
Test name
Test status
Simulation time 50355871 ps
CPU time 0.77 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:36 PM PST 24
Peak memory 199664 kb
Host smart-9eb701f9-829a-48b8-a88c-8a9870cd96d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800803412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3800803412
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.1444239319
Short name T397
Test name
Test status
Simulation time 102408061 ps
CPU time 1.07 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:05:09 PM PST 24
Peak memory 200648 kb
Host smart-927dc200-7b9f-451e-8c63-ffdcf7f02d57
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444239319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.1444239319
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.2601095354
Short name T849
Test name
Test status
Simulation time 24733693 ps
CPU time 0.84 seconds
Started Jan 03 01:03:28 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200612 kb
Host smart-0e4433cc-fc67-4374-861b-1eee8408b220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601095354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.2601095354
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.1373334748
Short name T896
Test name
Test status
Simulation time 1880974814 ps
CPU time 10.21 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:05:05 PM PST 24
Peak memory 200992 kb
Host smart-ac6990aa-868c-4ec4-93f5-be542ef5aa3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373334748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1373334748
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.2242615301
Short name T881
Test name
Test status
Simulation time 616774513 ps
CPU time 4.5 seconds
Started Jan 03 01:04:19 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200800 kb
Host smart-9836c3d4-33a3-4fa6-8e8a-05b3e23703d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242615301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.2242615301
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.2250124507
Short name T685
Test name
Test status
Simulation time 41224359 ps
CPU time 0.77 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200756 kb
Host smart-10657fdc-c120-4b57-9d8a-117d30717101
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250124507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.2250124507
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.4294749880
Short name T326
Test name
Test status
Simulation time 21374056 ps
CPU time 0.82 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:24 PM PST 24
Peak memory 200796 kb
Host smart-0374ed84-2f8e-485a-896b-6499808baa1b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294749880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.4294749880
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.2714627764
Short name T406
Test name
Test status
Simulation time 37816488 ps
CPU time 0.91 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:04:55 PM PST 24
Peak memory 200712 kb
Host smart-b831d124-2ce3-4f26-a35d-8668e95704d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714627764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.2714627764
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.2390688748
Short name T815
Test name
Test status
Simulation time 31082821 ps
CPU time 0.83 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:46 PM PST 24
Peak memory 200672 kb
Host smart-77ab2e35-09c3-4533-b507-f6ad12c92a43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390688748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2390688748
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.3416771625
Short name T874
Test name
Test status
Simulation time 535286160 ps
CPU time 2.61 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 200912 kb
Host smart-2f251b6b-43ee-47d8-b33a-3a2980575525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416771625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3416771625
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.2323727790
Short name T907
Test name
Test status
Simulation time 17173135 ps
CPU time 0.8 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:04 PM PST 24
Peak memory 200704 kb
Host smart-93d068f5-cbb4-4346-892d-6e9c797841a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323727790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2323727790
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.3361748403
Short name T356
Test name
Test status
Simulation time 3194589967 ps
CPU time 17.9 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:05:10 PM PST 24
Peak memory 201040 kb
Host smart-a8c73b40-a1c9-4eaf-bf66-ea249c1d01d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361748403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.3361748403
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.3439783556
Short name T822
Test name
Test status
Simulation time 146668471 ps
CPU time 1.38 seconds
Started Jan 03 01:03:44 PM PST 24
Finished Jan 03 01:04:39 PM PST 24
Peak memory 200728 kb
Host smart-4d0d8ffa-831d-4e23-a75e-31fd11a58536
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439783556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.3439783556
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.3981006050
Short name T654
Test name
Test status
Simulation time 27270420 ps
CPU time 0.83 seconds
Started Jan 03 01:03:29 PM PST 24
Finished Jan 03 01:04:26 PM PST 24
Peak memory 200748 kb
Host smart-b8f79889-616d-41a2-a136-701800d5d41a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981006050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.3981006050
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.1205461024
Short name T989
Test name
Test status
Simulation time 87358051 ps
CPU time 1.05 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:31 PM PST 24
Peak memory 200732 kb
Host smart-95a26b6e-349d-44ec-bdc5-91c0a9a67298
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205461024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.1205461024
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.1648749048
Short name T847
Test name
Test status
Simulation time 45070321 ps
CPU time 0.78 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 199684 kb
Host smart-32266b7c-47ae-402a-95fd-74f496b98548
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648749048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1648749048
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.787243388
Short name T831
Test name
Test status
Simulation time 22387965 ps
CPU time 0.81 seconds
Started Jan 03 01:03:40 PM PST 24
Finished Jan 03 01:04:35 PM PST 24
Peak memory 200780 kb
Host smart-69327dbd-0721-4f14-967d-fb22f8d1a883
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787243388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.clkmgr_div_intersig_mubi.787243388
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.3458055090
Short name T710
Test name
Test status
Simulation time 44017794 ps
CPU time 0.83 seconds
Started Jan 03 01:04:10 PM PST 24
Finished Jan 03 01:05:20 PM PST 24
Peak memory 200740 kb
Host smart-50141a64-9804-433e-8a44-45840470ea60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458055090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.3458055090
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.1617058583
Short name T782
Test name
Test status
Simulation time 226960825 ps
CPU time 1.55 seconds
Started Jan 03 01:04:10 PM PST 24
Finished Jan 03 01:05:20 PM PST 24
Peak memory 200776 kb
Host smart-2cca0b00-9d36-4dcd-8f32-bf281b48bc5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617058583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.1617058583
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.3398577231
Short name T834
Test name
Test status
Simulation time 2058245247 ps
CPU time 13.52 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:43 PM PST 24
Peak memory 201052 kb
Host smart-aeb11ff1-5163-4805-b58a-4cf1ad818de5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398577231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.3398577231
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.4089356295
Short name T456
Test name
Test status
Simulation time 70107856 ps
CPU time 1.09 seconds
Started Jan 03 01:04:07 PM PST 24
Finished Jan 03 01:05:14 PM PST 24
Peak memory 200620 kb
Host smart-118a3c9a-a5f5-4ea3-b6eb-3a4ddfb74fcf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089356295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.4089356295
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.984688427
Short name T163
Test name
Test status
Simulation time 27676358 ps
CPU time 0.8 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:05:05 PM PST 24
Peak memory 200732 kb
Host smart-a1056c67-937c-443f-ad46-45c9efdb22c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984688427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.clkmgr_lc_clk_byp_req_intersig_mubi.984688427
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.1788714869
Short name T302
Test name
Test status
Simulation time 12499415 ps
CPU time 0.72 seconds
Started Jan 03 01:04:18 PM PST 24
Finished Jan 03 01:05:34 PM PST 24
Peak memory 200608 kb
Host smart-74c677cd-a894-4461-b05a-42f5be82fa38
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788714869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.1788714869
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.3906550649
Short name T320
Test name
Test status
Simulation time 14604711 ps
CPU time 0.71 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:05:28 PM PST 24
Peak memory 200636 kb
Host smart-8b034d58-8069-4185-9b3a-cd8441b453cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906550649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3906550649
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.2270652506
Short name T463
Test name
Test status
Simulation time 836880239 ps
CPU time 3.76 seconds
Started Jan 03 01:03:28 PM PST 24
Finished Jan 03 01:04:28 PM PST 24
Peak memory 200868 kb
Host smart-72e2da36-e8ff-4b4d-9af0-6e95241e5ae7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270652506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2270652506
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.2105390094
Short name T611
Test name
Test status
Simulation time 68070843 ps
CPU time 0.95 seconds
Started Jan 03 01:04:27 PM PST 24
Finished Jan 03 01:05:50 PM PST 24
Peak memory 200748 kb
Host smart-859c990c-f584-43d9-8377-c7a7d17fdb1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105390094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.2105390094
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.3746420006
Short name T146
Test name
Test status
Simulation time 3418767250 ps
CPU time 13.59 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:49 PM PST 24
Peak memory 201048 kb
Host smart-685d6591-ef93-4d18-a28e-5dffd0d8aef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746420006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.3746420006
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.1645556215
Short name T754
Test name
Test status
Simulation time 54864839089 ps
CPU time 520.64 seconds
Started Jan 03 01:03:37 PM PST 24
Finished Jan 03 01:13:11 PM PST 24
Peak memory 217528 kb
Host smart-85cea0cb-930f-4bc4-8a40-8991debe7e27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1645556215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.1645556215
Directory /workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.clkmgr_trans.1352003823
Short name T477
Test name
Test status
Simulation time 14542926 ps
CPU time 0.76 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:44 PM PST 24
Peak memory 200632 kb
Host smart-b63b735f-e662-40ea-906d-663bfcd5ae16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352003823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.1352003823
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.889508411
Short name T391
Test name
Test status
Simulation time 57645374 ps
CPU time 0.92 seconds
Started Jan 03 01:02:38 PM PST 24
Finished Jan 03 01:03:45 PM PST 24
Peak memory 200756 kb
Host smart-965cf1eb-a1a4-4b1b-85fc-86c288612ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889508411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_alert_test.889508411
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2779842826
Short name T560
Test name
Test status
Simulation time 23925883 ps
CPU time 0.84 seconds
Started Jan 03 01:02:45 PM PST 24
Finished Jan 03 01:03:52 PM PST 24
Peak memory 200792 kb
Host smart-9c404508-7c50-4269-b6b2-edef9492a747
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779842826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.2779842826
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.1519440903
Short name T716
Test name
Test status
Simulation time 20282774 ps
CPU time 0.74 seconds
Started Jan 03 01:02:32 PM PST 24
Finished Jan 03 01:03:40 PM PST 24
Peak memory 200464 kb
Host smart-6ab796cf-4bb4-48f8-b7f9-099611b5b111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519440903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1519440903
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.2830175965
Short name T392
Test name
Test status
Simulation time 42781750 ps
CPU time 0.89 seconds
Started Jan 03 01:02:53 PM PST 24
Finished Jan 03 01:03:58 PM PST 24
Peak memory 200760 kb
Host smart-1179ae65-adf9-4dfe-bb2f-668dbadeb7f6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830175965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.2830175965
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.3903893976
Short name T502
Test name
Test status
Simulation time 219597255 ps
CPU time 1.4 seconds
Started Jan 03 01:02:52 PM PST 24
Finished Jan 03 01:03:58 PM PST 24
Peak memory 200732 kb
Host smart-d4c4b4d1-d496-4fab-9b9e-2a3088ada373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903893976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.3903893976
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.141250980
Short name T753
Test name
Test status
Simulation time 875588584 ps
CPU time 3.92 seconds
Started Jan 03 01:02:46 PM PST 24
Finished Jan 03 01:03:56 PM PST 24
Peak memory 200732 kb
Host smart-44801d12-ac39-4268-a84a-f4fd2b37ac0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141250980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.141250980
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.2470110107
Short name T985
Test name
Test status
Simulation time 1474286540 ps
CPU time 6.09 seconds
Started Jan 03 01:02:41 PM PST 24
Finished Jan 03 01:03:52 PM PST 24
Peak memory 200792 kb
Host smart-18cd0edb-f85c-4cc7-9415-87a4050c0305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470110107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.2470110107
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.1487167615
Short name T769
Test name
Test status
Simulation time 31373012 ps
CPU time 0.94 seconds
Started Jan 03 01:02:36 PM PST 24
Finished Jan 03 01:03:44 PM PST 24
Peak memory 200716 kb
Host smart-269f32b2-3d9c-47a9-a012-d217347a1759
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487167615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.1487167615
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.4135568712
Short name T143
Test name
Test status
Simulation time 19724384 ps
CPU time 0.81 seconds
Started Jan 03 01:02:30 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 200704 kb
Host smart-4bd29dbf-afbf-48b1-9f62-c9badc499b37
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135568712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.4135568712
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3567827283
Short name T934
Test name
Test status
Simulation time 51446780 ps
CPU time 0.97 seconds
Started Jan 03 01:02:43 PM PST 24
Finished Jan 03 01:03:50 PM PST 24
Peak memory 200656 kb
Host smart-c84eb1cb-ac99-4e42-83a5-69b79097715d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567827283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.3567827283
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.2804396361
Short name T674
Test name
Test status
Simulation time 17160191 ps
CPU time 0.75 seconds
Started Jan 03 01:02:32 PM PST 24
Finished Jan 03 01:03:40 PM PST 24
Peak memory 200588 kb
Host smart-a8504eae-8ab4-4ec7-b119-7f5546c82bf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804396361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2804396361
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.3690403882
Short name T66
Test name
Test status
Simulation time 620904681 ps
CPU time 3.74 seconds
Started Jan 03 01:02:32 PM PST 24
Finished Jan 03 01:03:43 PM PST 24
Peak memory 216732 kb
Host smart-627cf7c0-ea03-4513-8f37-873a93a662ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690403882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.3690403882
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.3223986568
Short name T512
Test name
Test status
Simulation time 69086371 ps
CPU time 1.03 seconds
Started Jan 03 01:02:55 PM PST 24
Finished Jan 03 01:04:00 PM PST 24
Peak memory 200768 kb
Host smart-e58d6b31-7dc9-4b12-8a52-c95d005b427e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223986568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3223986568
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.3511325316
Short name T375
Test name
Test status
Simulation time 1569767807 ps
CPU time 7.25 seconds
Started Jan 03 01:02:30 PM PST 24
Finished Jan 03 01:03:45 PM PST 24
Peak memory 200944 kb
Host smart-64b40ab7-0e24-4885-926f-72b44e9d1977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511325316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.3511325316
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.2713112232
Short name T151
Test name
Test status
Simulation time 25790383778 ps
CPU time 370.47 seconds
Started Jan 03 01:02:31 PM PST 24
Finished Jan 03 01:09:48 PM PST 24
Peak memory 217500 kb
Host smart-c1676aca-1e2d-4372-b0ee-0ee2694d9dfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2713112232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.2713112232
Directory /workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.clkmgr_trans.2345562565
Short name T795
Test name
Test status
Simulation time 32334536 ps
CPU time 0.75 seconds
Started Jan 03 01:02:36 PM PST 24
Finished Jan 03 01:03:43 PM PST 24
Peak memory 200812 kb
Host smart-4be95600-02a6-4b4e-8466-bbee9068c915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345562565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2345562565
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.1903940533
Short name T744
Test name
Test status
Simulation time 20064743 ps
CPU time 0.73 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:22 PM PST 24
Peak memory 200736 kb
Host smart-3bddbecc-b177-4c9f-869d-4229eb5df427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903940533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.1903940533
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.2449509275
Short name T365
Test name
Test status
Simulation time 94713163 ps
CPU time 1 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 200776 kb
Host smart-d6b95d07-8a92-419a-9ddf-4b854063a06d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449509275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.2449509275
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.678894146
Short name T976
Test name
Test status
Simulation time 37115301 ps
CPU time 0.78 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 199296 kb
Host smart-3ad2ee64-edf7-4e55-87a0-7103907853d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678894146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.678894146
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.786535086
Short name T457
Test name
Test status
Simulation time 154664940 ps
CPU time 1.23 seconds
Started Jan 03 01:03:52 PM PST 24
Finished Jan 03 01:04:50 PM PST 24
Peak memory 200680 kb
Host smart-91578cbc-d9ef-4c3f-aba0-3164fad272fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786535086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_div_intersig_mubi.786535086
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.353207669
Short name T870
Test name
Test status
Simulation time 46814349 ps
CPU time 0.78 seconds
Started Jan 03 01:03:27 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200632 kb
Host smart-1379bcbb-1cf0-433a-b2f1-bef323480918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353207669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.353207669
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.2835933419
Short name T118
Test name
Test status
Simulation time 1856874448 ps
CPU time 6.73 seconds
Started Jan 03 01:03:30 PM PST 24
Finished Jan 03 01:04:33 PM PST 24
Peak memory 200652 kb
Host smart-9d0cc0b1-18cf-43d6-b893-65629261db54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835933419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2835933419
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.3021533402
Short name T355
Test name
Test status
Simulation time 866203089 ps
CPU time 4.65 seconds
Started Jan 03 01:03:28 PM PST 24
Finished Jan 03 01:04:29 PM PST 24
Peak memory 200772 kb
Host smart-f94877d9-3c2c-4197-9b4e-a0454a391cff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021533402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.3021533402
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.1477045503
Short name T864
Test name
Test status
Simulation time 118958266 ps
CPU time 1.18 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:35 PM PST 24
Peak memory 200748 kb
Host smart-76941295-421c-4d77-886c-3edf1d4f9016
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477045503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.1477045503
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.1037701974
Short name T724
Test name
Test status
Simulation time 98573505 ps
CPU time 1.02 seconds
Started Jan 03 01:03:46 PM PST 24
Finished Jan 03 01:04:43 PM PST 24
Peak memory 200776 kb
Host smart-684b1876-6c0d-4e47-93d4-2dc30c7b149d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037701974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.1037701974
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3527911873
Short name T475
Test name
Test status
Simulation time 38591288 ps
CPU time 0.87 seconds
Started Jan 03 01:03:49 PM PST 24
Finished Jan 03 01:04:46 PM PST 24
Peak memory 200832 kb
Host smart-49336365-5fb8-4a90-a0f1-aec7df1749f3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527911873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.3527911873
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.36911970
Short name T526
Test name
Test status
Simulation time 44578210 ps
CPU time 0.8 seconds
Started Jan 03 01:03:43 PM PST 24
Finished Jan 03 01:04:37 PM PST 24
Peak memory 200748 kb
Host smart-9506146e-b166-4560-a6bb-b29e9970eafa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36911970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.36911970
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.1237823762
Short name T906
Test name
Test status
Simulation time 681199986 ps
CPU time 2.71 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:46 PM PST 24
Peak memory 200920 kb
Host smart-de14a272-852c-4924-89f9-15e43052acd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237823762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1237823762
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.309337192
Short name T715
Test name
Test status
Simulation time 18249668 ps
CPU time 0.8 seconds
Started Jan 03 01:03:40 PM PST 24
Finished Jan 03 01:04:34 PM PST 24
Peak memory 200672 kb
Host smart-8a6732d7-944a-44f7-ba2f-eb21c1171b2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309337192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.309337192
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.476455916
Short name T689
Test name
Test status
Simulation time 1013728987 ps
CPU time 7.76 seconds
Started Jan 03 01:03:52 PM PST 24
Finished Jan 03 01:04:58 PM PST 24
Peak memory 201080 kb
Host smart-f50f4b3e-2ef2-4aee-890a-c166fd73ac69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476455916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.476455916
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.4217275106
Short name T579
Test name
Test status
Simulation time 23755313953 ps
CPU time 294.12 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:09:58 PM PST 24
Peak memory 215360 kb
Host smart-48060256-c50c-4602-a496-269d61f1351e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4217275106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.4217275106
Directory /workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.clkmgr_trans.2087182505
Short name T567
Test name
Test status
Simulation time 19093189 ps
CPU time 0.79 seconds
Started Jan 03 01:03:49 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 200704 kb
Host smart-19e66392-6c96-4958-9821-5da73fa2e4ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087182505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.2087182505
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.1631792330
Short name T474
Test name
Test status
Simulation time 26391304 ps
CPU time 0.74 seconds
Started Jan 03 01:04:04 PM PST 24
Finished Jan 03 01:05:12 PM PST 24
Peak memory 200772 kb
Host smart-2e4640e3-5e4c-41af-a7f2-5706b9e596c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631792330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.1631792330
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3504372755
Short name T806
Test name
Test status
Simulation time 38314411 ps
CPU time 0.88 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:21 PM PST 24
Peak memory 200752 kb
Host smart-483b34d6-c304-47d8-ad09-289bdef36c90
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504372755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.3504372755
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.2275872532
Short name T614
Test name
Test status
Simulation time 99417433 ps
CPU time 0.9 seconds
Started Jan 03 01:03:59 PM PST 24
Finished Jan 03 01:05:02 PM PST 24
Peak memory 199712 kb
Host smart-85f8f7d0-5beb-4b2d-82a8-5fc81ec55e78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275872532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.2275872532
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.3091107858
Short name T851
Test name
Test status
Simulation time 21619170 ps
CPU time 0.79 seconds
Started Jan 03 01:04:07 PM PST 24
Finished Jan 03 01:05:15 PM PST 24
Peak memory 200796 kb
Host smart-f5e69dc6-cd33-4c0c-843c-703b6b1475a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091107858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.3091107858
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.2390719506
Short name T508
Test name
Test status
Simulation time 17349305 ps
CPU time 0.76 seconds
Started Jan 03 01:03:57 PM PST 24
Finished Jan 03 01:04:57 PM PST 24
Peak memory 200720 kb
Host smart-ff720880-7f97-4c92-b4e3-bc540f03b9b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390719506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.2390719506
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.2514224304
Short name T17
Test name
Test status
Simulation time 681622358 ps
CPU time 5.62 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 200784 kb
Host smart-7bb9464e-5733-438e-99f2-f902c2b4e3b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514224304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2514224304
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.4036184493
Short name T607
Test name
Test status
Simulation time 867130871 ps
CPU time 4.52 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:21 PM PST 24
Peak memory 200808 kb
Host smart-12cad47e-386f-44f6-93c8-dfadff90c236
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036184493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.4036184493
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.542084433
Short name T941
Test name
Test status
Simulation time 117185946 ps
CPU time 1.3 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:13 PM PST 24
Peak memory 200720 kb
Host smart-6b7edac2-9632-4e13-ad32-ce3044b93e89
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542084433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.clkmgr_idle_intersig_mubi.542084433
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.206348765
Short name T951
Test name
Test status
Simulation time 55595157 ps
CPU time 0.86 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:12 PM PST 24
Peak memory 200804 kb
Host smart-2db3b6de-e5a2-4aba-b3dc-379b36d8d542
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206348765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.clkmgr_lc_clk_byp_req_intersig_mubi.206348765
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.407223899
Short name T380
Test name
Test status
Simulation time 32143272 ps
CPU time 0.8 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:18 PM PST 24
Peak memory 200696 kb
Host smart-a7c1b3a0-8ee4-41f8-85a4-8f6cb166cc45
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407223899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.clkmgr_lc_ctrl_intersig_mubi.407223899
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.4284771339
Short name T389
Test name
Test status
Simulation time 41151370 ps
CPU time 0.78 seconds
Started Jan 03 01:04:10 PM PST 24
Finished Jan 03 01:05:20 PM PST 24
Peak memory 200656 kb
Host smart-ca19acdb-9b5e-4783-998b-22a0fef46949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284771339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.4284771339
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.3146424345
Short name T886
Test name
Test status
Simulation time 480566857 ps
CPU time 2.49 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:21 PM PST 24
Peak memory 200684 kb
Host smart-3a6dc4ca-9c29-4cc6-ba9e-2bd222e531a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146424345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.3146424345
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.1086495518
Short name T443
Test name
Test status
Simulation time 47809880 ps
CPU time 0.93 seconds
Started Jan 03 01:04:04 PM PST 24
Finished Jan 03 01:05:09 PM PST 24
Peak memory 200748 kb
Host smart-2a81bf32-f286-4b23-8214-26c24ea794a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086495518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.1086495518
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.1051590576
Short name T61
Test name
Test status
Simulation time 4941741336 ps
CPU time 19.72 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:48 PM PST 24
Peak memory 201100 kb
Host smart-dfff8443-f9bd-40fd-bb09-8a0b395a410b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051590576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.1051590576
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.2351832977
Short name T617
Test name
Test status
Simulation time 68713304684 ps
CPU time 375.96 seconds
Started Jan 03 01:04:37 PM PST 24
Finished Jan 03 01:12:13 PM PST 24
Peak memory 217544 kb
Host smart-6b2af967-6bcf-4db9-884f-f34d9c04766f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2351832977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.2351832977
Directory /workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.clkmgr_trans.440178900
Short name T116
Test name
Test status
Simulation time 20152564 ps
CPU time 0.83 seconds
Started Jan 03 01:04:07 PM PST 24
Finished Jan 03 01:05:14 PM PST 24
Peak memory 200812 kb
Host smart-e488ecb0-2213-47a5-a624-70af4755fda4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440178900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.440178900
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.3164396188
Short name T793
Test name
Test status
Simulation time 112414321 ps
CPU time 1.09 seconds
Started Jan 03 01:03:46 PM PST 24
Finished Jan 03 01:04:42 PM PST 24
Peak memory 200796 kb
Host smart-29510b5d-703b-4e28-bea6-d535337a9f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164396188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.3164396188
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.931924171
Short name T553
Test name
Test status
Simulation time 41432075 ps
CPU time 0.79 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:35 PM PST 24
Peak memory 200804 kb
Host smart-26ab9428-1478-4798-b4f9-76a084bb13a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931924171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.931924171
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.3320871894
Short name T686
Test name
Test status
Simulation time 14626597 ps
CPU time 0.71 seconds
Started Jan 03 01:03:40 PM PST 24
Finished Jan 03 01:04:33 PM PST 24
Peak memory 199688 kb
Host smart-5e258161-dc91-421f-a63b-69737bfd7f1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320871894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.3320871894
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.2454560794
Short name T594
Test name
Test status
Simulation time 14217582 ps
CPU time 0.71 seconds
Started Jan 03 01:03:44 PM PST 24
Finished Jan 03 01:04:38 PM PST 24
Peak memory 200760 kb
Host smart-5b720c73-c2bc-482c-8806-47871e300b7f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454560794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.2454560794
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.1857014111
Short name T437
Test name
Test status
Simulation time 22425037 ps
CPU time 0.72 seconds
Started Jan 03 01:04:33 PM PST 24
Finished Jan 03 01:05:53 PM PST 24
Peak memory 200780 kb
Host smart-54e88b3f-2cad-4617-b800-396e0c24272b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857014111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.1857014111
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.3424121494
Short name T943
Test name
Test status
Simulation time 318654353 ps
CPU time 2.96 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:45 PM PST 24
Peak memory 200648 kb
Host smart-7538cf1a-1992-430b-8c58-b91729d14b69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424121494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3424121494
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.1923045538
Short name T948
Test name
Test status
Simulation time 1700429786 ps
CPU time 12.16 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:26 PM PST 24
Peak memory 200700 kb
Host smart-965d363a-dac0-4e48-a9be-7db50060de1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923045538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.1923045538
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.4202618914
Short name T929
Test name
Test status
Simulation time 35013678 ps
CPU time 0.98 seconds
Started Jan 03 01:03:28 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 200756 kb
Host smart-cb96ae7b-2fd2-4eda-9bf8-f8874a56f370
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202618914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.4202618914
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2037020546
Short name T703
Test name
Test status
Simulation time 22483270 ps
CPU time 0.81 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:05:05 PM PST 24
Peak memory 200828 kb
Host smart-9852b853-ead6-4f41-9973-09ef2c684b32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037020546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.2037020546
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.3154474603
Short name T938
Test name
Test status
Simulation time 58722373 ps
CPU time 0.93 seconds
Started Jan 03 01:03:43 PM PST 24
Finished Jan 03 01:04:37 PM PST 24
Peak memory 200812 kb
Host smart-64144109-a5bf-4e9b-8530-04992176a5e6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154474603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.3154474603
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.1766790244
Short name T308
Test name
Test status
Simulation time 24132037 ps
CPU time 0.77 seconds
Started Jan 03 01:03:32 PM PST 24
Finished Jan 03 01:04:27 PM PST 24
Peak memory 200732 kb
Host smart-57a1166c-e70d-4df1-be80-1e08b0365d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766790244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.1766790244
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.2476783839
Short name T695
Test name
Test status
Simulation time 481066119 ps
CPU time 2.44 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:04:58 PM PST 24
Peak memory 200708 kb
Host smart-f2d7af18-9a4a-439f-8af4-dfb7e5257404
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476783839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2476783839
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.476095299
Short name T736
Test name
Test status
Simulation time 51914433 ps
CPU time 0.88 seconds
Started Jan 03 01:04:36 PM PST 24
Finished Jan 03 01:06:16 PM PST 24
Peak memory 200788 kb
Host smart-00f57662-f512-491b-bb9e-71c68d862228
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476095299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.476095299
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.614621595
Short name T473
Test name
Test status
Simulation time 2207736288 ps
CPU time 9.54 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 201036 kb
Host smart-fc054f9e-0700-4a60-a09a-f8627627cff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614621595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.614621595
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.2174229445
Short name T673
Test name
Test status
Simulation time 20836062775 ps
CPU time 368.53 seconds
Started Jan 03 01:03:34 PM PST 24
Finished Jan 03 01:10:36 PM PST 24
Peak memory 217500 kb
Host smart-f1d84246-2094-4303-99c9-e2c713e33425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2174229445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.2174229445
Directory /workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_trans.2705637199
Short name T420
Test name
Test status
Simulation time 214586876 ps
CPU time 1.49 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:04:56 PM PST 24
Peak memory 200756 kb
Host smart-ee0e9cb5-6f73-49e0-bb8c-cce6a4a99a76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705637199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.2705637199
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.381986888
Short name T349
Test name
Test status
Simulation time 13249968 ps
CPU time 0.73 seconds
Started Jan 03 01:03:37 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 200760 kb
Host smart-044d230a-5b39-4a8c-aaa6-5f1a102cafa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381986888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkm
gr_alert_test.381986888
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.2872121303
Short name T447
Test name
Test status
Simulation time 124664449 ps
CPU time 1.15 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:04:55 PM PST 24
Peak memory 200760 kb
Host smart-60e6c03c-ef11-4459-9200-2f57343c5121
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872121303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.2872121303
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.1276023208
Short name T499
Test name
Test status
Simulation time 44834603 ps
CPU time 0.77 seconds
Started Jan 03 01:03:49 PM PST 24
Finished Jan 03 01:04:46 PM PST 24
Peak memory 199696 kb
Host smart-65f487e0-3dfb-4937-b903-56971466480a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276023208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.1276023208
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.2827512759
Short name T482
Test name
Test status
Simulation time 103955692 ps
CPU time 1.12 seconds
Started Jan 03 01:03:50 PM PST 24
Finished Jan 03 01:04:48 PM PST 24
Peak memory 200720 kb
Host smart-a788f256-b8cc-4068-81e9-8c8b8215f32a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827512759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.2827512759
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.1821695740
Short name T848
Test name
Test status
Simulation time 17980051 ps
CPU time 0.76 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200616 kb
Host smart-83a798ac-23bd-4755-adf6-c81c6573a0c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821695740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.1821695740
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.1166856129
Short name T609
Test name
Test status
Simulation time 1576924387 ps
CPU time 6.99 seconds
Started Jan 03 01:03:28 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 200608 kb
Host smart-1f971bb7-cf71-4856-a183-fa886ea05256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166856129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.1166856129
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.3621739745
Short name T534
Test name
Test status
Simulation time 1099689618 ps
CPU time 8.31 seconds
Started Jan 03 01:03:46 PM PST 24
Finished Jan 03 01:04:50 PM PST 24
Peak memory 200820 kb
Host smart-2925b2f3-9935-43c6-ac36-167f464070ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621739745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.3621739745
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.3529529678
Short name T677
Test name
Test status
Simulation time 77053105 ps
CPU time 1.05 seconds
Started Jan 03 01:03:49 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 200708 kb
Host smart-4e7f0df7-76ae-436e-846a-737a1adccdc0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529529678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.3529529678
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3321509831
Short name T423
Test name
Test status
Simulation time 169468722 ps
CPU time 1.2 seconds
Started Jan 03 01:03:49 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 200752 kb
Host smart-315c8d4a-7bc2-4b3d-a65d-01d64b9e34ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321509831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.3321509831
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.2796778164
Short name T554
Test name
Test status
Simulation time 27242053 ps
CPU time 0.9 seconds
Started Jan 03 01:03:36 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 200664 kb
Host smart-4027f481-a10d-410c-88e9-d122c292981a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796778164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.2796778164
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.2916150420
Short name T18
Test name
Test status
Simulation time 12204553 ps
CPU time 0.7 seconds
Started Jan 03 01:03:49 PM PST 24
Finished Jan 03 01:04:46 PM PST 24
Peak memory 200680 kb
Host smart-fd10cf57-1a8e-4535-85d8-a609be226b6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916150420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.2916150420
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.2930097746
Short name T573
Test name
Test status
Simulation time 870906263 ps
CPU time 5.16 seconds
Started Jan 03 01:03:29 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 200924 kb
Host smart-2639236a-4244-42e9-8968-390a2f9bff0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930097746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.2930097746
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.1112054778
Short name T700
Test name
Test status
Simulation time 69513590 ps
CPU time 0.94 seconds
Started Jan 03 01:03:43 PM PST 24
Finished Jan 03 01:04:37 PM PST 24
Peak memory 200824 kb
Host smart-181130bc-a2c3-4b5f-a155-d79313efbbab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112054778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.1112054778
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.1754755262
Short name T788
Test name
Test status
Simulation time 4881208356 ps
CPU time 35.14 seconds
Started Jan 03 01:03:28 PM PST 24
Finished Jan 03 01:05:00 PM PST 24
Peak memory 201060 kb
Host smart-2a18991d-441b-4273-a431-79a529a49894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754755262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.1754755262
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.1637815728
Short name T687
Test name
Test status
Simulation time 180864525806 ps
CPU time 1235.36 seconds
Started Jan 03 01:03:43 PM PST 24
Finished Jan 03 01:25:11 PM PST 24
Peak memory 215744 kb
Host smart-9fc2544a-89ee-4c68-ad2c-92753050241e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1637815728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.1637815728
Directory /workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.clkmgr_trans.850235526
Short name T995
Test name
Test status
Simulation time 17361668 ps
CPU time 0.73 seconds
Started Jan 03 01:03:57 PM PST 24
Finished Jan 03 01:04:58 PM PST 24
Peak memory 200812 kb
Host smart-1f351f9d-d671-4d59-82b3-99296f50326a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850235526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.850235526
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.2802331170
Short name T41
Test name
Test status
Simulation time 23005453 ps
CPU time 0.75 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:35 PM PST 24
Peak memory 200740 kb
Host smart-d7e2fb0e-e31e-4fe1-8d55-d643224d31d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802331170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.2802331170
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.1226010261
Short name T20
Test name
Test status
Simulation time 74350080 ps
CPU time 1.01 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:35 PM PST 24
Peak memory 200832 kb
Host smart-570fc564-7bee-41e0-af92-efddc4dd082e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226010261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.1226010261
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.3966594203
Short name T810
Test name
Test status
Simulation time 46464844 ps
CPU time 0.77 seconds
Started Jan 03 01:03:46 PM PST 24
Finished Jan 03 01:04:40 PM PST 24
Peak memory 199660 kb
Host smart-8d00c184-9753-411a-8319-5bcc1b3bcd8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966594203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.3966594203
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.653261931
Short name T888
Test name
Test status
Simulation time 21646639 ps
CPU time 0.81 seconds
Started Jan 03 01:03:42 PM PST 24
Finished Jan 03 01:04:36 PM PST 24
Peak memory 200568 kb
Host smart-d830e8d2-972f-4cc0-a034-6313dfbc9468
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653261931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.clkmgr_div_intersig_mubi.653261931
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.2201757870
Short name T562
Test name
Test status
Simulation time 34144405 ps
CPU time 0.8 seconds
Started Jan 03 01:03:30 PM PST 24
Finished Jan 03 01:04:26 PM PST 24
Peak memory 200740 kb
Host smart-e3a386c8-acef-46ad-b495-006231052bc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201757870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.2201757870
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.1061752920
Short name T360
Test name
Test status
Simulation time 2000904189 ps
CPU time 15.53 seconds
Started Jan 03 01:03:45 PM PST 24
Finished Jan 03 01:04:54 PM PST 24
Peak memory 200920 kb
Host smart-31aa1bc0-7424-4677-829b-dd110cd689ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061752920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.1061752920
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.2333867575
Short name T756
Test name
Test status
Simulation time 617817568 ps
CPU time 3.8 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:38 PM PST 24
Peak memory 200940 kb
Host smart-fb3309b7-c47f-4ef4-b6a1-ccf74b6974a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333867575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.2333867575
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.147969220
Short name T412
Test name
Test status
Simulation time 21989155 ps
CPU time 0.71 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:05:07 PM PST 24
Peak memory 200708 kb
Host smart-3b056d63-45c0-43f6-a8b8-d49b189ab4ea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147969220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.clkmgr_idle_intersig_mubi.147969220
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1321344327
Short name T69
Test name
Test status
Simulation time 43673455 ps
CPU time 0.81 seconds
Started Jan 03 01:03:47 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200744 kb
Host smart-9582858d-c7e2-4019-ae94-096c616f7474
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321344327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.1321344327
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.2391361608
Short name T922
Test name
Test status
Simulation time 22619571 ps
CPU time 0.83 seconds
Started Jan 03 01:03:50 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 200728 kb
Host smart-81fd2d46-dd71-490c-9fd3-266354e49ddf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391361608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.2391361608
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.3260557784
Short name T802
Test name
Test status
Simulation time 13189587 ps
CPU time 0.68 seconds
Started Jan 03 01:03:42 PM PST 24
Finished Jan 03 01:04:35 PM PST 24
Peak memory 200620 kb
Host smart-115bdec9-48d1-46e6-aa21-9dea1de419ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260557784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3260557784
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.2109464322
Short name T404
Test name
Test status
Simulation time 913381523 ps
CPU time 4.13 seconds
Started Jan 03 01:03:50 PM PST 24
Finished Jan 03 01:04:51 PM PST 24
Peak memory 200924 kb
Host smart-7644b6e0-e624-4a1c-8728-d870124b0826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109464322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.2109464322
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.2490893624
Short name T388
Test name
Test status
Simulation time 18538038 ps
CPU time 0.77 seconds
Started Jan 03 01:03:47 PM PST 24
Finished Jan 03 01:04:43 PM PST 24
Peak memory 200824 kb
Host smart-8b1d441e-d461-430a-bd49-92d061885ce2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490893624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2490893624
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.1437920168
Short name T933
Test name
Test status
Simulation time 8654202421 ps
CPU time 35.64 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:05:30 PM PST 24
Peak memory 201068 kb
Host smart-58cf8419-b5be-40bb-b936-88c7a4945d92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437920168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.1437920168
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.2292815689
Short name T807
Test name
Test status
Simulation time 25630423625 ps
CPU time 245.23 seconds
Started Jan 03 01:03:49 PM PST 24
Finished Jan 03 01:08:50 PM PST 24
Peak memory 209440 kb
Host smart-4ac42b31-768f-47ca-b719-970e0aa4e2c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2292815689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.2292815689
Directory /workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.clkmgr_trans.2326785062
Short name T290
Test name
Test status
Simulation time 26635790 ps
CPU time 0.88 seconds
Started Jan 03 01:03:45 PM PST 24
Finished Jan 03 01:04:39 PM PST 24
Peak memory 200720 kb
Host smart-b42ea2fa-8350-4c59-bcb5-9c42062833fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326785062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2326785062
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.3763204196
Short name T962
Test name
Test status
Simulation time 49981741 ps
CPU time 0.82 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:35 PM PST 24
Peak memory 200756 kb
Host smart-ba2ce3e0-da1b-41c7-a310-7d8a8f5c9c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763204196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.3763204196
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.2404789718
Short name T433
Test name
Test status
Simulation time 52904312 ps
CPU time 0.79 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:04:56 PM PST 24
Peak memory 200796 kb
Host smart-70cc17cf-960d-40c5-9871-8889e7b7c0bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404789718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.2404789718
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.933398119
Short name T838
Test name
Test status
Simulation time 31223109 ps
CPU time 0.72 seconds
Started Jan 03 01:03:43 PM PST 24
Finished Jan 03 01:04:37 PM PST 24
Peak memory 199688 kb
Host smart-c216b6da-5265-4e70-bd19-1bfb6f6f5717
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933398119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.933398119
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.646608166
Short name T64
Test name
Test status
Simulation time 45427573 ps
CPU time 0.89 seconds
Started Jan 03 01:03:46 PM PST 24
Finished Jan 03 01:04:40 PM PST 24
Peak memory 200780 kb
Host smart-e0712da8-d262-4fd3-9270-ca9de14933c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646608166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_div_intersig_mubi.646608166
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.181776444
Short name T59
Test name
Test status
Simulation time 45493681 ps
CPU time 0.9 seconds
Started Jan 03 01:03:39 PM PST 24
Finished Jan 03 01:04:33 PM PST 24
Peak memory 200816 kb
Host smart-deea4dd8-899b-4ca0-92ee-b26d1f063a2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181776444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.181776444
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.3531111226
Short name T13
Test name
Test status
Simulation time 1158095016 ps
CPU time 9.25 seconds
Started Jan 03 01:03:42 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200492 kb
Host smart-1cc509c9-57de-4e03-9290-827c9ebaf91e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531111226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.3531111226
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.3638834711
Short name T658
Test name
Test status
Simulation time 1943731866 ps
CPU time 8.84 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200892 kb
Host smart-8a229cd1-c497-449c-9561-f67dc935a766
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638834711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.3638834711
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.3266844368
Short name T539
Test name
Test status
Simulation time 134024344 ps
CPU time 1.31 seconds
Started Jan 03 01:03:37 PM PST 24
Finished Jan 03 01:04:33 PM PST 24
Peak memory 200712 kb
Host smart-d3441bb0-9f62-4915-89fb-750f61a52ac8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266844368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.3266844368
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.4169756590
Short name T632
Test name
Test status
Simulation time 15070752 ps
CPU time 0.71 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:04 PM PST 24
Peak memory 200708 kb
Host smart-00e65b6e-664f-4197-be18-3f1a2186ef78
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169756590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.4169756590
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.966296042
Short name T310
Test name
Test status
Simulation time 25052390 ps
CPU time 0.86 seconds
Started Jan 03 01:03:43 PM PST 24
Finished Jan 03 01:04:37 PM PST 24
Peak memory 200696 kb
Host smart-5996e0af-de78-4228-8802-11f76ba8ccd5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966296042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.clkmgr_lc_ctrl_intersig_mubi.966296042
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.3785157748
Short name T704
Test name
Test status
Simulation time 13613189 ps
CPU time 0.73 seconds
Started Jan 03 01:03:46 PM PST 24
Finished Jan 03 01:04:40 PM PST 24
Peak memory 200648 kb
Host smart-d508ece6-9a00-4e92-b125-53d34164987c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785157748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.3785157748
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.195476379
Short name T476
Test name
Test status
Simulation time 797279318 ps
CPU time 4.83 seconds
Started Jan 03 01:03:29 PM PST 24
Finished Jan 03 01:04:30 PM PST 24
Peak memory 200860 kb
Host smart-52c04b72-eda8-4301-a688-c222c8e562dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195476379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.195476379
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.491950076
Short name T915
Test name
Test status
Simulation time 76293326 ps
CPU time 1 seconds
Started Jan 03 01:03:36 PM PST 24
Finished Jan 03 01:04:31 PM PST 24
Peak memory 200796 kb
Host smart-d297cb26-bf70-451f-ae72-5b54b5eedb54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491950076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.491950076
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.483343439
Short name T1
Test name
Test status
Simulation time 3033126241 ps
CPU time 13.56 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:16 PM PST 24
Peak memory 201008 kb
Host smart-3229779b-2561-40ee-aafb-6810a8eefedb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483343439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.483343439
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.3774373330
Short name T11
Test name
Test status
Simulation time 18279064415 ps
CPU time 126.14 seconds
Started Jan 03 01:03:39 PM PST 24
Finished Jan 03 01:06:38 PM PST 24
Peak memory 209312 kb
Host smart-62f1752d-8c9d-4d3c-a1c1-dc6678f9cacc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3774373330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.3774373330
Directory /workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.clkmgr_trans.2654561541
Short name T969
Test name
Test status
Simulation time 109186303 ps
CPU time 1.16 seconds
Started Jan 03 01:03:45 PM PST 24
Finished Jan 03 01:04:39 PM PST 24
Peak memory 200776 kb
Host smart-39a8499d-a4ae-4243-a2a0-53007f72bdf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654561541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.2654561541
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.4146598665
Short name T40
Test name
Test status
Simulation time 16047259 ps
CPU time 0.71 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:21 PM PST 24
Peak memory 200248 kb
Host smart-605ea7bd-de60-411e-9bd9-d3181758ef1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146598665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.4146598665
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.4062073803
Short name T768
Test name
Test status
Simulation time 21166037 ps
CPU time 0.79 seconds
Started Jan 03 01:03:44 PM PST 24
Finished Jan 03 01:04:39 PM PST 24
Peak memory 200808 kb
Host smart-4790dc79-8705-4ae7-bdef-6e651586c952
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062073803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.4062073803
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.2320959388
Short name T623
Test name
Test status
Simulation time 36262124 ps
CPU time 0.74 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:04:56 PM PST 24
Peak memory 199636 kb
Host smart-1fc567c5-7822-4975-914a-cbfc390c534f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320959388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.2320959388
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.2409046771
Short name T878
Test name
Test status
Simulation time 37035945 ps
CPU time 0.81 seconds
Started Jan 03 01:04:06 PM PST 24
Finished Jan 03 01:05:13 PM PST 24
Peak memory 200772 kb
Host smart-e72479a9-622f-494c-884d-6caf1dd3e4e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409046771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.2409046771
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.3559213163
Short name T723
Test name
Test status
Simulation time 51770371 ps
CPU time 0.96 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200800 kb
Host smart-861ae086-1be0-4579-962e-f863d168ece7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559213163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.3559213163
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.1101741972
Short name T431
Test name
Test status
Simulation time 919917911 ps
CPU time 7.23 seconds
Started Jan 03 01:03:47 PM PST 24
Finished Jan 03 01:04:50 PM PST 24
Peak memory 200704 kb
Host smart-28453c68-733f-49d9-baad-5e17ddc7105f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101741972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.1101741972
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.179774669
Short name T585
Test name
Test status
Simulation time 757318834 ps
CPU time 3.34 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 200800 kb
Host smart-a5b56390-bfca-4874-8980-cc09916cd8ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179774669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_ti
meout.179774669
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.2400085342
Short name T743
Test name
Test status
Simulation time 52557101 ps
CPU time 0.88 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 200780 kb
Host smart-7ca1be5c-7f86-47c6-a3cc-a40cb1de1335
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400085342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.2400085342
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.4150909522
Short name T435
Test name
Test status
Simulation time 14654955 ps
CPU time 0.73 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:19 PM PST 24
Peak memory 200704 kb
Host smart-1adb74cf-a8ed-4b53-99bd-2a18db0fcdce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150909522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.4150909522
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.753298303
Short name T71
Test name
Test status
Simulation time 106324071 ps
CPU time 0.95 seconds
Started Jan 03 01:03:44 PM PST 24
Finished Jan 03 01:04:39 PM PST 24
Peak memory 200696 kb
Host smart-86d3c9d8-2c3f-48e1-92aa-564d8cb96e6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753298303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.clkmgr_lc_ctrl_intersig_mubi.753298303
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.1893912310
Short name T72
Test name
Test status
Simulation time 15317585 ps
CPU time 0.74 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:45 PM PST 24
Peak memory 200592 kb
Host smart-8b6b494a-dad5-4278-880c-aadd1a313619
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893912310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.1893912310
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.4286090011
Short name T401
Test name
Test status
Simulation time 465840603 ps
CPU time 2.39 seconds
Started Jan 03 01:03:58 PM PST 24
Finished Jan 03 01:05:02 PM PST 24
Peak memory 200752 kb
Host smart-1830a6c1-3a0c-41bd-904c-a339614be0a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286090011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.4286090011
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.1203908145
Short name T115
Test name
Test status
Simulation time 120038309 ps
CPU time 1.09 seconds
Started Jan 03 01:03:40 PM PST 24
Finished Jan 03 01:04:35 PM PST 24
Peak memory 200732 kb
Host smart-606453bf-bb6a-47bd-bf2d-230a3a3b2e76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203908145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.1203908145
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.325758675
Short name T707
Test name
Test status
Simulation time 5661534791 ps
CPU time 19.94 seconds
Started Jan 03 01:03:51 PM PST 24
Finished Jan 03 01:05:08 PM PST 24
Peak memory 201140 kb
Host smart-99075e53-4441-48d0-b144-4cfc78cd6bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325758675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.325758675
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.1115094469
Short name T936
Test name
Test status
Simulation time 44088622785 ps
CPU time 694.65 seconds
Started Jan 03 01:04:12 PM PST 24
Finished Jan 03 01:16:56 PM PST 24
Peak memory 211348 kb
Host smart-74757c56-4850-4ac0-83af-79ab9b20616a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1115094469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.1115094469
Directory /workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.clkmgr_trans.100311641
Short name T603
Test name
Test status
Simulation time 21590585 ps
CPU time 0.76 seconds
Started Jan 03 01:03:52 PM PST 24
Finished Jan 03 01:04:51 PM PST 24
Peak memory 200728 kb
Host smart-f70ed349-f8b0-420b-9a10-413ba8661828
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100311641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.100311641
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.1421897935
Short name T39
Test name
Test status
Simulation time 28183329 ps
CPU time 0.77 seconds
Started Jan 03 01:03:51 PM PST 24
Finished Jan 03 01:04:49 PM PST 24
Peak memory 200780 kb
Host smart-3abf17d2-b676-434c-b845-9b54b4dc495d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421897935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.1421897935
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.3384731974
Short name T767
Test name
Test status
Simulation time 43341936 ps
CPU time 0.81 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200700 kb
Host smart-f90ed7a1-4d83-44fc-9402-37df8c2d28a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384731974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.3384731974
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.1160683430
Short name T876
Test name
Test status
Simulation time 16160989 ps
CPU time 0.69 seconds
Started Jan 03 01:04:02 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 200564 kb
Host smart-e2542668-818a-4d5f-b688-0682c8c2b129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160683430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1160683430
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3132835420
Short name T750
Test name
Test status
Simulation time 30159260 ps
CPU time 0.73 seconds
Started Jan 03 01:03:47 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200768 kb
Host smart-ba94eb7f-81ca-495f-93b6-77becc4de9fa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132835420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3132835420
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.3983484608
Short name T727
Test name
Test status
Simulation time 158174157 ps
CPU time 1.25 seconds
Started Jan 03 01:04:19 PM PST 24
Finished Jan 03 01:05:36 PM PST 24
Peak memory 200636 kb
Host smart-4463a2d9-77cd-4152-8214-d260f7b4f494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983484608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.3983484608
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.2239127784
Short name T479
Test name
Test status
Simulation time 2388148429 ps
CPU time 8.69 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:05:04 PM PST 24
Peak memory 201068 kb
Host smart-fef35966-baa8-4af2-bfd2-056507216bb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239127784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.2239127784
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.1666168788
Short name T394
Test name
Test status
Simulation time 1747152304 ps
CPU time 6.93 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:35 PM PST 24
Peak memory 200868 kb
Host smart-936919fe-2b4b-4f88-8ba8-bcd1587f270f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666168788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.1666168788
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.4004719285
Short name T581
Test name
Test status
Simulation time 41835540 ps
CPU time 0.92 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:04:54 PM PST 24
Peak memory 200700 kb
Host smart-99a2a043-0fd4-4a28-960a-75ad2bff5b51
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004719285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.4004719285
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.3493874738
Short name T751
Test name
Test status
Simulation time 16391244 ps
CPU time 0.75 seconds
Started Jan 03 01:03:50 PM PST 24
Finished Jan 03 01:04:48 PM PST 24
Peak memory 200780 kb
Host smart-86dda1a5-f071-4554-8e27-193b79c0bd45
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493874738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.3493874738
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.516602436
Short name T837
Test name
Test status
Simulation time 24252422 ps
CPU time 0.85 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:04:55 PM PST 24
Peak memory 200740 kb
Host smart-1f81af37-9219-4129-b25d-912d84d49413
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516602436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.clkmgr_lc_ctrl_intersig_mubi.516602436
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.2094794660
Short name T298
Test name
Test status
Simulation time 12870280 ps
CPU time 0.69 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:38 PM PST 24
Peak memory 200676 kb
Host smart-ea5491ab-9383-4f47-954d-d004a73e6bcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094794660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.2094794660
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.775846787
Short name T636
Test name
Test status
Simulation time 798324503 ps
CPU time 3.32 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:37 PM PST 24
Peak memory 200944 kb
Host smart-4deda378-9a92-457c-9f15-c3b79dd2f5eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775846787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.775846787
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.2311928223
Short name T693
Test name
Test status
Simulation time 80706787 ps
CPU time 1 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:31 PM PST 24
Peak memory 200872 kb
Host smart-1e8c11a8-1973-4332-bfdb-1407a350be38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311928223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.2311928223
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.4270656109
Short name T652
Test name
Test status
Simulation time 2818491696 ps
CPU time 20.46 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:05:14 PM PST 24
Peak memory 201040 kb
Host smart-28250aa3-f416-4257-9327-83f6b3f1f3d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270656109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.4270656109
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.1806388280
Short name T27
Test name
Test status
Simulation time 45153210585 ps
CPU time 846.09 seconds
Started Jan 03 01:03:38 PM PST 24
Finished Jan 03 01:18:38 PM PST 24
Peak memory 213340 kb
Host smart-e82e1c60-3d5c-46bc-8d39-f285578eac57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1806388280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.1806388280
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_trans.1586195091
Short name T741
Test name
Test status
Simulation time 26900980 ps
CPU time 0.89 seconds
Started Jan 03 01:04:20 PM PST 24
Finished Jan 03 01:05:38 PM PST 24
Peak memory 200876 kb
Host smart-bad31dbd-a428-48fa-b488-31c81f1d5254
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586195091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.1586195091
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.1599707587
Short name T613
Test name
Test status
Simulation time 36092195 ps
CPU time 0.86 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:25 PM PST 24
Peak memory 200692 kb
Host smart-181789d3-a216-407e-9891-f3d7a3d3b189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599707587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.1599707587
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.3660858338
Short name T640
Test name
Test status
Simulation time 59966668 ps
CPU time 0.9 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:25 PM PST 24
Peak memory 200676 kb
Host smart-9c2ad14f-9f45-4cdb-85d2-0cfeabff3563
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660858338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.3660858338
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.3295824417
Short name T44
Test name
Test status
Simulation time 109411145 ps
CPU time 0.93 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:21 PM PST 24
Peak memory 199604 kb
Host smart-6b5434d1-c6aa-4358-9399-eff70b0fde15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295824417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3295824417
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.1955038984
Short name T956
Test name
Test status
Simulation time 81922310 ps
CPU time 1.03 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200792 kb
Host smart-220b1477-0f20-48ca-8e7b-7dd0702d1c54
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955038984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.1955038984
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.122413718
Short name T509
Test name
Test status
Simulation time 163551686 ps
CPU time 1.29 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:04:58 PM PST 24
Peak memory 200692 kb
Host smart-d728a6e0-b67b-451f-b538-c819f6e89b4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122413718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.122413718
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.4169276904
Short name T529
Test name
Test status
Simulation time 2238596298 ps
CPU time 9.97 seconds
Started Jan 03 01:03:45 PM PST 24
Finished Jan 03 01:04:49 PM PST 24
Peak memory 200972 kb
Host smart-2ef92c39-9e1d-4306-8fbe-6e8ac28e25ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169276904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.4169276904
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.442433918
Short name T543
Test name
Test status
Simulation time 1004368764 ps
CPU time 4.23 seconds
Started Jan 03 01:03:57 PM PST 24
Finished Jan 03 01:05:01 PM PST 24
Peak memory 200848 kb
Host smart-3845efe6-d6fd-4f5c-bd6a-6fbef4dded29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442433918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_ti
meout.442433918
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.1363049400
Short name T483
Test name
Test status
Simulation time 17951038 ps
CPU time 0.77 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200632 kb
Host smart-5136a45c-c9f6-4dec-8e58-5e68c5c7375b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363049400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.1363049400
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.1266939898
Short name T378
Test name
Test status
Simulation time 25206209 ps
CPU time 0.83 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:20 PM PST 24
Peak memory 200604 kb
Host smart-7e3aaae5-1e63-4839-b6fd-7adb8080825e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266939898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.1266939898
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.1023864860
Short name T940
Test name
Test status
Simulation time 26066305 ps
CPU time 0.77 seconds
Started Jan 03 01:03:50 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 200632 kb
Host smart-419d6da4-a385-456c-aa79-dd6db313a4df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023864860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.1023864860
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.2713037505
Short name T892
Test name
Test status
Simulation time 1228844555 ps
CPU time 6.4 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:40 PM PST 24
Peak memory 200884 kb
Host smart-d511b9fa-ea7a-4f6b-ab9f-9dc4a5f4c252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713037505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2713037505
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.2891895863
Short name T323
Test name
Test status
Simulation time 16719102 ps
CPU time 0.79 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:04:55 PM PST 24
Peak memory 200756 kb
Host smart-ccca0de5-c9b3-4754-81ea-cea324cb73e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891895863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.2891895863
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.1536666665
Short name T367
Test name
Test status
Simulation time 4788403606 ps
CPU time 35.19 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:06:07 PM PST 24
Peak memory 200984 kb
Host smart-f936d387-cbe9-4515-85a4-7cec4fae0838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536666665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.1536666665
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.3805903441
Short name T855
Test name
Test status
Simulation time 43278808653 ps
CPU time 516.29 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:14:19 PM PST 24
Peak memory 217528 kb
Host smart-b262d983-2b37-499b-95e6-1e3883113143
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3805903441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.3805903441
Directory /workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.clkmgr_trans.3306255792
Short name T680
Test name
Test status
Simulation time 78018942 ps
CPU time 0.9 seconds
Started Jan 03 01:03:52 PM PST 24
Finished Jan 03 01:04:52 PM PST 24
Peak memory 200736 kb
Host smart-a6b87976-1e53-4b55-a603-3ce5ad0dcc91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306255792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3306255792
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.60390452
Short name T978
Test name
Test status
Simulation time 14620942 ps
CPU time 0.71 seconds
Started Jan 03 01:04:20 PM PST 24
Finished Jan 03 01:05:38 PM PST 24
Peak memory 200716 kb
Host smart-723e3884-f44c-4802-8e9f-39806b49e0a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60390452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmg
r_alert_test.60390452
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3340593632
Short name T764
Test name
Test status
Simulation time 75213077 ps
CPU time 0.97 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:12 PM PST 24
Peak memory 200816 kb
Host smart-cb90bed1-f2e0-4612-8a88-2045ab69e707
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340593632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.3340593632
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.2345111908
Short name T564
Test name
Test status
Simulation time 15899976 ps
CPU time 0.76 seconds
Started Jan 03 01:04:29 PM PST 24
Finished Jan 03 01:05:52 PM PST 24
Peak memory 199684 kb
Host smart-f9e6c9cb-a419-488f-a1f1-74d4cf9071ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345111908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2345111908
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.3076839325
Short name T379
Test name
Test status
Simulation time 20153105 ps
CPU time 0.78 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:32 PM PST 24
Peak memory 200744 kb
Host smart-cdb6e3c0-9c3b-4505-8db3-0fe3c7689e1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076839325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.3076839325
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.267486200
Short name T434
Test name
Test status
Simulation time 24298102 ps
CPU time 0.83 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:33 PM PST 24
Peak memory 200664 kb
Host smart-91fe277f-4a93-423f-b076-ece675b47b93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267486200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.267486200
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.2109801164
Short name T597
Test name
Test status
Simulation time 677116453 ps
CPU time 5.5 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:38 PM PST 24
Peak memory 200704 kb
Host smart-e80100f0-6b3a-41ce-b77c-9d9169bbd0bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109801164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2109801164
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.2184486636
Short name T728
Test name
Test status
Simulation time 1117422266 ps
CPU time 4.39 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:36 PM PST 24
Peak memory 200828 kb
Host smart-b4410a45-e3f4-4c9f-b2d6-ab01065e00ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184486636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.2184486636
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3760643193
Short name T800
Test name
Test status
Simulation time 46696530 ps
CPU time 0.92 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:05:28 PM PST 24
Peak memory 200804 kb
Host smart-2709de32-a0b8-4de4-b34d-70acdd1689f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760643193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.3760643193
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1639993877
Short name T112
Test name
Test status
Simulation time 19580625 ps
CPU time 0.77 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200748 kb
Host smart-d3cd7727-3e0d-4df5-b1ab-5a80b5bd4e67
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639993877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1639993877
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.3391332197
Short name T760
Test name
Test status
Simulation time 38112052 ps
CPU time 0.77 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:29 PM PST 24
Peak memory 200624 kb
Host smart-4653028a-e6cc-4bbd-be2d-095fe700b013
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391332197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.3391332197
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.176627674
Short name T569
Test name
Test status
Simulation time 14860918 ps
CPU time 0.69 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:40 PM PST 24
Peak memory 200556 kb
Host smart-18834f1b-84db-4067-ae32-b250b1007e8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176627674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.176627674
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.1676201596
Short name T8
Test name
Test status
Simulation time 824690813 ps
CPU time 4.73 seconds
Started Jan 03 01:04:18 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200972 kb
Host smart-585fb1ea-6dae-42ff-9078-6cf1b45ebb21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676201596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.1676201596
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.3692417723
Short name T307
Test name
Test status
Simulation time 22367271 ps
CPU time 0.85 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:40 PM PST 24
Peak memory 200824 kb
Host smart-b7c0d901-19b7-46f0-a86d-2fedc0c2d3bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692417723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.3692417723
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.3451259276
Short name T616
Test name
Test status
Simulation time 1309952053 ps
CPU time 5.13 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:47 PM PST 24
Peak memory 200816 kb
Host smart-bf1f491f-1a58-4f67-99ec-6f30885b6a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451259276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.3451259276
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.3211232912
Short name T824
Test name
Test status
Simulation time 16398571060 ps
CPU time 233.25 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:09:33 PM PST 24
Peak memory 217504 kb
Host smart-57d00c3c-5db7-498f-baad-4a50264fbfcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3211232912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.3211232912
Directory /workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.clkmgr_trans.966546381
Short name T496
Test name
Test status
Simulation time 30746576 ps
CPU time 0.91 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:12 PM PST 24
Peak memory 200804 kb
Host smart-911f3b9c-612b-492d-8f2c-5e040be12319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966546381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.966546381
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.536880952
Short name T811
Test name
Test status
Simulation time 27401589 ps
CPU time 0.78 seconds
Started Jan 03 01:02:29 PM PST 24
Finished Jan 03 01:03:37 PM PST 24
Peak memory 200772 kb
Host smart-56f93582-efd3-4bbe-b488-af6f7d178ccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536880952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_alert_test.536880952
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.22897261
Short name T332
Test name
Test status
Simulation time 21038555 ps
CPU time 0.78 seconds
Started Jan 03 01:02:29 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 200788 kb
Host smart-d5d23d3a-fcf2-4a1a-8fbb-99d6149dbf55
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.clkmgr_clk_handshake_intersig_mubi.22897261
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.2385739365
Short name T575
Test name
Test status
Simulation time 151311833 ps
CPU time 1.05 seconds
Started Jan 03 01:02:35 PM PST 24
Finished Jan 03 01:03:43 PM PST 24
Peak memory 199668 kb
Host smart-a6f804a9-c64f-474b-a017-9718a18841f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385739365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2385739365
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.1870008892
Short name T542
Test name
Test status
Simulation time 57431971 ps
CPU time 0.96 seconds
Started Jan 03 01:02:31 PM PST 24
Finished Jan 03 01:03:39 PM PST 24
Peak memory 200756 kb
Host smart-f808c5f2-d47a-4100-a6b2-bb711ccab579
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870008892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.1870008892
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.3353653793
Short name T842
Test name
Test status
Simulation time 30216551 ps
CPU time 0.81 seconds
Started Jan 03 01:02:27 PM PST 24
Finished Jan 03 01:03:36 PM PST 24
Peak memory 200668 kb
Host smart-c2c17e7a-f3c1-4161-9eaa-cac0bb7e9741
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353653793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.3353653793
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.345608808
Short name T472
Test name
Test status
Simulation time 2136043705 ps
CPU time 9.4 seconds
Started Jan 03 01:02:49 PM PST 24
Finished Jan 03 01:04:04 PM PST 24
Peak memory 200900 kb
Host smart-795c043a-53e5-4d69-b46f-bbfd50f7c3fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345608808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.345608808
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.414186388
Short name T438
Test name
Test status
Simulation time 1334865474 ps
CPU time 10.36 seconds
Started Jan 03 01:02:51 PM PST 24
Finished Jan 03 01:04:07 PM PST 24
Peak memory 200732 kb
Host smart-2f7dc367-794b-41c4-bf9d-ec9a1a5b2802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414186388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_tim
eout.414186388
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.4156667672
Short name T24
Test name
Test status
Simulation time 41367457 ps
CPU time 0.89 seconds
Started Jan 03 01:02:34 PM PST 24
Finished Jan 03 01:03:42 PM PST 24
Peak memory 200712 kb
Host smart-5205543e-c129-43c6-b264-179c484c58c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156667672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.4156667672
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.2930301072
Short name T959
Test name
Test status
Simulation time 32122742 ps
CPU time 0.86 seconds
Started Jan 03 01:02:29 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 200728 kb
Host smart-bb915837-5c4f-48c8-92ee-396be8a34cc5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930301072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.2930301072
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3935972958
Short name T755
Test name
Test status
Simulation time 21454357 ps
CPU time 0.8 seconds
Started Jan 03 01:02:37 PM PST 24
Finished Jan 03 01:03:44 PM PST 24
Peak memory 200832 kb
Host smart-5e76a1c7-bc9e-4980-9ce8-d93954f46a2b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935972958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.3935972958
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.3424121025
Short name T153
Test name
Test status
Simulation time 39301101 ps
CPU time 0.81 seconds
Started Jan 03 01:02:29 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 200548 kb
Host smart-fa937603-b613-44aa-be11-6904bd3b715f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424121025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.3424121025
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.3181158911
Short name T402
Test name
Test status
Simulation time 978352943 ps
CPU time 5.56 seconds
Started Jan 03 01:02:46 PM PST 24
Finished Jan 03 01:03:58 PM PST 24
Peak memory 200884 kb
Host smart-337dacd5-c11d-4414-84d5-3df81e308a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181158911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.3181158911
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.1167293011
Short name T56
Test name
Test status
Simulation time 334196146 ps
CPU time 2.35 seconds
Started Jan 03 01:02:28 PM PST 24
Finished Jan 03 01:03:39 PM PST 24
Peak memory 215240 kb
Host smart-69829ebc-2403-4440-bd8b-ee03ed12bd33
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167293011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.1167293011
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.2320970336
Short name T885
Test name
Test status
Simulation time 43916074 ps
CPU time 0.91 seconds
Started Jan 03 01:02:28 PM PST 24
Finished Jan 03 01:03:37 PM PST 24
Peak memory 200832 kb
Host smart-d0336b0e-e0d6-4cba-a40b-c793e53c4006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320970336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2320970336
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.4002148137
Short name T403
Test name
Test status
Simulation time 3022949095 ps
CPU time 20.8 seconds
Started Jan 03 01:02:39 PM PST 24
Finished Jan 03 01:04:05 PM PST 24
Peak memory 201044 kb
Host smart-b80cbd7d-a5e0-4adb-b25e-a465a3c0062e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002148137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.4002148137
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.2172381350
Short name T497
Test name
Test status
Simulation time 53477901991 ps
CPU time 842.3 seconds
Started Jan 03 01:02:27 PM PST 24
Finished Jan 03 01:17:37 PM PST 24
Peak memory 212812 kb
Host smart-6508466a-d5fc-4dff-8c8d-fde35b89ec05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2172381350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.2172381350
Directory /workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.clkmgr_trans.3250590340
Short name T620
Test name
Test status
Simulation time 25058696 ps
CPU time 0.83 seconds
Started Jan 03 01:02:50 PM PST 24
Finished Jan 03 01:03:56 PM PST 24
Peak memory 200768 kb
Host smart-9fcff98d-190b-4941-8b9c-b4db11b4a97f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250590340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.3250590340
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.3072942179
Short name T446
Test name
Test status
Simulation time 12752580 ps
CPU time 0.7 seconds
Started Jan 03 01:03:44 PM PST 24
Finished Jan 03 01:04:38 PM PST 24
Peak memory 200796 kb
Host smart-db64f721-eb5d-458e-a43e-c693fa521017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072942179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.3072942179
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1451780841
Short name T742
Test name
Test status
Simulation time 101959404 ps
CPU time 0.93 seconds
Started Jan 03 01:03:52 PM PST 24
Finished Jan 03 01:04:50 PM PST 24
Peak memory 200708 kb
Host smart-66d982e1-a03c-4060-9c8b-e92651ad6a14
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451780841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.1451780841
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.2819255346
Short name T908
Test name
Test status
Simulation time 17308710 ps
CPU time 0.72 seconds
Started Jan 03 01:04:35 PM PST 24
Finished Jan 03 01:05:55 PM PST 24
Peak memory 199592 kb
Host smart-8c128332-b68e-412f-a6e6-26e24ef5641a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819255346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2819255346
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.392036454
Short name T820
Test name
Test status
Simulation time 66287045 ps
CPU time 0.91 seconds
Started Jan 03 01:03:52 PM PST 24
Finished Jan 03 01:04:52 PM PST 24
Peak memory 200776 kb
Host smart-f6282de6-05cd-4ce2-b401-75c2ee0ab002
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392036454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.clkmgr_div_intersig_mubi.392036454
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.793260038
Short name T913
Test name
Test status
Simulation time 55365666 ps
CPU time 0.87 seconds
Started Jan 03 01:04:34 PM PST 24
Finished Jan 03 01:05:57 PM PST 24
Peak memory 200696 kb
Host smart-209d05bb-a07e-4aca-bb4c-d975531d0de3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793260038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.793260038
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.520437471
Short name T364
Test name
Test status
Simulation time 801006688 ps
CPU time 4.77 seconds
Started Jan 03 01:04:43 PM PST 24
Finished Jan 03 01:06:11 PM PST 24
Peak memory 200776 kb
Host smart-94c883d4-cf59-4a34-b083-0ed7c0916c38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520437471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.520437471
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.483957807
Short name T4
Test name
Test status
Simulation time 2296160803 ps
CPU time 15.92 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:06:01 PM PST 24
Peak memory 201104 kb
Host smart-ea541c28-88bc-416b-947b-f46b3129c752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483957807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_ti
meout.483957807
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.1449959944
Short name T780
Test name
Test status
Simulation time 35623738 ps
CPU time 1 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200768 kb
Host smart-470515d1-2893-4b0d-be2a-f12c46af0858
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449959944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.1449959944
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.2106498905
Short name T289
Test name
Test status
Simulation time 65743994 ps
CPU time 0.85 seconds
Started Jan 03 01:03:52 PM PST 24
Finished Jan 03 01:04:51 PM PST 24
Peak memory 200792 kb
Host smart-af75a151-fe3b-48d5-a491-36b5514a3ebd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106498905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.2106498905
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.2682788337
Short name T532
Test name
Test status
Simulation time 16861310 ps
CPU time 0.7 seconds
Started Jan 03 01:03:45 PM PST 24
Finished Jan 03 01:04:39 PM PST 24
Peak memory 200720 kb
Host smart-8a4d1376-8827-4141-8aac-bceca3b12236
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682788337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.2682788337
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.1894470945
Short name T340
Test name
Test status
Simulation time 34648257 ps
CPU time 0.76 seconds
Started Jan 03 01:04:33 PM PST 24
Finished Jan 03 01:06:01 PM PST 24
Peak memory 200672 kb
Host smart-abeab783-d109-4dd4-91e8-979e34fe7cfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894470945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.1894470945
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.2035484367
Short name T670
Test name
Test status
Simulation time 1344078067 ps
CPU time 7.02 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200996 kb
Host smart-0893a40a-df98-4118-b01b-e7618182af81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035484367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.2035484367
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.1433613391
Short name T635
Test name
Test status
Simulation time 27650850 ps
CPU time 0.87 seconds
Started Jan 03 01:04:31 PM PST 24
Finished Jan 03 01:05:54 PM PST 24
Peak memory 200804 kb
Host smart-24e7ca04-4f5c-4384-9762-0935697a5cc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433613391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.1433613391
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.461366707
Short name T868
Test name
Test status
Simulation time 11206971638 ps
CPU time 54.56 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:05:58 PM PST 24
Peak memory 201032 kb
Host smart-7e413f3c-576c-41d9-a588-339d46e1dc97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461366707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.461366707
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.4127442887
Short name T627
Test name
Test status
Simulation time 25437986630 ps
CPU time 463.81 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:12:27 PM PST 24
Peak memory 209464 kb
Host smart-14851b6a-db90-46ba-a872-b8c0d807c2f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4127442887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.4127442887
Directory /workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.clkmgr_trans.2750831142
Short name T853
Test name
Test status
Simulation time 87234944 ps
CPU time 1.08 seconds
Started Jan 03 01:04:39 PM PST 24
Finished Jan 03 01:06:03 PM PST 24
Peak memory 200712 kb
Host smart-d4a16452-ec57-4d1b-8147-3b78792feff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750831142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.2750831142
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.832392930
Short name T504
Test name
Test status
Simulation time 11679148 ps
CPU time 0.68 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:16 PM PST 24
Peak memory 200756 kb
Host smart-29d606fd-9f6c-4797-9d50-6496306286fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832392930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkm
gr_alert_test.832392930
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.1450590448
Short name T785
Test name
Test status
Simulation time 19808822 ps
CPU time 0.75 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:05:09 PM PST 24
Peak memory 200732 kb
Host smart-e801833c-3363-49a1-8e21-9128acb93cae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450590448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.1450590448
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.3471019474
Short name T712
Test name
Test status
Simulation time 17252151 ps
CPU time 0.73 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:04:56 PM PST 24
Peak memory 199756 kb
Host smart-ad25626d-76f5-4a25-a33d-66f0ce4b4cac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471019474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.3471019474
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.2470419367
Short name T832
Test name
Test status
Simulation time 35493549 ps
CPU time 0.82 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 200756 kb
Host smart-5986c1ae-f69c-4c1f-9363-edf11274d512
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470419367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.2470419367
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.2360942431
Short name T696
Test name
Test status
Simulation time 20216617 ps
CPU time 0.79 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:04:55 PM PST 24
Peak memory 200712 kb
Host smart-4bd5d320-11e2-4a76-bb1d-0633cc438012
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360942431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.2360942431
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.2646272456
Short name T975
Test name
Test status
Simulation time 1521548532 ps
CPU time 8.6 seconds
Started Jan 03 01:03:45 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 200716 kb
Host smart-518fef10-198a-4736-8b78-82762a7aa4e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646272456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.2646272456
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.1628061752
Short name T732
Test name
Test status
Simulation time 278454245 ps
CPU time 1.73 seconds
Started Jan 03 01:03:39 PM PST 24
Finished Jan 03 01:04:34 PM PST 24
Peak memory 200840 kb
Host smart-547f6c44-8db3-4a53-9bce-51df111b9a9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628061752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.1628061752
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.3024897283
Short name T561
Test name
Test status
Simulation time 108596085 ps
CPU time 1.08 seconds
Started Jan 03 01:03:58 PM PST 24
Finished Jan 03 01:05:00 PM PST 24
Peak memory 200784 kb
Host smart-f8005e60-69c3-4e55-807a-894f3c3a0172
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024897283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.3024897283
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.2300929009
Short name T303
Test name
Test status
Simulation time 19574548 ps
CPU time 0.84 seconds
Started Jan 03 01:03:47 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200608 kb
Host smart-ab5796ca-33de-4dcc-ace5-a2890029bf53
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300929009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.2300929009
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.3108614899
Short name T321
Test name
Test status
Simulation time 68676253 ps
CPU time 0.94 seconds
Started Jan 03 01:03:44 PM PST 24
Finished Jan 03 01:04:39 PM PST 24
Peak memory 200820 kb
Host smart-eff58349-5393-4884-8972-bb0b22e12f51
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108614899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.3108614899
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.1634488234
Short name T774
Test name
Test status
Simulation time 308531925 ps
CPU time 1.59 seconds
Started Jan 03 01:03:52 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 200684 kb
Host smart-92cd75a1-642e-4013-9046-d0ea5c6e6bce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634488234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.1634488234
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.1294671220
Short name T418
Test name
Test status
Simulation time 134641421 ps
CPU time 1.13 seconds
Started Jan 03 01:03:51 PM PST 24
Finished Jan 03 01:04:49 PM PST 24
Peak memory 200808 kb
Host smart-431f142d-bf31-4a80-8c9e-f7129a81b640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294671220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.1294671220
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.2984291682
Short name T758
Test name
Test status
Simulation time 12334931687 ps
CPU time 40.61 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:55 PM PST 24
Peak memory 201096 kb
Host smart-412e9c33-c4cb-451d-a15c-94a03d9de549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984291682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.2984291682
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_trans.120832763
Short name T520
Test name
Test status
Simulation time 116414848 ps
CPU time 1.22 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 200804 kb
Host smart-b262e746-6971-4932-be95-c1734614fd34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120832763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.120832763
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.1138390286
Short name T541
Test name
Test status
Simulation time 16633337 ps
CPU time 0.72 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:25 PM PST 24
Peak memory 200700 kb
Host smart-4cb836b4-e364-479a-816f-5b3dffd858f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138390286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.1138390286
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3485106263
Short name T730
Test name
Test status
Simulation time 18749444 ps
CPU time 0.8 seconds
Started Jan 03 01:04:18 PM PST 24
Finished Jan 03 01:05:35 PM PST 24
Peak memory 200788 kb
Host smart-feb20a23-d5a1-4880-a18c-0ce90cff606a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485106263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.3485106263
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.3246941689
Short name T697
Test name
Test status
Simulation time 19696085 ps
CPU time 0.69 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:43 PM PST 24
Peak memory 199616 kb
Host smart-c35d2dbb-87d6-43cf-8336-6e227cc4aaa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246941689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3246941689
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.1517488643
Short name T895
Test name
Test status
Simulation time 59634807 ps
CPU time 0.91 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200620 kb
Host smart-68e2aa10-c7f5-4809-a860-26f3162b2127
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517488643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.1517488643
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.951760111
Short name T559
Test name
Test status
Simulation time 29642050 ps
CPU time 0.88 seconds
Started Jan 03 01:04:07 PM PST 24
Finished Jan 03 01:05:14 PM PST 24
Peak memory 200756 kb
Host smart-8001cbb7-ef39-48a2-99b2-462518c10807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951760111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.951760111
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.1932229153
Short name T666
Test name
Test status
Simulation time 342153329 ps
CPU time 2.06 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:19 PM PST 24
Peak memory 200672 kb
Host smart-7cf73c7a-9cf5-491c-a4eb-a2e04d76a435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932229153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.1932229153
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.4292106325
Short name T637
Test name
Test status
Simulation time 1728133557 ps
CPU time 6.7 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:32 PM PST 24
Peak memory 200820 kb
Host smart-48d50048-7ae5-4326-9aad-dbcd735c8ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292106325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.4292106325
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.1488783069
Short name T845
Test name
Test status
Simulation time 18686724 ps
CPU time 0.77 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200776 kb
Host smart-0f3af56f-b426-4128-8d0e-276c984dd27c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488783069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.1488783069
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.203110583
Short name T578
Test name
Test status
Simulation time 14640893 ps
CPU time 0.69 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:15 PM PST 24
Peak memory 200712 kb
Host smart-7f169247-2683-4aa7-8bdc-4d65bb978721
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203110583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_clk_byp_req_intersig_mubi.203110583
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.992606587
Short name T405
Test name
Test status
Simulation time 73642697 ps
CPU time 0.97 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:44 PM PST 24
Peak memory 200652 kb
Host smart-488943cf-c5c9-469c-93e4-aa4451472798
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992606587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_ctrl_intersig_mubi.992606587
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.3447334702
Short name T813
Test name
Test status
Simulation time 15323656 ps
CPU time 0.73 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:18 PM PST 24
Peak memory 200832 kb
Host smart-af8c9cdd-6f0a-4f49-a495-94d48b71b3d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447334702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3447334702
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.4014162663
Short name T770
Test name
Test status
Simulation time 110489454 ps
CPU time 1.07 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:26 PM PST 24
Peak memory 200732 kb
Host smart-2b2be7ed-c6ad-4fc8-8af9-e0ce2f41e6ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014162663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.4014162663
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.2074233226
Short name T942
Test name
Test status
Simulation time 48595426 ps
CPU time 0.88 seconds
Started Jan 03 01:03:57 PM PST 24
Finished Jan 03 01:04:58 PM PST 24
Peak memory 200768 kb
Host smart-560f7857-2ba7-4607-afc8-6237d7514acb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074233226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.2074233226
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.147399633
Short name T527
Test name
Test status
Simulation time 4876721783 ps
CPU time 33.81 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:06:03 PM PST 24
Peak memory 201032 kb
Host smart-db4e5b4c-42a5-4af8-ad54-163589972e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147399633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.147399633
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.4291407983
Short name T835
Test name
Test status
Simulation time 40559619726 ps
CPU time 588.73 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:15:22 PM PST 24
Peak memory 209300 kb
Host smart-0430a089-b65c-47c8-8af5-2825e1eb690a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4291407983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.4291407983
Directory /workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.clkmgr_trans.3214981573
Short name T471
Test name
Test status
Simulation time 66388183 ps
CPU time 0.9 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:05:45 PM PST 24
Peak memory 200736 kb
Host smart-97b9678a-6c33-4f41-8ea7-d7ea1ef4c3f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214981573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.3214981573
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.2691039682
Short name T746
Test name
Test status
Simulation time 30443735 ps
CPU time 0.76 seconds
Started Jan 03 01:03:49 PM PST 24
Finished Jan 03 01:04:46 PM PST 24
Peak memory 200804 kb
Host smart-8d480e10-fc56-4227-8288-47ca5a386f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691039682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.2691039682
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.2068583032
Short name T533
Test name
Test status
Simulation time 24818851 ps
CPU time 0.87 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:30 PM PST 24
Peak memory 200716 kb
Host smart-66400d18-3298-4fad-b3c9-45b95e5a1a11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068583032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.2068583032
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.1575186090
Short name T988
Test name
Test status
Simulation time 76003314 ps
CPU time 0.86 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:05:57 PM PST 24
Peak memory 199588 kb
Host smart-fc24147b-37c4-436a-9791-d4541996443c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575186090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1575186090
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.3955917738
Short name T808
Test name
Test status
Simulation time 53700493 ps
CPU time 0.97 seconds
Started Jan 03 01:03:51 PM PST 24
Finished Jan 03 01:04:49 PM PST 24
Peak memory 200744 kb
Host smart-0f140795-906f-412f-9307-a9de9e6e4317
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955917738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.3955917738
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.398477669
Short name T306
Test name
Test status
Simulation time 153315116 ps
CPU time 1.19 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:05:45 PM PST 24
Peak memory 200708 kb
Host smart-09003fac-afbe-4890-83bd-e4b2bbca0635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398477669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.398477669
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.2782828825
Short name T514
Test name
Test status
Simulation time 1277194389 ps
CPU time 8.93 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:37 PM PST 24
Peak memory 200556 kb
Host smart-abfd4ba8-ea53-495b-b25a-f76188cc2fb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782828825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.2782828825
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.1197643111
Short name T667
Test name
Test status
Simulation time 1005301313 ps
CPU time 4.27 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:44 PM PST 24
Peak memory 200668 kb
Host smart-e9c4fcf0-23c9-487b-94f0-80b8cca008a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197643111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.1197643111
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.3881383787
Short name T409
Test name
Test status
Simulation time 54963721 ps
CPU time 0.99 seconds
Started Jan 03 01:04:12 PM PST 24
Finished Jan 03 01:05:30 PM PST 24
Peak memory 200740 kb
Host smart-e3833d36-3c0d-4262-aa96-625e95fcf553
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881383787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_idle_intersig_mubi.3881383787
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1134066439
Short name T790
Test name
Test status
Simulation time 30442067 ps
CPU time 0.74 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:40 PM PST 24
Peak memory 200760 kb
Host smart-7367b426-b573-4d56-801b-cf5f97afcc27
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134066439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.1134066439
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1769128787
Short name T470
Test name
Test status
Simulation time 97431793 ps
CPU time 1.06 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:05:45 PM PST 24
Peak memory 200720 kb
Host smart-9c2a8d2d-caaf-4653-82dd-880788f8be3d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769128787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.1769128787
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.70775392
Short name T538
Test name
Test status
Simulation time 1475079521 ps
CPU time 5.36 seconds
Started Jan 03 01:03:47 PM PST 24
Finished Jan 03 01:04:48 PM PST 24
Peak memory 201004 kb
Host smart-f35bd709-5c18-4cdd-8d8b-793fabcc979c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70775392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.70775392
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.4064651944
Short name T919
Test name
Test status
Simulation time 71768514 ps
CPU time 0.96 seconds
Started Jan 03 01:04:39 PM PST 24
Finished Jan 03 01:06:04 PM PST 24
Peak memory 200584 kb
Host smart-192c3724-a3f7-4532-b345-3721ea865024
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064651944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.4064651944
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.408048865
Short name T359
Test name
Test status
Simulation time 1267738640 ps
CPU time 5.72 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:41 PM PST 24
Peak memory 200748 kb
Host smart-f55eb2f2-d092-441d-b2e7-e6d8bc9b0514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408048865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.408048865
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.2477510610
Short name T300
Test name
Test status
Simulation time 27090000 ps
CPU time 0.93 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200740 kb
Host smart-9b40c0cc-384c-425b-94be-0ad710ff3823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477510610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.2477510610
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.2288728200
Short name T318
Test name
Test status
Simulation time 18854208 ps
CPU time 0.75 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:16 PM PST 24
Peak memory 200692 kb
Host smart-a9a79bfa-a6eb-4cce-9d83-1e918ba35f21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288728200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.2288728200
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.1784348302
Short name T522
Test name
Test status
Simulation time 41797218 ps
CPU time 0.8 seconds
Started Jan 03 01:04:04 PM PST 24
Finished Jan 03 01:05:09 PM PST 24
Peak memory 200656 kb
Host smart-bbfc3873-4717-49f7-929f-8fcf176ca771
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784348302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.1784348302
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.1135740664
Short name T678
Test name
Test status
Simulation time 22329322 ps
CPU time 0.72 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 199576 kb
Host smart-71cc39dc-d5c5-4a2b-80c3-cfd17690f8f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135740664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.1135740664
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.654055990
Short name T869
Test name
Test status
Simulation time 48247339 ps
CPU time 0.93 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 200688 kb
Host smart-2c4f9c79-a88d-4e15-96b3-82113d102c7c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654055990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.clkmgr_div_intersig_mubi.654055990
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.2807104257
Short name T588
Test name
Test status
Simulation time 114521115 ps
CPU time 1.15 seconds
Started Jan 03 01:03:42 PM PST 24
Finished Jan 03 01:04:37 PM PST 24
Peak memory 200636 kb
Host smart-7ff3a418-ba2d-4b1a-94f1-a496859e0b68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807104257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.2807104257
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.3883207042
Short name T454
Test name
Test status
Simulation time 1234949892 ps
CPU time 5.6 seconds
Started Jan 03 01:03:47 PM PST 24
Finished Jan 03 01:04:48 PM PST 24
Peak memory 200624 kb
Host smart-eb693b76-fb64-4701-a351-9263f75e6435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883207042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.3883207042
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.2232848247
Short name T628
Test name
Test status
Simulation time 1541244412 ps
CPU time 5.13 seconds
Started Jan 03 01:04:06 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 200816 kb
Host smart-5017a04c-5731-4675-9089-a8b5ee4f6de9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232848247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.2232848247
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.81257631
Short name T458
Test name
Test status
Simulation time 18559614 ps
CPU time 0.76 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 200748 kb
Host smart-b398dbea-73aa-40a8-b26e-fb3677fd2a45
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81257631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.clkmgr_idle_intersig_mubi.81257631
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2455298837
Short name T313
Test name
Test status
Simulation time 71682093 ps
CPU time 0.95 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 200776 kb
Host smart-74da1dec-c8c5-43e9-bf4e-80f8f722a87a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455298837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.2455298837
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.286123237
Short name T819
Test name
Test status
Simulation time 20736257 ps
CPU time 0.82 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 200744 kb
Host smart-03a2c7ec-5114-4ab3-ae18-4980bf43d4b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286123237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.clkmgr_lc_ctrl_intersig_mubi.286123237
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.703326568
Short name T584
Test name
Test status
Simulation time 41631818 ps
CPU time 0.84 seconds
Started Jan 03 01:03:53 PM PST 24
Finished Jan 03 01:04:52 PM PST 24
Peak memory 200620 kb
Host smart-78e7fec6-aee8-4d18-b753-b56cb516fe48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703326568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.703326568
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.2038716769
Short name T9
Test name
Test status
Simulation time 1108417502 ps
CPU time 6.14 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:51 PM PST 24
Peak memory 200988 kb
Host smart-db19cf0f-9ed0-4e3c-a021-0967afcad016
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038716769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2038716769
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.1389477548
Short name T826
Test name
Test status
Simulation time 309893789 ps
CPU time 1.62 seconds
Started Jan 03 01:03:41 PM PST 24
Finished Jan 03 01:04:37 PM PST 24
Peak memory 200724 kb
Host smart-e1528da8-35f8-49a8-8f58-a70774ac0bac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389477548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.1389477548
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.2435123051
Short name T709
Test name
Test status
Simulation time 2808681426 ps
CPU time 11.2 seconds
Started Jan 03 01:03:53 PM PST 24
Finished Jan 03 01:05:02 PM PST 24
Peak memory 201012 kb
Host smart-2c37d1c9-e6a0-458d-a880-6cc0da1564d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435123051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.2435123051
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.3844095182
Short name T893
Test name
Test status
Simulation time 228840235246 ps
CPU time 890.69 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:19:46 PM PST 24
Peak memory 217436 kb
Host smart-4577490f-4062-4103-a700-5b7bcd973f6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3844095182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.3844095182
Directory /workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.clkmgr_trans.2888550295
Short name T931
Test name
Test status
Simulation time 40522603 ps
CPU time 0.81 seconds
Started Jan 03 01:04:04 PM PST 24
Finished Jan 03 01:05:09 PM PST 24
Peak memory 200768 kb
Host smart-2b6611b0-e1c4-44fd-be18-ca2a7a2b0326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888550295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.2888550295
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.19659181
Short name T563
Test name
Test status
Simulation time 16285770 ps
CPU time 0.72 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:03 PM PST 24
Peak memory 200740 kb
Host smart-cc4d8b05-6760-4c9c-bebe-6790976d43bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19659181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmg
r_alert_test.19659181
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.215293252
Short name T523
Test name
Test status
Simulation time 37947815 ps
CPU time 0.77 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200732 kb
Host smart-3ac8089c-60f3-49ee-8bd1-3b9af2f4cffb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215293252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.215293252
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.2709910091
Short name T45
Test name
Test status
Simulation time 22805190 ps
CPU time 0.68 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:04:56 PM PST 24
Peak memory 199692 kb
Host smart-93e12b98-1b4e-4c30-aad1-a6f4bcf6b679
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709910091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.2709910091
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.2768657193
Short name T480
Test name
Test status
Simulation time 18826150 ps
CPU time 0.83 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 200668 kb
Host smart-a669c46e-5b18-4c05-9ff1-2a776d5216a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768657193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.2768657193
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.2424091111
Short name T322
Test name
Test status
Simulation time 15376998 ps
CPU time 0.72 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:12 PM PST 24
Peak memory 200660 kb
Host smart-9edc7b64-e1af-4a68-86ed-245d8d760846
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424091111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.2424091111
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.1126609478
Short name T376
Test name
Test status
Simulation time 2486045133 ps
CPU time 13.72 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:05:20 PM PST 24
Peak memory 201052 kb
Host smart-b54aafef-3674-47fd-8e78-5d4a78bc4b6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126609478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1126609478
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.782807280
Short name T872
Test name
Test status
Simulation time 377841043 ps
CPU time 2.98 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 200872 kb
Host smart-7db7530d-db6b-44ea-aae2-1d794523703b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782807280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_ti
meout.782807280
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.126775241
Short name T329
Test name
Test status
Simulation time 217445584 ps
CPU time 1.49 seconds
Started Jan 03 01:03:52 PM PST 24
Finished Jan 03 01:04:50 PM PST 24
Peak memory 200720 kb
Host smart-bd417750-5f77-4e59-b3fa-7161909950c0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126775241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.clkmgr_idle_intersig_mubi.126775241
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2296524797
Short name T407
Test name
Test status
Simulation time 48227499 ps
CPU time 0.78 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:05:05 PM PST 24
Peak memory 200768 kb
Host smart-f52c11ce-9734-4648-b793-112daff8561a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296524797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.2296524797
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.22326884
Short name T683
Test name
Test status
Simulation time 28929235 ps
CPU time 0.72 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:12 PM PST 24
Peak memory 200804 kb
Host smart-6efeace7-3408-4f36-9c20-9594505577ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_lc_ctrl_intersig_mubi.22326884
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.2116156679
Short name T577
Test name
Test status
Simulation time 35537464 ps
CPU time 0.77 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 200764 kb
Host smart-a374fed6-8880-45c3-b23d-1bea738fdfe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116156679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.2116156679
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.1754657600
Short name T930
Test name
Test status
Simulation time 1157417107 ps
CPU time 5.16 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:08 PM PST 24
Peak memory 200884 kb
Host smart-c647baf0-f462-4c94-ab0b-cd9cc11274e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754657600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.1754657600
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.1465392125
Short name T465
Test name
Test status
Simulation time 87190393 ps
CPU time 0.98 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:35 PM PST 24
Peak memory 200804 kb
Host smart-540a465a-fca8-4559-9357-f5673f929d2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465392125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.1465392125
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.835529801
Short name T840
Test name
Test status
Simulation time 2563495151 ps
CPU time 19.94 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:31 PM PST 24
Peak memory 201040 kb
Host smart-c853803a-030a-4bd9-acbd-88e5417568e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835529801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.835529801
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.3192799484
Short name T970
Test name
Test status
Simulation time 33470955461 ps
CPU time 498.71 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:14:01 PM PST 24
Peak memory 209444 kb
Host smart-402e104c-c14b-4280-a560-51545c320087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3192799484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.3192799484
Directory /workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.clkmgr_trans.1355662941
Short name T911
Test name
Test status
Simulation time 26094919 ps
CPU time 0.88 seconds
Started Jan 03 01:03:58 PM PST 24
Finished Jan 03 01:05:00 PM PST 24
Peak memory 200792 kb
Host smart-aa8319b4-f82f-46a2-9490-c69b76c56663
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355662941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1355662941
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.1970931815
Short name T540
Test name
Test status
Simulation time 17578321 ps
CPU time 0.76 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:26 PM PST 24
Peak memory 200764 kb
Host smart-5eee10d2-30c6-410a-86e4-6d48ad0ef2d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970931815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.1970931815
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.1312776411
Short name T877
Test name
Test status
Simulation time 48433237 ps
CPU time 0.82 seconds
Started Jan 03 01:03:51 PM PST 24
Finished Jan 03 01:04:49 PM PST 24
Peak memory 200724 kb
Host smart-69e1f43c-5c72-43c9-b3ca-dcaa31415894
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312776411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.1312776411
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.4158237415
Short name T571
Test name
Test status
Simulation time 17609021 ps
CPU time 0.72 seconds
Started Jan 03 01:04:12 PM PST 24
Finished Jan 03 01:05:22 PM PST 24
Peak memory 200644 kb
Host smart-b338f44e-27f6-4602-9d34-7bf7be5cd778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158237415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.4158237415
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.2660111924
Short name T357
Test name
Test status
Simulation time 90474364 ps
CPU time 1.02 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:05:07 PM PST 24
Peak memory 200704 kb
Host smart-7ca2580e-17c9-4fd6-bae6-4e40547b4f24
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660111924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.2660111924
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.2724151282
Short name T345
Test name
Test status
Simulation time 58386047 ps
CPU time 0.86 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:04:56 PM PST 24
Peak memory 200736 kb
Host smart-0d19de60-f8a7-4258-979d-9f9ed2fbbbaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724151282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.2724151282
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.1789230060
Short name T937
Test name
Test status
Simulation time 1926277899 ps
CPU time 8.62 seconds
Started Jan 03 01:04:06 PM PST 24
Finished Jan 03 01:05:21 PM PST 24
Peak memory 200872 kb
Host smart-cc7b57b6-ecba-4c60-9a9f-850faed6f789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789230060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1789230060
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.2659648704
Short name T525
Test name
Test status
Simulation time 1589316396 ps
CPU time 7.92 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:05:02 PM PST 24
Peak memory 200800 kb
Host smart-fe1f69ca-6a1a-408a-84cb-76f146be2307
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659648704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.2659648704
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.562500735
Short name T165
Test name
Test status
Simulation time 28572013 ps
CPU time 0.87 seconds
Started Jan 03 01:04:36 PM PST 24
Finished Jan 03 01:06:05 PM PST 24
Peak memory 200780 kb
Host smart-bdf9992c-eb49-49f1-881f-56a7e2b6a03d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562500735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.clkmgr_idle_intersig_mubi.562500735
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.719097383
Short name T957
Test name
Test status
Simulation time 27738864 ps
CPU time 0.86 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:12 PM PST 24
Peak memory 200624 kb
Host smart-f867e625-0f85-4c63-9df9-9f8396cbc031
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719097383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.clkmgr_lc_clk_byp_req_intersig_mubi.719097383
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.3930906611
Short name T501
Test name
Test status
Simulation time 49722373 ps
CPU time 0.96 seconds
Started Jan 03 01:04:07 PM PST 24
Finished Jan 03 01:05:14 PM PST 24
Peak memory 200820 kb
Host smart-efd06bc9-da72-4c2e-8076-67c3dcd7c310
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930906611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.3930906611
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.1342669506
Short name T935
Test name
Test status
Simulation time 22394114 ps
CPU time 0.72 seconds
Started Jan 03 01:04:02 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 200500 kb
Host smart-bdeab9c2-9288-468d-a60b-25ead922470e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342669506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1342669506
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.3944720956
Short name T485
Test name
Test status
Simulation time 319999428 ps
CPU time 1.64 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:04:54 PM PST 24
Peak memory 200760 kb
Host smart-d69abef2-a221-45f3-af48-6309c5a842c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944720956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.3944720956
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.353607576
Short name T903
Test name
Test status
Simulation time 94153964 ps
CPU time 1.08 seconds
Started Jan 03 01:04:06 PM PST 24
Finished Jan 03 01:05:13 PM PST 24
Peak memory 200744 kb
Host smart-9f03e21a-e61e-452a-a7c4-409b0b2908c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353607576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.353607576
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.2889251141
Short name T400
Test name
Test status
Simulation time 142720221308 ps
CPU time 1005.93 seconds
Started Jan 03 01:03:51 PM PST 24
Finished Jan 03 01:21:34 PM PST 24
Peak memory 215220 kb
Host smart-4ad64aa6-fe35-459d-9196-fa7002634b2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2889251141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.2889251141
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.2074494806
Short name T990
Test name
Test status
Simulation time 100986460 ps
CPU time 0.95 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:05:45 PM PST 24
Peak memory 200616 kb
Host smart-d5cd37c8-2f58-46ac-9ff2-34e2692ed017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074494806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.2074494806
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.2673645559
Short name T604
Test name
Test status
Simulation time 44706007 ps
CPU time 0.8 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:33 PM PST 24
Peak memory 200708 kb
Host smart-0f8deeed-e0da-4dd4-b857-0d607658ed5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673645559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.2673645559
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.1672524271
Short name T960
Test name
Test status
Simulation time 31300363 ps
CPU time 0.82 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:04:56 PM PST 24
Peak memory 200768 kb
Host smart-2bd23dc4-c857-4753-80d6-c305841910e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672524271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.1672524271
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.2559468350
Short name T867
Test name
Test status
Simulation time 87559286 ps
CPU time 0.88 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:22 PM PST 24
Peak memory 199548 kb
Host smart-802c61a5-75c8-46d1-ac7b-c0a15e4fce73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559468350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2559468350
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.2418221116
Short name T629
Test name
Test status
Simulation time 27485221 ps
CPU time 0.76 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:05:07 PM PST 24
Peak memory 200788 kb
Host smart-2c50cdd0-375e-4e61-83bf-bb2dc1154d2b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418221116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.2418221116
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.2222063903
Short name T665
Test name
Test status
Simulation time 19908428 ps
CPU time 0.83 seconds
Started Jan 03 01:04:02 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 200736 kb
Host smart-74b1185f-ea0f-4713-bef1-b9c8aca9cc73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222063903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2222063903
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.3528509075
Short name T413
Test name
Test status
Simulation time 2020794774 ps
CPU time 8.75 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:05:03 PM PST 24
Peak memory 200860 kb
Host smart-d031ca28-b9a4-4731-a3f1-c6436cf05649
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528509075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.3528509075
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.3125196564
Short name T797
Test name
Test status
Simulation time 157010507 ps
CPU time 1.19 seconds
Started Jan 03 01:03:51 PM PST 24
Finished Jan 03 01:04:49 PM PST 24
Peak memory 200844 kb
Host smart-22486353-ed25-4724-a10d-b6f86f524d6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125196564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.3125196564
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.4206987114
Short name T721
Test name
Test status
Simulation time 34100229 ps
CPU time 0.97 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:05:05 PM PST 24
Peak memory 200676 kb
Host smart-63b7cdb0-9e1e-40bd-8040-2a393a4bb777
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206987114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.4206987114
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1388040303
Short name T953
Test name
Test status
Simulation time 47373629 ps
CPU time 0.85 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:30 PM PST 24
Peak memory 200780 kb
Host smart-2fe9d083-197f-4958-bdfd-1b3a008c87db
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388040303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.1388040303
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.175124462
Short name T346
Test name
Test status
Simulation time 45526164 ps
CPU time 0.91 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 200664 kb
Host smart-82bac0e1-4c3f-41c1-9a6d-e7d589c3fe71
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175124462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.clkmgr_lc_ctrl_intersig_mubi.175124462
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.1592425185
Short name T398
Test name
Test status
Simulation time 14693990 ps
CPU time 0.73 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:16 PM PST 24
Peak memory 200740 kb
Host smart-cf1d2490-45ba-4ea9-8ce6-6ab20e87259b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592425185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.1592425185
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.701707361
Short name T590
Test name
Test status
Simulation time 234718896 ps
CPU time 1.88 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:42 PM PST 24
Peak memory 200744 kb
Host smart-42d97ee8-26c9-41ab-973f-26b5a3881284
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701707361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.701707361
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.3232130405
Short name T901
Test name
Test status
Simulation time 23373019 ps
CPU time 0.77 seconds
Started Jan 03 01:04:06 PM PST 24
Finished Jan 03 01:05:13 PM PST 24
Peak memory 200784 kb
Host smart-02d5e9f5-8f35-4418-b9b5-8ebdf50e273e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232130405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.3232130405
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.567553053
Short name T796
Test name
Test status
Simulation time 5113782782 ps
CPU time 34.05 seconds
Started Jan 03 01:03:46 PM PST 24
Finished Jan 03 01:05:13 PM PST 24
Peak memory 200988 kb
Host smart-bf079889-479a-4fe2-9cc5-7aceb43214c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567553053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.567553053
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.1738669156
Short name T325
Test name
Test status
Simulation time 74777446426 ps
CPU time 791.73 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:18:23 PM PST 24
Peak memory 217500 kb
Host smart-58965ede-5539-4274-b858-5efae21a9b6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1738669156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.1738669156
Directory /workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.clkmgr_trans.1198942259
Short name T414
Test name
Test status
Simulation time 44406829 ps
CPU time 0.8 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:04:55 PM PST 24
Peak memory 200772 kb
Host smart-d7a2a3f2-925a-4865-8b4b-f8ff8a56552d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198942259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.1198942259
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.209099394
Short name T304
Test name
Test status
Simulation time 25232878 ps
CPU time 0.76 seconds
Started Jan 03 01:04:31 PM PST 24
Finished Jan 03 01:05:55 PM PST 24
Peak memory 200792 kb
Host smart-b11ba3be-8705-4594-b1df-ace41aa47130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209099394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkm
gr_alert_test.209099394
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.335633572
Short name T979
Test name
Test status
Simulation time 30446214 ps
CPU time 0.91 seconds
Started Jan 03 01:04:04 PM PST 24
Finished Jan 03 01:05:10 PM PST 24
Peak memory 200772 kb
Host smart-de7c25c6-0d7d-4f3a-b900-430dda38312d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335633572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.335633572
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.699114321
Short name T582
Test name
Test status
Simulation time 29044653 ps
CPU time 0.68 seconds
Started Jan 03 01:04:39 PM PST 24
Finished Jan 03 01:06:02 PM PST 24
Peak memory 199612 kb
Host smart-adaf63c4-fdba-48b7-b45e-1503b42523aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699114321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.699114321
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.101297637
Short name T694
Test name
Test status
Simulation time 15184413 ps
CPU time 0.76 seconds
Started Jan 03 01:03:55 PM PST 24
Finished Jan 03 01:04:56 PM PST 24
Peak memory 200812 kb
Host smart-3a5f4a53-d796-4fb8-9542-88cd48e3b23b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101297637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.clkmgr_div_intersig_mubi.101297637
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.2145096026
Short name T524
Test name
Test status
Simulation time 20725282 ps
CPU time 0.81 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:45 PM PST 24
Peak memory 200828 kb
Host smart-b29ce699-4017-4575-8e20-38a4b7058669
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145096026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.2145096026
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.787735212
Short name T399
Test name
Test status
Simulation time 1043210912 ps
CPU time 6.15 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 200780 kb
Host smart-ab412a24-f243-4d78-adad-c45ef5f20702
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787735212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.787735212
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.586396384
Short name T612
Test name
Test status
Simulation time 496135503 ps
CPU time 4.04 seconds
Started Jan 03 01:03:59 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 200804 kb
Host smart-ce24b28d-cfae-4ee1-8c2f-f74ed492f672
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586396384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_ti
meout.586396384
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1625155231
Short name T977
Test name
Test status
Simulation time 19207865 ps
CPU time 0.77 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:32 PM PST 24
Peak memory 200692 kb
Host smart-f977d5a2-3aa4-450e-b069-17a2c47d3fc3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625155231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.1625155231
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.820230885
Short name T555
Test name
Test status
Simulation time 25343209 ps
CPU time 0.74 seconds
Started Jan 03 01:04:07 PM PST 24
Finished Jan 03 01:05:14 PM PST 24
Peak memory 200724 kb
Host smart-4d3530dd-2424-4c65-a64a-c6fb8aebc479
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820230885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.clkmgr_lc_clk_byp_req_intersig_mubi.820230885
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.722958190
Short name T863
Test name
Test status
Simulation time 257592361 ps
CPU time 1.53 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:04 PM PST 24
Peak memory 200800 kb
Host smart-dfdf2ddc-9554-407a-9c2a-8dd934b15897
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722958190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.clkmgr_lc_ctrl_intersig_mubi.722958190
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.348287097
Short name T63
Test name
Test status
Simulation time 13413531 ps
CPU time 0.68 seconds
Started Jan 03 01:04:18 PM PST 24
Finished Jan 03 01:05:34 PM PST 24
Peak memory 200588 kb
Host smart-43200edb-1d63-463a-9e9d-6d74093114b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348287097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.348287097
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.4032166391
Short name T384
Test name
Test status
Simulation time 653283362 ps
CPU time 3.51 seconds
Started Jan 03 01:03:58 PM PST 24
Finished Jan 03 01:05:03 PM PST 24
Peak memory 200936 kb
Host smart-70b9993f-b2c2-4902-8db8-c21dd2e04bec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032166391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.4032166391
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.915806935
Short name T890
Test name
Test status
Simulation time 31044602 ps
CPU time 0.83 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:05:28 PM PST 24
Peak memory 200728 kb
Host smart-d3678550-2b6a-4a6a-8ea1-f743923c89f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915806935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.915806935
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.2760922627
Short name T646
Test name
Test status
Simulation time 40157574 ps
CPU time 0.88 seconds
Started Jan 03 01:04:19 PM PST 24
Finished Jan 03 01:05:36 PM PST 24
Peak memory 200744 kb
Host smart-6e907106-2e6a-480a-ba83-3ed6cdae67c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760922627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.2760922627
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.4229267313
Short name T552
Test name
Test status
Simulation time 246378958921 ps
CPU time 1131.56 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:23:44 PM PST 24
Peak memory 213320 kb
Host smart-5c3687f2-fed1-4747-8ead-b6d2dbe05f48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4229267313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.4229267313
Directory /workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.clkmgr_trans.376714147
Short name T505
Test name
Test status
Simulation time 25969764 ps
CPU time 0.75 seconds
Started Jan 03 01:04:40 PM PST 24
Finished Jan 03 01:06:03 PM PST 24
Peak memory 200720 kb
Host smart-9f180ee6-e0a4-4e2b-a335-46b479e0ce0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376714147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.376714147
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.881734561
Short name T643
Test name
Test status
Simulation time 48204622 ps
CPU time 0.84 seconds
Started Jan 03 01:04:43 PM PST 24
Finished Jan 03 01:06:04 PM PST 24
Peak memory 200696 kb
Host smart-5f6d5273-428a-4cab-8c9d-f992b04c37ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881734561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkm
gr_alert_test.881734561
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.1017432840
Short name T991
Test name
Test status
Simulation time 106871343 ps
CPU time 1.08 seconds
Started Jan 03 01:04:44 PM PST 24
Finished Jan 03 01:06:15 PM PST 24
Peak memory 200828 kb
Host smart-61f1ee52-9bd8-4b1f-8b38-c34bddd64921
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017432840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.1017432840
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.2779094985
Short name T141
Test name
Test status
Simulation time 17438629 ps
CPU time 0.72 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:05:07 PM PST 24
Peak memory 200576 kb
Host smart-421e5d13-4279-48e9-9f5a-ea66a9728d6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779094985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.2779094985
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.163825192
Short name T486
Test name
Test status
Simulation time 13833568 ps
CPU time 0.69 seconds
Started Jan 03 01:04:45 PM PST 24
Finished Jan 03 01:06:15 PM PST 24
Peak memory 200648 kb
Host smart-61c4a4de-bb72-4c4d-9366-0e8b682d204a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163825192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.clkmgr_div_intersig_mubi.163825192
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.229817360
Short name T973
Test name
Test status
Simulation time 25848018 ps
CPU time 0.77 seconds
Started Jan 03 01:04:27 PM PST 24
Finished Jan 03 01:05:48 PM PST 24
Peak memory 200812 kb
Host smart-c4052651-624f-4eb3-8ac3-deda3585f6fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229817360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.229817360
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.3879263187
Short name T442
Test name
Test status
Simulation time 440962143 ps
CPU time 3.77 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:32 PM PST 24
Peak memory 200700 kb
Host smart-4d9ca941-fb5c-4236-a54a-c0ec95583a9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879263187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.3879263187
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.4292025567
Short name T337
Test name
Test status
Simulation time 1825520900 ps
CPU time 9.65 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:52 PM PST 24
Peak memory 200864 kb
Host smart-f87749d9-1291-4066-9b1d-67066fef9542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292025567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.4292025567
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.3564048839
Short name T551
Test name
Test status
Simulation time 28102900 ps
CPU time 0.86 seconds
Started Jan 03 01:04:30 PM PST 24
Finished Jan 03 01:05:51 PM PST 24
Peak memory 200640 kb
Host smart-a2b5b79b-2c9b-452e-98fb-55687d7fa7b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564048839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.3564048839
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2955991696
Short name T164
Test name
Test status
Simulation time 13874977 ps
CPU time 0.73 seconds
Started Jan 03 01:04:32 PM PST 24
Finished Jan 03 01:05:53 PM PST 24
Peak memory 200664 kb
Host smart-ceaa8ab6-ec6b-40a3-baf0-f0d43958f7f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955991696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.2955991696
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.53413991
Short name T740
Test name
Test status
Simulation time 87151927 ps
CPU time 0.97 seconds
Started Jan 03 01:04:20 PM PST 24
Finished Jan 03 01:05:38 PM PST 24
Peak memory 200804 kb
Host smart-e42584e2-3a6a-4e41-81a2-ed83ca2e911f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53413991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_lc_ctrl_intersig_mubi.53413991
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.912320910
Short name T779
Test name
Test status
Simulation time 21307655 ps
CPU time 0.75 seconds
Started Jan 03 01:04:49 PM PST 24
Finished Jan 03 01:06:08 PM PST 24
Peak memory 200556 kb
Host smart-b86e3000-7482-4c26-b7e9-f4a5fffd2114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912320910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.912320910
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.3015573859
Short name T691
Test name
Test status
Simulation time 344827281 ps
CPU time 2.34 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:05:29 PM PST 24
Peak memory 200700 kb
Host smart-1bfdea2a-9f6f-4b79-886b-43953b4b762c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015573859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.3015573859
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.3588835694
Short name T335
Test name
Test status
Simulation time 75667855 ps
CPU time 0.98 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:30 PM PST 24
Peak memory 200732 kb
Host smart-b5256933-adc9-46c6-b98d-cfe7f782e541
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588835694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.3588835694
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.3926123768
Short name T369
Test name
Test status
Simulation time 4872410148 ps
CPU time 21.1 seconds
Started Jan 03 01:04:45 PM PST 24
Finished Jan 03 01:06:24 PM PST 24
Peak memory 201084 kb
Host smart-ea2231d5-d123-4883-9a3b-73436d38c4fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926123768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.3926123768
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.4082290963
Short name T161
Test name
Test status
Simulation time 89007161681 ps
CPU time 512.21 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:14:36 PM PST 24
Peak memory 211696 kb
Host smart-b18c4247-78a0-42d5-9a27-e3b22555665b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4082290963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.4082290963
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.clkmgr_trans.2192047069
Short name T114
Test name
Test status
Simulation time 146284004 ps
CPU time 1.14 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:35 PM PST 24
Peak memory 200712 kb
Host smart-4ba3f347-e55a-4b1e-8dd6-38c148186b02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192047069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.2192047069
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.90079281
Short name T619
Test name
Test status
Simulation time 36183801 ps
CPU time 0.78 seconds
Started Jan 03 01:02:46 PM PST 24
Finished Jan 03 01:03:53 PM PST 24
Peak memory 200724 kb
Host smart-3b92ae6e-fbdd-430e-80d6-36bbe97516c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90079281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr
_alert_test.90079281
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.2114258253
Short name T317
Test name
Test status
Simulation time 46755947 ps
CPU time 0.94 seconds
Started Jan 03 01:02:29 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 200812 kb
Host smart-24283433-d78a-4282-a8a5-28042f40c818
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114258253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.2114258253
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.214215287
Short name T672
Test name
Test status
Simulation time 66231149 ps
CPU time 0.8 seconds
Started Jan 03 01:02:45 PM PST 24
Finished Jan 03 01:03:51 PM PST 24
Peak memory 199664 kb
Host smart-b7bd5403-3cba-4a60-8a0b-f2b5d03bb890
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214215287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.214215287
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.1549065627
Short name T909
Test name
Test status
Simulation time 19139276 ps
CPU time 0.79 seconds
Started Jan 03 01:02:44 PM PST 24
Finished Jan 03 01:03:51 PM PST 24
Peak memory 200780 kb
Host smart-ceab541c-86d2-4fa2-83ae-0cdc878ffa4c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549065627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.1549065627
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.1739341276
Short name T843
Test name
Test status
Simulation time 28227997 ps
CPU time 0.78 seconds
Started Jan 03 01:02:38 PM PST 24
Finished Jan 03 01:03:45 PM PST 24
Peak memory 200688 kb
Host smart-38c97627-6674-463c-ae08-90e822d119d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739341276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.1739341276
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.3307341736
Short name T336
Test name
Test status
Simulation time 1160204548 ps
CPU time 9.27 seconds
Started Jan 03 01:02:29 PM PST 24
Finished Jan 03 01:03:47 PM PST 24
Peak memory 200684 kb
Host smart-7f9b9c2f-9e15-4c0d-a193-7ec8029a1bcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307341736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.3307341736
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.3366494065
Short name T315
Test name
Test status
Simulation time 767840685 ps
CPU time 3.54 seconds
Started Jan 03 01:02:35 PM PST 24
Finished Jan 03 01:03:45 PM PST 24
Peak memory 200768 kb
Host smart-e2a10178-3fa8-432f-bd3a-100cd1a759e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366494065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.3366494065
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.4149331737
Short name T645
Test name
Test status
Simulation time 86525879 ps
CPU time 0.95 seconds
Started Jan 03 01:02:29 PM PST 24
Finished Jan 03 01:03:38 PM PST 24
Peak memory 200768 kb
Host smart-d0293e9b-d7c6-4927-8a1e-677c7f137e5b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149331737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.4149331737
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.3566840394
Short name T825
Test name
Test status
Simulation time 21667475 ps
CPU time 0.9 seconds
Started Jan 03 01:02:32 PM PST 24
Finished Jan 03 01:03:40 PM PST 24
Peak memory 200572 kb
Host smart-fdcfa8d6-5324-4dfd-9296-619ede1e4d83
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566840394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.3566840394
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.1956460023
Short name T775
Test name
Test status
Simulation time 39397604 ps
CPU time 0.87 seconds
Started Jan 03 01:02:45 PM PST 24
Finished Jan 03 01:03:52 PM PST 24
Peak memory 200708 kb
Host smart-7ae91dbc-d7c8-4433-af1e-992180685433
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956460023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.1956460023
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.4016461953
Short name T600
Test name
Test status
Simulation time 15007985 ps
CPU time 0.72 seconds
Started Jan 03 01:02:32 PM PST 24
Finished Jan 03 01:03:40 PM PST 24
Peak memory 200548 kb
Host smart-64720457-46f8-4e5c-8585-f298884126d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016461953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.4016461953
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.2886359011
Short name T351
Test name
Test status
Simulation time 1127138708 ps
CPU time 4.17 seconds
Started Jan 03 01:02:31 PM PST 24
Finished Jan 03 01:03:42 PM PST 24
Peak memory 200920 kb
Host smart-6e161409-2773-412f-8900-3267946effb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886359011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.2886359011
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.3407399917
Short name T67
Test name
Test status
Simulation time 629990071 ps
CPU time 3.76 seconds
Started Jan 03 01:02:50 PM PST 24
Finished Jan 03 01:04:00 PM PST 24
Peak memory 216516 kb
Host smart-58393587-4951-48ea-b3c1-8da8c70b28dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407399917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.3407399917
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.481862355
Short name T152
Test name
Test status
Simulation time 15883878 ps
CPU time 0.78 seconds
Started Jan 03 01:02:34 PM PST 24
Finished Jan 03 01:03:42 PM PST 24
Peak memory 200816 kb
Host smart-a0ab1ca0-6177-4ee0-90c6-227338738c6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481862355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.481862355
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.1319055415
Short name T26
Test name
Test status
Simulation time 6197411102 ps
CPU time 32.98 seconds
Started Jan 03 01:02:39 PM PST 24
Finished Jan 03 01:04:17 PM PST 24
Peak memory 201008 kb
Host smart-c3545400-7e44-44b4-ba1c-3526e0260179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319055415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.1319055415
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.4259757697
Short name T803
Test name
Test status
Simulation time 14145087011 ps
CPU time 262.17 seconds
Started Jan 03 01:02:48 PM PST 24
Finished Jan 03 01:08:16 PM PST 24
Peak memory 209300 kb
Host smart-2e1e306b-8481-421e-99b6-ecd4c682ee3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4259757697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.4259757697
Directory /workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.clkmgr_trans.1406948989
Short name T347
Test name
Test status
Simulation time 51609618 ps
CPU time 0.82 seconds
Started Jan 03 01:02:37 PM PST 24
Finished Jan 03 01:03:44 PM PST 24
Peak memory 200696 kb
Host smart-865db9cf-f27b-40f2-8276-8f5b475d15f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406948989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.1406948989
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.2585767435
Short name T368
Test name
Test status
Simulation time 23515492 ps
CPU time 0.73 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:20 PM PST 24
Peak memory 200712 kb
Host smart-e756af83-1411-4d37-ad74-52cf5d841d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585767435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.2585767435
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.3512269001
Short name T341
Test name
Test status
Simulation time 19016498 ps
CPU time 0.75 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:22 PM PST 24
Peak memory 200740 kb
Host smart-353a3268-1e68-4643-83e5-8513c9abe114
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512269001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.3512269001
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.3892930978
Short name T137
Test name
Test status
Simulation time 26582047 ps
CPU time 0.71 seconds
Started Jan 03 01:04:30 PM PST 24
Finished Jan 03 01:05:54 PM PST 24
Peak memory 200588 kb
Host smart-7e986750-83c1-4da4-a3e0-b6b3d3cfb764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892930978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.3892930978
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.2333117606
Short name T860
Test name
Test status
Simulation time 49393140 ps
CPU time 0.83 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:19 PM PST 24
Peak memory 200732 kb
Host smart-f7a16a90-5da0-4944-ba84-b9901e6cb32b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333117606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.2333117606
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.2570752555
Short name T426
Test name
Test status
Simulation time 113741469 ps
CPU time 0.98 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200528 kb
Host smart-c29a9341-c340-4ade-85b1-82895e70593c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570752555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.2570752555
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.1119366679
Short name T679
Test name
Test status
Simulation time 712933838 ps
CPU time 3.55 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:15 PM PST 24
Peak memory 200772 kb
Host smart-a623b082-8889-4e9c-9818-172367fd991d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119366679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1119366679
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.301803902
Short name T662
Test name
Test status
Simulation time 619090261 ps
CPU time 4.94 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:08 PM PST 24
Peak memory 200800 kb
Host smart-74dfbdad-a922-4cdc-807a-c6e306242d8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301803902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_ti
meout.301803902
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.2156566886
Short name T902
Test name
Test status
Simulation time 29985392 ps
CPU time 0.78 seconds
Started Jan 03 01:03:45 PM PST 24
Finished Jan 03 01:04:39 PM PST 24
Peak memory 200760 kb
Host smart-b6115afc-9a81-4f13-ad59-120ab9c471b5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156566886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.2156566886
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.3208521124
Short name T968
Test name
Test status
Simulation time 21107133 ps
CPU time 0.82 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:21 PM PST 24
Peak memory 200824 kb
Host smart-c528ff04-6de3-4d5a-931b-1bad7f4a8d31
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208521124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.3208521124
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.557855249
Short name T719
Test name
Test status
Simulation time 25684796 ps
CPU time 0.81 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:04 PM PST 24
Peak memory 200752 kb
Host smart-f4005a72-bac2-45d3-970c-ce3a576f9bf3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557855249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.clkmgr_lc_ctrl_intersig_mubi.557855249
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.2308105809
Short name T777
Test name
Test status
Simulation time 11491038 ps
CPU time 0.69 seconds
Started Jan 03 01:04:01 PM PST 24
Finished Jan 03 01:05:04 PM PST 24
Peak memory 200604 kb
Host smart-dca06e2c-451e-4968-9c10-edcaf7637ee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308105809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2308105809
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.864682797
Short name T385
Test name
Test status
Simulation time 1842879903 ps
CPU time 5.98 seconds
Started Jan 03 01:04:12 PM PST 24
Finished Jan 03 01:05:28 PM PST 24
Peak memory 201028 kb
Host smart-e838c435-6a04-4122-92b0-8918d82f1b80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864682797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.864682797
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.962045695
Short name T621
Test name
Test status
Simulation time 346662266 ps
CPU time 1.69 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:06:07 PM PST 24
Peak memory 200792 kb
Host smart-45c54967-6ee3-444a-9945-af657c4e0b26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962045695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.962045695
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.2802987317
Short name T429
Test name
Test status
Simulation time 1824249874 ps
CPU time 10.2 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:06:06 PM PST 24
Peak memory 200880 kb
Host smart-d5ace4f0-1610-4ccd-8da5-541a6b2a96ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802987317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.2802987317
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.29830653
Short name T461
Test name
Test status
Simulation time 120383347 ps
CPU time 1.26 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:12 PM PST 24
Peak memory 200740 kb
Host smart-096ea3e7-5c71-41fe-9de8-3568651600b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29830653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.29830653
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.3933479785
Short name T370
Test name
Test status
Simulation time 21160438 ps
CPU time 0.76 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:26 PM PST 24
Peak memory 200780 kb
Host smart-64a35555-b82c-426e-bb82-889aee6522ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933479785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.3933479785
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.996946642
Short name T593
Test name
Test status
Simulation time 13663487 ps
CPU time 0.72 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 200724 kb
Host smart-cbe95dfd-3e22-4463-8613-c1c62158ae57
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996946642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.996946642
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.687590912
Short name T958
Test name
Test status
Simulation time 88410143 ps
CPU time 0.82 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:05:28 PM PST 24
Peak memory 199680 kb
Host smart-5d95d666-0e8c-4605-99f3-bdc6e6368245
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687590912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.687590912
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.175082823
Short name T548
Test name
Test status
Simulation time 20329822 ps
CPU time 0.8 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 200804 kb
Host smart-58d3b1c5-6a2d-41bc-bc4a-8c7c41f7a30a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175082823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.clkmgr_div_intersig_mubi.175082823
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.1234529227
Short name T444
Test name
Test status
Simulation time 15986206 ps
CPU time 0.74 seconds
Started Jan 03 01:04:10 PM PST 24
Finished Jan 03 01:05:19 PM PST 24
Peak memory 200588 kb
Host smart-0f06cd10-8a48-4581-8af8-48572fa1650a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234529227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.1234529227
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.3953845240
Short name T889
Test name
Test status
Simulation time 2242390572 ps
CPU time 17.2 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:57 PM PST 24
Peak memory 200948 kb
Host smart-e5cae33a-928a-461c-ac7b-b7589ab15973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953845240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.3953845240
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.2273295994
Short name T589
Test name
Test status
Simulation time 2300565541 ps
CPU time 15.69 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 201120 kb
Host smart-b4be0b13-ca4b-4161-9910-74be74e9b11e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273295994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.2273295994
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1921593908
Short name T684
Test name
Test status
Simulation time 21725294 ps
CPU time 0.71 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200668 kb
Host smart-ef13dd04-f4df-4adc-bbf2-d9ff2fe0c228
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921593908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.1921593908
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3481297855
Short name T301
Test name
Test status
Simulation time 69861328 ps
CPU time 0.95 seconds
Started Jan 03 01:04:34 PM PST 24
Finished Jan 03 01:05:57 PM PST 24
Peak memory 200744 kb
Host smart-c2215fc7-56b6-48a2-bc6b-0412a1caee3c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481297855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.3481297855
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.2392262392
Short name T821
Test name
Test status
Simulation time 22645858 ps
CPU time 0.81 seconds
Started Jan 03 01:04:19 PM PST 24
Finished Jan 03 01:05:36 PM PST 24
Peak memory 200752 kb
Host smart-4c35f408-b637-417d-b151-67b6881eea79
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392262392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.2392262392
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.529798177
Short name T833
Test name
Test status
Simulation time 14430556 ps
CPU time 0.73 seconds
Started Jan 03 01:04:26 PM PST 24
Finished Jan 03 01:05:46 PM PST 24
Peak memory 200552 kb
Host smart-0274ee9c-0881-4c87-8921-4e33cdc90609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529798177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.529798177
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.1755331271
Short name T30
Test name
Test status
Simulation time 356671095 ps
CPU time 2.58 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:24 PM PST 24
Peak memory 200724 kb
Host smart-21dcdd4e-fc2a-45dc-bfe3-1b437b31266c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755331271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.1755331271
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.3404463749
Short name T610
Test name
Test status
Simulation time 18488043 ps
CPU time 0.79 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:32 PM PST 24
Peak memory 200740 kb
Host smart-f8111fb1-153e-487e-ba3d-f62e1975828f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404463749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.3404463749
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.3424254558
Short name T739
Test name
Test status
Simulation time 7245137947 ps
CPU time 52.49 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:06:37 PM PST 24
Peak memory 201128 kb
Host smart-b2dd41f9-f576-446e-ad2a-043337040beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424254558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.3424254558
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.706771196
Short name T568
Test name
Test status
Simulation time 145368196062 ps
CPU time 973.08 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:21:38 PM PST 24
Peak memory 214988 kb
Host smart-8c47aca1-df9a-4cfc-8ea5-96931ad953a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=706771196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.706771196
Directory /workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.clkmgr_trans.4025055813
Short name T749
Test name
Test status
Simulation time 244105673 ps
CPU time 1.42 seconds
Started Jan 03 01:04:20 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200732 kb
Host smart-7cf9ef7e-0825-4d2f-a286-843568b56306
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025055813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.4025055813
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.1545785862
Short name T966
Test name
Test status
Simulation time 58750302 ps
CPU time 0.94 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:31 PM PST 24
Peak memory 200724 kb
Host smart-a3e10337-978b-4782-9231-d2bfea5f1014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545785862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.1545785862
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2308948535
Short name T898
Test name
Test status
Simulation time 81573784 ps
CPU time 1 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:05:45 PM PST 24
Peak memory 200600 kb
Host smart-98e1a227-2178-40dc-b244-d5e8980515bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308948535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.2308948535
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.143061442
Short name T566
Test name
Test status
Simulation time 46919698 ps
CPU time 0.74 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:25 PM PST 24
Peak memory 199624 kb
Host smart-f4f942af-f6a5-43cc-ada7-e9712fcbd61e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143061442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.143061442
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.3878809104
Short name T850
Test name
Test status
Simulation time 14929158 ps
CPU time 0.77 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200740 kb
Host smart-7449d063-3bab-41b3-b845-4248aafc5b33
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878809104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.3878809104
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.3472383157
Short name T459
Test name
Test status
Simulation time 42728211 ps
CPU time 0.79 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:05:28 PM PST 24
Peak memory 200664 kb
Host smart-ca7875e6-33e8-4b73-9c09-570e23133ed1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472383157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.3472383157
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.1977264728
Short name T545
Test name
Test status
Simulation time 1175360262 ps
CPU time 5.6 seconds
Started Jan 03 01:04:06 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 200680 kb
Host smart-9ed7c57c-8dca-4122-98f3-68a954645090
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977264728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.1977264728
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.2415682646
Short name T28
Test name
Test status
Simulation time 2178277499 ps
CPU time 15.34 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:33 PM PST 24
Peak memory 201148 kb
Host smart-f1e3e6f1-f55c-4d54-a2ab-bc39fd28ca34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415682646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.2415682646
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.740330949
Short name T516
Test name
Test status
Simulation time 59161002 ps
CPU time 0.9 seconds
Started Jan 03 01:04:27 PM PST 24
Finished Jan 03 01:05:50 PM PST 24
Peak memory 200756 kb
Host smart-8d03d265-e37d-4ad6-857f-1f544ca08418
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740330949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.clkmgr_idle_intersig_mubi.740330949
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.1369904701
Short name T961
Test name
Test status
Simulation time 34706149 ps
CPU time 0.84 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:05:51 PM PST 24
Peak memory 200684 kb
Host smart-229e590e-be65-4e5a-a90d-3efe96f01bb2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369904701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.1369904701
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.1870052653
Short name T62
Test name
Test status
Simulation time 114122181 ps
CPU time 1 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:38 PM PST 24
Peak memory 200744 kb
Host smart-3da5cc61-6ab9-4729-8e75-69cf18b2a9ea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870052653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.1870052653
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.2947268200
Short name T344
Test name
Test status
Simulation time 13916635 ps
CPU time 0.72 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:05:45 PM PST 24
Peak memory 200564 kb
Host smart-6e6a9888-99c1-4354-ab67-d280e07a30b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947268200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.2947268200
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.2051193829
Short name T460
Test name
Test status
Simulation time 1221688450 ps
CPU time 4.34 seconds
Started Jan 03 01:04:02 PM PST 24
Finished Jan 03 01:05:10 PM PST 24
Peak memory 200952 kb
Host smart-657bb0c0-014d-4e9e-8410-3ff30b0ce0ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051193829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.2051193829
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.2750234827
Short name T918
Test name
Test status
Simulation time 44528035 ps
CPU time 0.89 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:40 PM PST 24
Peak memory 200736 kb
Host smart-5e58f9b9-41b1-4940-b222-f58698a22e41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750234827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.2750234827
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.2591615632
Short name T43
Test name
Test status
Simulation time 9089224411 ps
CPU time 47.12 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:06:27 PM PST 24
Peak memory 201088 kb
Host smart-49ac5004-a3d2-4494-ad92-06306ceabb3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591615632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.2591615632
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.2908729272
Short name T565
Test name
Test status
Simulation time 20370382342 ps
CPU time 304.49 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:11:00 PM PST 24
Peak memory 217448 kb
Host smart-cfb24ea5-90f5-445e-98f7-d7e4ecb40e14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2908729272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.2908729272
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.2843438895
Short name T605
Test name
Test status
Simulation time 125387425 ps
CPU time 1.23 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200752 kb
Host smart-0c6dac11-c93b-4857-84b5-9634a02f00d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843438895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.2843438895
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.2544378688
Short name T690
Test name
Test status
Simulation time 48077206 ps
CPU time 0.81 seconds
Started Jan 03 01:04:26 PM PST 24
Finished Jan 03 01:05:46 PM PST 24
Peak memory 200780 kb
Host smart-73bcb15b-b847-4bde-a852-13798694d19b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544378688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.2544378688
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.2283540923
Short name T296
Test name
Test status
Simulation time 25680868 ps
CPU time 0.93 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:43 PM PST 24
Peak memory 200776 kb
Host smart-e34b6afd-be65-48cf-a4c5-67d364d1a5d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283540923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.2283540923
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.974316913
Short name T722
Test name
Test status
Simulation time 21822708 ps
CPU time 0.7 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 199644 kb
Host smart-fa454a67-bdcf-4210-8d5d-96f2850edcda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974316913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.974316913
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.4217246471
Short name T866
Test name
Test status
Simulation time 21920794 ps
CPU time 0.79 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:05:27 PM PST 24
Peak memory 200708 kb
Host smart-ba4db3dd-5205-4a8b-9dea-0bceb3126a98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217246471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.4217246471
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.3192786020
Short name T583
Test name
Test status
Simulation time 32028126 ps
CPU time 0.76 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:05:57 PM PST 24
Peak memory 200540 kb
Host smart-e001e964-3b4a-4409-bab4-04f0f9789355
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192786020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.3192786020
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.1661593074
Short name T333
Test name
Test status
Simulation time 1530937230 ps
CPU time 7.71 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:37 PM PST 24
Peak memory 200748 kb
Host smart-4f770e42-b6fc-4c40-b5b4-fb1a1f3b1ab7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661593074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1661593074
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.4193033669
Short name T489
Test name
Test status
Simulation time 675823528 ps
CPU time 3.07 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:45 PM PST 24
Peak memory 200776 kb
Host smart-29035a77-12da-4925-b9f9-0f425a273b8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193033669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.4193033669
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1157772551
Short name T319
Test name
Test status
Simulation time 272588693 ps
CPU time 1.57 seconds
Started Jan 03 01:04:41 PM PST 24
Finished Jan 03 01:06:16 PM PST 24
Peak memory 200760 kb
Host smart-a88af089-d9d8-4b03-bb08-54b327a799c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157772551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.1157772551
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2431696361
Short name T449
Test name
Test status
Simulation time 25574427 ps
CPU time 0.83 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:35 PM PST 24
Peak memory 200816 kb
Host smart-851fec7d-b6d4-40cd-88c2-33ff277d87af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431696361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.2431696361
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.348805925
Short name T145
Test name
Test status
Simulation time 18635983 ps
CPU time 0.77 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:05:52 PM PST 24
Peak memory 200696 kb
Host smart-15b14991-e263-4801-9743-9eb120cd7ee6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348805925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_ctrl_intersig_mubi.348805925
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.2286068444
Short name T492
Test name
Test status
Simulation time 22429235 ps
CPU time 0.73 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:40 PM PST 24
Peak memory 200644 kb
Host smart-5aed2092-cb88-48a1-aae2-0ba83294fb4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286068444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.2286068444
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.2636419212
Short name T891
Test name
Test status
Simulation time 162576943 ps
CPU time 1.39 seconds
Started Jan 03 01:04:20 PM PST 24
Finished Jan 03 01:05:38 PM PST 24
Peak memory 200668 kb
Host smart-78df9312-2595-473f-af85-51228db630bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636419212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.2636419212
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.2547600448
Short name T452
Test name
Test status
Simulation time 180078858 ps
CPU time 1.22 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200720 kb
Host smart-03bdc444-54c9-499e-b6f0-f2bc07e82f4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547600448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.2547600448
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.4291153629
Short name T117
Test name
Test status
Simulation time 9752750179 ps
CPU time 66.43 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:06:49 PM PST 24
Peak memory 201048 kb
Host smart-13a00772-654a-485d-9265-a1ca125e9290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291153629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.4291153629
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.2755272330
Short name T639
Test name
Test status
Simulation time 19392338510 ps
CPU time 270.65 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:10:10 PM PST 24
Peak memory 217496 kb
Host smart-7f4151e7-001b-49cf-9c89-19ad4125bced
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2755272330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.2755272330
Directory /workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.clkmgr_trans.868849
Short name T649
Test name
Test status
Simulation time 41287708 ps
CPU time 0.76 seconds
Started Jan 03 01:04:27 PM PST 24
Finished Jan 03 01:05:48 PM PST 24
Peak memory 200684 kb
Host smart-627ec57e-fb22-44cc-902d-b79dc03e82fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.868849
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.3186599171
Short name T297
Test name
Test status
Simulation time 17993753 ps
CPU time 0.77 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:26 PM PST 24
Peak memory 200784 kb
Host smart-ef7f20c1-201f-4b2c-846c-f9b6ea5d933e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186599171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.3186599171
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1450065579
Short name T817
Test name
Test status
Simulation time 25825973 ps
CPU time 0.89 seconds
Started Jan 03 01:04:45 PM PST 24
Finished Jan 03 01:06:04 PM PST 24
Peak memory 200700 kb
Host smart-04c10a9b-af5a-4da3-8756-5238c0c749cf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450065579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.1450065579
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.3598275171
Short name T982
Test name
Test status
Simulation time 52878635 ps
CPU time 0.81 seconds
Started Jan 03 01:04:20 PM PST 24
Finished Jan 03 01:05:38 PM PST 24
Peak memory 199660 kb
Host smart-8bff39c5-bd60-4687-9310-69c2d4bdc5c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598275171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.3598275171
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.2045919367
Short name T421
Test name
Test status
Simulation time 27059708 ps
CPU time 0.76 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:35 PM PST 24
Peak memory 200664 kb
Host smart-8c2e6e87-8d66-464f-8dc4-be768ac01031
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045919367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.2045919367
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.221197356
Short name T316
Test name
Test status
Simulation time 28901102 ps
CPU time 0.92 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:43 PM PST 24
Peak memory 200652 kb
Host smart-7d452ee4-f8c3-4dcd-84db-ee5fe4f936ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221197356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.221197356
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.1854353208
Short name T488
Test name
Test status
Simulation time 1406513505 ps
CPU time 8.6 seconds
Started Jan 03 01:04:42 PM PST 24
Finished Jan 03 01:06:14 PM PST 24
Peak memory 200812 kb
Host smart-2d348c3e-20e7-467e-9a7d-c117fa12882d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854353208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.1854353208
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.2018582314
Short name T498
Test name
Test status
Simulation time 2463407117 ps
CPU time 9.84 seconds
Started Jan 03 01:04:27 PM PST 24
Finished Jan 03 01:05:59 PM PST 24
Peak memory 200992 kb
Host smart-b618846b-9c7e-48e5-8559-2cc3b3110947
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018582314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.2018582314
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.2150955515
Short name T858
Test name
Test status
Simulation time 162765151 ps
CPU time 1.41 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:45 PM PST 24
Peak memory 200744 kb
Host smart-4fb299be-ab18-49e4-8181-7492790f8e52
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150955515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.2150955515
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1037324150
Short name T651
Test name
Test status
Simulation time 23442325 ps
CPU time 0.85 seconds
Started Jan 03 01:04:10 PM PST 24
Finished Jan 03 01:05:20 PM PST 24
Peak memory 200704 kb
Host smart-37c12f51-c5cf-4be1-94cf-7df89cf732da
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037324150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1037324150
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1029899730
Short name T854
Test name
Test status
Simulation time 30346851 ps
CPU time 0.78 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:05:59 PM PST 24
Peak memory 200764 kb
Host smart-03465f4a-6326-48f4-b669-97aa984746cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029899730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.1029899730
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.1361901103
Short name T805
Test name
Test status
Simulation time 22393582 ps
CPU time 0.74 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200552 kb
Host smart-924f642a-d36a-4ff9-9dec-3381d18f7a7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361901103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.1361901103
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.2653276329
Short name T102
Test name
Test status
Simulation time 172869625 ps
CPU time 1.62 seconds
Started Jan 03 01:04:43 PM PST 24
Finished Jan 03 01:06:11 PM PST 24
Peak memory 200752 kb
Host smart-e622ce84-1629-4c0c-b352-d6f9695d52d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653276329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.2653276329
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.469593594
Short name T644
Test name
Test status
Simulation time 30459735 ps
CPU time 0.88 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200808 kb
Host smart-b9111127-f817-457c-8e0c-12cc0a576647
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469593594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.469593594
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.3941494664
Short name T445
Test name
Test status
Simulation time 4643343384 ps
CPU time 32.84 seconds
Started Jan 03 01:04:37 PM PST 24
Finished Jan 03 01:06:32 PM PST 24
Peak memory 200980 kb
Host smart-d7cfc803-1d71-4048-b4e0-fc6668279376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941494664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.3941494664
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.1481319985
Short name T338
Test name
Test status
Simulation time 32028584937 ps
CPU time 366.59 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:11:58 PM PST 24
Peak memory 209304 kb
Host smart-ca062dcb-070a-4dc1-b44a-e2e046c1286b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1481319985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.1481319985
Directory /workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.clkmgr_trans.3588016271
Short name T292
Test name
Test status
Simulation time 40069808 ps
CPU time 0.86 seconds
Started Jan 03 01:04:54 PM PST 24
Finished Jan 03 01:06:15 PM PST 24
Peak memory 200660 kb
Host smart-15f2a320-8760-4b43-af86-7d3c3e283fd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588016271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.3588016271
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.3239610519
Short name T513
Test name
Test status
Simulation time 31224479 ps
CPU time 0.79 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:05:27 PM PST 24
Peak memory 200680 kb
Host smart-023fefbb-3790-495e-b9cb-35552af1a15c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239610519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.3239610519
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.3027378703
Short name T944
Test name
Test status
Simulation time 24967686 ps
CPU time 0.84 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:22 PM PST 24
Peak memory 200780 kb
Host smart-46abf4c2-c889-48fb-ac7e-c1117f3d54a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027378703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.3027378703
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.1152338502
Short name T511
Test name
Test status
Simulation time 24075561 ps
CPU time 0.71 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 199664 kb
Host smart-3a24e9b3-1352-47b0-8c3b-f8eb1efde0b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152338502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1152338502
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.4026927819
Short name T642
Test name
Test status
Simulation time 25115705 ps
CPU time 0.84 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:20 PM PST 24
Peak memory 200860 kb
Host smart-37ee5415-1092-457c-a46e-50d774a0e46b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026927819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.4026927819
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.3251057597
Short name T671
Test name
Test status
Simulation time 17885920 ps
CPU time 0.74 seconds
Started Jan 03 01:04:18 PM PST 24
Finished Jan 03 01:05:35 PM PST 24
Peak memory 200776 kb
Host smart-04c1ed76-1028-49a6-9610-9648d87fb869
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251057597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.3251057597
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.1221436314
Short name T377
Test name
Test status
Simulation time 2009855191 ps
CPU time 8.74 seconds
Started Jan 03 01:04:30 PM PST 24
Finished Jan 03 01:05:58 PM PST 24
Peak memory 200940 kb
Host smart-a068c112-aed4-449f-81dd-deb047a5f2e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221436314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.1221436314
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.2035386645
Short name T331
Test name
Test status
Simulation time 1095175541 ps
CPU time 7.75 seconds
Started Jan 03 01:03:59 PM PST 24
Finished Jan 03 01:05:09 PM PST 24
Peak memory 200816 kb
Host smart-944ed312-0cc7-4ed0-8932-9dddccac9549
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035386645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.2035386645
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.779830968
Short name T587
Test name
Test status
Simulation time 88511987 ps
CPU time 1.12 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:32 PM PST 24
Peak memory 200748 kb
Host smart-23c3db33-2471-46c2-b183-7d517151d8b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779830968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.clkmgr_idle_intersig_mubi.779830968
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.3946160933
Short name T309
Test name
Test status
Simulation time 99636590 ps
CPU time 1.1 seconds
Started Jan 03 01:04:38 PM PST 24
Finished Jan 03 01:05:59 PM PST 24
Peak memory 200832 kb
Host smart-cbf5cc92-dd9f-4014-94c9-3eb4dac1943e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946160933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.3946160933
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.997489887
Short name T425
Test name
Test status
Simulation time 21652019 ps
CPU time 0.82 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:29 PM PST 24
Peak memory 200812 kb
Host smart-cacc79fe-6c34-4aff-b1d3-c848503d41ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997489887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.clkmgr_lc_ctrl_intersig_mubi.997489887
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.858582933
Short name T718
Test name
Test status
Simulation time 83928051 ps
CPU time 0.84 seconds
Started Jan 03 01:04:12 PM PST 24
Finished Jan 03 01:05:23 PM PST 24
Peak memory 200752 kb
Host smart-b8c7fccc-25dc-4c51-9282-1391c74cdbc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858582933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.858582933
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.4170174318
Short name T506
Test name
Test status
Simulation time 1338486467 ps
CPU time 5.68 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:36 PM PST 24
Peak memory 200952 kb
Host smart-4fbe5d3a-96bb-4242-9e80-445bc6065342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170174318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.4170174318
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.953896281
Short name T766
Test name
Test status
Simulation time 47245050 ps
CPU time 0.86 seconds
Started Jan 03 01:04:06 PM PST 24
Finished Jan 03 01:05:13 PM PST 24
Peak memory 200804 kb
Host smart-0179a8c2-f0f3-4dba-a80e-51581b33526e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953896281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.953896281
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.1763788833
Short name T965
Test name
Test status
Simulation time 4745974326 ps
CPU time 19.93 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:52 PM PST 24
Peak memory 201048 kb
Host smart-f7f23b7b-2968-47cb-808a-c04b4f2954d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763788833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.1763788833
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.2633547716
Short name T42
Test name
Test status
Simulation time 142041623864 ps
CPU time 848.24 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:19:36 PM PST 24
Peak memory 209464 kb
Host smart-0ef7675c-aa77-4ada-a581-64c6062db989
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2633547716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.2633547716
Directory /workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.clkmgr_trans.246751718
Short name T734
Test name
Test status
Simulation time 16250402 ps
CPU time 0.75 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200732 kb
Host smart-45fa1489-f631-4a6a-8bb9-cb06ea687ff6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246751718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.246751718
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.995057580
Short name T371
Test name
Test status
Simulation time 56447358 ps
CPU time 0.89 seconds
Started Jan 03 01:04:02 PM PST 24
Finished Jan 03 01:05:06 PM PST 24
Peak memory 200772 kb
Host smart-4d30c4c1-a071-41f4-8a27-97ebf5b3ba61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995057580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkm
gr_alert_test.995057580
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.2026493668
Short name T144
Test name
Test status
Simulation time 19798114 ps
CPU time 0.78 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:05:28 PM PST 24
Peak memory 200748 kb
Host smart-2f8ed3a4-884c-48e8-a9b4-4f62a170b961
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026493668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.2026493668
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.2751805424
Short name T950
Test name
Test status
Simulation time 25131519 ps
CPU time 0.75 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:31 PM PST 24
Peak memory 199564 kb
Host smart-28f28d02-0e24-49c7-a7be-588bb3f604ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751805424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.2751805424
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.2044777422
Short name T518
Test name
Test status
Simulation time 25153894 ps
CPU time 0.85 seconds
Started Jan 03 01:04:23 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200696 kb
Host smart-d47af037-7939-4caa-836b-0dad50f4d78b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044777422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.2044777422
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.61566692
Short name T157
Test name
Test status
Simulation time 46498444 ps
CPU time 0.88 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200696 kb
Host smart-4d35936b-5baf-4461-991f-2ec72fea31ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61566692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.61566692
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.4038988873
Short name T3
Test name
Test status
Simulation time 736635703 ps
CPU time 3.58 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:36 PM PST 24
Peak memory 200704 kb
Host smart-1d2a1410-b7b9-4466-b855-5fa55337b703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038988873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.4038988873
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.1845266367
Short name T416
Test name
Test status
Simulation time 275547220 ps
CPU time 1.73 seconds
Started Jan 03 01:04:32 PM PST 24
Finished Jan 03 01:05:56 PM PST 24
Peak memory 200884 kb
Host smart-639bca8a-3589-493b-bfba-b973fe6acc46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845266367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.1845266367
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.18834537
Short name T713
Test name
Test status
Simulation time 20418501 ps
CPU time 0.76 seconds
Started Jan 03 01:04:19 PM PST 24
Finished Jan 03 01:05:36 PM PST 24
Peak memory 200760 kb
Host smart-cba4117e-6773-40bb-91ad-60d012603311
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18834537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.clkmgr_idle_intersig_mubi.18834537
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.2116321144
Short name T729
Test name
Test status
Simulation time 48633283 ps
CPU time 0.92 seconds
Started Jan 03 01:04:21 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 200600 kb
Host smart-a7252076-d6f7-41f2-b894-2871a46c92d1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116321144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.2116321144
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3811217175
Short name T656
Test name
Test status
Simulation time 28524303 ps
CPU time 0.74 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:30 PM PST 24
Peak memory 200804 kb
Host smart-0af08504-c626-4a8b-afb9-9ded38d09ef6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811217175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.3811217175
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.3620067057
Short name T963
Test name
Test status
Simulation time 18254120 ps
CPU time 0.76 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:35 PM PST 24
Peak memory 200776 kb
Host smart-c7d349e6-2601-4914-9a7d-3c16799610ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620067057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3620067057
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.1457046226
Short name T641
Test name
Test status
Simulation time 409660131 ps
CPU time 2.7 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:14 PM PST 24
Peak memory 200728 kb
Host smart-20be4f0c-bced-4332-aebe-65fe265c83ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457046226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.1457046226
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.2624899767
Short name T328
Test name
Test status
Simulation time 22820006 ps
CPU time 0.83 seconds
Started Jan 03 01:04:18 PM PST 24
Finished Jan 03 01:05:34 PM PST 24
Peak memory 200744 kb
Host smart-fc37273e-b3ef-47f6-a348-5fa6b487702b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624899767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.2624899767
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.1879346836
Short name T772
Test name
Test status
Simulation time 13155470068 ps
CPU time 99.15 seconds
Started Jan 03 01:04:40 PM PST 24
Finished Jan 03 01:07:39 PM PST 24
Peak memory 201124 kb
Host smart-7a2e94fa-1f67-4c58-98e3-cd376fbfebe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879346836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.1879346836
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.2065854735
Short name T626
Test name
Test status
Simulation time 95160369612 ps
CPU time 571.31 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:14:55 PM PST 24
Peak memory 209304 kb
Host smart-0c725003-9126-4017-a41b-878daf354d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2065854735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.2065854735
Directory /workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.clkmgr_trans.1248946725
Short name T752
Test name
Test status
Simulation time 121442029 ps
CPU time 1.23 seconds
Started Jan 03 01:04:10 PM PST 24
Finished Jan 03 01:05:20 PM PST 24
Peak memory 200808 kb
Host smart-9c8dca57-f36f-44ba-abed-44241483fc51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248946725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.1248946725
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.2797767217
Short name T439
Test name
Test status
Simulation time 26803344 ps
CPU time 0.74 seconds
Started Jan 03 01:04:40 PM PST 24
Finished Jan 03 01:06:01 PM PST 24
Peak memory 200684 kb
Host smart-d32e43e5-ff39-4b4d-a8c0-ad90d50eecea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797767217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.2797767217
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3462400128
Short name T381
Test name
Test status
Simulation time 37309707 ps
CPU time 0.9 seconds
Started Jan 03 01:04:25 PM PST 24
Finished Jan 03 01:05:45 PM PST 24
Peak memory 200728 kb
Host smart-59bcbaec-e00e-44ed-bc13-96406822a8c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462400128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.3462400128
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.289493078
Short name T521
Test name
Test status
Simulation time 16840182 ps
CPU time 0.71 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:39 PM PST 24
Peak memory 199604 kb
Host smart-f00368b1-7cb8-4ff3-8d8a-b3979eadd827
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289493078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.289493078
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.902435736
Short name T343
Test name
Test status
Simulation time 18098285 ps
CPU time 0.75 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:40 PM PST 24
Peak memory 200768 kb
Host smart-6e2efe58-6d9a-4242-ab54-44384356ff7e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902435736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_div_intersig_mubi.902435736
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.681532747
Short name T661
Test name
Test status
Simulation time 26272494 ps
CPU time 0.83 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:05:59 PM PST 24
Peak memory 200672 kb
Host smart-f22ac61a-9528-4297-b560-c63cc69123d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681532747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.681532747
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.428101521
Short name T844
Test name
Test status
Simulation time 2241588910 ps
CPU time 16.2 seconds
Started Jan 03 01:04:31 PM PST 24
Finished Jan 03 01:06:17 PM PST 24
Peak memory 200984 kb
Host smart-e1142b74-66b4-42b9-b16c-d3e6ad38c403
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428101521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.428101521
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.3653643635
Short name T939
Test name
Test status
Simulation time 266992105 ps
CPU time 1.84 seconds
Started Jan 03 01:04:19 PM PST 24
Finished Jan 03 01:05:37 PM PST 24
Peak memory 200792 kb
Host smart-bd702791-ed6f-4353-9b7d-c08f68749fb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653643635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.3653643635
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.147010653
Short name T386
Test name
Test status
Simulation time 37306984 ps
CPU time 1 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:05:57 PM PST 24
Peak memory 200676 kb
Host smart-fa4e5600-d161-4a2d-903a-aef00d7d3bf8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147010653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_idle_intersig_mubi.147010653
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.2949887629
Short name T702
Test name
Test status
Simulation time 244599341 ps
CPU time 1.45 seconds
Started Jan 03 01:04:48 PM PST 24
Finished Jan 03 01:06:09 PM PST 24
Peak memory 200740 kb
Host smart-441d11a1-4b40-4fa5-ac4e-098ae293eb96
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949887629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.2949887629
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.2518408035
Short name T23
Test name
Test status
Simulation time 19494947 ps
CPU time 0.79 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:05:57 PM PST 24
Peak memory 200772 kb
Host smart-d2491e5f-27b4-4e06-81bf-ff1e6ff13131
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518408035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.2518408035
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.2537638700
Short name T912
Test name
Test status
Simulation time 14246540 ps
CPU time 0.73 seconds
Started Jan 03 01:04:27 PM PST 24
Finished Jan 03 01:05:47 PM PST 24
Peak memory 200632 kb
Host smart-dc42ddae-ec7c-4abc-83d6-07d6fc64bb1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537638700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.2537638700
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.85837649
Short name T717
Test name
Test status
Simulation time 596691126 ps
CPU time 3.55 seconds
Started Jan 03 01:04:36 PM PST 24
Finished Jan 03 01:06:15 PM PST 24
Peak memory 200908 kb
Host smart-65920198-1120-4115-b112-6f68b7bf8af7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85837649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.85837649
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.222716056
Short name T701
Test name
Test status
Simulation time 99857595 ps
CPU time 1.06 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:33 PM PST 24
Peak memory 200748 kb
Host smart-77cbde5f-1bec-4741-8e62-8dcd0e092b0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222716056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.222716056
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.187583438
Short name T926
Test name
Test status
Simulation time 2006070922 ps
CPU time 9.14 seconds
Started Jan 03 01:04:43 PM PST 24
Finished Jan 03 01:06:15 PM PST 24
Peak memory 201056 kb
Host smart-35df05c7-01d9-4651-ab2b-0d573a568749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187583438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.187583438
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.232393476
Short name T954
Test name
Test status
Simulation time 27641277883 ps
CPU time 382.22 seconds
Started Jan 03 01:04:27 PM PST 24
Finished Jan 03 01:12:10 PM PST 24
Peak memory 217088 kb
Host smart-c5edc333-1521-448b-8099-41adf0f88d31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=232393476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.232393476
Directory /workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.clkmgr_trans.634899501
Short name T660
Test name
Test status
Simulation time 25549282 ps
CPU time 0.89 seconds
Started Jan 03 01:04:26 PM PST 24
Finished Jan 03 01:05:46 PM PST 24
Peak memory 200772 kb
Host smart-315b4e62-1a52-46db-a5df-26dd9ac688e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634899501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.634899501
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.4115141537
Short name T987
Test name
Test status
Simulation time 28921508 ps
CPU time 0.76 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:05:07 PM PST 24
Peak memory 200736 kb
Host smart-d8f58062-ef69-4302-9676-593b708bf3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115141537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.4115141537
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2155842964
Short name T669
Test name
Test status
Simulation time 141030071 ps
CPU time 1.22 seconds
Started Jan 03 01:04:00 PM PST 24
Finished Jan 03 01:05:04 PM PST 24
Peak memory 200784 kb
Host smart-c3d9c396-68cf-4fe4-81f8-39de52e26961
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155842964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.2155842964
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.4185928260
Short name T140
Test name
Test status
Simulation time 48273838 ps
CPU time 0.74 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:33 PM PST 24
Peak memory 199664 kb
Host smart-aaed641b-4734-4668-b644-151a10c4002c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185928260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.4185928260
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.1006269055
Short name T776
Test name
Test status
Simulation time 30386450 ps
CPU time 0.79 seconds
Started Jan 03 01:04:16 PM PST 24
Finished Jan 03 01:05:30 PM PST 24
Peak memory 200784 kb
Host smart-c01ec35c-d4d8-4202-ae2f-d8f1863333bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006269055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.1006269055
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.110570217
Short name T974
Test name
Test status
Simulation time 24958020 ps
CPU time 0.86 seconds
Started Jan 03 01:03:59 PM PST 24
Finished Jan 03 01:05:01 PM PST 24
Peak memory 200752 kb
Host smart-453f8cd1-490a-463f-ac68-dc32b7ec3d02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110570217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.110570217
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.3533909
Short name T676
Test name
Test status
Simulation time 925197713 ps
CPU time 6.38 seconds
Started Jan 03 01:04:19 PM PST 24
Finished Jan 03 01:05:42 PM PST 24
Peak memory 200692 kb
Host smart-7703e092-7cf9-41ed-89dc-28cdcf603f73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.3533909
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.144058027
Short name T299
Test name
Test status
Simulation time 887480494 ps
CPU time 4.02 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:24 PM PST 24
Peak memory 200808 kb
Host smart-eec29695-2165-47c2-ac94-edb0e5ca6868
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144058027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_ti
meout.144058027
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.3893197669
Short name T904
Test name
Test status
Simulation time 22310300 ps
CPU time 0.81 seconds
Started Jan 03 01:04:09 PM PST 24
Finished Jan 03 01:05:17 PM PST 24
Peak memory 200704 kb
Host smart-5d721317-e915-4ef6-9e67-fab977e6fd08
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893197669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.3893197669
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3244549851
Short name T464
Test name
Test status
Simulation time 35242209 ps
CPU time 0.89 seconds
Started Jan 03 01:04:30 PM PST 24
Finished Jan 03 01:05:54 PM PST 24
Peak memory 200720 kb
Host smart-7fa75d70-53e9-44fc-bdf7-7961c7b7fb8b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244549851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.3244549851
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.3197156739
Short name T781
Test name
Test status
Simulation time 15742468 ps
CPU time 0.76 seconds
Started Jan 03 01:04:08 PM PST 24
Finished Jan 03 01:05:15 PM PST 24
Peak memory 200648 kb
Host smart-e301821f-5421-434d-a17c-2998c66de59c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197156739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.3197156739
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.3082835943
Short name T455
Test name
Test status
Simulation time 12903161 ps
CPU time 0.71 seconds
Started Jan 03 01:04:11 PM PST 24
Finished Jan 03 01:05:20 PM PST 24
Peak memory 200680 kb
Host smart-6573e0a9-9e76-42f8-aab9-c5e63c5c39aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082835943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.3082835943
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.856026789
Short name T440
Test name
Test status
Simulation time 892713647 ps
CPU time 3.37 seconds
Started Jan 03 01:03:52 PM PST 24
Finished Jan 03 01:04:52 PM PST 24
Peak memory 201008 kb
Host smart-ac4355ca-582b-4073-a368-7c6c3e5ffe6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856026789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.856026789
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.2790168095
Short name T361
Test name
Test status
Simulation time 22099112 ps
CPU time 0.85 seconds
Started Jan 03 01:04:31 PM PST 24
Finished Jan 03 01:06:13 PM PST 24
Peak memory 200808 kb
Host smart-fd9d5e53-e35b-43bc-b44d-597f32cf9567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790168095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2790168095
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.456060967
Short name T905
Test name
Test status
Simulation time 5832879768 ps
CPU time 21.61 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:06:00 PM PST 24
Peak memory 201080 kb
Host smart-7eefa444-0c8f-44cb-95a3-20fd9bf0f6d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456060967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.456060967
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.2997594799
Short name T862
Test name
Test status
Simulation time 10985026967 ps
CPU time 164.7 seconds
Started Jan 03 01:04:14 PM PST 24
Finished Jan 03 01:08:11 PM PST 24
Peak memory 209296 kb
Host smart-00f9a8c6-51a2-43e7-88d8-59d913fb84ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2997594799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.2997594799
Directory /workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.clkmgr_trans.3028247807
Short name T725
Test name
Test status
Simulation time 56824401 ps
CPU time 0.9 seconds
Started Jan 03 01:04:05 PM PST 24
Finished Jan 03 01:05:12 PM PST 24
Peak memory 200780 kb
Host smart-1f1463db-45c5-4324-b39b-32a74637189e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028247807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3028247807
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.3959166386
Short name T366
Test name
Test status
Simulation time 21868608 ps
CPU time 0.83 seconds
Started Jan 03 01:04:20 PM PST 24
Finished Jan 03 01:05:38 PM PST 24
Peak memory 200764 kb
Host smart-1dbbe45d-9402-4124-8bdd-37986d8b6a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959166386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.3959166386
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.2660383581
Short name T910
Test name
Test status
Simulation time 27464189 ps
CPU time 0.78 seconds
Started Jan 03 01:04:18 PM PST 24
Finished Jan 03 01:05:34 PM PST 24
Peak memory 200740 kb
Host smart-25101a79-def7-4d9e-a198-3328e1ba4cf5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660383581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.2660383581
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.2915380352
Short name T856
Test name
Test status
Simulation time 15781913 ps
CPU time 0.71 seconds
Started Jan 03 01:04:28 PM PST 24
Finished Jan 03 01:05:51 PM PST 24
Peak memory 199592 kb
Host smart-82a40296-e674-4bf5-9233-07fd1e00ab57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915380352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.2915380352
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.3493409112
Short name T738
Test name
Test status
Simulation time 25793392 ps
CPU time 0.86 seconds
Started Jan 03 01:04:19 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200712 kb
Host smart-b5e5b7ae-be6e-4ea4-8d6b-48d4c38227e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493409112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.3493409112
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.3328196577
Short name T816
Test name
Test status
Simulation time 51082923 ps
CPU time 0.9 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:05:29 PM PST 24
Peak memory 200792 kb
Host smart-b678d238-8d1e-45d6-81db-8f08142974f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328196577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3328196577
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.111781765
Short name T14
Test name
Test status
Simulation time 1760827774 ps
CPU time 12.74 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:36 PM PST 24
Peak memory 200832 kb
Host smart-fe4f72ad-46db-4306-9530-b1153a4c990d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111781765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.111781765
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.2637746454
Short name T859
Test name
Test status
Simulation time 613332897 ps
CPU time 4.74 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:47 PM PST 24
Peak memory 200716 kb
Host smart-2dfb0ba4-54a2-4725-b8b2-a72bc6acaf6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637746454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.2637746454
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.3631103186
Short name T422
Test name
Test status
Simulation time 285850960 ps
CPU time 1.69 seconds
Started Jan 03 01:04:34 PM PST 24
Finished Jan 03 01:05:58 PM PST 24
Peak memory 200592 kb
Host smart-355afd40-0bd9-4280-b3fe-b3fc53300277
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631103186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.3631103186
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3257512476
Short name T761
Test name
Test status
Simulation time 12918855 ps
CPU time 0.7 seconds
Started Jan 03 01:04:13 PM PST 24
Finished Jan 03 01:05:24 PM PST 24
Peak memory 200588 kb
Host smart-0457a159-d1b4-4df3-a0c7-e3854779bc49
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257512476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.3257512476
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3018218121
Short name T980
Test name
Test status
Simulation time 90452344 ps
CPU time 1.05 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200600 kb
Host smart-3be9f8f2-c89d-4526-a2cc-3d0b11f7a989
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018218121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.3018218121
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.2203000185
Short name T882
Test name
Test status
Simulation time 44502139 ps
CPU time 0.8 seconds
Started Jan 03 01:04:20 PM PST 24
Finished Jan 03 01:05:37 PM PST 24
Peak memory 200696 kb
Host smart-128f7a5d-0845-49d5-841b-173acdea05b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203000185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.2203000185
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.3917935008
Short name T390
Test name
Test status
Simulation time 943596196 ps
CPU time 3.54 seconds
Started Jan 03 01:04:24 PM PST 24
Finished Jan 03 01:05:46 PM PST 24
Peak memory 200912 kb
Host smart-df8ff8b4-633e-4e7d-a1ea-9ecd0373598a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917935008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3917935008
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.2822563376
Short name T955
Test name
Test status
Simulation time 87071177 ps
CPU time 1.02 seconds
Started Jan 03 01:04:22 PM PST 24
Finished Jan 03 01:05:41 PM PST 24
Peak memory 200812 kb
Host smart-d82ae1fd-e74a-4e13-9295-94822226efeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822563376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.2822563376
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.3068613595
Short name T462
Test name
Test status
Simulation time 4453238335 ps
CPU time 32.16 seconds
Started Jan 03 01:04:15 PM PST 24
Finished Jan 03 01:06:00 PM PST 24
Peak memory 201084 kb
Host smart-c390b41c-40d9-4af8-91a6-b60a1c2bd8f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068613595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.3068613595
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.3581222897
Short name T16
Test name
Test status
Simulation time 107635780549 ps
CPU time 1128.51 seconds
Started Jan 03 01:04:30 PM PST 24
Finished Jan 03 01:24:42 PM PST 24
Peak memory 209336 kb
Host smart-7452a4cb-ad79-4162-9962-9c2eb0f29c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3581222897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.3581222897
Directory /workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.clkmgr_trans.2512702372
Short name T875
Test name
Test status
Simulation time 22413719 ps
CPU time 0.8 seconds
Started Jan 03 01:04:17 PM PST 24
Finished Jan 03 01:05:35 PM PST 24
Peak memory 200712 kb
Host smart-c372303b-79a9-47d0-b2f1-1099ccdfd296
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512702372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.2512702372
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.3596026011
Short name T451
Test name
Test status
Simulation time 14552930 ps
CPU time 0.7 seconds
Started Jan 03 01:02:48 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 200780 kb
Host smart-b3fcec0b-d405-4e8d-954a-62e1f158a137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596026011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.3596026011
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.636754361
Short name T468
Test name
Test status
Simulation time 15155271 ps
CPU time 0.74 seconds
Started Jan 03 01:02:43 PM PST 24
Finished Jan 03 01:03:49 PM PST 24
Peak memory 200740 kb
Host smart-dc44d1e7-f3a4-4226-a66d-956d53e79b3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636754361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.636754361
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.944536232
Short name T139
Test name
Test status
Simulation time 16407920 ps
CPU time 0.71 seconds
Started Jan 03 01:02:49 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 199592 kb
Host smart-2bcd171c-ed86-4860-bd2e-f5116ca4f0fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944536232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.944536232
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.1003944501
Short name T814
Test name
Test status
Simulation time 172301143 ps
CPU time 1.2 seconds
Started Jan 03 01:02:44 PM PST 24
Finished Jan 03 01:03:51 PM PST 24
Peak memory 200716 kb
Host smart-144cc54b-82f8-4f5a-af13-1611c60bbaee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003944501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.1003944501
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.2765675568
Short name T427
Test name
Test status
Simulation time 40117568 ps
CPU time 0.9 seconds
Started Jan 03 01:02:46 PM PST 24
Finished Jan 03 01:03:53 PM PST 24
Peak memory 200740 kb
Host smart-964181e8-3193-46ac-a7f2-c0555349e7e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765675568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.2765675568
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.537580127
Short name T334
Test name
Test status
Simulation time 1281619155 ps
CPU time 9.77 seconds
Started Jan 03 01:02:50 PM PST 24
Finished Jan 03 01:04:06 PM PST 24
Peak memory 200752 kb
Host smart-0f53527d-03e5-452e-a6df-1cfbef07eb91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537580127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.537580127
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.1029536390
Short name T546
Test name
Test status
Simulation time 258659775 ps
CPU time 1.76 seconds
Started Jan 03 01:02:28 PM PST 24
Finished Jan 03 01:03:37 PM PST 24
Peak memory 200876 kb
Host smart-e732ae01-5fde-4229-8d16-44852a2dc8ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029536390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.1029536390
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.1519765435
Short name T787
Test name
Test status
Simulation time 28324317 ps
CPU time 0.9 seconds
Started Jan 03 01:02:54 PM PST 24
Finished Jan 03 01:03:59 PM PST 24
Peak memory 200796 kb
Host smart-c75b33c6-2734-49fd-a107-af9919f2f265
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519765435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.1519765435
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.128619951
Short name T311
Test name
Test status
Simulation time 16725926 ps
CPU time 0.73 seconds
Started Jan 03 01:03:01 PM PST 24
Finished Jan 03 01:04:08 PM PST 24
Peak memory 200708 kb
Host smart-646018b8-b387-4af3-97e4-8f447fd2f271
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128619951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_clk_byp_req_intersig_mubi.128619951
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.2385903928
Short name T481
Test name
Test status
Simulation time 68662569 ps
CPU time 0.98 seconds
Started Jan 03 01:03:05 PM PST 24
Finished Jan 03 01:04:12 PM PST 24
Peak memory 200788 kb
Host smart-3a11ff60-6677-4435-aefe-65d1f47667d1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385903928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.2385903928
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.3605335632
Short name T598
Test name
Test status
Simulation time 81446210 ps
CPU time 0.88 seconds
Started Jan 03 01:02:32 PM PST 24
Finished Jan 03 01:03:40 PM PST 24
Peak memory 200608 kb
Host smart-445c57b9-1fc2-4760-aa14-1476bb6cd376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605335632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3605335632
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.1530190990
Short name T103
Test name
Test status
Simulation time 632275233 ps
CPU time 2.85 seconds
Started Jan 03 01:02:43 PM PST 24
Finished Jan 03 01:03:51 PM PST 24
Peak memory 200896 kb
Host smart-5c1fa5a3-d1d5-4a5c-bd1b-45eda448ceb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530190990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1530190990
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.521143742
Short name T448
Test name
Test status
Simulation time 18199614 ps
CPU time 0.8 seconds
Started Jan 03 01:02:43 PM PST 24
Finished Jan 03 01:03:50 PM PST 24
Peak memory 200744 kb
Host smart-f4a90864-8e5a-41cc-9b3f-12803ea5844c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521143742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.521143742
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.3049137737
Short name T735
Test name
Test status
Simulation time 13199074488 ps
CPU time 56.81 seconds
Started Jan 03 01:02:43 PM PST 24
Finished Jan 03 01:04:46 PM PST 24
Peak memory 200984 kb
Host smart-2704b8a8-6ec5-46ba-8f75-ad4a5a0e5acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049137737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.3049137737
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.1769484323
Short name T765
Test name
Test status
Simulation time 172353095116 ps
CPU time 971.38 seconds
Started Jan 03 01:02:46 PM PST 24
Finished Jan 03 01:20:03 PM PST 24
Peak memory 217524 kb
Host smart-2fcf1334-ee2f-466a-b5dc-a0d7d152f0b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1769484323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.1769484323
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.clkmgr_trans.3178807100
Short name T293
Test name
Test status
Simulation time 27361367 ps
CPU time 0.88 seconds
Started Jan 03 01:02:32 PM PST 24
Finished Jan 03 01:03:40 PM PST 24
Peak memory 200696 kb
Host smart-02c0cbf1-e9a4-4b8b-9369-11a303730295
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178807100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.3178807100
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.117726403
Short name T784
Test name
Test status
Simulation time 15832635 ps
CPU time 0.73 seconds
Started Jan 03 01:02:47 PM PST 24
Finished Jan 03 01:03:53 PM PST 24
Peak memory 200816 kb
Host smart-93562611-f303-4d96-beec-4b8b36f574cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117726403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg
r_alert_test.117726403
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.1909227940
Short name T156
Test name
Test status
Simulation time 175185333 ps
CPU time 1.36 seconds
Started Jan 03 01:02:46 PM PST 24
Finished Jan 03 01:03:53 PM PST 24
Peak memory 200704 kb
Host smart-8cf5ee9e-986a-4644-ab96-558e4589eb31
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909227940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.1909227940
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.860194664
Short name T916
Test name
Test status
Simulation time 51680443 ps
CPU time 0.78 seconds
Started Jan 03 01:02:49 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 200668 kb
Host smart-74340c31-b7f9-4f7c-bece-edd28cd4d277
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860194664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.860194664
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3085838866
Short name T786
Test name
Test status
Simulation time 24497353 ps
CPU time 0.84 seconds
Started Jan 03 01:02:54 PM PST 24
Finished Jan 03 01:03:59 PM PST 24
Peak memory 200696 kb
Host smart-95c67a0a-408c-4767-ae6d-4491d1532e42
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085838866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.3085838866
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.3578819646
Short name T358
Test name
Test status
Simulation time 43974308 ps
CPU time 0.96 seconds
Started Jan 03 01:02:56 PM PST 24
Finished Jan 03 01:04:02 PM PST 24
Peak memory 200732 kb
Host smart-82217e92-525a-460c-8d3a-f048335030c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578819646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.3578819646
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.2881963024
Short name T791
Test name
Test status
Simulation time 1761796836 ps
CPU time 14.1 seconds
Started Jan 03 01:03:07 PM PST 24
Finished Jan 03 01:04:27 PM PST 24
Peak memory 200800 kb
Host smart-0be9767e-a222-4b5f-bf1e-3672e9ad2b99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881963024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.2881963024
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.4256504759
Short name T324
Test name
Test status
Simulation time 855120401 ps
CPU time 6.28 seconds
Started Jan 03 01:02:55 PM PST 24
Finished Jan 03 01:04:05 PM PST 24
Peak memory 200824 kb
Host smart-09d7cbdb-1d96-40e9-b0ab-f64f47ba1a6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256504759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.4256504759
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.3914809077
Short name T925
Test name
Test status
Simulation time 27965244 ps
CPU time 0.86 seconds
Started Jan 03 01:02:45 PM PST 24
Finished Jan 03 01:03:52 PM PST 24
Peak memory 200700 kb
Host smart-aa4795d9-3d98-465f-b620-f3b57f0cf41f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914809077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.3914809077
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2177051913
Short name T914
Test name
Test status
Simulation time 124295872 ps
CPU time 1.13 seconds
Started Jan 03 01:02:45 PM PST 24
Finished Jan 03 01:03:52 PM PST 24
Peak memory 200724 kb
Host smart-e3ae772f-22aa-4bf8-be04-8c5c62cc2b4b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177051913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.2177051913
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.634819196
Short name T305
Test name
Test status
Simulation time 21762748 ps
CPU time 0.75 seconds
Started Jan 03 01:02:47 PM PST 24
Finished Jan 03 01:03:54 PM PST 24
Peak memory 200700 kb
Host smart-ea42dd20-a2f5-49e2-81bf-c502c4d98ff3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634819196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.clkmgr_lc_ctrl_intersig_mubi.634819196
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.4098509864
Short name T142
Test name
Test status
Simulation time 44453251 ps
CPU time 0.75 seconds
Started Jan 03 01:02:47 PM PST 24
Finished Jan 03 01:03:54 PM PST 24
Peak memory 200692 kb
Host smart-de7f925a-b7d7-4477-aae7-f1fd6865e923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098509864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.4098509864
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.4188222372
Short name T804
Test name
Test status
Simulation time 649133200 ps
CPU time 2.47 seconds
Started Jan 03 01:02:55 PM PST 24
Finished Jan 03 01:04:02 PM PST 24
Peak memory 200676 kb
Host smart-0905e4fd-763f-446f-9d3b-9f04830bd600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188222372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.4188222372
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.2075719722
Short name T350
Test name
Test status
Simulation time 70519890 ps
CPU time 0.94 seconds
Started Jan 03 01:02:48 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 200788 kb
Host smart-f6c16204-39da-4dc3-9c1f-7cf90c3f7a0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075719722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.2075719722
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.2217535216
Short name T572
Test name
Test status
Simulation time 220505875 ps
CPU time 2.93 seconds
Started Jan 03 01:02:55 PM PST 24
Finished Jan 03 01:04:02 PM PST 24
Peak memory 200976 kb
Host smart-454b701a-16ba-431f-98c9-4730fe991b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217535216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.2217535216
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.707704457
Short name T160
Test name
Test status
Simulation time 29905712997 ps
CPU time 532.79 seconds
Started Jan 03 01:02:43 PM PST 24
Finished Jan 03 01:12:42 PM PST 24
Peak memory 209264 kb
Host smart-c2d300e6-bc92-4c9e-8348-c1e0f914e973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=707704457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.707704457
Directory /workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.clkmgr_trans.3045728908
Short name T495
Test name
Test status
Simulation time 48066601 ps
CPU time 0.9 seconds
Started Jan 03 01:02:47 PM PST 24
Finished Jan 03 01:03:54 PM PST 24
Peak memory 200796 kb
Host smart-fee1a4ae-6b3a-4ce2-a528-066614e4a3ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045728908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.3045728908
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.1788009956
Short name T880
Test name
Test status
Simulation time 108262637 ps
CPU time 1.07 seconds
Started Jan 03 01:02:52 PM PST 24
Finished Jan 03 01:03:58 PM PST 24
Peak memory 200692 kb
Host smart-0f92ab4f-7962-41f3-b73b-94532c789d68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788009956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.1788009956
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.2414980837
Short name T762
Test name
Test status
Simulation time 22389481 ps
CPU time 0.76 seconds
Started Jan 03 01:02:51 PM PST 24
Finished Jan 03 01:03:57 PM PST 24
Peak memory 200796 kb
Host smart-be46786f-1847-4e72-907b-f1eba8963280
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414980837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.2414980837
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.4132439205
Short name T517
Test name
Test status
Simulation time 15137095 ps
CPU time 0.7 seconds
Started Jan 03 01:02:48 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 200552 kb
Host smart-23081967-624f-449a-a446-3ae9f4c3668e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132439205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.4132439205
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.1400475329
Short name T353
Test name
Test status
Simulation time 20188577 ps
CPU time 0.82 seconds
Started Jan 03 01:03:01 PM PST 24
Finished Jan 03 01:04:08 PM PST 24
Peak memory 200792 kb
Host smart-21a6ac38-805d-4d6c-8aa5-c6a8e73adf17
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400475329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.1400475329
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.2106081845
Short name T408
Test name
Test status
Simulation time 177822487 ps
CPU time 1.22 seconds
Started Jan 03 01:02:48 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 200644 kb
Host smart-4580225d-c2bd-491c-8893-3b8a869ed86e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106081845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.2106081845
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.3293797244
Short name T15
Test name
Test status
Simulation time 1769096068 ps
CPU time 7.86 seconds
Started Jan 03 01:02:45 PM PST 24
Finished Jan 03 01:03:59 PM PST 24
Peak memory 201032 kb
Host smart-50240f53-f7e6-4f44-972f-0b5ec40d0ab6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293797244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3293797244
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.2946830418
Short name T789
Test name
Test status
Simulation time 1461042276 ps
CPU time 10.47 seconds
Started Jan 03 01:02:55 PM PST 24
Finished Jan 03 01:04:09 PM PST 24
Peak memory 200784 kb
Host smart-50c2efa9-2169-4866-9d7a-b4cb6792303c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946830418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.2946830418
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.1020260916
Short name T726
Test name
Test status
Simulation time 19968896 ps
CPU time 0.82 seconds
Started Jan 03 01:02:48 PM PST 24
Finished Jan 03 01:03:55 PM PST 24
Peak memory 200788 kb
Host smart-04f1954a-0586-4d7c-a58c-c16823b91b11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020260916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.1020260916
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.3608920384
Short name T19
Test name
Test status
Simulation time 20372464 ps
CPU time 0.83 seconds
Started Jan 03 01:02:47 PM PST 24
Finished Jan 03 01:03:54 PM PST 24
Peak memory 200792 kb
Host smart-33c148bb-8ad7-4614-9837-0cbaa90ec214
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608920384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.3608920384
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3981934144
Short name T595
Test name
Test status
Simulation time 17185599 ps
CPU time 0.75 seconds
Started Jan 03 01:02:47 PM PST 24
Finished Jan 03 01:03:54 PM PST 24
Peak memory 200744 kb
Host smart-49eba9a2-574c-4d25-95b5-f95ddd6d462b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981934144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.3981934144
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.1374621551
Short name T871
Test name
Test status
Simulation time 12540655 ps
CPU time 0.71 seconds
Started Jan 03 01:02:56 PM PST 24
Finished Jan 03 01:04:01 PM PST 24
Peak memory 200744 kb
Host smart-c5490412-8fb7-40c0-88f4-cd7ae552e06c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374621551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.1374621551
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.2330923809
Short name T599
Test name
Test status
Simulation time 503993409 ps
CPU time 2.28 seconds
Started Jan 03 01:03:05 PM PST 24
Finished Jan 03 01:04:13 PM PST 24
Peak memory 200724 kb
Host smart-353b0c72-09bd-470c-9ee3-0488770a93f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330923809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.2330923809
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.3123560943
Short name T827
Test name
Test status
Simulation time 126889640 ps
CPU time 1.07 seconds
Started Jan 03 01:02:52 PM PST 24
Finished Jan 03 01:03:57 PM PST 24
Peak memory 200664 kb
Host smart-9b860c27-2efa-4b30-b937-f11f7e7b95e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123560943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3123560943
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.997754823
Short name T348
Test name
Test status
Simulation time 2451812403 ps
CPU time 11.18 seconds
Started Jan 03 01:02:54 PM PST 24
Finished Jan 03 01:04:10 PM PST 24
Peak memory 200972 kb
Host smart-fd162672-d034-4122-8994-676242a9d1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997754823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.997754823
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.3873307544
Short name T493
Test name
Test status
Simulation time 85278415392 ps
CPU time 581.94 seconds
Started Jan 03 01:02:49 PM PST 24
Finished Jan 03 01:13:37 PM PST 24
Peak memory 217572 kb
Host smart-1f359041-85c8-455c-a962-89a0e805815e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3873307544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.3873307544
Directory /workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.clkmgr_trans.440242260
Short name T899
Test name
Test status
Simulation time 28766024 ps
CPU time 0.76 seconds
Started Jan 03 01:03:00 PM PST 24
Finished Jan 03 01:04:07 PM PST 24
Peak memory 200788 kb
Host smart-b3551d38-8c7b-470d-be86-b7ce73d9f4ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440242260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.440242260
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.3301617474
Short name T295
Test name
Test status
Simulation time 30972569 ps
CPU time 0.72 seconds
Started Jan 03 01:03:42 PM PST 24
Finished Jan 03 01:04:43 PM PST 24
Peak memory 200828 kb
Host smart-d13a8c78-4103-411b-998a-a1c90f9d13d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301617474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.3301617474
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.321836376
Short name T314
Test name
Test status
Simulation time 31544169 ps
CPU time 0.92 seconds
Started Jan 03 01:03:34 PM PST 24
Finished Jan 03 01:04:29 PM PST 24
Peak memory 200748 kb
Host smart-57e248e2-f8b3-474a-aeec-da8d2a0152e8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321836376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.321836376
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.33365712
Short name T828
Test name
Test status
Simulation time 46474768 ps
CPU time 0.8 seconds
Started Jan 03 01:03:23 PM PST 24
Finished Jan 03 01:04:23 PM PST 24
Peak memory 199700 kb
Host smart-2720663e-0827-449d-9141-7bbf577b3a85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33365712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.33365712
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.2891973219
Short name T490
Test name
Test status
Simulation time 17208689 ps
CPU time 0.78 seconds
Started Jan 03 01:03:38 PM PST 24
Finished Jan 03 01:04:32 PM PST 24
Peak memory 200716 kb
Host smart-3378c6c0-4653-4c70-944b-70aa1994f069
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891973219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.2891973219
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.1851657954
Short name T515
Test name
Test status
Simulation time 23769220 ps
CPU time 0.85 seconds
Started Jan 03 01:02:58 PM PST 24
Finished Jan 03 01:04:04 PM PST 24
Peak memory 200716 kb
Host smart-c25462e9-3fc3-40bd-b3e5-d2fe67da62d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851657954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.1851657954
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.906388670
Short name T65
Test name
Test status
Simulation time 2240794885 ps
CPU time 16.57 seconds
Started Jan 03 01:02:56 PM PST 24
Finished Jan 03 01:04:16 PM PST 24
Peak memory 200932 kb
Host smart-540d863e-778d-4273-8b02-b3275c996ec8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906388670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.906388670
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.3760129022
Short name T60
Test name
Test status
Simulation time 1711876250 ps
CPU time 6.97 seconds
Started Jan 03 01:03:04 PM PST 24
Finished Jan 03 01:04:17 PM PST 24
Peak memory 200840 kb
Host smart-2507b80c-af70-4805-b4e4-ed63d982ffe3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760129022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.3760129022
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1594142980
Short name T783
Test name
Test status
Simulation time 25707535 ps
CPU time 0.74 seconds
Started Jan 03 01:03:04 PM PST 24
Finished Jan 03 01:04:11 PM PST 24
Peak memory 200744 kb
Host smart-03f2d250-070b-4890-af9c-c2e46e4dd5ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594142980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.1594142980
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.129901817
Short name T921
Test name
Test status
Simulation time 35128950 ps
CPU time 0.79 seconds
Started Jan 03 01:03:06 PM PST 24
Finished Jan 03 01:04:12 PM PST 24
Peak memory 200704 kb
Host smart-91c5a3c8-68ab-43fc-8edb-b4689d033415
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129901817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.clkmgr_lc_clk_byp_req_intersig_mubi.129901817
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1845244159
Short name T841
Test name
Test status
Simulation time 18555084 ps
CPU time 0.84 seconds
Started Jan 03 01:03:12 PM PST 24
Finished Jan 03 01:04:17 PM PST 24
Peak memory 200832 kb
Host smart-f7fdf890-bed5-4ab4-b122-322f3fb648e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845244159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.1845244159
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.3573502842
Short name T393
Test name
Test status
Simulation time 16473103 ps
CPU time 0.76 seconds
Started Jan 03 01:03:24 PM PST 24
Finished Jan 03 01:04:23 PM PST 24
Peak memory 200548 kb
Host smart-497e7161-e44d-4847-a855-bc20a1cebfba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573502842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.3573502842
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.1503421538
Short name T664
Test name
Test status
Simulation time 627798534 ps
CPU time 2.81 seconds
Started Jan 03 01:03:10 PM PST 24
Finished Jan 03 01:04:18 PM PST 24
Peak memory 200932 kb
Host smart-0a4f77e3-fede-407f-8691-a8493ce3f5cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503421538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.1503421538
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.4164510199
Short name T731
Test name
Test status
Simulation time 73114988 ps
CPU time 1 seconds
Started Jan 03 01:02:55 PM PST 24
Finished Jan 03 01:04:00 PM PST 24
Peak memory 200680 kb
Host smart-6d44c42e-74ad-41a8-b478-ae6ad6cb7a93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164510199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.4164510199
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.2060701976
Short name T865
Test name
Test status
Simulation time 1479731130 ps
CPU time 8.41 seconds
Started Jan 03 01:03:39 PM PST 24
Finished Jan 03 01:04:40 PM PST 24
Peak memory 201096 kb
Host smart-d57db72a-74a5-4981-9f96-6f15ada7a123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060701976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.2060701976
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.1198729360
Short name T150
Test name
Test status
Simulation time 99047794815 ps
CPU time 1078.78 seconds
Started Jan 03 01:03:12 PM PST 24
Finished Jan 03 01:22:15 PM PST 24
Peak memory 216900 kb
Host smart-26b7e4f7-21fd-44be-9072-a3937db658a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1198729360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.1198729360
Directory /workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.clkmgr_trans.638511875
Short name T763
Test name
Test status
Simulation time 101187173 ps
CPU time 1.22 seconds
Started Jan 03 01:03:06 PM PST 24
Finished Jan 03 01:04:12 PM PST 24
Peak memory 200792 kb
Host smart-fdb9fbbf-7fb9-4af1-936c-8c7d9e8bff65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638511875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.638511875
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.2128296381
Short name T638
Test name
Test status
Simulation time 45610441 ps
CPU time 0.85 seconds
Started Jan 03 01:02:58 PM PST 24
Finished Jan 03 01:04:04 PM PST 24
Peak memory 200780 kb
Host smart-7d80b42e-e169-4f99-8705-8f06f5bd76a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128296381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.2128296381
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.3854854197
Short name T624
Test name
Test status
Simulation time 27073736 ps
CPU time 0.93 seconds
Started Jan 03 01:03:54 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 200792 kb
Host smart-ea52a822-437c-4e94-b102-88c03bf85a18
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854854197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.3854854197
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.836376775
Short name T839
Test name
Test status
Simulation time 55623458 ps
CPU time 0.8 seconds
Started Jan 03 01:03:57 PM PST 24
Finished Jan 03 01:04:58 PM PST 24
Peak memory 200696 kb
Host smart-bd1d2163-ee74-429f-8437-a5efafa3dca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836376775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.836376775
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.2543539219
Short name T994
Test name
Test status
Simulation time 106123808 ps
CPU time 0.99 seconds
Started Jan 03 01:03:58 PM PST 24
Finished Jan 03 01:04:59 PM PST 24
Peak memory 200812 kb
Host smart-ab865d02-6e12-49e8-8076-09f24e09c453
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543539219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.2543539219
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.1899506495
Short name T949
Test name
Test status
Simulation time 47780645 ps
CPU time 0.81 seconds
Started Jan 03 01:03:56 PM PST 24
Finished Jan 03 01:04:57 PM PST 24
Peak memory 200616 kb
Host smart-c188f011-48c2-4942-8e28-9dc2aa034490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899506495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1899506495
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.2704222031
Short name T410
Test name
Test status
Simulation time 919499190 ps
CPU time 7.36 seconds
Started Jan 03 01:03:48 PM PST 24
Finished Jan 03 01:04:51 PM PST 24
Peak memory 199532 kb
Host smart-b063ae49-5acd-44ac-87f6-c5683a533fef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704222031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2704222031
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.4278146209
Short name T487
Test name
Test status
Simulation time 2190710114 ps
CPU time 11.32 seconds
Started Jan 03 01:03:38 PM PST 24
Finished Jan 03 01:04:43 PM PST 24
Peak memory 201032 kb
Host smart-f060f11e-cbe4-44a6-983e-cb041fc6101c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278146209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.4278146209
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.2997458240
Short name T574
Test name
Test status
Simulation time 24274030 ps
CPU time 0.87 seconds
Started Jan 03 01:03:57 PM PST 24
Finished Jan 03 01:04:58 PM PST 24
Peak memory 200752 kb
Host smart-62408c55-4aee-423d-b7da-c6c499f32d74
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997458240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.2997458240
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2526973090
Short name T657
Test name
Test status
Simulation time 34123291 ps
CPU time 0.76 seconds
Started Jan 03 01:04:03 PM PST 24
Finished Jan 03 01:05:07 PM PST 24
Peak memory 200816 kb
Host smart-2476c012-ac60-4135-b92e-d2fa8fa81992
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526973090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.2526973090
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.3156504192
Short name T653
Test name
Test status
Simulation time 21757784 ps
CPU time 0.8 seconds
Started Jan 03 01:04:06 PM PST 24
Finished Jan 03 01:05:13 PM PST 24
Peak memory 200692 kb
Host smart-e51fcbbd-efbf-4d70-a428-0a382aecdb85
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156504192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.3156504192
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.3158308747
Short name T419
Test name
Test status
Simulation time 31161508 ps
CPU time 0.79 seconds
Started Jan 03 01:03:42 PM PST 24
Finished Jan 03 01:04:36 PM PST 24
Peak memory 200712 kb
Host smart-134ea5c1-4e1b-463a-8f10-19ed106462e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158308747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.3158308747
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.3670633488
Short name T971
Test name
Test status
Simulation time 138142300 ps
CPU time 1.2 seconds
Started Jan 03 01:02:54 PM PST 24
Finished Jan 03 01:04:00 PM PST 24
Peak memory 200700 kb
Host smart-228a56a7-1fe3-41cb-8812-3dc0f8dc9090
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670633488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.3670633488
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.436393771
Short name T530
Test name
Test status
Simulation time 37615735 ps
CPU time 0.85 seconds
Started Jan 03 01:03:33 PM PST 24
Finished Jan 03 01:04:28 PM PST 24
Peak memory 200804 kb
Host smart-0dd95b08-4f36-4618-b65a-fed0e980bf33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436393771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.436393771
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.738129257
Short name T733
Test name
Test status
Simulation time 1474284593 ps
CPU time 12 seconds
Started Jan 03 01:03:00 PM PST 24
Finished Jan 03 01:04:18 PM PST 24
Peak memory 201012 kb
Host smart-50d514e6-586a-4b9a-bed9-a7780680263a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738129257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.738129257
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.1404919816
Short name T799
Test name
Test status
Simulation time 36626740162 ps
CPU time 560.98 seconds
Started Jan 03 01:03:57 PM PST 24
Finished Jan 03 01:14:18 PM PST 24
Peak memory 209952 kb
Host smart-75fdfcc5-afdd-467b-bbf6-ea4bba60f534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1404919816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.1404919816
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.825699369
Short name T330
Test name
Test status
Simulation time 136099143 ps
CPU time 1.22 seconds
Started Jan 03 01:03:50 PM PST 24
Finished Jan 03 01:04:47 PM PST 24
Peak memory 200712 kb
Host smart-2bd02351-510c-401c-820b-e47800045c67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825699369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.825699369
Directory /workspace/9.clkmgr_trans/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%