Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262017348

1

T4

2862

T5

2548

T6

4204

auto[1]

355800

1

T4

388

T21

136

T2

13518

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262053242

1

T4

3006

T5

2548

T6

3930

auto[1]

319906

1

T4

244

T6

274

T21

150

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

261937210

1

T4

2862

T5

2548

T6

3732

auto[1]

435938

1

T4

388

T6

472

T15

262

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239677300

1

T4

996

T5

2548

T6

606

auto[1]

22695848

1

T4

2254

T6

3598

T21

1510

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161429628

1

T4

2756

T5

544

T6

3792

auto[1]

100943520

1

T4

494

T5

2004

T6

412

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

140710284

1

T4

428

T5

544

T6

358

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

98689174

1

T4

350

T5

2004

T6

84

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

26304

1

T4

82

T2

1200

T3

32

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6850

1

T2

302

T27

30

T161

36

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

20213438

1

T4

1924

T6

3048

T21

70

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2154022

1

T4

78

T6

172

T21

1276

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49366

1

T21

14

T2

2212

T3

78

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11634

1

T2

544

T8

90

T101

76

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

27762

1

T2

128

T16

134

T3

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1662

1

T16

44

T85

18

T13

22

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

9890

1

T2

348

T3

66

T161

60

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2178

1

T85

44

T13

140

T23

254

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

9416

1

T6

20

T21

12

T2

414

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2386

1

T6

50

T21

16

T8

20

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

18054

1

T21

64

T2

960

T8

150

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4790

1

T21

58

T8

62

T101

52

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

59514

1

T6

52

T15

92

T2

556

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3966

1

T6

50

T2

288

T101

20

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

29314

1

T2

848

T27

136

T163

58

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6074

1

T2

330

T161

48

T163

52

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

29304

1

T4

20

T6

166

T15

26

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6142

1

T4

12

T2

226

T3

26

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

46890

1

T4

58

T2

1636

T3

158

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10966

1

T4

54

T2

358

T8

100

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

51144

1

T4

38

T6

62

T15

40

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5326

1

T2

116

T27

32

T83

30

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

39044

1

T4

98

T2

1138

T3

78

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8814

1

T2

268

T27

188

T163

108

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

42900

1

T4

12

T6

86

T15

104

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10908

1

T6

56

T2

594

T8

36

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

67004

1

T4

96

T2

2272

T3

298

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

18628

1

T2

1102

T8

142

T101

206