Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 314986452 1 T5 2230 T1 151284 T6 2826
auto[1] 394256 1 T21 178 T2 4480 T16 144


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 315001468 1 T5 2230 T1 151284 T6 2826
auto[1] 379240 1 T4 1210 T21 198 T2 2704


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 314904390 1 T5 2230 T1 151284 T6 2826
auto[1] 476318 1 T21 198 T2 4194 T16 16


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 293593590 1 T5 2230 T1 151284 T6 2826
auto[1] 21787118 1 T21 306 T2 16100 T3 28176


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 175417826 1 T5 2230 T1 151268 T6 502
auto[1] 139962882 1 T1 16 T6 2324 T33 26


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 155998582 1 T5 2230 T1 151268 T6 502
auto[0] auto[0] auto[0] auto[0] auto[1] 137262954 1 T1 16 T6 2324 T33 26
auto[0] auto[0] auto[0] auto[1] auto[0] 30520 1 T21 16 T2 362 T16 68
auto[0] auto[0] auto[0] auto[1] auto[1] 7292 1 T2 28 T16 76 T3 136
auto[0] auto[0] auto[1] auto[0] auto[0] 18852030 1 T21 140 T2 9810 T3 12046
auto[0] auto[0] auto[1] auto[0] auto[1] 2588334 1 T2 2548 T3 3236 T26 74
auto[0] auto[0] auto[1] auto[1] auto[0] 49432 1 T21 38 T2 544 T3 2120
auto[0] auto[0] auto[1] auto[1] auto[1] 12170 1 T2 38 T3 382 T102 6
auto[0] auto[1] auto[0] auto[0] auto[0] 51856 1 T4 1210 T2 12 T3 190
auto[0] auto[1] auto[0] auto[0] auto[1] 1860 1 T3 96 T100 8 T142 30
auto[0] auto[1] auto[0] auto[1] auto[0] 11888 1 T2 54 T3 432 T19 114
auto[0] auto[1] auto[0] auto[1] auto[1] 3122 1 T3 142 T142 132 T14 48
auto[0] auto[1] auto[1] auto[0] auto[0] 9308 1 T2 10 T3 662 T101 16
auto[0] auto[1] auto[1] auto[0] auto[1] 2340 1 T2 8 T3 16 T102 2
auto[0] auto[1] auto[1] auto[1] auto[0] 17526 1 T2 52 T3 360 T110 80
auto[0] auto[1] auto[1] auto[1] auto[1] 5176 1 T3 102 T102 62 T103 64
auto[1] auto[0] auto[0] auto[0] auto[0] 57062 1 T2 110 T16 8 T3 622
auto[1] auto[0] auto[0] auto[0] auto[1] 3924 1 T2 58 T104 40 T100 4
auto[1] auto[0] auto[0] auto[1] auto[0] 33492 1 T2 290 T3 716 T19 62
auto[1] auto[0] auto[0] auto[1] auto[1] 6666 1 T2 130 T100 36 T32 52
auto[1] auto[0] auto[1] auto[0] auto[0] 26156 1 T2 150 T3 1228 T19 14
auto[1] auto[0] auto[1] auto[0] auto[1] 7180 1 T2 52 T3 318 T10 234
auto[1] auto[0] auto[1] auto[1] auto[0] 51706 1 T2 670 T3 2684 T26 142
auto[1] auto[0] auto[1] auto[1] auto[1] 13968 1 T2 166 T3 850 T10 284
auto[1] auto[1] auto[0] auto[0] auto[0] 65144 1 T21 2 T2 80 T3 596
auto[1] auto[1] auto[0] auto[0] auto[1] 6270 1 T2 4 T16 8 T3 316
auto[1] auto[1] auto[0] auto[1] auto[0] 41920 1 T21 68 T2 340 T3 818
auto[1] auto[1] auto[0] auto[1] auto[1] 11038 1 T2 92 T3 354 T104 64
auto[1] auto[1] auto[1] auto[0] auto[0] 42388 1 T21 72 T2 260 T3 1352
auto[1] auto[1] auto[1] auto[0] auto[1] 11064 1 T2 78 T3 98 T26 70
auto[1] auto[1] auto[1] auto[1] auto[0] 78816 1 T21 56 T2 1402 T3 2536
auto[1] auto[1] auto[1] auto[1] auto[1] 19524 1 T2 312 T3 186 T10 144

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