Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.54 99.15 95.84 100.00 100.00 98.81 97.01 98.97


Total test records in report: 998
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T754 /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.299606728 Jan 10 12:41:16 PM PST 24 Jan 10 12:42:21 PM PST 24 43975381 ps
T755 /workspace/coverage/default/23.clkmgr_smoke.4253297044 Jan 10 12:40:46 PM PST 24 Jan 10 12:41:34 PM PST 24 52252806 ps
T756 /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.76312289 Jan 10 12:41:34 PM PST 24 Jan 10 12:42:40 PM PST 24 15920777 ps
T757 /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.550992378 Jan 10 12:40:56 PM PST 24 Jan 10 12:41:51 PM PST 24 32079934 ps
T758 /workspace/coverage/default/1.clkmgr_peri.3558079133 Jan 10 12:39:42 PM PST 24 Jan 10 12:40:13 PM PST 24 46922821 ps
T759 /workspace/coverage/default/45.clkmgr_regwen.1739477336 Jan 10 12:41:52 PM PST 24 Jan 10 12:43:04 PM PST 24 804446208 ps
T760 /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2534798170 Jan 10 12:41:08 PM PST 24 Jan 10 12:42:09 PM PST 24 71881703 ps
T761 /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.4184988218 Jan 10 12:40:18 PM PST 24 Jan 10 12:52:03 PM PST 24 92843255187 ps
T762 /workspace/coverage/default/34.clkmgr_frequency.761098268 Jan 10 12:41:26 PM PST 24 Jan 10 12:42:42 PM PST 24 2160414999 ps
T763 /workspace/coverage/default/42.clkmgr_peri.3715963529 Jan 10 12:41:37 PM PST 24 Jan 10 12:42:44 PM PST 24 14665041 ps
T764 /workspace/coverage/default/15.clkmgr_frequency_timeout.4115898941 Jan 10 12:40:46 PM PST 24 Jan 10 12:41:49 PM PST 24 2417303542 ps
T765 /workspace/coverage/default/36.clkmgr_stress_all.865971753 Jan 10 12:41:34 PM PST 24 Jan 10 12:42:48 PM PST 24 1696954067 ps
T766 /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.4065639831 Jan 10 12:41:10 PM PST 24 Jan 10 12:54:52 PM PST 24 86598197584 ps
T767 /workspace/coverage/default/37.clkmgr_smoke.2838801572 Jan 10 12:41:29 PM PST 24 Jan 10 12:42:36 PM PST 24 16910113 ps
T768 /workspace/coverage/default/49.clkmgr_alert_test.1069363326 Jan 10 12:41:55 PM PST 24 Jan 10 12:43:07 PM PST 24 48086053 ps
T769 /workspace/coverage/default/32.clkmgr_frequency.2817481636 Jan 10 12:41:16 PM PST 24 Jan 10 12:42:27 PM PST 24 1014253026 ps
T770 /workspace/coverage/default/8.clkmgr_smoke.2625403872 Jan 10 12:39:56 PM PST 24 Jan 10 12:40:35 PM PST 24 15527747 ps
T771 /workspace/coverage/default/23.clkmgr_peri.2945017617 Jan 10 12:41:05 PM PST 24 Jan 10 12:42:03 PM PST 24 38963513 ps
T772 /workspace/coverage/default/29.clkmgr_frequency.3028293967 Jan 10 12:41:08 PM PST 24 Jan 10 12:42:10 PM PST 24 345751019 ps
T773 /workspace/coverage/default/14.clkmgr_peri.1795064668 Jan 10 12:40:44 PM PST 24 Jan 10 12:41:30 PM PST 24 14725624 ps
T774 /workspace/coverage/default/19.clkmgr_stress_all.3877912221 Jan 10 12:40:52 PM PST 24 Jan 10 12:42:31 PM PST 24 6833390083 ps
T775 /workspace/coverage/default/14.clkmgr_alert_test.4091921538 Jan 10 12:40:49 PM PST 24 Jan 10 12:41:37 PM PST 24 22419273 ps
T54 /workspace/coverage/default/2.clkmgr_sec_cm.104948052 Jan 10 12:39:43 PM PST 24 Jan 10 12:40:16 PM PST 24 156289761 ps
T776 /workspace/coverage/default/36.clkmgr_peri.3409787040 Jan 10 12:41:16 PM PST 24 Jan 10 12:42:24 PM PST 24 21705454 ps
T777 /workspace/coverage/default/23.clkmgr_clk_status.2268911624 Jan 10 12:40:56 PM PST 24 Jan 10 12:41:51 PM PST 24 28267584 ps
T778 /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.700748523 Jan 10 12:49:06 PM PST 24 Jan 10 12:50:38 PM PST 24 83494168 ps
T779 /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.967157732 Jan 10 12:40:05 PM PST 24 Jan 10 12:40:51 PM PST 24 46100789 ps
T780 /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.1317846389 Jan 10 12:39:56 PM PST 24 Jan 10 12:40:37 PM PST 24 28762201 ps
T781 /workspace/coverage/default/44.clkmgr_regwen.3673916871 Jan 10 12:41:50 PM PST 24 Jan 10 12:43:05 PM PST 24 1111958877 ps
T782 /workspace/coverage/default/31.clkmgr_peri.758406332 Jan 10 12:41:16 PM PST 24 Jan 10 12:42:20 PM PST 24 14218676 ps
T783 /workspace/coverage/default/35.clkmgr_clk_status.1203297983 Jan 10 12:41:19 PM PST 24 Jan 10 12:42:25 PM PST 24 15489887 ps
T784 /workspace/coverage/default/28.clkmgr_stress_all.1580037433 Jan 10 12:41:05 PM PST 24 Jan 10 12:42:46 PM PST 24 6451480435 ps
T785 /workspace/coverage/default/11.clkmgr_smoke.3729046604 Jan 10 12:40:20 PM PST 24 Jan 10 12:41:08 PM PST 24 18748043 ps
T786 /workspace/coverage/default/27.clkmgr_clk_status.1035200974 Jan 10 12:41:10 PM PST 24 Jan 10 12:42:11 PM PST 24 18188698 ps
T787 /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.1632749222 Jan 10 12:40:42 PM PST 24 Jan 10 12:48:53 PM PST 24 75725693875 ps
T788 /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.2001885911 Jan 10 12:40:27 PM PST 24 Jan 10 12:41:14 PM PST 24 99624638 ps
T789 /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.2742289257 Jan 10 12:39:29 PM PST 24 Jan 10 12:40:00 PM PST 24 42398216 ps
T790 /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.449819584 Jan 10 12:41:01 PM PST 24 Jan 10 12:46:18 PM PST 24 34931477649 ps
T791 /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.2185026247 Jan 10 12:41:29 PM PST 24 Jan 10 12:42:36 PM PST 24 41192314 ps
T792 /workspace/coverage/default/13.clkmgr_frequency_timeout.3229544130 Jan 10 12:40:25 PM PST 24 Jan 10 12:41:19 PM PST 24 980407943 ps
T793 /workspace/coverage/default/31.clkmgr_regwen.916527161 Jan 10 12:41:17 PM PST 24 Jan 10 12:42:28 PM PST 24 1167335429 ps
T794 /workspace/coverage/default/35.clkmgr_stress_all.3355245265 Jan 10 12:41:18 PM PST 24 Jan 10 12:43:00 PM PST 24 9298797671 ps
T795 /workspace/coverage/default/8.clkmgr_frequency_timeout.1619619735 Jan 10 12:39:58 PM PST 24 Jan 10 12:40:43 PM PST 24 979299046 ps
T796 /workspace/coverage/default/46.clkmgr_div_intersig_mubi.734540062 Jan 10 12:41:45 PM PST 24 Jan 10 12:42:54 PM PST 24 155171441 ps
T797 /workspace/coverage/default/35.clkmgr_frequency.3685799097 Jan 10 12:41:30 PM PST 24 Jan 10 12:42:41 PM PST 24 1552350971 ps
T798 /workspace/coverage/default/34.clkmgr_trans.1372406226 Jan 10 12:41:30 PM PST 24 Jan 10 12:42:37 PM PST 24 24195735 ps
T799 /workspace/coverage/default/10.clkmgr_frequency_timeout.847259529 Jan 10 12:40:06 PM PST 24 Jan 10 12:40:54 PM PST 24 752315746 ps
T800 /workspace/coverage/default/20.clkmgr_smoke.4141484857 Jan 10 12:40:50 PM PST 24 Jan 10 12:41:40 PM PST 24 69094585 ps
T801 /workspace/coverage/default/27.clkmgr_trans.850533152 Jan 10 12:41:07 PM PST 24 Jan 10 12:42:08 PM PST 24 158608734 ps
T802 /workspace/coverage/default/36.clkmgr_alert_test.1353373954 Jan 10 12:41:29 PM PST 24 Jan 10 12:42:36 PM PST 24 25697647 ps
T803 /workspace/coverage/default/13.clkmgr_regwen.3670573277 Jan 10 12:40:28 PM PST 24 Jan 10 12:41:17 PM PST 24 962142868 ps
T804 /workspace/coverage/default/11.clkmgr_peri.3976323306 Jan 10 12:40:22 PM PST 24 Jan 10 12:41:09 PM PST 24 44238425 ps
T805 /workspace/coverage/default/18.clkmgr_div_intersig_mubi.1826788592 Jan 10 12:40:45 PM PST 24 Jan 10 12:41:32 PM PST 24 114296788 ps
T806 /workspace/coverage/default/9.clkmgr_alert_test.1977353202 Jan 10 12:40:03 PM PST 24 Jan 10 12:40:48 PM PST 24 54728205 ps
T807 /workspace/coverage/default/19.clkmgr_frequency_timeout.2219554232 Jan 10 12:40:49 PM PST 24 Jan 10 12:41:48 PM PST 24 1460402834 ps
T808 /workspace/coverage/default/34.clkmgr_clk_status.3826156641 Jan 10 12:41:25 PM PST 24 Jan 10 12:42:32 PM PST 24 15316504 ps
T809 /workspace/coverage/default/44.clkmgr_smoke.691784826 Jan 10 12:41:44 PM PST 24 Jan 10 12:42:52 PM PST 24 17829376 ps
T810 /workspace/coverage/default/18.clkmgr_frequency.1348661661 Jan 10 12:40:45 PM PST 24 Jan 10 12:41:39 PM PST 24 1844643275 ps
T811 /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2522381221 Jan 10 12:41:52 PM PST 24 Jan 10 12:43:02 PM PST 24 39867839 ps
T812 /workspace/coverage/default/38.clkmgr_stress_all.1656786040 Jan 10 12:41:35 PM PST 24 Jan 10 12:42:50 PM PST 24 2170732683 ps
T813 /workspace/coverage/default/11.clkmgr_div_intersig_mubi.3667678760 Jan 10 12:40:15 PM PST 24 Jan 10 12:41:03 PM PST 24 29186324 ps
T814 /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.1035486275 Jan 10 12:40:43 PM PST 24 Jan 10 12:41:29 PM PST 24 37913181 ps
T815 /workspace/coverage/default/26.clkmgr_frequency.568633069 Jan 10 12:40:57 PM PST 24 Jan 10 12:42:00 PM PST 24 1158879490 ps
T816 /workspace/coverage/default/4.clkmgr_clk_status.3879214259 Jan 10 12:40:01 PM PST 24 Jan 10 12:40:43 PM PST 24 36508279 ps
T817 /workspace/coverage/default/0.clkmgr_trans.4148149898 Jan 10 12:39:25 PM PST 24 Jan 10 12:39:56 PM PST 24 25211604 ps
T818 /workspace/coverage/default/49.clkmgr_regwen.2908360015 Jan 10 12:41:53 PM PST 24 Jan 10 12:43:07 PM PST 24 1218572613 ps
T819 /workspace/coverage/default/28.clkmgr_regwen.3588058866 Jan 10 12:41:03 PM PST 24 Jan 10 12:42:04 PM PST 24 631540419 ps
T55 /workspace/coverage/default/1.clkmgr_sec_cm.2417807497 Jan 10 12:39:40 PM PST 24 Jan 10 12:40:13 PM PST 24 321311007 ps
T820 /workspace/coverage/default/8.clkmgr_frequency.2770003146 Jan 10 12:39:58 PM PST 24 Jan 10 12:40:55 PM PST 24 2473790716 ps
T821 /workspace/coverage/default/17.clkmgr_extclk.4257088118 Jan 10 12:40:34 PM PST 24 Jan 10 12:41:19 PM PST 24 30928854 ps
T822 /workspace/coverage/default/40.clkmgr_stress_all.2285123090 Jan 10 12:41:48 PM PST 24 Jan 10 12:43:02 PM PST 24 852613532 ps
T823 /workspace/coverage/default/21.clkmgr_trans.2958989455 Jan 10 12:40:49 PM PST 24 Jan 10 12:41:38 PM PST 24 90904314 ps
T824 /workspace/coverage/default/33.clkmgr_stress_all.1906605833 Jan 10 12:41:21 PM PST 24 Jan 10 12:42:57 PM PST 24 4169220114 ps
T825 /workspace/coverage/default/7.clkmgr_stress_all.549785527 Jan 10 12:39:54 PM PST 24 Jan 10 12:40:55 PM PST 24 3161691460 ps
T826 /workspace/coverage/default/43.clkmgr_div_intersig_mubi.2877519603 Jan 10 12:41:47 PM PST 24 Jan 10 12:42:56 PM PST 24 26323904 ps
T827 /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.2926014946 Jan 10 12:40:04 PM PST 24 Jan 10 12:53:32 PM PST 24 102345773158 ps
T828 /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.1259590848 Jan 10 12:57:02 PM PST 24 Jan 10 12:58:16 PM PST 24 91270126 ps
T829 /workspace/coverage/default/12.clkmgr_alert_test.1977334219 Jan 10 12:40:21 PM PST 24 Jan 10 12:41:08 PM PST 24 46984463 ps
T830 /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.326949705 Jan 10 12:40:27 PM PST 24 Jan 10 12:41:14 PM PST 24 100960854 ps
T831 /workspace/coverage/default/13.clkmgr_clk_status.3731583967 Jan 10 12:40:23 PM PST 24 Jan 10 12:41:11 PM PST 24 16763417 ps
T832 /workspace/coverage/default/3.clkmgr_div_intersig_mubi.22618596 Jan 10 12:39:42 PM PST 24 Jan 10 12:40:12 PM PST 24 106492713 ps
T833 /workspace/coverage/default/15.clkmgr_div_intersig_mubi.3589876922 Jan 10 12:40:46 PM PST 24 Jan 10 12:41:33 PM PST 24 23812182 ps
T834 /workspace/coverage/default/33.clkmgr_div_intersig_mubi.3477358009 Jan 10 12:41:23 PM PST 24 Jan 10 12:42:30 PM PST 24 84204650 ps
T835 /workspace/coverage/default/13.clkmgr_frequency.1399745023 Jan 10 12:40:26 PM PST 24 Jan 10 12:41:16 PM PST 24 936037194 ps
T836 /workspace/coverage/default/11.clkmgr_extclk.2548043016 Jan 10 12:40:20 PM PST 24 Jan 10 12:41:08 PM PST 24 12874360 ps
T64 /workspace/coverage/default/3.clkmgr_sec_cm.3319578365 Jan 10 12:39:39 PM PST 24 Jan 10 12:40:11 PM PST 24 472316670 ps
T837 /workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.609327520 Jan 10 12:41:50 PM PST 24 Jan 10 12:48:49 PM PST 24 24573182557 ps
T838 /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.4041697630 Jan 10 12:40:53 PM PST 24 Jan 10 12:41:45 PM PST 24 70194565 ps
T839 /workspace/coverage/default/43.clkmgr_clk_status.3417729979 Jan 10 12:41:43 PM PST 24 Jan 10 12:42:50 PM PST 24 29904110 ps
T840 /workspace/coverage/default/1.clkmgr_frequency.1829349935 Jan 10 12:39:28 PM PST 24 Jan 10 12:40:05 PM PST 24 1562748503 ps
T841 /workspace/coverage/default/15.clkmgr_smoke.499399402 Jan 10 12:40:24 PM PST 24 Jan 10 12:41:11 PM PST 24 21479560 ps
T842 /workspace/coverage/default/44.clkmgr_peri.3853088089 Jan 10 12:41:52 PM PST 24 Jan 10 12:43:02 PM PST 24 24050236 ps
T843 /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.1056594311 Jan 10 12:41:48 PM PST 24 Jan 10 12:42:58 PM PST 24 73126616 ps
T844 /workspace/coverage/default/26.clkmgr_peri.1810434187 Jan 10 12:40:50 PM PST 24 Jan 10 12:41:41 PM PST 24 38443226 ps
T845 /workspace/coverage/default/42.clkmgr_frequency.3473120493 Jan 10 12:41:44 PM PST 24 Jan 10 12:42:59 PM PST 24 1040405320 ps
T846 /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.3115339689 Jan 10 12:40:44 PM PST 24 Jan 10 12:41:30 PM PST 24 75611835 ps
T847 /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.2471727287 Jan 10 12:41:45 PM PST 24 Jan 10 12:42:53 PM PST 24 57826496 ps
T848 /workspace/coverage/default/19.clkmgr_peri.2575115407 Jan 10 12:40:31 PM PST 24 Jan 10 12:41:16 PM PST 24 15368239 ps
T849 /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.2171349588 Jan 10 12:41:31 PM PST 24 Jan 10 12:50:48 PM PST 24 83757951662 ps
T850 /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.2801783295 Jan 10 12:41:17 PM PST 24 Jan 10 12:42:22 PM PST 24 34657757 ps
T851 /workspace/coverage/default/19.clkmgr_clk_status.947674814 Jan 10 12:40:51 PM PST 24 Jan 10 12:41:41 PM PST 24 20499052 ps
T852 /workspace/coverage/default/38.clkmgr_regwen.2340640429 Jan 10 12:41:38 PM PST 24 Jan 10 12:42:49 PM PST 24 893631087 ps
T853 /workspace/coverage/default/7.clkmgr_div_intersig_mubi.760979652 Jan 10 12:39:54 PM PST 24 Jan 10 12:40:32 PM PST 24 14466696 ps
T854 /workspace/coverage/default/17.clkmgr_alert_test.637188250 Jan 10 12:40:32 PM PST 24 Jan 10 12:41:17 PM PST 24 15229296 ps
T855 /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.4004394417 Jan 10 12:41:16 PM PST 24 Jan 10 12:51:51 PM PST 24 32281548377 ps
T856 /workspace/coverage/default/47.clkmgr_clk_status.71637448 Jan 10 12:41:51 PM PST 24 Jan 10 12:43:02 PM PST 24 12864122 ps
T857 /workspace/coverage/default/10.clkmgr_div_intersig_mubi.1598717543 Jan 10 12:40:15 PM PST 24 Jan 10 12:41:03 PM PST 24 14889491 ps
T858 /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.2340792609 Jan 10 12:41:16 PM PST 24 Jan 10 12:48:38 PM PST 24 21263726521 ps
T859 /workspace/coverage/default/7.clkmgr_peri.2512280729 Jan 10 12:39:54 PM PST 24 Jan 10 12:40:32 PM PST 24 64389956 ps
T860 /workspace/coverage/default/16.clkmgr_extclk.904949532 Jan 10 12:40:38 PM PST 24 Jan 10 12:41:23 PM PST 24 14263189 ps
T861 /workspace/coverage/default/42.clkmgr_smoke.3516184412 Jan 10 12:41:47 PM PST 24 Jan 10 12:42:56 PM PST 24 31717018 ps
T862 /workspace/coverage/default/39.clkmgr_stress_all.180779381 Jan 10 12:41:30 PM PST 24 Jan 10 12:42:50 PM PST 24 1862810758 ps
T863 /workspace/coverage/default/8.clkmgr_alert_test.2818939349 Jan 10 12:39:55 PM PST 24 Jan 10 12:40:33 PM PST 24 55106593 ps
T864 /workspace/coverage/default/40.clkmgr_extclk.1677255698 Jan 10 12:41:43 PM PST 24 Jan 10 12:42:50 PM PST 24 33550371 ps
T865 /workspace/coverage/default/30.clkmgr_alert_test.2481801387 Jan 10 12:41:19 PM PST 24 Jan 10 12:42:26 PM PST 24 48629916 ps
T866 /workspace/coverage/default/13.clkmgr_trans.4013340708 Jan 10 12:40:25 PM PST 24 Jan 10 12:41:12 PM PST 24 100397222 ps
T867 /workspace/coverage/default/28.clkmgr_frequency_timeout.2934724632 Jan 10 12:41:04 PM PST 24 Jan 10 12:42:08 PM PST 24 1517118912 ps
T868 /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.680616106 Jan 10 12:41:48 PM PST 24 Jan 10 12:42:58 PM PST 24 31100187 ps
T869 /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2993136472 Jan 10 12:41:34 PM PST 24 Jan 10 12:42:41 PM PST 24 94937762 ps
T870 /workspace/coverage/default/36.clkmgr_smoke.625479077 Jan 10 12:41:17 PM PST 24 Jan 10 12:42:23 PM PST 24 33187794 ps
T871 /workspace/coverage/default/25.clkmgr_extclk.3822800054 Jan 10 12:40:52 PM PST 24 Jan 10 12:41:44 PM PST 24 18913753 ps
T872 /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.4180671548 Jan 10 12:39:50 PM PST 24 Jan 10 12:40:24 PM PST 24 22556379 ps
T873 /workspace/coverage/default/22.clkmgr_frequency_timeout.1148768449 Jan 10 12:40:44 PM PST 24 Jan 10 12:41:40 PM PST 24 1458374873 ps
T874 /workspace/coverage/default/27.clkmgr_smoke.3662938354 Jan 10 12:41:06 PM PST 24 Jan 10 12:42:06 PM PST 24 18951510 ps
T875 /workspace/coverage/default/43.clkmgr_alert_test.2321600056 Jan 10 12:41:46 PM PST 24 Jan 10 12:42:56 PM PST 24 38415082 ps
T876 /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.650938581 Jan 10 12:41:35 PM PST 24 Jan 10 12:42:42 PM PST 24 67138457 ps
T877 /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1642228895 Jan 10 12:40:54 PM PST 24 Jan 10 12:41:47 PM PST 24 134307909 ps
T878 /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.2853153635 Jan 10 12:40:26 PM PST 24 Jan 10 12:41:13 PM PST 24 17981847 ps
T879 /workspace/coverage/default/43.clkmgr_frequency_timeout.1550940050 Jan 10 12:41:47 PM PST 24 Jan 10 12:43:06 PM PST 24 1337446486 ps
T880 /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.2902368354 Jan 10 12:40:32 PM PST 24 Jan 10 12:45:43 PM PST 24 29893476819 ps
T881 /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1981291452 Jan 10 12:40:26 PM PST 24 Jan 10 12:41:12 PM PST 24 20223715 ps
T882 /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.208139693 Jan 10 12:41:37 PM PST 24 Jan 10 12:42:43 PM PST 24 38694224 ps
T883 /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.855828183 Jan 10 12:39:26 PM PST 24 Jan 10 12:39:56 PM PST 24 15103887 ps
T884 /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.553240683 Jan 10 12:40:53 PM PST 24 Jan 10 12:41:45 PM PST 24 52802776 ps
T885 /workspace/coverage/default/43.clkmgr_peri.3653618948 Jan 10 12:41:42 PM PST 24 Jan 10 12:42:49 PM PST 24 16288591 ps
T886 /workspace/coverage/default/34.clkmgr_regwen.1660307971 Jan 10 12:41:23 PM PST 24 Jan 10 12:42:34 PM PST 24 830313032 ps
T887 /workspace/coverage/default/45.clkmgr_smoke.1227133092 Jan 10 12:41:44 PM PST 24 Jan 10 12:42:52 PM PST 24 51491881 ps
T888 /workspace/coverage/default/0.clkmgr_frequency_timeout.3742847135 Jan 10 12:39:33 PM PST 24 Jan 10 12:40:03 PM PST 24 278262545 ps
T889 /workspace/coverage/default/31.clkmgr_trans.802558854 Jan 10 12:41:19 PM PST 24 Jan 10 12:42:27 PM PST 24 81984098 ps
T890 /workspace/coverage/default/45.clkmgr_frequency_timeout.1002512164 Jan 10 12:41:49 PM PST 24 Jan 10 12:43:02 PM PST 24 289481677 ps
T891 /workspace/coverage/default/11.clkmgr_stress_all.2209825439 Jan 10 12:40:15 PM PST 24 Jan 10 12:41:06 PM PST 24 391460119 ps
T892 /workspace/coverage/default/5.clkmgr_trans.3956275532 Jan 10 12:39:55 PM PST 24 Jan 10 12:40:33 PM PST 24 75979816 ps
T893 /workspace/coverage/default/35.clkmgr_alert_test.3805653845 Jan 10 12:41:27 PM PST 24 Jan 10 12:42:34 PM PST 24 26294071 ps
T894 /workspace/coverage/default/1.clkmgr_smoke.1086632399 Jan 10 12:39:26 PM PST 24 Jan 10 12:39:57 PM PST 24 152712800 ps
T895 /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.4090740878 Jan 10 12:40:49 PM PST 24 Jan 10 12:41:38 PM PST 24 30261830 ps
T896 /workspace/coverage/default/18.clkmgr_frequency_timeout.1699630289 Jan 10 12:40:39 PM PST 24 Jan 10 12:41:33 PM PST 24 1828770809 ps
T897 /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.2242670214 Jan 10 12:41:52 PM PST 24 Jan 10 12:43:02 PM PST 24 42349436 ps
T898 /workspace/coverage/default/23.clkmgr_regwen.2209344669 Jan 10 12:40:52 PM PST 24 Jan 10 12:41:45 PM PST 24 455802305 ps
T899 /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1742914327 Jan 10 12:40:16 PM PST 24 Jan 10 12:41:04 PM PST 24 34656436 ps
T900 /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.3845486330 Jan 10 12:40:29 PM PST 24 Jan 10 12:41:15 PM PST 24 32097059 ps
T901 /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2998934967 Jan 10 12:41:58 PM PST 24 Jan 10 12:43:12 PM PST 24 43886369 ps
T902 /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1492992404 Jan 10 12:40:01 PM PST 24 Jan 10 12:40:44 PM PST 24 83544278 ps
T903 /workspace/coverage/default/47.clkmgr_regwen.1068935567 Jan 10 12:41:50 PM PST 24 Jan 10 12:43:01 PM PST 24 46068806 ps
T904 /workspace/coverage/default/29.clkmgr_extclk.1876528179 Jan 10 12:41:12 PM PST 24 Jan 10 12:42:15 PM PST 24 83410582 ps
T905 /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1281630530 Jan 10 12:41:32 PM PST 24 Jan 10 12:42:39 PM PST 24 81204112 ps
T906 /workspace/coverage/default/42.clkmgr_div_intersig_mubi.1834872889 Jan 10 12:41:48 PM PST 24 Jan 10 12:42:58 PM PST 24 39759731 ps
T907 /workspace/coverage/default/46.clkmgr_extclk.416326264 Jan 10 12:41:48 PM PST 24 Jan 10 12:42:58 PM PST 24 98226180 ps
T908 /workspace/coverage/default/6.clkmgr_trans.346757137 Jan 10 12:39:48 PM PST 24 Jan 10 12:40:21 PM PST 24 17867323 ps
T909 /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3817354003 Jan 10 12:41:29 PM PST 24 Jan 10 12:42:36 PM PST 24 252768088 ps
T910 /workspace/coverage/default/27.clkmgr_frequency_timeout.1743172736 Jan 10 12:41:12 PM PST 24 Jan 10 12:42:22 PM PST 24 2209369918 ps
T911 /workspace/coverage/default/36.clkmgr_div_intersig_mubi.2870738512 Jan 10 12:41:33 PM PST 24 Jan 10 12:42:39 PM PST 24 22240294 ps
T912 /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.1516732411 Jan 10 12:41:25 PM PST 24 Jan 10 12:42:32 PM PST 24 15799050 ps
T913 /workspace/coverage/default/25.clkmgr_stress_all.1087715552 Jan 10 12:40:56 PM PST 24 Jan 10 12:42:13 PM PST 24 3041434848 ps
T914 /workspace/coverage/default/12.clkmgr_peri.241339889 Jan 10 12:40:29 PM PST 24 Jan 10 12:41:15 PM PST 24 12856344 ps
T915 /workspace/coverage/default/37.clkmgr_regwen.2966961344 Jan 10 12:41:25 PM PST 24 Jan 10 12:42:36 PM PST 24 1188212879 ps
T916 /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.3825667156 Jan 10 12:41:09 PM PST 24 Jan 10 12:42:10 PM PST 24 79853763 ps
T917 /workspace/coverage/default/8.clkmgr_div_intersig_mubi.4011038971 Jan 10 12:39:54 PM PST 24 Jan 10 12:40:32 PM PST 24 76008139 ps
T918 /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.2839990686 Jan 10 12:39:43 PM PST 24 Jan 10 12:40:13 PM PST 24 30676386 ps
T919 /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.3749454252 Jan 10 12:40:01 PM PST 24 Jan 10 12:40:44 PM PST 24 17349654 ps
T920 /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1807015420 Jan 10 12:41:52 PM PST 24 Jan 10 12:43:02 PM PST 24 196844341 ps
T921 /workspace/coverage/default/14.clkmgr_frequency_timeout.2062023053 Jan 10 12:40:26 PM PST 24 Jan 10 12:41:15 PM PST 24 658867122 ps
T922 /workspace/coverage/default/48.clkmgr_peri.454664736 Jan 10 12:41:51 PM PST 24 Jan 10 12:43:02 PM PST 24 35965225 ps
T923 /workspace/coverage/default/13.clkmgr_extclk.719531648 Jan 10 12:40:22 PM PST 24 Jan 10 12:41:09 PM PST 24 19231964 ps
T924 /workspace/coverage/default/10.clkmgr_clk_status.2940781920 Jan 10 12:40:08 PM PST 24 Jan 10 12:40:54 PM PST 24 14376452 ps
T925 /workspace/coverage/default/33.clkmgr_extclk.1277656426 Jan 10 12:41:17 PM PST 24 Jan 10 12:42:23 PM PST 24 76171307 ps
T926 /workspace/coverage/default/36.clkmgr_frequency_timeout.1780502145 Jan 10 12:41:18 PM PST 24 Jan 10 12:42:26 PM PST 24 256980193 ps
T927 /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.201184420 Jan 10 12:41:09 PM PST 24 Jan 10 12:42:10 PM PST 24 63872870 ps
T928 /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3724561525 Jan 10 12:39:41 PM PST 24 Jan 10 12:40:12 PM PST 24 101331649 ps
T929 /workspace/coverage/default/30.clkmgr_frequency_timeout.2879780802 Jan 10 12:41:20 PM PST 24 Jan 10 12:42:30 PM PST 24 741375380 ps
T930 /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.4021154628 Jan 10 12:41:49 PM PST 24 Jan 10 12:42:58 PM PST 24 16516158 ps
T931 /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.673964634 Jan 10 12:40:51 PM PST 24 Jan 10 12:41:41 PM PST 24 12322608 ps
T932 /workspace/coverage/default/49.clkmgr_frequency_timeout.896994302 Jan 10 12:41:55 PM PST 24 Jan 10 12:43:07 PM PST 24 140123101 ps
T933 /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1085763367 Jan 10 12:41:06 PM PST 24 Jan 10 12:42:06 PM PST 24 139017293 ps
T934 /workspace/coverage/default/1.clkmgr_extclk.3702299826 Jan 10 12:39:27 PM PST 24 Jan 10 12:39:59 PM PST 24 272089225 ps
T935 /workspace/coverage/default/32.clkmgr_trans.1024863700 Jan 10 12:41:20 PM PST 24 Jan 10 12:42:27 PM PST 24 17308396 ps
T936 /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.3069678906 Jan 10 12:41:22 PM PST 24 Jan 10 12:45:02 PM PST 24 9993715397 ps
T937 /workspace/coverage/default/25.clkmgr_clk_status.2604222361 Jan 10 12:40:53 PM PST 24 Jan 10 12:41:44 PM PST 24 48775597 ps
T938 /workspace/coverage/default/29.clkmgr_frequency_timeout.2197760094 Jan 10 12:41:10 PM PST 24 Jan 10 12:42:13 PM PST 24 381813810 ps
T939 /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.852500775 Jan 10 12:40:42 PM PST 24 Jan 10 12:41:29 PM PST 24 30260967 ps
T940 /workspace/coverage/default/3.clkmgr_stress_all.295298470 Jan 10 12:40:02 PM PST 24 Jan 10 12:41:21 PM PST 24 8484400444 ps
T941 /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.2983940853 Jan 10 12:39:57 PM PST 24 Jan 10 12:40:36 PM PST 24 33439974 ps
T942 /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.4189406504 Jan 10 12:41:14 PM PST 24 Jan 10 12:42:18 PM PST 24 24275643 ps
T943 /workspace/coverage/default/40.clkmgr_smoke.4031209977 Jan 10 12:41:44 PM PST 24 Jan 10 12:42:52 PM PST 24 25651274 ps
T944 /workspace/coverage/default/36.clkmgr_clk_status.249236093 Jan 10 12:41:24 PM PST 24 Jan 10 12:42:31 PM PST 24 23534047 ps
T945 /workspace/coverage/default/0.clkmgr_alert_test.2826110717 Jan 10 12:39:33 PM PST 24 Jan 10 12:40:03 PM PST 24 12231798 ps
T946 /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.2525807742 Jan 10 12:39:41 PM PST 24 Jan 10 12:40:12 PM PST 24 76015668 ps
T947 /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.4174252379 Jan 10 12:40:39 PM PST 24 Jan 10 12:41:25 PM PST 24 29729693 ps
T948 /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.310734828 Jan 10 12:41:16 PM PST 24 Jan 10 12:42:24 PM PST 24 16134215 ps
T949 /workspace/coverage/default/25.clkmgr_smoke.2592951047 Jan 10 12:41:07 PM PST 24 Jan 10 12:42:07 PM PST 24 15878023 ps
T950 /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.100554947 Jan 10 12:41:48 PM PST 24 Jan 10 12:42:58 PM PST 24 15867983 ps
T951 /workspace/coverage/default/43.clkmgr_smoke.2395032393 Jan 10 12:41:54 PM PST 24 Jan 10 12:43:05 PM PST 24 153392156 ps
T952 /workspace/coverage/default/5.clkmgr_alert_test.2666683980 Jan 10 12:40:09 PM PST 24 Jan 10 12:40:57 PM PST 24 32861477 ps
T953 /workspace/coverage/default/32.clkmgr_clk_status.4235263663 Jan 10 12:41:22 PM PST 24 Jan 10 12:42:29 PM PST 24 56332340 ps
T954 /workspace/coverage/default/24.clkmgr_stress_all.1823776305 Jan 10 12:41:06 PM PST 24 Jan 10 12:42:26 PM PST 24 4939203094 ps
T955 /workspace/coverage/default/20.clkmgr_trans.2323520614 Jan 10 12:40:33 PM PST 24 Jan 10 12:41:17 PM PST 24 31697502 ps
T956 /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.2592888062 Jan 10 12:40:41 PM PST 24 Jan 10 12:41:26 PM PST 24 30365373 ps
T957 /workspace/coverage/default/39.clkmgr_div_intersig_mubi.1234701828 Jan 10 12:41:27 PM PST 24 Jan 10 12:42:34 PM PST 24 29176968 ps
T958 /workspace/coverage/default/15.clkmgr_stress_all.3347700569 Jan 10 12:40:22 PM PST 24 Jan 10 12:41:31 PM PST 24 3091768534 ps
T959 /workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.2391247375 Jan 10 12:41:23 PM PST 24 Jan 10 12:52:00 PM PST 24 101021083004 ps
T960 /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.1874964222 Jan 10 12:40:04 PM PST 24 Jan 10 12:40:49 PM PST 24 152117480 ps
T961 /workspace/coverage/default/44.clkmgr_alert_test.1945656452 Jan 10 12:41:45 PM PST 24 Jan 10 12:42:53 PM PST 24 14067349 ps
T962 /workspace/coverage/default/27.clkmgr_extclk.2156756950 Jan 10 12:41:06 PM PST 24 Jan 10 12:42:07 PM PST 24 46720878 ps
T963 /workspace/coverage/default/39.clkmgr_frequency_timeout.1262938776 Jan 10 12:41:31 PM PST 24 Jan 10 12:42:41 PM PST 24 862859436 ps
T964 /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.3418122857 Jan 10 12:41:18 PM PST 24 Jan 10 12:42:24 PM PST 24 64995001 ps
T965 /workspace/coverage/default/11.clkmgr_alert_test.4144244423 Jan 10 12:40:18 PM PST 24 Jan 10 12:41:05 PM PST 24 27539929 ps
T966 /workspace/coverage/default/40.clkmgr_peri.178667074 Jan 10 12:41:35 PM PST 24 Jan 10 12:42:42 PM PST 24 17245009 ps
T967 /workspace/coverage/default/47.clkmgr_div_intersig_mubi.1698508616 Jan 10 12:41:44 PM PST 24 Jan 10 12:42:52 PM PST 24 39274478 ps
T968 /workspace/coverage/default/42.clkmgr_stress_all.636848051 Jan 10 12:41:51 PM PST 24 Jan 10 12:44:13 PM PST 24 11894380344 ps
T969 /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.2094103172 Jan 10 12:40:56 PM PST 24 Jan 10 12:41:51 PM PST 24 65999515 ps
T970 /workspace/coverage/default/33.clkmgr_frequency_timeout.438765035 Jan 10 12:41:22 PM PST 24 Jan 10 12:42:38 PM PST 24 1461062233 ps
T971 /workspace/coverage/default/40.clkmgr_trans.2982941968 Jan 10 12:41:34 PM PST 24 Jan 10 12:42:41 PM PST 24 110737175 ps
T972 /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2545822988 Jan 10 12:42:01 PM PST 24 Jan 10 12:43:16 PM PST 24 29611677 ps
T973 /workspace/coverage/default/36.clkmgr_extclk.1161389208 Jan 10 12:41:17 PM PST 24 Jan 10 12:42:22 PM PST 24 14635834 ps
T974 /workspace/coverage/default/18.clkmgr_trans.3763144888 Jan 10 12:40:45 PM PST 24 Jan 10 12:41:33 PM PST 24 51149811 ps
T975 /workspace/coverage/default/47.clkmgr_frequency.1628161067 Jan 10 12:41:45 PM PST 24 Jan 10 12:42:55 PM PST 24 316689122 ps
T976 /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3093816254 Jan 10 12:39:28 PM PST 24 Jan 10 12:39:59 PM PST 24 16978277 ps
T977 /workspace/coverage/default/41.clkmgr_trans.1284884071 Jan 10 12:41:39 PM PST 24 Jan 10 12:42:45 PM PST 24 24933496 ps
T978 /workspace/coverage/default/46.clkmgr_frequency.4249178493 Jan 10 12:41:45 PM PST 24 Jan 10 12:43:07 PM PST 24 2239539919 ps
T979 /workspace/coverage/default/38.clkmgr_trans.2495934199 Jan 10 12:41:29 PM PST 24 Jan 10 12:42:36 PM PST 24 28552562 ps
T980 /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.4071623477 Jan 10 12:40:40 PM PST 24 Jan 10 12:54:52 PM PST 24 114815791045 ps
T981 /workspace/coverage/default/35.clkmgr_extclk.3370057632 Jan 10 12:41:20 PM PST 24 Jan 10 12:42:27 PM PST 24 67707178 ps
T982 /workspace/coverage/default/16.clkmgr_alert_test.3919995900 Jan 10 12:40:34 PM PST 24 Jan 10 12:41:19 PM PST 24 48946704 ps
T983 /workspace/coverage/default/24.clkmgr_alert_test.1320074005 Jan 10 12:40:57 PM PST 24 Jan 10 12:41:53 PM PST 24 17486634 ps
T984 /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1339798387 Jan 10 12:39:44 PM PST 24 Jan 10 12:40:16 PM PST 24 51824888 ps
T985 /workspace/coverage/default/32.clkmgr_stress_all.146698806 Jan 10 12:41:17 PM PST 24 Jan 10 12:42:51 PM PST 24 3790216722 ps
T986 /workspace/coverage/default/42.clkmgr_trans.2830449496 Jan 10 12:41:32 PM PST 24 Jan 10 12:42:38 PM PST 24 73396944 ps
T987 /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.1623887874 Jan 10 12:41:46 PM PST 24 Jan 10 12:56:35 PM PST 24 53050758284 ps
T988 /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.4206620127 Jan 10 12:40:04 PM PST 24 Jan 10 12:40:49 PM PST 24 34460312 ps
T989 /workspace/coverage/default/24.clkmgr_frequency_timeout.2319968037 Jan 10 12:40:54 PM PST 24 Jan 10 12:41:52 PM PST 24 740504468 ps
T990 /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.3513112046 Jan 10 12:41:14 PM PST 24 Jan 10 12:42:18 PM PST 24 15649204 ps
T991 /workspace/coverage/default/9.clkmgr_div_intersig_mubi.1029709001 Jan 10 12:40:06 PM PST 24 Jan 10 12:40:53 PM PST 24 32821003 ps
T992 /workspace/coverage/default/15.clkmgr_clk_status.1726022910 Jan 10 12:40:25 PM PST 24 Jan 10 12:41:12 PM PST 24 15181458 ps
T993 /workspace/coverage/default/37.clkmgr_alert_test.2847550177 Jan 10 12:41:33 PM PST 24 Jan 10 12:42:40 PM PST 24 30332308 ps
T994 /workspace/coverage/default/28.clkmgr_extclk.3871859095 Jan 10 12:41:14 PM PST 24 Jan 10 12:42:18 PM PST 24 95626741 ps
T995 /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3178647566 Jan 10 12:41:49 PM PST 24 Jan 10 12:42:59 PM PST 24 13049233 ps
T996 /workspace/coverage/default/45.clkmgr_stress_all.1796701029 Jan 10 12:41:40 PM PST 24 Jan 10 12:43:36 PM PST 24 6863210524 ps
T997 /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.2950443416 Jan 10 12:41:17 PM PST 24 Jan 10 12:51:17 PM PST 24 76678317952 ps
T998 /workspace/coverage/default/19.clkmgr_frequency.4226694177 Jan 10 12:40:41 PM PST 24 Jan 10 12:41:29 PM PST 24 822067187 ps

Test location /workspace/coverage/default/0.clkmgr_frequency.3178387642
Short name T1
Test name
Test status
Simulation time 798633460 ps
CPU time 6.39 seconds
Started Jan 10 12:39:26 PM PST 24
Finished Jan 10 12:40:02 PM PST 24
Peak memory 200600 kb
Host smart-36ceb39a-d017-4685-8a4f-bf42c632dbe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178387642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.3178387642
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.426234384
Short name T3
Test name
Test status
Simulation time 39615443964 ps
CPU time 540.4 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:51:59 PM PST 24
Peak memory 209196 kb
Host smart-a944ec4a-72b9-4ed8-b1bf-72c9db39ffa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=426234384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.426234384
Directory /workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.93172375
Short name T65
Test name
Test status
Simulation time 285254683 ps
CPU time 2.2 seconds
Started Jan 10 12:59:20 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 209312 kb
Host smart-84e4de5d-0a88-4051-8a8f-2c0745a50e3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93172375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_
test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.clkmgr_shadow_reg_errors.93172375
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1737390446
Short name T46
Test name
Test status
Simulation time 68723253 ps
CPU time 1.71 seconds
Started Jan 10 12:59:11 PM PST 24
Finished Jan 10 01:00:48 PM PST 24
Peak memory 200980 kb
Host smart-bc837d10-cec1-4ad7-8aae-3c3a16666aed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737390446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.1737390446
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.1746539907
Short name T73
Test name
Test status
Simulation time 281561015 ps
CPU time 3.73 seconds
Started Jan 10 12:59:11 PM PST 24
Finished Jan 10 01:00:50 PM PST 24
Peak memory 200988 kb
Host smart-4379699a-bc18-4bf2-8bf5-a801c09b4ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746539907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.1746539907
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.832213009
Short name T129
Test name
Test status
Simulation time 17395568 ps
CPU time 0.71 seconds
Started Jan 10 12:40:24 PM PST 24
Finished Jan 10 12:41:11 PM PST 24
Peak memory 200640 kb
Host smart-8aca9680-5131-40b5-9b1f-578221754b26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832213009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.832213009
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.10642474
Short name T32
Test name
Test status
Simulation time 1823103782 ps
CPU time 7.35 seconds
Started Jan 10 12:41:05 PM PST 24
Finished Jan 10 12:42:11 PM PST 24
Peak memory 201004 kb
Host smart-f1984a4b-e016-49ef-8152-d795001f4330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_stress_all.10642474
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.1938278394
Short name T52
Test name
Test status
Simulation time 381506759 ps
CPU time 3.23 seconds
Started Jan 10 12:39:27 PM PST 24
Finished Jan 10 12:40:02 PM PST 24
Peak memory 220524 kb
Host smart-f05b296a-97bc-4c73-b18b-aadb200e1448
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938278394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.1938278394
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2191030849
Short name T69
Test name
Test status
Simulation time 135284848 ps
CPU time 2.19 seconds
Started Jan 10 12:59:05 PM PST 24
Finished Jan 10 01:00:44 PM PST 24
Peak memory 217000 kb
Host smart-7968f6ff-4414-427d-bc33-2748c3aa3d04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191030849 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.2191030849
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.3526516481
Short name T366
Test name
Test status
Simulation time 73085665 ps
CPU time 1.02 seconds
Started Jan 10 12:40:40 PM PST 24
Finished Jan 10 12:41:26 PM PST 24
Peak memory 200700 kb
Host smart-064dd47c-c01d-4737-9060-67c6242990a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526516481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.3526516481
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.2353567331
Short name T30
Test name
Test status
Simulation time 565972765 ps
CPU time 2.52 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200748 kb
Host smart-8a6f9478-b1a3-42be-90fe-19685cbeb79c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353567331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.2353567331
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.1392300662
Short name T100
Test name
Test status
Simulation time 22927688 ps
CPU time 0.82 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 200700 kb
Host smart-4957cc85-e246-421b-a00c-dc5c69f280ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392300662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.1392300662
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.2526735377
Short name T66
Test name
Test status
Simulation time 54539413 ps
CPU time 0.95 seconds
Started Jan 10 12:59:09 PM PST 24
Finished Jan 10 01:00:43 PM PST 24
Peak memory 200804 kb
Host smart-a7d83d1c-c66a-4392-ab82-330435dd0d92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526735377 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.2526735377
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1879456189
Short name T94
Test name
Test status
Simulation time 146458755 ps
CPU time 2.43 seconds
Started Jan 10 12:59:13 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 200936 kb
Host smart-2449ad13-9dcd-4084-bc3e-bc766476e9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879456189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.1879456189
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.841107011
Short name T285
Test name
Test status
Simulation time 35714958 ps
CPU time 0.86 seconds
Started Jan 10 12:40:29 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 200668 kb
Host smart-857a6ba9-dd67-4e28-b995-d263ea544ec5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841107011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.841107011
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1800246330
Short name T49
Test name
Test status
Simulation time 35536827 ps
CPU time 1.09 seconds
Started Jan 10 12:59:21 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 200620 kb
Host smart-57812b4a-6fb4-4c00-b926-74d6bb856f43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800246330 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.1800246330
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.155229701
Short name T321
Test name
Test status
Simulation time 52061561 ps
CPU time 0.84 seconds
Started Jan 10 12:40:35 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200608 kb
Host smart-24c31713-c4fe-493c-b1a1-63cecbe16349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155229701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkm
gr_alert_test.155229701
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.3199936793
Short name T8
Test name
Test status
Simulation time 1139196739 ps
CPU time 6.41 seconds
Started Jan 10 12:39:42 PM PST 24
Finished Jan 10 12:40:18 PM PST 24
Peak memory 200848 kb
Host smart-3cfb358c-b35a-4263-9892-0ef8446a50cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199936793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.3199936793
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2422134926
Short name T177
Test name
Test status
Simulation time 149863562 ps
CPU time 2.72 seconds
Started Jan 10 12:59:00 PM PST 24
Finished Jan 10 01:00:32 PM PST 24
Peak memory 200928 kb
Host smart-dfaaadf6-1064-4cee-a065-e1fca14336ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422134926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.2422134926
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1642124227
Short name T113
Test name
Test status
Simulation time 60454194 ps
CPU time 1.25 seconds
Started Jan 10 12:59:13 PM PST 24
Finished Jan 10 01:00:48 PM PST 24
Peak memory 201048 kb
Host smart-0185651a-4be1-457c-b80e-2cfb1d7a997b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642124227 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.1642124227
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2640265394
Short name T97
Test name
Test status
Simulation time 391190053 ps
CPU time 3.25 seconds
Started Jan 10 12:59:11 PM PST 24
Finished Jan 10 01:00:50 PM PST 24
Peak memory 200864 kb
Host smart-bcf80db0-f58b-4a1d-990c-c3f4a53b0a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640265394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.2640265394
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.3338951181
Short name T2
Test name
Test status
Simulation time 52818463900 ps
CPU time 387.81 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:47:19 PM PST 24
Peak memory 209212 kb
Host smart-66a8f15e-72bb-4cec-a9f5-bfe29a87614f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3338951181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.3338951181
Directory /workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.2037664266
Short name T151
Test name
Test status
Simulation time 7813165873 ps
CPU time 30.25 seconds
Started Jan 10 12:40:28 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 201064 kb
Host smart-1150a63a-58c6-44be-a926-b4289ac57939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037664266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.2037664266
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2084210856
Short name T119
Test name
Test status
Simulation time 272364166 ps
CPU time 1.65 seconds
Started Jan 10 12:59:13 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 200992 kb
Host smart-ec8cbdae-a842-42c0-865a-02b61355c94a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084210856 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.2084210856
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1727594455
Short name T99
Test name
Test status
Simulation time 182798356 ps
CPU time 1.92 seconds
Started Jan 10 12:59:11 PM PST 24
Finished Jan 10 01:00:48 PM PST 24
Peak memory 200980 kb
Host smart-c1c844d9-64a2-42b5-ae60-3b059a29eb70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727594455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.1727594455
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1328353977
Short name T93
Test name
Test status
Simulation time 66592385 ps
CPU time 1.55 seconds
Started Jan 10 12:59:16 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 200952 kb
Host smart-287a8ed9-03e3-49f2-a2c5-f40cdd3e086c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328353977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.1328353977
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3841295442
Short name T227
Test name
Test status
Simulation time 211619135 ps
CPU time 2.05 seconds
Started Jan 10 12:59:06 PM PST 24
Finished Jan 10 01:00:42 PM PST 24
Peak memory 200868 kb
Host smart-ab86fc7c-98b9-42ff-8f15-28bc29623591
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841295442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.3841295442
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.859975214
Short name T80
Test name
Test status
Simulation time 991159935 ps
CPU time 9.08 seconds
Started Jan 10 12:59:00 PM PST 24
Finished Jan 10 01:00:40 PM PST 24
Peak memory 200924 kb
Host smart-7d4ee08b-6ad5-4736-bfe7-10321e4d9898
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859975214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_bit_bash.859975214
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1970538074
Short name T238
Test name
Test status
Simulation time 70352856 ps
CPU time 0.86 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:51 PM PST 24
Peak memory 200712 kb
Host smart-8f004659-59b0-4d36-84bf-67921946308d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970538074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.1970538074
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2481816622
Short name T38
Test name
Test status
Simulation time 33615986 ps
CPU time 1.14 seconds
Started Jan 10 12:59:00 PM PST 24
Finished Jan 10 01:00:31 PM PST 24
Peak memory 200856 kb
Host smart-eba68d3b-dae7-4b04-a9f3-6c07b6ea2e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481816622 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.2481816622
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1946433805
Short name T192
Test name
Test status
Simulation time 16517208 ps
CPU time 0.75 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 200552 kb
Host smart-fe485fd8-db83-4f10-9bcf-c5fc5db0dc51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946433805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.1946433805
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1402820794
Short name T87
Test name
Test status
Simulation time 48624772 ps
CPU time 0.75 seconds
Started Jan 10 12:58:58 PM PST 24
Finished Jan 10 01:00:28 PM PST 24
Peak memory 199044 kb
Host smart-d497090a-3fe1-438c-853e-763261493f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402820794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.1402820794
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.4007003924
Short name T181
Test name
Test status
Simulation time 113341375 ps
CPU time 1.15 seconds
Started Jan 10 12:58:56 PM PST 24
Finished Jan 10 01:00:25 PM PST 24
Peak memory 200744 kb
Host smart-e2639ce3-d87b-4ad6-a0ee-4510f8600bb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007003924 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.4007003924
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3833078109
Short name T121
Test name
Test status
Simulation time 65788698 ps
CPU time 1.21 seconds
Started Jan 10 12:58:51 PM PST 24
Finished Jan 10 01:00:19 PM PST 24
Peak memory 201000 kb
Host smart-0388d735-5a9a-407e-96f6-55f84674ebd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833078109 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.3833078109
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.438530610
Short name T239
Test name
Test status
Simulation time 491259756 ps
CPU time 4.2 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:33 PM PST 24
Peak memory 217680 kb
Host smart-20dfb93a-f12b-4a4b-ac56-5becce4fd76c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438530610 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.438530610
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1032683133
Short name T269
Test name
Test status
Simulation time 1117473918 ps
CPU time 4.27 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:35 PM PST 24
Peak memory 200860 kb
Host smart-859e7f6d-f04c-4ab0-91d7-82372dc7f62a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032683133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.1032683133
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1436179149
Short name T225
Test name
Test status
Simulation time 284124027 ps
CPU time 1.8 seconds
Started Jan 10 12:58:57 PM PST 24
Finished Jan 10 01:00:27 PM PST 24
Peak memory 200644 kb
Host smart-0687df51-b316-4d01-bb75-4c334dbbd66d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436179149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.1436179149
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1068087477
Short name T191
Test name
Test status
Simulation time 507514717 ps
CPU time 4.83 seconds
Started Jan 10 12:58:58 PM PST 24
Finished Jan 10 01:00:31 PM PST 24
Peak memory 200928 kb
Host smart-d487b218-c7b7-49fd-be92-38cf675b81a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068087477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.1068087477
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.255601752
Short name T85
Test name
Test status
Simulation time 233244768 ps
CPU time 1.3 seconds
Started Jan 10 12:59:00 PM PST 24
Finished Jan 10 01:00:30 PM PST 24
Peak memory 200712 kb
Host smart-ccb75e5d-0ead-4b1f-93aa-617c3b6f463b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255601752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_hw_reset.255601752
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.4138508767
Short name T196
Test name
Test status
Simulation time 14988446 ps
CPU time 0.76 seconds
Started Jan 10 12:59:02 PM PST 24
Finished Jan 10 01:00:39 PM PST 24
Peak memory 200680 kb
Host smart-80ad538c-63fc-48c6-a248-ebe69b8d2992
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138508767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.4138508767
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.4266145388
Short name T165
Test name
Test status
Simulation time 26517528 ps
CPU time 0.66 seconds
Started Jan 10 12:58:57 PM PST 24
Finished Jan 10 01:00:26 PM PST 24
Peak memory 199148 kb
Host smart-dd9e8e8b-9404-42a7-a8bb-0d5a160f9a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266145388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.4266145388
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1042194986
Short name T210
Test name
Test status
Simulation time 57831565 ps
CPU time 1.38 seconds
Started Jan 10 12:59:02 PM PST 24
Finished Jan 10 01:00:36 PM PST 24
Peak memory 200892 kb
Host smart-2d5b49bd-2049-42e3-899f-28b4ee22cf5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042194986 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.1042194986
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2658637028
Short name T36
Test name
Test status
Simulation time 249752127 ps
CPU time 2.21 seconds
Started Jan 10 12:59:01 PM PST 24
Finished Jan 10 01:00:34 PM PST 24
Peak memory 216988 kb
Host smart-02c0a4fb-9fe0-406f-a785-9ace7416fc76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658637028 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.2658637028
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3278549188
Short name T88
Test name
Test status
Simulation time 90487540 ps
CPU time 1.9 seconds
Started Jan 10 12:58:58 PM PST 24
Finished Jan 10 01:00:29 PM PST 24
Peak memory 201156 kb
Host smart-655afcf9-c319-439d-9442-a995341807c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278549188 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.3278549188
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3395065207
Short name T75
Test name
Test status
Simulation time 72732566 ps
CPU time 2.03 seconds
Started Jan 10 12:59:00 PM PST 24
Finished Jan 10 01:00:32 PM PST 24
Peak memory 200924 kb
Host smart-26023572-82d2-4b75-a7bb-b9b3bb50d7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395065207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.3395065207
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.332284985
Short name T259
Test name
Test status
Simulation time 138135952 ps
CPU time 2.33 seconds
Started Jan 10 12:58:57 PM PST 24
Finished Jan 10 01:00:28 PM PST 24
Peak memory 200864 kb
Host smart-1eeadbf6-dc1c-4c99-9eba-e04d35058340
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332284985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.clkmgr_tl_intg_err.332284985
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.1863240467
Short name T147
Test name
Test status
Simulation time 33135525 ps
CPU time 0.97 seconds
Started Jan 10 12:59:11 PM PST 24
Finished Jan 10 01:00:47 PM PST 24
Peak memory 200976 kb
Host smart-377beebc-2661-4992-80ac-ec07c2e920b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863240467 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.1863240467
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3175580911
Short name T217
Test name
Test status
Simulation time 53361353 ps
CPU time 0.85 seconds
Started Jan 10 12:59:14 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 200600 kb
Host smart-b49cf8d3-b518-4da3-807c-5499330d4714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175580911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.3175580911
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1317277729
Short name T230
Test name
Test status
Simulation time 14074336 ps
CPU time 0.64 seconds
Started Jan 10 12:59:15 PM PST 24
Finished Jan 10 01:00:50 PM PST 24
Peak memory 199148 kb
Host smart-6d0943c0-442a-4ea6-aeb7-a26d458e83ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317277729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.1317277729
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.7234621
Short name T156
Test name
Test status
Simulation time 49349783 ps
CPU time 1.08 seconds
Started Jan 10 12:59:13 PM PST 24
Finished Jan 10 01:00:48 PM PST 24
Peak memory 200824 kb
Host smart-23477e76-7c59-45cb-81b4-20a86db121b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7234621 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_same_csr_outstanding.7234621
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.1652151335
Short name T203
Test name
Test status
Simulation time 117463951 ps
CPU time 2.11 seconds
Started Jan 10 12:59:11 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 201276 kb
Host smart-d31da01b-b758-4ebd-87a2-7beb78b4ec55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652151335 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.1652151335
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2738157115
Short name T207
Test name
Test status
Simulation time 43512163 ps
CPU time 2.33 seconds
Started Jan 10 12:59:17 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 201020 kb
Host smart-65cc44f1-57de-472a-8550-0704ff3b74a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738157115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.2738157115
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.716478031
Short name T96
Test name
Test status
Simulation time 351867376 ps
CPU time 3.13 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:50 PM PST 24
Peak memory 200936 kb
Host smart-b9933072-9e56-401f-916e-f9881092220e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716478031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.clkmgr_tl_intg_err.716478031
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.2052648495
Short name T160
Test name
Test status
Simulation time 22099217 ps
CPU time 0.76 seconds
Started Jan 10 12:59:21 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 200596 kb
Host smart-33f9b7ce-eacc-4704-a1b9-40da000f979f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052648495 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.2052648495
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2618397906
Short name T276
Test name
Test status
Simulation time 22653481 ps
CPU time 0.76 seconds
Started Jan 10 12:59:15 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 200668 kb
Host smart-19c093b5-8157-4871-a9f3-bfc124307268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618397906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.2618397906
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2981434482
Short name T154
Test name
Test status
Simulation time 19937614 ps
CPU time 0.65 seconds
Started Jan 10 12:59:10 PM PST 24
Finished Jan 10 01:00:44 PM PST 24
Peak memory 199116 kb
Host smart-97e29d16-0801-424a-be9f-19d6d343a3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981434482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.2981434482
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3685563637
Short name T51
Test name
Test status
Simulation time 173622834 ps
CPU time 1.55 seconds
Started Jan 10 12:59:13 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 200712 kb
Host smart-58d3d438-b4d5-4e59-9f7c-ad9fcb49d831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685563637 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.3685563637
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2129790809
Short name T206
Test name
Test status
Simulation time 501004836 ps
CPU time 3.67 seconds
Started Jan 10 12:59:10 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 201120 kb
Host smart-677e1c7b-4d64-4b38-bc8f-92475698c67a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129790809 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.2129790809
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1776423309
Short name T68
Test name
Test status
Simulation time 55344146 ps
CPU time 1.87 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 200912 kb
Host smart-48367d87-8557-48c3-8478-d99e6ecaad74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776423309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.1776423309
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3744667624
Short name T126
Test name
Test status
Simulation time 86760761 ps
CPU time 1.16 seconds
Started Jan 10 12:59:22 PM PST 24
Finished Jan 10 01:00:58 PM PST 24
Peak memory 200664 kb
Host smart-75b6526a-e61e-4897-9c04-e166d3e386d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744667624 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.3744667624
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2774976306
Short name T253
Test name
Test status
Simulation time 53674476 ps
CPU time 0.81 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 200632 kb
Host smart-4fecc6c3-c678-4d26-9713-ffa964b3a364
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774976306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.2774976306
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.121896784
Short name T205
Test name
Test status
Simulation time 41660957 ps
CPU time 0.71 seconds
Started Jan 10 12:59:13 PM PST 24
Finished Jan 10 01:00:48 PM PST 24
Peak memory 199096 kb
Host smart-41c6c1d0-d8b3-4d3e-be27-a8733dcc7c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121896784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clk
mgr_intr_test.121896784
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1173451939
Short name T237
Test name
Test status
Simulation time 740266165 ps
CPU time 2.85 seconds
Started Jan 10 12:59:16 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 200972 kb
Host smart-cc8634ae-e01f-47bf-bc84-9e650b817371
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173451939 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.1173451939
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2696991457
Short name T89
Test name
Test status
Simulation time 176929593 ps
CPU time 1.83 seconds
Started Jan 10 12:59:31 PM PST 24
Finished Jan 10 01:01:06 PM PST 24
Peak memory 201064 kb
Host smart-34d6c350-596c-43b8-ae91-9b747829c8a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696991457 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.2696991457
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.249953268
Short name T263
Test name
Test status
Simulation time 91740349 ps
CPU time 1.51 seconds
Started Jan 10 12:59:11 PM PST 24
Finished Jan 10 01:00:48 PM PST 24
Peak memory 200872 kb
Host smart-b3f68786-4abc-49df-9cd8-86f265dfabcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249953268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clk
mgr_tl_errors.249953268
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3586029077
Short name T143
Test name
Test status
Simulation time 399778354 ps
CPU time 2.08 seconds
Started Jan 10 12:59:15 PM PST 24
Finished Jan 10 01:00:51 PM PST 24
Peak memory 200800 kb
Host smart-5d4143b1-e2fb-4ec6-baea-b525e4b78162
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586029077 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.3586029077
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2505402914
Short name T270
Test name
Test status
Simulation time 177892966 ps
CPU time 1.14 seconds
Started Jan 10 12:59:13 PM PST 24
Finished Jan 10 01:00:48 PM PST 24
Peak memory 200696 kb
Host smart-2507dac4-4302-4246-98cd-ed0e8d27fb02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505402914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.2505402914
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.338049091
Short name T267
Test name
Test status
Simulation time 39729763 ps
CPU time 0.72 seconds
Started Jan 10 12:59:09 PM PST 24
Finished Jan 10 01:00:43 PM PST 24
Peak memory 198980 kb
Host smart-10423778-0648-45d9-b703-5704433ff9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338049091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk
mgr_intr_test.338049091
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.4209334009
Short name T202
Test name
Test status
Simulation time 21598365 ps
CPU time 0.95 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:51 PM PST 24
Peak memory 200692 kb
Host smart-e14f744c-116b-45c8-b752-ee4988e85919
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209334009 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.4209334009
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1592314490
Short name T118
Test name
Test status
Simulation time 432195614 ps
CPU time 3.45 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:50 PM PST 24
Peak memory 201336 kb
Host smart-6309c85f-772d-40ff-b45c-3db31dbd0d07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592314490 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1592314490
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3570423103
Short name T83
Test name
Test status
Simulation time 24829390 ps
CPU time 0.98 seconds
Started Jan 10 12:59:21 PM PST 24
Finished Jan 10 01:00:58 PM PST 24
Peak memory 200664 kb
Host smart-0c9d2155-dbbe-4015-9d8f-4d01cacf400e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570423103 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.3570423103
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.3434095052
Short name T166
Test name
Test status
Simulation time 46914689 ps
CPU time 0.82 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:51 PM PST 24
Peak memory 200556 kb
Host smart-c2f0655e-1f3a-4055-b8ae-1920eec141b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434095052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.3434095052
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3225951154
Short name T84
Test name
Test status
Simulation time 12756868 ps
CPU time 0.7 seconds
Started Jan 10 12:59:16 PM PST 24
Finished Jan 10 01:00:50 PM PST 24
Peak memory 199072 kb
Host smart-d09b7199-46ff-411b-81f8-0a1a0da00f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225951154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.3225951154
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.480510259
Short name T48
Test name
Test status
Simulation time 91842949 ps
CPU time 1.5 seconds
Started Jan 10 12:59:11 PM PST 24
Finished Jan 10 01:00:48 PM PST 24
Peak memory 200948 kb
Host smart-55f41a50-59af-4d7b-bc4b-91033c83ef9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480510259 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 14.clkmgr_same_csr_outstanding.480510259
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.3725714123
Short name T116
Test name
Test status
Simulation time 56709758 ps
CPU time 1.21 seconds
Started Jan 10 12:59:16 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 201016 kb
Host smart-4d693d2d-17eb-48bd-a878-59da6eacb407
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725714123 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.3725714123
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.4098075573
Short name T273
Test name
Test status
Simulation time 166322368 ps
CPU time 1.92 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 217380 kb
Host smart-5101218c-7579-4802-acf9-0c8019b00b49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098075573 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.4098075573
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1386476669
Short name T235
Test name
Test status
Simulation time 107904678 ps
CPU time 1.74 seconds
Started Jan 10 12:59:10 PM PST 24
Finished Jan 10 01:00:46 PM PST 24
Peak memory 200924 kb
Host smart-f4f655ad-b505-45b6-9184-981a19ab1d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386476669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.1386476669
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.324164544
Short name T141
Test name
Test status
Simulation time 352059553 ps
CPU time 2.93 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:50 PM PST 24
Peak memory 200872 kb
Host smart-7e993fa0-26ac-4e8e-a42b-8ab92d8659c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324164544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.clkmgr_tl_intg_err.324164544
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3907934360
Short name T213
Test name
Test status
Simulation time 28892363 ps
CPU time 1.36 seconds
Started Jan 10 12:59:14 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 200900 kb
Host smart-15eeb324-c8a5-47d0-a382-4653ea0bceca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907934360 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.3907934360
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.4011192356
Short name T221
Test name
Test status
Simulation time 42079124 ps
CPU time 0.87 seconds
Started Jan 10 12:59:24 PM PST 24
Finished Jan 10 01:01:05 PM PST 24
Peak memory 200556 kb
Host smart-51ab4377-b5f3-4052-a314-3f5e07410fd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011192356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.4011192356
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.4098150596
Short name T240
Test name
Test status
Simulation time 25963304 ps
CPU time 0.66 seconds
Started Jan 10 12:59:17 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 199000 kb
Host smart-4b2823ab-f789-4334-bc20-9f50e8b41989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098150596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.4098150596
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.522423801
Short name T198
Test name
Test status
Simulation time 684922535 ps
CPU time 2.89 seconds
Started Jan 10 12:59:22 PM PST 24
Finished Jan 10 01:00:59 PM PST 24
Peak memory 200864 kb
Host smart-d90969e6-c36e-4a31-9e05-1adac643d7d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522423801 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 15.clkmgr_same_csr_outstanding.522423801
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3623828510
Short name T264
Test name
Test status
Simulation time 277590621 ps
CPU time 2.11 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 201108 kb
Host smart-5c40a2c2-767b-4197-aa50-feab24d197df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623828510 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.3623828510
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2342232151
Short name T224
Test name
Test status
Simulation time 40308030 ps
CPU time 1.22 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 200776 kb
Host smart-55f34a53-1241-4326-9368-da77f7ec92b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342232151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.2342232151
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3963252538
Short name T74
Test name
Test status
Simulation time 30022491 ps
CPU time 1.12 seconds
Started Jan 10 12:59:17 PM PST 24
Finished Jan 10 01:00:53 PM PST 24
Peak memory 200828 kb
Host smart-c76311ab-f5d2-4658-88e7-f525b545d496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963252538 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.3963252538
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3387106535
Short name T200
Test name
Test status
Simulation time 73272774 ps
CPU time 0.89 seconds
Started Jan 10 12:59:17 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 200892 kb
Host smart-be2a47aa-2811-4b6b-b5f1-b19c39377a22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387106535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.3387106535
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3270494032
Short name T171
Test name
Test status
Simulation time 125013563 ps
CPU time 0.9 seconds
Started Jan 10 12:59:16 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 199092 kb
Host smart-c81c5bfe-296c-4091-89c5-f7e3b8976fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270494032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.3270494032
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2795232228
Short name T128
Test name
Test status
Simulation time 194161456 ps
CPU time 1.69 seconds
Started Jan 10 12:59:24 PM PST 24
Finished Jan 10 01:01:05 PM PST 24
Peak memory 200860 kb
Host smart-39ad92e9-8bca-4398-9eca-4762c9d8ef66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795232228 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.2795232228
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3424459127
Short name T114
Test name
Test status
Simulation time 186897570 ps
CPU time 1.98 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 209436 kb
Host smart-f1914398-e6e2-4515-a7c4-87af65595321
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424459127 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.3424459127
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.716340925
Short name T233
Test name
Test status
Simulation time 88982606 ps
CPU time 1.93 seconds
Started Jan 10 12:59:17 PM PST 24
Finished Jan 10 01:00:53 PM PST 24
Peak memory 201284 kb
Host smart-7090f698-f057-45e3-86a9-d6a41889e2ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716340925 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.716340925
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3145347815
Short name T76
Test name
Test status
Simulation time 63246027 ps
CPU time 1.95 seconds
Started Jan 10 12:59:24 PM PST 24
Finished Jan 10 01:01:06 PM PST 24
Peak memory 200876 kb
Host smart-285040ef-db1d-4d07-a8d9-7262e38d6abc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145347815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.3145347815
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3779224255
Short name T98
Test name
Test status
Simulation time 420493299 ps
CPU time 2.18 seconds
Started Jan 10 12:59:16 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 200872 kb
Host smart-226146dc-5a13-4bd1-802f-9bd99ff58a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779224255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.3779224255
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.184889458
Short name T204
Test name
Test status
Simulation time 45667001 ps
CPU time 1.62 seconds
Started Jan 10 12:59:20 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 201016 kb
Host smart-fad631ce-edcf-484a-b2af-139f94804afa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184889458 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.184889458
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.1204089438
Short name T82
Test name
Test status
Simulation time 22822305 ps
CPU time 0.77 seconds
Started Jan 10 12:59:21 PM PST 24
Finished Jan 10 01:01:02 PM PST 24
Peak memory 200632 kb
Host smart-f6ac5024-076a-4950-a9d2-d0b076119f97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204089438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.1204089438
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3227658037
Short name T155
Test name
Test status
Simulation time 13057214 ps
CPU time 0.65 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:53 PM PST 24
Peak memory 199068 kb
Host smart-b8a41705-4535-4d5a-9762-cf15179c56f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227658037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.3227658037
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2696765508
Short name T185
Test name
Test status
Simulation time 519095774 ps
CPU time 2.38 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 200968 kb
Host smart-1e10fddd-e7f5-4f91-b183-ac2da98c8ea3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696765508 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.2696765508
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3071959936
Short name T117
Test name
Test status
Simulation time 101566555 ps
CPU time 1.72 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:57 PM PST 24
Peak memory 217048 kb
Host smart-87d16fdd-1f0b-4f28-80f5-ae5b2e35df49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071959936 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.3071959936
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2020661969
Short name T199
Test name
Test status
Simulation time 65288927 ps
CPU time 1.58 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 217528 kb
Host smart-ccab7faa-801b-4d96-a253-2c33fe58fa8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020661969 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.2020661969
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2325298297
Short name T170
Test name
Test status
Simulation time 54828237 ps
CPU time 1.57 seconds
Started Jan 10 12:59:24 PM PST 24
Finished Jan 10 01:01:01 PM PST 24
Peak memory 200852 kb
Host smart-52ed825a-ee2d-4b79-bbc3-439a744f55b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325298297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.2325298297
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.82626901
Short name T220
Test name
Test status
Simulation time 93236244 ps
CPU time 1.62 seconds
Started Jan 10 12:59:21 PM PST 24
Finished Jan 10 01:01:03 PM PST 24
Peak memory 200884 kb
Host smart-912c68f2-3d98-4b38-8448-675e1a095b64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82626901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.clkmgr_tl_intg_err.82626901
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3031606631
Short name T35
Test name
Test status
Simulation time 90565488 ps
CPU time 1.15 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:53 PM PST 24
Peak memory 200720 kb
Host smart-67ddb811-cc60-4c1e-9c5e-693282042847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031606631 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.3031606631
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2043582311
Short name T228
Test name
Test status
Simulation time 83689351 ps
CPU time 0.93 seconds
Started Jan 10 12:59:21 PM PST 24
Finished Jan 10 01:01:02 PM PST 24
Peak memory 200720 kb
Host smart-a26fd211-6b8d-4c36-934d-12fd57be188d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043582311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.2043582311
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.588277947
Short name T234
Test name
Test status
Simulation time 37942423 ps
CPU time 0.7 seconds
Started Jan 10 12:59:17 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 199140 kb
Host smart-4f2bc5a8-7d7c-41b9-96f1-49547d4e62f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588277947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk
mgr_intr_test.588277947
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.505070518
Short name T182
Test name
Test status
Simulation time 63101528 ps
CPU time 1.18 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 200692 kb
Host smart-80c76712-a358-4d75-8431-f7be4d2f20e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505070518 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 18.clkmgr_same_csr_outstanding.505070518
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1464089211
Short name T257
Test name
Test status
Simulation time 135752744 ps
CPU time 1.95 seconds
Started Jan 10 12:59:23 PM PST 24
Finished Jan 10 01:00:58 PM PST 24
Peak memory 217476 kb
Host smart-9d2aecf9-e333-4189-831b-8e6424ec2a17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464089211 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.1464089211
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3515620465
Short name T124
Test name
Test status
Simulation time 358906159 ps
CPU time 3.07 seconds
Started Jan 10 12:59:15 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 209492 kb
Host smart-862fe894-57a0-4e2c-ba54-2fbee9bad986
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515620465 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.3515620465
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1921889069
Short name T179
Test name
Test status
Simulation time 50082840 ps
CPU time 1.66 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 200872 kb
Host smart-a3c72aea-8a29-41ca-b6b7-d8884f6609c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921889069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.1921889069
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.673664071
Short name T197
Test name
Test status
Simulation time 452684194 ps
CPU time 3.45 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:57 PM PST 24
Peak memory 200772 kb
Host smart-e2091596-463c-4634-b396-19fa92cad104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673664071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.clkmgr_tl_intg_err.673664071
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.2245870691
Short name T145
Test name
Test status
Simulation time 57381615 ps
CPU time 1.77 seconds
Started Jan 10 12:59:17 PM PST 24
Finished Jan 10 01:00:53 PM PST 24
Peak memory 200960 kb
Host smart-06e9f9a3-0023-4d02-8322-9c989d52c6e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245870691 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.2245870691
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1759199574
Short name T218
Test name
Test status
Simulation time 37005249 ps
CPU time 0.86 seconds
Started Jan 10 01:01:11 PM PST 24
Finished Jan 10 01:02:39 PM PST 24
Peak memory 200296 kb
Host smart-6658ac6e-d6d7-4bb0-b4bc-1950badbc54d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759199574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.1759199574
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.384132419
Short name T231
Test name
Test status
Simulation time 57164062 ps
CPU time 0.75 seconds
Started Jan 10 12:59:16 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 199068 kb
Host smart-4a88f078-eabf-4085-9466-a09afe1de5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384132419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk
mgr_intr_test.384132419
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.982933135
Short name T161
Test name
Test status
Simulation time 135720625 ps
CPU time 1.49 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 200780 kb
Host smart-8a4b4f5a-e3b2-4a55-9b08-b8aad9938dfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982933135 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 19.clkmgr_same_csr_outstanding.982933135
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1218727402
Short name T72
Test name
Test status
Simulation time 644282849 ps
CPU time 2.84 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:57 PM PST 24
Peak memory 200924 kb
Host smart-4649ffd2-de69-4a67-b350-4039bed902a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218727402 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.1218727402
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.17716515
Short name T201
Test name
Test status
Simulation time 254528980 ps
CPU time 2.83 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:58 PM PST 24
Peak memory 209460 kb
Host smart-2cc24144-1af3-422e-a663-20600e409d9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17716515 -assert nopostproc +UVM_TESTNAME=
clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.17716515
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.226293811
Short name T67
Test name
Test status
Simulation time 1170586691 ps
CPU time 4.99 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:58 PM PST 24
Peak memory 200776 kb
Host smart-b6b43b03-bb9f-485b-9e8a-0500d49d09bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226293811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk
mgr_tl_errors.226293811
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.4146245211
Short name T178
Test name
Test status
Simulation time 121728518 ps
CPU time 1.61 seconds
Started Jan 10 12:59:23 PM PST 24
Finished Jan 10 01:00:58 PM PST 24
Peak memory 200968 kb
Host smart-a6d94bc3-3a5c-4f06-9c5a-5a11bb65be7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146245211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.4146245211
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2697697733
Short name T236
Test name
Test status
Simulation time 30875089 ps
CPU time 1.5 seconds
Started Jan 10 12:59:10 PM PST 24
Finished Jan 10 01:00:45 PM PST 24
Peak memory 200920 kb
Host smart-97ba18df-4eb5-43d6-97fe-325524cc060a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697697733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.2697697733
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.4247712716
Short name T168
Test name
Test status
Simulation time 456353237 ps
CPU time 6.49 seconds
Started Jan 10 12:59:02 PM PST 24
Finished Jan 10 01:00:40 PM PST 24
Peak memory 200880 kb
Host smart-a1ca3d44-6119-4843-9d90-f3326016aaad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247712716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.4247712716
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.361516261
Short name T246
Test name
Test status
Simulation time 24475091 ps
CPU time 0.86 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:29 PM PST 24
Peak memory 200700 kb
Host smart-4731ca62-ed2e-4769-a45e-a8092802dcfa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361516261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_csr_hw_reset.361516261
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3450751271
Short name T187
Test name
Test status
Simulation time 27722680 ps
CPU time 0.87 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:32 PM PST 24
Peak memory 200752 kb
Host smart-0984ac22-f2d2-4a55-9278-ca79944fae53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450751271 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.3450751271
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2605175913
Short name T190
Test name
Test status
Simulation time 18203119 ps
CPU time 0.79 seconds
Started Jan 10 12:58:56 PM PST 24
Finished Jan 10 01:00:25 PM PST 24
Peak memory 200668 kb
Host smart-1e1618a1-7019-4a32-a066-5c0eb331344d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605175913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.2605175913
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.2670503647
Short name T265
Test name
Test status
Simulation time 16911040 ps
CPU time 0.64 seconds
Started Jan 10 12:59:02 PM PST 24
Finished Jan 10 01:00:39 PM PST 24
Peak memory 199040 kb
Host smart-c0790ed7-a843-4a73-bd9e-41ae2861e42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670503647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.2670503647
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.2345918789
Short name T275
Test name
Test status
Simulation time 22521608 ps
CPU time 0.89 seconds
Started Jan 10 12:59:10 PM PST 24
Finished Jan 10 01:00:45 PM PST 24
Peak memory 200712 kb
Host smart-4ccbbe1e-1851-4b15-b417-7fac3c940777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345918789 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.2345918789
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2372122627
Short name T125
Test name
Test status
Simulation time 109350803 ps
CPU time 1.45 seconds
Started Jan 10 12:59:04 PM PST 24
Finished Jan 10 01:00:37 PM PST 24
Peak memory 201064 kb
Host smart-b5e3bf7e-6e99-493c-acf2-1ebad5e060a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372122627 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.2372122627
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.608076707
Short name T278
Test name
Test status
Simulation time 175812178 ps
CPU time 2.07 seconds
Started Jan 10 12:58:57 PM PST 24
Finished Jan 10 01:00:28 PM PST 24
Peak memory 201108 kb
Host smart-329d5229-9c53-488a-8c66-b570a4156b80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608076707 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.608076707
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3787635634
Short name T33
Test name
Test status
Simulation time 84851761 ps
CPU time 2.29 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:31 PM PST 24
Peak memory 200776 kb
Host smart-52c2020d-c595-457e-820a-ad00b4d92f15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787635634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_tl_errors.3787635634
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3420874266
Short name T242
Test name
Test status
Simulation time 194566933 ps
CPU time 2.68 seconds
Started Jan 10 12:59:02 PM PST 24
Finished Jan 10 01:00:41 PM PST 24
Peak memory 201016 kb
Host smart-6236535c-6505-492b-9ed1-a379d7308d01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420874266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.3420874266
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.729267047
Short name T262
Test name
Test status
Simulation time 21228628 ps
CPU time 0.68 seconds
Started Jan 10 12:59:22 PM PST 24
Finished Jan 10 01:00:58 PM PST 24
Peak memory 199080 kb
Host smart-20197320-a1e4-4148-9629-12655f4d8812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729267047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clk
mgr_intr_test.729267047
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.701902328
Short name T175
Test name
Test status
Simulation time 12946423 ps
CPU time 0.66 seconds
Started Jan 10 12:59:22 PM PST 24
Finished Jan 10 01:00:58 PM PST 24
Peak memory 198880 kb
Host smart-e9300ac5-563d-455f-ae0c-85ff67135c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701902328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clk
mgr_intr_test.701902328
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.5274407
Short name T194
Test name
Test status
Simulation time 13679786 ps
CPU time 0.66 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 199136 kb
Host smart-a61942c1-5d6b-4dd3-8569-e15388741d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5274407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=
clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmg
r_intr_test.5274407
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2730658190
Short name T184
Test name
Test status
Simulation time 34319424 ps
CPU time 0.73 seconds
Started Jan 10 12:59:24 PM PST 24
Finished Jan 10 01:01:04 PM PST 24
Peak memory 198848 kb
Host smart-ac1307a7-2cc5-4f44-8418-fdc5c12e622a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730658190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.2730658190
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1353834174
Short name T162
Test name
Test status
Simulation time 11460835 ps
CPU time 0.64 seconds
Started Jan 10 12:59:21 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 199008 kb
Host smart-108c87d6-45d1-4858-85f3-33430374b233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353834174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.1353834174
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.767849836
Short name T248
Test name
Test status
Simulation time 13812251 ps
CPU time 0.67 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 198984 kb
Host smart-9ba12b65-faf4-4fd1-99f8-8cc9a299a482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767849836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clk
mgr_intr_test.767849836
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.2012673829
Short name T172
Test name
Test status
Simulation time 26767985 ps
CPU time 0.64 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 198960 kb
Host smart-38e5008b-729b-4197-98a2-012c8290cfe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012673829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.2012673829
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2055107063
Short name T249
Test name
Test status
Simulation time 19286466 ps
CPU time 0.64 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 199140 kb
Host smart-cb84f257-1304-4ef5-87f8-09fc34591145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055107063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.2055107063
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.561509421
Short name T216
Test name
Test status
Simulation time 12773414 ps
CPU time 0.67 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 199052 kb
Host smart-7c39bffc-f043-49bd-9e8c-8b36b34aa176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561509421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clk
mgr_intr_test.561509421
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.250198761
Short name T169
Test name
Test status
Simulation time 38987900 ps
CPU time 0.71 seconds
Started Jan 10 12:59:22 PM PST 24
Finished Jan 10 01:00:58 PM PST 24
Peak memory 199092 kb
Host smart-2a59c806-7b03-45ca-8fab-069c52ae97eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250198761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clk
mgr_intr_test.250198761
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3409936040
Short name T232
Test name
Test status
Simulation time 117702000 ps
CPU time 1.39 seconds
Started Jan 10 12:58:56 PM PST 24
Finished Jan 10 01:00:25 PM PST 24
Peak memory 200576 kb
Host smart-d5b0051e-4aaa-4312-9407-3452eb1d7b27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409936040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.3409936040
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1527606707
Short name T251
Test name
Test status
Simulation time 538348937 ps
CPU time 8.42 seconds
Started Jan 10 12:58:58 PM PST 24
Finished Jan 10 01:00:36 PM PST 24
Peak memory 200824 kb
Host smart-39b9c2cf-b44e-4b9e-9f72-b25db8d39cc8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527606707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.1527606707
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1937065600
Short name T78
Test name
Test status
Simulation time 42849117 ps
CPU time 0.78 seconds
Started Jan 10 12:59:07 PM PST 24
Finished Jan 10 01:00:42 PM PST 24
Peak memory 200708 kb
Host smart-618de043-bdcc-456d-80f0-000cf74ac4ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937065600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.1937065600
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.957227877
Short name T144
Test name
Test status
Simulation time 61508081 ps
CPU time 1.87 seconds
Started Jan 10 12:58:57 PM PST 24
Finished Jan 10 01:00:27 PM PST 24
Peak memory 210232 kb
Host smart-686d161f-fbf2-42eb-9c12-ef68619e7385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957227877 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.957227877
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2042359928
Short name T193
Test name
Test status
Simulation time 34263039 ps
CPU time 0.76 seconds
Started Jan 10 12:58:57 PM PST 24
Finished Jan 10 01:00:26 PM PST 24
Peak memory 200696 kb
Host smart-4d9d4e94-e0d8-47f2-858d-88184e06c6e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042359928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.2042359928
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3678956526
Short name T209
Test name
Test status
Simulation time 23145706 ps
CPU time 0.65 seconds
Started Jan 10 12:59:00 PM PST 24
Finished Jan 10 01:00:30 PM PST 24
Peak memory 199132 kb
Host smart-77a74548-c58a-4e3c-a051-b02ec5eb41cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678956526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.3678956526
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2501737902
Short name T256
Test name
Test status
Simulation time 22393709 ps
CPU time 0.92 seconds
Started Jan 10 12:59:09 PM PST 24
Finished Jan 10 01:00:44 PM PST 24
Peak memory 200580 kb
Host smart-c284ef31-c572-4c5c-a7b8-8423eb8049fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501737902 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.2501737902
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3235785628
Short name T71
Test name
Test status
Simulation time 504110147 ps
CPU time 3.42 seconds
Started Jan 10 12:59:00 PM PST 24
Finished Jan 10 01:00:33 PM PST 24
Peak memory 217576 kb
Host smart-6d0a53c9-e050-41c6-b685-5ff7b407b864
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235785628 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.3235785628
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.822361454
Short name T188
Test name
Test status
Simulation time 186119174 ps
CPU time 1.89 seconds
Started Jan 10 12:59:15 PM PST 24
Finished Jan 10 01:00:51 PM PST 24
Peak memory 200924 kb
Host smart-dde4afde-4742-43a3-b54d-a91c03929c0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822361454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkm
gr_tl_errors.822361454
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2947052617
Short name T91
Test name
Test status
Simulation time 85285400 ps
CPU time 1.79 seconds
Started Jan 10 12:58:57 PM PST 24
Finished Jan 10 01:00:27 PM PST 24
Peak memory 200928 kb
Host smart-6968452f-5f3b-43bd-a1e8-ac143a5d1724
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947052617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.2947052617
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.1522296911
Short name T167
Test name
Test status
Simulation time 33035432 ps
CPU time 0.7 seconds
Started Jan 10 12:59:20 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 198960 kb
Host smart-63c89217-77e1-4df1-bda8-05bbdb31ebc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522296911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.1522296911
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1711620756
Short name T226
Test name
Test status
Simulation time 10793476 ps
CPU time 0.66 seconds
Started Jan 10 12:59:18 PM PST 24
Finished Jan 10 01:00:53 PM PST 24
Peak memory 199096 kb
Host smart-20abd834-fc5e-4287-a0ba-cad28ef01676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711620756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.1711620756
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1522444599
Short name T159
Test name
Test status
Simulation time 35009347 ps
CPU time 0.77 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 199096 kb
Host smart-5d6e9df9-677a-4277-b891-318e535f7ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522444599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.1522444599
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2702710769
Short name T245
Test name
Test status
Simulation time 29721721 ps
CPU time 0.74 seconds
Started Jan 10 12:59:20 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 199244 kb
Host smart-1c069330-2af0-485a-960b-59f13c73d810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702710769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.2702710769
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2787928774
Short name T34
Test name
Test status
Simulation time 17483929 ps
CPU time 0.65 seconds
Started Jan 10 12:59:21 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 199080 kb
Host smart-fd04155b-179d-4842-8e1c-4025fc104275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787928774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.2787928774
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1902242161
Short name T219
Test name
Test status
Simulation time 38308038 ps
CPU time 0.69 seconds
Started Jan 10 12:59:22 PM PST 24
Finished Jan 10 01:00:57 PM PST 24
Peak memory 199072 kb
Host smart-7bc6462b-ea39-44f1-9a17-d4990205d359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902242161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.1902242161
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.3823948969
Short name T173
Test name
Test status
Simulation time 14026253 ps
CPU time 0.69 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 198888 kb
Host smart-2fc40a02-635e-4a62-a5e1-ac08153bb85e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823948969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.3823948969
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.604185212
Short name T164
Test name
Test status
Simulation time 250474859 ps
CPU time 1.61 seconds
Started Jan 10 12:59:11 PM PST 24
Finished Jan 10 01:00:48 PM PST 24
Peak memory 200672 kb
Host smart-0167b5bd-c108-4323-8003-0dc61753e716
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604185212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_aliasing.604185212
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1530813076
Short name T272
Test name
Test status
Simulation time 440331391 ps
CPU time 8.25 seconds
Started Jan 10 12:59:10 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 200732 kb
Host smart-6cc96604-43f9-4167-a602-69a4f268233d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530813076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.1530813076
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.972823267
Short name T79
Test name
Test status
Simulation time 14141541 ps
CPU time 0.71 seconds
Started Jan 10 12:59:23 PM PST 24
Finished Jan 10 01:00:57 PM PST 24
Peak memory 200444 kb
Host smart-9ada1ccf-6ebc-4ba3-9bf6-943dee75c8ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972823267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_hw_reset.972823267
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.540361037
Short name T127
Test name
Test status
Simulation time 26959328 ps
CPU time 0.96 seconds
Started Jan 10 12:59:08 PM PST 24
Finished Jan 10 01:00:43 PM PST 24
Peak memory 200808 kb
Host smart-5a5a39c0-d1bf-4326-a774-a43bfe0230f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540361037 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.540361037
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2022694706
Short name T252
Test name
Test status
Simulation time 60187003 ps
CPU time 0.84 seconds
Started Jan 10 12:59:20 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 200708 kb
Host smart-88048a4e-078e-448b-9379-30d426b2ba80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022694706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.2022694706
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.3741014583
Short name T176
Test name
Test status
Simulation time 33678361 ps
CPU time 0.67 seconds
Started Jan 10 12:59:06 PM PST 24
Finished Jan 10 01:00:40 PM PST 24
Peak memory 199024 kb
Host smart-91c9b008-5b48-40eb-a66d-854a6a1fadfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741014583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.3741014583
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2562158234
Short name T50
Test name
Test status
Simulation time 184857114 ps
CPU time 1.66 seconds
Started Jan 10 12:59:06 PM PST 24
Finished Jan 10 01:00:41 PM PST 24
Peak memory 200912 kb
Host smart-3f0cc7a8-d7e4-4817-9f87-1f0faf87b756
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562158234 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.2562158234
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.4194862806
Short name T47
Test name
Test status
Simulation time 233179446 ps
CPU time 1.95 seconds
Started Jan 10 12:58:59 PM PST 24
Finished Jan 10 01:00:33 PM PST 24
Peak memory 201152 kb
Host smart-52f5f53a-00f7-433f-8039-f1f266d5f118
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194862806 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.4194862806
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2575636331
Short name T223
Test name
Test status
Simulation time 500264646 ps
CPU time 3.51 seconds
Started Jan 10 12:59:05 PM PST 24
Finished Jan 10 01:00:46 PM PST 24
Peak memory 209412 kb
Host smart-c41303c2-b7aa-414a-9ca3-1e3db66b8088
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575636331 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.2575636331
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1589959823
Short name T77
Test name
Test status
Simulation time 98992174 ps
CPU time 1.78 seconds
Started Jan 10 12:59:07 PM PST 24
Finished Jan 10 01:00:42 PM PST 24
Peak memory 200976 kb
Host smart-af6be5bf-49f3-49c7-8c86-7b81857dfb93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589959823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.1589959823
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1365344432
Short name T268
Test name
Test status
Simulation time 466702336 ps
CPU time 3.53 seconds
Started Jan 10 12:59:12 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 200916 kb
Host smart-3d89fe0d-8983-4e14-a332-f8e095fad98d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365344432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.1365344432
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.3418144993
Short name T260
Test name
Test status
Simulation time 16893464 ps
CPU time 0.67 seconds
Started Jan 10 12:59:40 PM PST 24
Finished Jan 10 01:01:12 PM PST 24
Peak memory 199056 kb
Host smart-67077f11-eab5-4316-9de8-c082dda7c6a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418144993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.3418144993
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1777787520
Short name T250
Test name
Test status
Simulation time 16648852 ps
CPU time 0.66 seconds
Started Jan 10 12:59:32 PM PST 24
Finished Jan 10 01:01:04 PM PST 24
Peak memory 199052 kb
Host smart-56e9b166-2574-40b1-a19e-263b766f00f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777787520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.1777787520
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.551608397
Short name T120
Test name
Test status
Simulation time 15516187 ps
CPU time 0.66 seconds
Started Jan 10 12:59:29 PM PST 24
Finished Jan 10 01:01:01 PM PST 24
Peak memory 199076 kb
Host smart-ae93936f-707e-4860-a2d2-31237a378fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551608397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clk
mgr_intr_test.551608397
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2057559161
Short name T37
Test name
Test status
Simulation time 12096921 ps
CPU time 0.63 seconds
Started Jan 10 12:59:32 PM PST 24
Finished Jan 10 01:01:03 PM PST 24
Peak memory 198836 kb
Host smart-9f9eb11c-3325-4be3-95d8-8c79b2955000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057559161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.2057559161
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.518330255
Short name T157
Test name
Test status
Simulation time 20436244 ps
CPU time 0.7 seconds
Started Jan 10 12:59:29 PM PST 24
Finished Jan 10 01:01:01 PM PST 24
Peak memory 199156 kb
Host smart-47ef705a-1155-4c7b-92bf-d9d47880effc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518330255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clk
mgr_intr_test.518330255
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1444813364
Short name T241
Test name
Test status
Simulation time 34770875 ps
CPU time 0.69 seconds
Started Jan 10 12:59:30 PM PST 24
Finished Jan 10 01:01:14 PM PST 24
Peak memory 199124 kb
Host smart-e1a4355d-e04b-4902-bfbe-c181e5647953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444813364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.1444813364
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1372024514
Short name T229
Test name
Test status
Simulation time 22241626 ps
CPU time 1.05 seconds
Started Jan 10 12:59:06 PM PST 24
Finished Jan 10 01:00:43 PM PST 24
Peak memory 200652 kb
Host smart-5ca99636-3095-43cd-87d3-d2b6234c10d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372024514 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1372024514
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2638355388
Short name T195
Test name
Test status
Simulation time 15457779 ps
CPU time 0.77 seconds
Started Jan 10 12:59:06 PM PST 24
Finished Jan 10 01:00:39 PM PST 24
Peak memory 200688 kb
Host smart-dfb32353-9765-41a2-ad4f-f244774534a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638355388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.2638355388
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.905064668
Short name T183
Test name
Test status
Simulation time 36033494 ps
CPU time 0.72 seconds
Started Jan 10 12:59:10 PM PST 24
Finished Jan 10 01:00:46 PM PST 24
Peak memory 198744 kb
Host smart-b7576458-b11f-4cf6-90f4-311b936f5286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905064668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm
gr_intr_test.905064668
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1059835667
Short name T174
Test name
Test status
Simulation time 385340372 ps
CPU time 1.73 seconds
Started Jan 10 12:59:19 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 200672 kb
Host smart-bd11e904-7e8b-4f56-a305-b5060875f0e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059835667 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.1059835667
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3842055859
Short name T212
Test name
Test status
Simulation time 124535287 ps
CPU time 1.93 seconds
Started Jan 10 12:59:05 PM PST 24
Finished Jan 10 01:00:44 PM PST 24
Peak memory 201156 kb
Host smart-3885629c-1a7e-4081-81b4-9ef7b8992496
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842055859 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.3842055859
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1814279980
Short name T90
Test name
Test status
Simulation time 244742487 ps
CPU time 2.62 seconds
Started Jan 10 12:59:01 PM PST 24
Finished Jan 10 01:00:41 PM PST 24
Peak memory 217600 kb
Host smart-c2730e5e-9277-4845-958f-0f9220a76e5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814279980 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.1814279980
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1807248709
Short name T247
Test name
Test status
Simulation time 473621955 ps
CPU time 4.31 seconds
Started Jan 10 12:59:07 PM PST 24
Finished Jan 10 01:00:45 PM PST 24
Peak memory 200948 kb
Host smart-a833f580-e611-414d-b3a9-af80b830ea30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807248709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.1807248709
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1419718707
Short name T95
Test name
Test status
Simulation time 78129469 ps
CPU time 1.77 seconds
Started Jan 10 12:59:21 PM PST 24
Finished Jan 10 01:01:03 PM PST 24
Peak memory 201024 kb
Host smart-f553a109-9b50-43c2-b494-9133d94f8bee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419718707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.1419718707
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.592972768
Short name T189
Test name
Test status
Simulation time 107850790 ps
CPU time 1.07 seconds
Started Jan 10 12:59:09 PM PST 24
Finished Jan 10 01:00:43 PM PST 24
Peak memory 200708 kb
Host smart-8ce956d9-5f8d-4845-90f4-769059a32680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592972768 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.592972768
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.148325020
Short name T277
Test name
Test status
Simulation time 34082397 ps
CPU time 0.82 seconds
Started Jan 10 12:59:09 PM PST 24
Finished Jan 10 01:00:45 PM PST 24
Peak memory 200700 kb
Host smart-9ee5ecbb-35a5-4043-824f-4b881e9d0a75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148325020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.c
lkmgr_csr_rw.148325020
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3557317834
Short name T254
Test name
Test status
Simulation time 15875888 ps
CPU time 0.65 seconds
Started Jan 10 12:59:32 PM PST 24
Finished Jan 10 01:01:04 PM PST 24
Peak memory 199140 kb
Host smart-ff803322-00be-4c09-8386-e9359336dcf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557317834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.3557317834
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1750139080
Short name T158
Test name
Test status
Simulation time 103370675 ps
CPU time 1.33 seconds
Started Jan 10 12:59:06 PM PST 24
Finished Jan 10 01:00:40 PM PST 24
Peak memory 200936 kb
Host smart-c44ff6a3-689d-44fd-b962-a996347cede9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750139080 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.1750139080
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1315685355
Short name T122
Test name
Test status
Simulation time 42670868 ps
CPU time 1.07 seconds
Started Jan 10 12:59:10 PM PST 24
Finished Jan 10 01:00:47 PM PST 24
Peak memory 200612 kb
Host smart-ab327d77-ac6a-47b6-b045-337cd44b39b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315685355 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.1315685355
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1729197630
Short name T222
Test name
Test status
Simulation time 155694518 ps
CPU time 1.92 seconds
Started Jan 10 12:59:05 PM PST 24
Finished Jan 10 01:00:44 PM PST 24
Peak memory 209420 kb
Host smart-0ed63317-4283-44b1-8134-f5c04ed3f0e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729197630 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.1729197630
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.1119735921
Short name T258
Test name
Test status
Simulation time 333238509 ps
CPU time 3.8 seconds
Started Jan 10 12:59:04 PM PST 24
Finished Jan 10 01:00:40 PM PST 24
Peak memory 200960 kb
Host smart-50d2f0ab-9b7e-433a-a7f0-6a477264f820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119735921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.1119735921
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3755043234
Short name T140
Test name
Test status
Simulation time 118885507 ps
CPU time 2.5 seconds
Started Jan 10 12:59:15 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 200888 kb
Host smart-54c5ffef-78f9-44a8-9bab-26071859b97d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755043234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.3755043234
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1544527780
Short name T186
Test name
Test status
Simulation time 50093631 ps
CPU time 0.89 seconds
Started Jan 10 12:59:07 PM PST 24
Finished Jan 10 01:00:41 PM PST 24
Peak memory 200820 kb
Host smart-16b3e313-e11f-4a0a-b194-5fef2f029a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544527780 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1544527780
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.2519422422
Short name T86
Test name
Test status
Simulation time 18082413 ps
CPU time 0.78 seconds
Started Jan 10 12:59:05 PM PST 24
Finished Jan 10 01:00:43 PM PST 24
Peak memory 200648 kb
Host smart-292d1c7e-6203-4393-b3b8-c1b7af51f996
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519422422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.2519422422
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3807977615
Short name T271
Test name
Test status
Simulation time 24475750 ps
CPU time 0.68 seconds
Started Jan 10 12:59:38 PM PST 24
Finished Jan 10 01:01:16 PM PST 24
Peak memory 199084 kb
Host smart-bfe24673-c310-4d53-9126-4445b9713cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807977615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.3807977615
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2705595718
Short name T211
Test name
Test status
Simulation time 185492469 ps
CPU time 1.68 seconds
Started Jan 10 12:59:09 PM PST 24
Finished Jan 10 01:00:44 PM PST 24
Peak memory 200964 kb
Host smart-e4aab579-3f2a-44e4-a313-46fc12c18c33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705595718 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.2705595718
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3105264447
Short name T70
Test name
Test status
Simulation time 129830730 ps
CPU time 1.95 seconds
Started Jan 10 12:59:05 PM PST 24
Finished Jan 10 01:00:39 PM PST 24
Peak memory 217192 kb
Host smart-1ef208cf-50d0-4afb-8241-7691a68e7ba6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105264447 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.3105264447
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.553590985
Short name T274
Test name
Test status
Simulation time 36863474 ps
CPU time 1.3 seconds
Started Jan 10 12:59:21 PM PST 24
Finished Jan 10 01:00:56 PM PST 24
Peak memory 200984 kb
Host smart-aa802961-0b69-4742-a932-be0e58cf753d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553590985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm
gr_tl_errors.553590985
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.536215149
Short name T261
Test name
Test status
Simulation time 192293648 ps
CPU time 1.57 seconds
Started Jan 10 12:59:08 PM PST 24
Finished Jan 10 01:00:44 PM PST 24
Peak memory 200740 kb
Host smart-135f7fd5-d41d-438b-a843-b405f08e5b6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536215149 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.536215149
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.2585851499
Short name T81
Test name
Test status
Simulation time 34786371 ps
CPU time 0.77 seconds
Started Jan 10 12:59:35 PM PST 24
Finished Jan 10 01:01:16 PM PST 24
Peak memory 200632 kb
Host smart-7dde2764-eb8c-4514-8487-2a5904abf237
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585851499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.2585851499
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1487487592
Short name T214
Test name
Test status
Simulation time 14088882 ps
CPU time 0.67 seconds
Started Jan 10 12:59:07 PM PST 24
Finished Jan 10 01:00:40 PM PST 24
Peak memory 199044 kb
Host smart-bb58236e-2b56-45b7-9449-9db8296b16ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487487592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.1487487592
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.224633036
Short name T180
Test name
Test status
Simulation time 70118194 ps
CPU time 1.04 seconds
Started Jan 10 12:59:09 PM PST 24
Finished Jan 10 01:00:44 PM PST 24
Peak memory 200704 kb
Host smart-640113d4-a64e-49ed-9152-2f3247806aae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224633036 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.clkmgr_same_csr_outstanding.224633036
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.3253242190
Short name T123
Test name
Test status
Simulation time 1114070952 ps
CPU time 4.32 seconds
Started Jan 10 12:59:06 PM PST 24
Finished Jan 10 01:00:45 PM PST 24
Peak memory 216960 kb
Host smart-7a591f52-2b9c-4066-91b2-deaf97f31eb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253242190 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.3253242190
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2431308706
Short name T244
Test name
Test status
Simulation time 86198692 ps
CPU time 1.75 seconds
Started Jan 10 12:59:14 PM PST 24
Finished Jan 10 01:00:50 PM PST 24
Peak memory 209456 kb
Host smart-ba65d298-fdc6-4c5f-9889-955006c00132
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431308706 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.2431308706
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1566060002
Short name T92
Test name
Test status
Simulation time 123192195 ps
CPU time 1.63 seconds
Started Jan 10 12:59:07 PM PST 24
Finished Jan 10 01:00:41 PM PST 24
Peak memory 200844 kb
Host smart-a13b2219-cd57-4730-a58f-8c67caab0c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566060002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.1566060002
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.374955873
Short name T163
Test name
Test status
Simulation time 64691283 ps
CPU time 1.21 seconds
Started Jan 10 12:59:13 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 200808 kb
Host smart-a14c08e6-234b-44ce-9778-59e6e2c0c53d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374955873 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.374955873
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3857141024
Short name T266
Test name
Test status
Simulation time 82230335 ps
CPU time 0.88 seconds
Started Jan 10 12:59:20 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 200560 kb
Host smart-6170f958-d2fe-40a6-8fa4-32e29d3a6b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857141024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.3857141024
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1041225277
Short name T208
Test name
Test status
Simulation time 18523432 ps
CPU time 0.66 seconds
Started Jan 10 12:59:15 PM PST 24
Finished Jan 10 01:00:50 PM PST 24
Peak memory 199072 kb
Host smart-6d954dc9-7991-4df5-b99a-4a13ea6afc21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041225277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.1041225277
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1666915997
Short name T255
Test name
Test status
Simulation time 186115118 ps
CPU time 1.68 seconds
Started Jan 10 12:59:10 PM PST 24
Finished Jan 10 01:00:45 PM PST 24
Peak memory 200988 kb
Host smart-a4bf5904-6abb-4202-95bf-00a472eabc01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666915997 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.1666915997
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.1309544769
Short name T115
Test name
Test status
Simulation time 328515572 ps
CPU time 2.55 seconds
Started Jan 10 12:59:13 PM PST 24
Finished Jan 10 01:00:49 PM PST 24
Peak memory 201200 kb
Host smart-9ccde13f-1ca9-41a0-afd0-ddfe1cb61124
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309544769 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.1309544769
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3617571017
Short name T243
Test name
Test status
Simulation time 120163412 ps
CPU time 1.73 seconds
Started Jan 10 12:59:10 PM PST 24
Finished Jan 10 01:00:46 PM PST 24
Peak memory 201232 kb
Host smart-2e075ecd-a161-4bcf-897b-42924d12f581
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617571017 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.3617571017
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2548745647
Short name T215
Test name
Test status
Simulation time 87938745 ps
CPU time 2.66 seconds
Started Jan 10 12:59:15 PM PST 24
Finished Jan 10 01:00:52 PM PST 24
Peak memory 200912 kb
Host smart-79cb00b9-5192-4593-a0e5-3dc618a2c260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548745647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.2548745647
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.2826110717
Short name T945
Test name
Test status
Simulation time 12231798 ps
CPU time 0.69 seconds
Started Jan 10 12:39:33 PM PST 24
Finished Jan 10 12:40:03 PM PST 24
Peak memory 200656 kb
Host smart-976ac510-ffc2-49ed-baa7-c5ec17df4cec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826110717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.2826110717
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.3693438324
Short name T409
Test name
Test status
Simulation time 328302525 ps
CPU time 1.96 seconds
Started Jan 10 12:39:26 PM PST 24
Finished Jan 10 12:39:58 PM PST 24
Peak memory 200664 kb
Host smart-3131dc85-89c0-40cf-90fe-64dea3fa3518
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693438324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.3693438324
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.1625626207
Short name T135
Test name
Test status
Simulation time 28600483 ps
CPU time 0.77 seconds
Started Jan 10 12:39:26 PM PST 24
Finished Jan 10 12:39:57 PM PST 24
Peak memory 200844 kb
Host smart-5a951b92-54d1-44d6-beb5-99d16a154ec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625626207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.1625626207
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.3551258930
Short name T600
Test name
Test status
Simulation time 33110895 ps
CPU time 0.83 seconds
Started Jan 10 12:39:27 PM PST 24
Finished Jan 10 12:39:58 PM PST 24
Peak memory 200672 kb
Host smart-1124cbe3-7323-4415-b66d-86235ff287f6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551258930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.3551258930
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.4246380187
Short name T530
Test name
Test status
Simulation time 78244977 ps
CPU time 0.99 seconds
Started Jan 10 12:39:27 PM PST 24
Finished Jan 10 12:39:59 PM PST 24
Peak memory 200648 kb
Host smart-0d9f1d4b-05b6-4e81-90f1-1cc809c739b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246380187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.4246380187
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.3742847135
Short name T888
Test name
Test status
Simulation time 278262545 ps
CPU time 1.59 seconds
Started Jan 10 12:39:33 PM PST 24
Finished Jan 10 12:40:03 PM PST 24
Peak memory 200740 kb
Host smart-18165cd0-6742-4a59-8858-b4a9fa223cf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742847135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.3742847135
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.238715588
Short name T736
Test name
Test status
Simulation time 30082601 ps
CPU time 0.79 seconds
Started Jan 10 12:39:25 PM PST 24
Finished Jan 10 12:39:56 PM PST 24
Peak memory 200612 kb
Host smart-72ac4011-7c82-4495-9dc7-d2050a47c8ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238715588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_idle_intersig_mubi.238715588
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1790073179
Short name T579
Test name
Test status
Simulation time 59897595 ps
CPU time 0.88 seconds
Started Jan 10 12:39:32 PM PST 24
Finished Jan 10 12:40:02 PM PST 24
Peak memory 200564 kb
Host smart-7e0b5cdc-f70a-4494-9f40-3459a17b88d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790073179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.1790073179
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.2742289257
Short name T789
Test name
Test status
Simulation time 42398216 ps
CPU time 0.83 seconds
Started Jan 10 12:39:29 PM PST 24
Finished Jan 10 12:40:00 PM PST 24
Peak memory 200812 kb
Host smart-0d78032e-9dec-4740-937e-a4cefb8edcc5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742289257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_ctrl_intersig_mubi.2742289257
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.1210435924
Short name T687
Test name
Test status
Simulation time 15936579 ps
CPU time 0.74 seconds
Started Jan 10 12:39:35 PM PST 24
Finished Jan 10 12:40:04 PM PST 24
Peak memory 200544 kb
Host smart-92115ce5-1108-4095-9a3d-e3797a4960f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210435924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.1210435924
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.4016044007
Short name T350
Test name
Test status
Simulation time 777396312 ps
CPU time 3.79 seconds
Started Jan 10 12:39:29 PM PST 24
Finished Jan 10 12:40:03 PM PST 24
Peak memory 200964 kb
Host smart-d907a89a-b0f6-42dc-8f4d-d9d462545501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016044007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.4016044007
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.2744460087
Short name T408
Test name
Test status
Simulation time 21635627 ps
CPU time 0.84 seconds
Started Jan 10 12:39:23 PM PST 24
Finished Jan 10 12:39:52 PM PST 24
Peak memory 200696 kb
Host smart-9ba20d30-1766-468d-8db3-a9106c4b7322
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744460087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.2744460087
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.4090911191
Short name T344
Test name
Test status
Simulation time 7157327329 ps
CPU time 34.63 seconds
Started Jan 10 12:39:28 PM PST 24
Finished Jan 10 12:40:33 PM PST 24
Peak memory 201048 kb
Host smart-84349c8a-33ac-4873-9fd9-7c0d04f7811c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090911191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.4090911191
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.732883770
Short name T669
Test name
Test status
Simulation time 13132474722 ps
CPU time 180.11 seconds
Started Jan 10 12:39:29 PM PST 24
Finished Jan 10 12:42:59 PM PST 24
Peak memory 209332 kb
Host smart-0b6d7060-a29f-4a10-b030-4f3d0d45d60c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=732883770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.732883770
Directory /workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.clkmgr_trans.4148149898
Short name T817
Test name
Test status
Simulation time 25211604 ps
CPU time 0.84 seconds
Started Jan 10 12:39:25 PM PST 24
Finished Jan 10 12:39:56 PM PST 24
Peak memory 200812 kb
Host smart-9b7b5daa-144d-4976-87cc-45c3909b4cdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148149898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.4148149898
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.3339181390
Short name T349
Test name
Test status
Simulation time 13171883 ps
CPU time 0.75 seconds
Started Jan 10 12:39:44 PM PST 24
Finished Jan 10 12:40:15 PM PST 24
Peak memory 200712 kb
Host smart-3a6828cc-dcf9-450b-bade-51bd28b7e164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339181390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.3339181390
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.855828183
Short name T883
Test name
Test status
Simulation time 15103887 ps
CPU time 0.76 seconds
Started Jan 10 12:39:26 PM PST 24
Finished Jan 10 12:39:56 PM PST 24
Peak memory 200696 kb
Host smart-59a96353-897f-4ee0-9202-f94934ee7d85
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855828183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.855828183
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.2493307997
Short name T132
Test name
Test status
Simulation time 13546959 ps
CPU time 0.71 seconds
Started Jan 10 12:39:34 PM PST 24
Finished Jan 10 12:40:04 PM PST 24
Peak memory 199588 kb
Host smart-8f250893-f37d-4fb0-a898-36a11e3552d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493307997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.2493307997
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.1703715382
Short name T509
Test name
Test status
Simulation time 21856787 ps
CPU time 0.81 seconds
Started Jan 10 12:39:27 PM PST 24
Finished Jan 10 12:39:58 PM PST 24
Peak memory 200700 kb
Host smart-2dd01979-4a53-43cf-bbd8-654f478190e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703715382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.1703715382
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.3702299826
Short name T934
Test name
Test status
Simulation time 272089225 ps
CPU time 1.54 seconds
Started Jan 10 12:39:27 PM PST 24
Finished Jan 10 12:39:59 PM PST 24
Peak memory 200764 kb
Host smart-a4fc35a6-42a0-4898-a684-a285f6df6127
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702299826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.3702299826
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.1829349935
Short name T840
Test name
Test status
Simulation time 1562748503 ps
CPU time 7.17 seconds
Started Jan 10 12:39:28 PM PST 24
Finished Jan 10 12:40:05 PM PST 24
Peak memory 200736 kb
Host smart-522caa6c-b5fe-4306-ad67-57034067e09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829349935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1829349935
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.584481898
Short name T368
Test name
Test status
Simulation time 1226970315 ps
CPU time 6.59 seconds
Started Jan 10 12:39:25 PM PST 24
Finished Jan 10 12:40:01 PM PST 24
Peak memory 200872 kb
Host smart-63df1a1c-62c0-4fbb-bcbd-409b9b28cfa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584481898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_tim
eout.584481898
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.2995175053
Short name T548
Test name
Test status
Simulation time 307825043 ps
CPU time 1.71 seconds
Started Jan 10 12:39:41 PM PST 24
Finished Jan 10 12:40:13 PM PST 24
Peak memory 200624 kb
Host smart-6eeca9f5-32af-4890-8893-28c47cc5cbba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995175053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.2995175053
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3093816254
Short name T976
Test name
Test status
Simulation time 16978277 ps
CPU time 0.78 seconds
Started Jan 10 12:39:28 PM PST 24
Finished Jan 10 12:39:59 PM PST 24
Peak memory 200608 kb
Host smart-507ca628-7d49-4665-9d57-28f3c792e84d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093816254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.3093816254
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.358042573
Short name T716
Test name
Test status
Simulation time 85045749 ps
CPU time 1.03 seconds
Started Jan 10 12:39:41 PM PST 24
Finished Jan 10 12:40:12 PM PST 24
Peak memory 200648 kb
Host smart-a714bdf7-9342-4e65-8887-d1ccf4f82d65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358042573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.clkmgr_lc_ctrl_intersig_mubi.358042573
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.3558079133
Short name T758
Test name
Test status
Simulation time 46922821 ps
CPU time 0.81 seconds
Started Jan 10 12:39:42 PM PST 24
Finished Jan 10 12:40:13 PM PST 24
Peak memory 200380 kb
Host smart-a7a03883-4cd1-401d-ae9f-690fa49dd7f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558079133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.3558079133
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.2646251423
Short name T419
Test name
Test status
Simulation time 713598078 ps
CPU time 3.47 seconds
Started Jan 10 12:39:28 PM PST 24
Finished Jan 10 12:40:02 PM PST 24
Peak memory 200984 kb
Host smart-0d07e360-2081-41cb-af49-26ad8b4a30db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646251423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2646251423
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.2417807497
Short name T55
Test name
Test status
Simulation time 321311007 ps
CPU time 3.38 seconds
Started Jan 10 12:39:40 PM PST 24
Finished Jan 10 12:40:13 PM PST 24
Peak memory 220524 kb
Host smart-3efa4cce-c095-4405-b507-94274a0d3589
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417807497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.2417807497
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.1086632399
Short name T894
Test name
Test status
Simulation time 152712800 ps
CPU time 1.23 seconds
Started Jan 10 12:39:26 PM PST 24
Finished Jan 10 12:39:57 PM PST 24
Peak memory 200808 kb
Host smart-2e0d0b58-edfe-49e6-b233-22319f1a4122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086632399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1086632399
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.3702767229
Short name T442
Test name
Test status
Simulation time 6014696668 ps
CPU time 31.57 seconds
Started Jan 10 12:39:42 PM PST 24
Finished Jan 10 12:40:44 PM PST 24
Peak memory 201144 kb
Host smart-f83be48e-13f1-466f-8a86-03aefdb98c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702767229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.3702767229
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.357082579
Short name T403
Test name
Test status
Simulation time 28596367674 ps
CPU time 497.61 seconds
Started Jan 10 12:39:42 PM PST 24
Finished Jan 10 12:48:29 PM PST 24
Peak memory 217392 kb
Host smart-c1c6b0e9-3092-49ac-aab2-e45ee9d2239c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=357082579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.357082579
Directory /workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.clkmgr_trans.1722522031
Short name T391
Test name
Test status
Simulation time 62643037 ps
CPU time 0.93 seconds
Started Jan 10 12:39:27 PM PST 24
Finished Jan 10 12:39:58 PM PST 24
Peak memory 200772 kb
Host smart-fb967c14-55b7-42b6-8165-115996046a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722522031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.1722522031
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.1944884823
Short name T598
Test name
Test status
Simulation time 34312497 ps
CPU time 0.79 seconds
Started Jan 10 12:40:05 PM PST 24
Finished Jan 10 12:40:50 PM PST 24
Peak memory 200968 kb
Host smart-55617384-f64c-482f-a1e7-7d7accea2158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944884823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.1944884823
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.2593025397
Short name T358
Test name
Test status
Simulation time 21155054 ps
CPU time 0.83 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:40:52 PM PST 24
Peak memory 200704 kb
Host smart-469a3ede-fc94-4924-9d73-bafd1e5a65c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593025397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.2593025397
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.2940781920
Short name T924
Test name
Test status
Simulation time 14376452 ps
CPU time 0.7 seconds
Started Jan 10 12:40:08 PM PST 24
Finished Jan 10 12:40:54 PM PST 24
Peak memory 199668 kb
Host smart-2917d08f-b12c-4877-a63e-5250e0be29f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940781920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.2940781920
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.1598717543
Short name T857
Test name
Test status
Simulation time 14889491 ps
CPU time 0.72 seconds
Started Jan 10 12:40:15 PM PST 24
Finished Jan 10 12:41:03 PM PST 24
Peak memory 200656 kb
Host smart-e3fd6736-e040-47ea-b7cc-86a72ffd56bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598717543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.1598717543
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.2787512045
Short name T346
Test name
Test status
Simulation time 85262944 ps
CPU time 1.02 seconds
Started Jan 10 12:40:07 PM PST 24
Finished Jan 10 12:40:54 PM PST 24
Peak memory 200552 kb
Host smart-121739ab-e46c-4bf0-b6db-6cb52361b4b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787512045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.2787512045
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.2774917966
Short name T642
Test name
Test status
Simulation time 794146674 ps
CPU time 6.1 seconds
Started Jan 10 12:40:01 PM PST 24
Finished Jan 10 12:40:49 PM PST 24
Peak memory 200768 kb
Host smart-97c37d21-615d-4191-8963-cb48eb9fd77a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774917966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.2774917966
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.847259529
Short name T799
Test name
Test status
Simulation time 752315746 ps
CPU time 3.4 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:40:54 PM PST 24
Peak memory 200892 kb
Host smart-97ad75ce-1bec-4c36-8128-52b6796e6191
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847259529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_ti
meout.847259529
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.4206620127
Short name T988
Test name
Test status
Simulation time 34460312 ps
CPU time 1 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:40:49 PM PST 24
Peak memory 200688 kb
Host smart-d03d0f19-fe42-43ae-92ec-e8db0690318a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206620127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.4206620127
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.147030085
Short name T578
Test name
Test status
Simulation time 111642786 ps
CPU time 1.04 seconds
Started Jan 10 12:40:07 PM PST 24
Finished Jan 10 12:40:53 PM PST 24
Peak memory 200648 kb
Host smart-10dc74c0-8ce3-4abc-9c00-c8740fa9f7bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147030085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_clk_byp_req_intersig_mubi.147030085
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.967157732
Short name T779
Test name
Test status
Simulation time 46100789 ps
CPU time 0.94 seconds
Started Jan 10 12:40:05 PM PST 24
Finished Jan 10 12:40:51 PM PST 24
Peak memory 200772 kb
Host smart-64d3f280-fa39-4dfd-be20-048e402c039e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967157732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_ctrl_intersig_mubi.967157732
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.2195246749
Short name T586
Test name
Test status
Simulation time 26038651 ps
CPU time 0.79 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:40:51 PM PST 24
Peak memory 200804 kb
Host smart-5b318c4d-49df-47f2-a3a0-88502d20ebdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195246749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.2195246749
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.3261290705
Short name T148
Test name
Test status
Simulation time 1386507925 ps
CPU time 4.91 seconds
Started Jan 10 12:40:16 PM PST 24
Finished Jan 10 12:41:08 PM PST 24
Peak memory 200860 kb
Host smart-36e3a87f-a4e9-4096-95e7-84336ecfe892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261290705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.3261290705
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.357598893
Short name T298
Test name
Test status
Simulation time 43748381 ps
CPU time 0.83 seconds
Started Jan 10 12:40:21 PM PST 24
Finished Jan 10 12:41:08 PM PST 24
Peak memory 200596 kb
Host smart-68e2c0e6-a700-4a6d-aad9-4cc798acdfc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357598893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.357598893
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.4275121777
Short name T613
Test name
Test status
Simulation time 2337990973 ps
CPU time 16.99 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:41:08 PM PST 24
Peak memory 201140 kb
Host smart-a672908d-786c-4208-9ec3-65df18634fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275121777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.4275121777
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.2928774686
Short name T6
Test name
Test status
Simulation time 60610170 ps
CPU time 0.87 seconds
Started Jan 10 12:40:16 PM PST 24
Finished Jan 10 12:41:04 PM PST 24
Peak memory 200632 kb
Host smart-b2014a38-540b-481c-800b-19becc971ae2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928774686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2928774686
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.4144244423
Short name T965
Test name
Test status
Simulation time 27539929 ps
CPU time 0.77 seconds
Started Jan 10 12:40:18 PM PST 24
Finished Jan 10 12:41:05 PM PST 24
Peak memory 200780 kb
Host smart-141e6890-662a-408e-a0e8-b0300c75b55d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144244423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.4144244423
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.1358262464
Short name T289
Test name
Test status
Simulation time 15975275 ps
CPU time 0.79 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:40:52 PM PST 24
Peak memory 200532 kb
Host smart-3e04bded-ebd0-418e-bf2b-3328b94fa27c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358262464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.1358262464
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.1252460294
Short name T708
Test name
Test status
Simulation time 30782095 ps
CPU time 0.78 seconds
Started Jan 10 12:40:03 PM PST 24
Finished Jan 10 12:40:47 PM PST 24
Peak memory 199664 kb
Host smart-33753091-fed1-4467-8b24-629e0369e62c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252460294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.1252460294
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.3667678760
Short name T813
Test name
Test status
Simulation time 29186324 ps
CPU time 0.89 seconds
Started Jan 10 12:40:15 PM PST 24
Finished Jan 10 12:41:03 PM PST 24
Peak memory 200672 kb
Host smart-9d7150b5-42be-4e5d-b04e-8f6cbc9ade29
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667678760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.3667678760
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.2548043016
Short name T836
Test name
Test status
Simulation time 12874360 ps
CPU time 0.68 seconds
Started Jan 10 12:40:20 PM PST 24
Finished Jan 10 12:41:08 PM PST 24
Peak memory 200512 kb
Host smart-8e4d9f5b-c0fa-4228-a301-711dbd1d5ca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548043016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2548043016
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.2282102285
Short name T12
Test name
Test status
Simulation time 2011967582 ps
CPU time 9.11 seconds
Started Jan 10 12:40:15 PM PST 24
Finished Jan 10 12:41:11 PM PST 24
Peak memory 200880 kb
Host smart-e63b8b3f-c0b5-4499-b133-5f3815a18c0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282102285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.2282102285
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.3813000281
Short name T608
Test name
Test status
Simulation time 140978769 ps
CPU time 1.3 seconds
Started Jan 10 12:40:03 PM PST 24
Finished Jan 10 12:40:48 PM PST 24
Peak memory 200780 kb
Host smart-a11daf50-1c95-4fd5-a8b1-9fcb08fdd8d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813000281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.3813000281
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2985742112
Short name T630
Test name
Test status
Simulation time 233221055 ps
CPU time 1.47 seconds
Started Jan 10 12:40:16 PM PST 24
Finished Jan 10 12:41:05 PM PST 24
Peak memory 200652 kb
Host smart-8b8016b7-4061-4ba4-9cf4-d9d79ae1a729
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985742112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.2985742112
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1096072793
Short name T453
Test name
Test status
Simulation time 112280435 ps
CPU time 0.98 seconds
Started Jan 10 12:40:08 PM PST 24
Finished Jan 10 12:40:56 PM PST 24
Peak memory 200708 kb
Host smart-def47e4b-0aba-4268-82a5-e8b1bacc8695
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096072793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1096072793
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1002035454
Short name T491
Test name
Test status
Simulation time 53299718 ps
CPU time 1 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:40:49 PM PST 24
Peak memory 200768 kb
Host smart-04e4e0c2-0bd6-42c3-9df4-3d52cbac2ea0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002035454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.1002035454
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.3976323306
Short name T804
Test name
Test status
Simulation time 44238425 ps
CPU time 0.79 seconds
Started Jan 10 12:40:22 PM PST 24
Finished Jan 10 12:41:09 PM PST 24
Peak memory 200564 kb
Host smart-c9b937b3-bd96-461b-940d-53da892dfb89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976323306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.3976323306
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.3354808039
Short name T56
Test name
Test status
Simulation time 674666956 ps
CPU time 3.87 seconds
Started Jan 10 12:40:28 PM PST 24
Finished Jan 10 12:41:17 PM PST 24
Peak memory 200860 kb
Host smart-3916646a-c4dc-4de5-b89f-d270d1e5d5e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354808039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.3354808039
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.3729046604
Short name T785
Test name
Test status
Simulation time 18748043 ps
CPU time 0.81 seconds
Started Jan 10 12:40:20 PM PST 24
Finished Jan 10 12:41:08 PM PST 24
Peak memory 200480 kb
Host smart-91e975dc-857e-43e9-8a86-4da63e0a7191
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729046604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.3729046604
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.2209825439
Short name T891
Test name
Test status
Simulation time 391460119 ps
CPU time 3.7 seconds
Started Jan 10 12:40:15 PM PST 24
Finished Jan 10 12:41:06 PM PST 24
Peak memory 200692 kb
Host smart-368b879a-2507-4092-9378-aeedcb72cbf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209825439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.2209825439
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.4184988218
Short name T761
Test name
Test status
Simulation time 92843255187 ps
CPU time 658.05 seconds
Started Jan 10 12:40:18 PM PST 24
Finished Jan 10 12:52:03 PM PST 24
Peak memory 217448 kb
Host smart-35cd2a17-2df8-4efc-8e0b-875ee534e171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4184988218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.4184988218
Directory /workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.clkmgr_trans.42524055
Short name T430
Test name
Test status
Simulation time 109450990 ps
CPU time 1.21 seconds
Started Jan 10 12:40:10 PM PST 24
Finished Jan 10 12:40:58 PM PST 24
Peak memory 200708 kb
Host smart-3f803d43-a495-41fc-8100-119c8d69dc4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42524055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.42524055
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.1977334219
Short name T829
Test name
Test status
Simulation time 46984463 ps
CPU time 0.84 seconds
Started Jan 10 12:40:21 PM PST 24
Finished Jan 10 12:41:08 PM PST 24
Peak memory 200736 kb
Host smart-0347f5fe-4136-4502-9132-4b44f76bb804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977334219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.1977334219
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.2853153635
Short name T878
Test name
Test status
Simulation time 17981847 ps
CPU time 0.75 seconds
Started Jan 10 12:40:26 PM PST 24
Finished Jan 10 12:41:13 PM PST 24
Peak memory 200600 kb
Host smart-7de6f0dc-92f1-4233-96bf-32ae4e0a7707
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853153635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.2853153635
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.1546456551
Short name T520
Test name
Test status
Simulation time 57645278 ps
CPU time 0.8 seconds
Started Jan 10 12:40:17 PM PST 24
Finished Jan 10 12:41:04 PM PST 24
Peak memory 200648 kb
Host smart-6f85784b-eec1-4bf2-b7a0-9a9e6251f8a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546456551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.1546456551
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.3430710540
Short name T347
Test name
Test status
Simulation time 43501394 ps
CPU time 0.79 seconds
Started Jan 10 12:40:16 PM PST 24
Finished Jan 10 12:41:05 PM PST 24
Peak memory 200656 kb
Host smart-6d3d4e6c-e444-4215-a79a-28d5db444e5f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430710540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.3430710540
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.703345818
Short name T110
Test name
Test status
Simulation time 31571959 ps
CPU time 0.83 seconds
Started Jan 10 12:40:29 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 200672 kb
Host smart-8b2176a8-6ec9-41c8-904f-eef2b7a10ca0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703345818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.703345818
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.1121851702
Short name T740
Test name
Test status
Simulation time 1490402840 ps
CPU time 6.28 seconds
Started Jan 10 12:40:13 PM PST 24
Finished Jan 10 12:41:06 PM PST 24
Peak memory 200816 kb
Host smart-2baf1571-eecb-47fc-a5fa-44d5bf3ec810
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121851702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.1121851702
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.2690682372
Short name T670
Test name
Test status
Simulation time 1941854318 ps
CPU time 14.59 seconds
Started Jan 10 12:40:19 PM PST 24
Finished Jan 10 12:41:21 PM PST 24
Peak memory 200876 kb
Host smart-fc50f8af-48ba-4e82-9bde-1a0f65bddfe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690682372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.2690682372
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.3845486330
Short name T900
Test name
Test status
Simulation time 32097059 ps
CPU time 0.95 seconds
Started Jan 10 12:40:29 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 200720 kb
Host smart-6abfb535-c01e-4fe5-8f2f-7f916dbfbbcd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845486330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.3845486330
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.2395484951
Short name T743
Test name
Test status
Simulation time 30630372 ps
CPU time 0.78 seconds
Started Jan 10 12:40:28 PM PST 24
Finished Jan 10 12:41:14 PM PST 24
Peak memory 200724 kb
Host smart-e89a31b4-34bb-4de1-8e5a-a9796db10242
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395484951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_clk_byp_req_intersig_mubi.2395484951
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1742914327
Short name T899
Test name
Test status
Simulation time 34656436 ps
CPU time 0.78 seconds
Started Jan 10 12:40:16 PM PST 24
Finished Jan 10 12:41:04 PM PST 24
Peak memory 200820 kb
Host smart-c2003469-c757-4d52-9838-5b3830d098c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742914327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.1742914327
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.241339889
Short name T914
Test name
Test status
Simulation time 12856344 ps
CPU time 0.7 seconds
Started Jan 10 12:40:29 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 200584 kb
Host smart-572c5f01-a9ee-44c9-acc3-355ac64e03d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241339889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.241339889
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.1717978749
Short name T402
Test name
Test status
Simulation time 1321850955 ps
CPU time 7.77 seconds
Started Jan 10 12:40:17 PM PST 24
Finished Jan 10 12:41:12 PM PST 24
Peak memory 200844 kb
Host smart-c4742a49-8f32-434b-bba4-e632f62c2774
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717978749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.1717978749
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.2026761623
Short name T511
Test name
Test status
Simulation time 92150060 ps
CPU time 1.02 seconds
Started Jan 10 12:40:18 PM PST 24
Finished Jan 10 12:41:06 PM PST 24
Peak memory 200664 kb
Host smart-2c79d3de-2778-4b93-82dc-02c3a6302d51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026761623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2026761623
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.4233156348
Short name T749
Test name
Test status
Simulation time 12880085961 ps
CPU time 52.91 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:42:22 PM PST 24
Peak memory 200988 kb
Host smart-306c80e6-2fe7-45c2-98d2-d88deba96be4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233156348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.4233156348
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.3146403912
Short name T667
Test name
Test status
Simulation time 119029593620 ps
CPU time 1132.81 seconds
Started Jan 10 12:40:14 PM PST 24
Finished Jan 10 12:59:54 PM PST 24
Peak memory 217516 kb
Host smart-60c30645-c827-4e3c-aa11-10332028df3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3146403912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.3146403912
Directory /workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.clkmgr_trans.1161116082
Short name T505
Test name
Test status
Simulation time 39911893 ps
CPU time 0.91 seconds
Started Jan 10 12:40:17 PM PST 24
Finished Jan 10 12:41:05 PM PST 24
Peak memory 200812 kb
Host smart-64e9feb8-a129-4fc1-b719-650c2f808307
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161116082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1161116082
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.639076357
Short name T63
Test name
Test status
Simulation time 15475775 ps
CPU time 0.72 seconds
Started Jan 10 12:40:36 PM PST 24
Finished Jan 10 12:41:21 PM PST 24
Peak memory 200576 kb
Host smart-12c37daa-32eb-435e-86d2-bed52993150f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639076357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.639076357
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.3731583967
Short name T831
Test name
Test status
Simulation time 16763417 ps
CPU time 0.75 seconds
Started Jan 10 12:40:23 PM PST 24
Finished Jan 10 12:41:11 PM PST 24
Peak memory 199648 kb
Host smart-a4680014-be4f-449c-9d82-17218fc666ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731583967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3731583967
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.1289381697
Short name T701
Test name
Test status
Simulation time 14647051 ps
CPU time 0.7 seconds
Started Jan 10 12:40:42 PM PST 24
Finished Jan 10 12:41:28 PM PST 24
Peak memory 200628 kb
Host smart-a4ae715d-8b37-4c7a-9488-33f67cfbe2ca
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289381697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.1289381697
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.719531648
Short name T923
Test name
Test status
Simulation time 19231964 ps
CPU time 0.84 seconds
Started Jan 10 12:40:22 PM PST 24
Finished Jan 10 12:41:09 PM PST 24
Peak memory 200492 kb
Host smart-87adacb6-6efe-4117-8882-357f68eb2e80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719531648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.719531648
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.1399745023
Short name T835
Test name
Test status
Simulation time 936037194 ps
CPU time 3.87 seconds
Started Jan 10 12:40:26 PM PST 24
Finished Jan 10 12:41:16 PM PST 24
Peak memory 200816 kb
Host smart-b1c8e4d7-5ff8-485d-9125-3ddce9e94e51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399745023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.1399745023
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.3229544130
Short name T792
Test name
Test status
Simulation time 980407943 ps
CPU time 7.9 seconds
Started Jan 10 12:40:25 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 201068 kb
Host smart-53dffdb1-8849-44de-aa78-96c1e1f7ba34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229544130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.3229544130
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.326949705
Short name T830
Test name
Test status
Simulation time 100960854 ps
CPU time 0.93 seconds
Started Jan 10 12:40:27 PM PST 24
Finished Jan 10 12:41:14 PM PST 24
Peak memory 200668 kb
Host smart-435efa91-ee86-49c0-93a8-9c00b5736b97
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326949705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.clkmgr_idle_intersig_mubi.326949705
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.435440060
Short name T565
Test name
Test status
Simulation time 35124706 ps
CPU time 0.77 seconds
Started Jan 10 12:40:24 PM PST 24
Finished Jan 10 12:41:11 PM PST 24
Peak memory 200740 kb
Host smart-0237ae74-717f-49da-9a8c-3ad87235a837
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435440060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_clk_byp_req_intersig_mubi.435440060
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.1854683465
Short name T103
Test name
Test status
Simulation time 141776029 ps
CPU time 1.14 seconds
Started Jan 10 12:40:27 PM PST 24
Finished Jan 10 12:41:14 PM PST 24
Peak memory 200840 kb
Host smart-b0e29cdf-90ff-4711-b8a2-db581ff21693
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854683465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.1854683465
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.1023761844
Short name T685
Test name
Test status
Simulation time 52442325 ps
CPU time 0.86 seconds
Started Jan 10 12:40:27 PM PST 24
Finished Jan 10 12:41:13 PM PST 24
Peak memory 200760 kb
Host smart-4c7dc8d2-d90b-476e-ac5f-b09f4953f24c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023761844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.1023761844
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.3670573277
Short name T803
Test name
Test status
Simulation time 962142868 ps
CPU time 3.6 seconds
Started Jan 10 12:40:28 PM PST 24
Finished Jan 10 12:41:17 PM PST 24
Peak memory 200928 kb
Host smart-1980b2fe-f542-4637-bd7a-75f073601d49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670573277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3670573277
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.2609105120
Short name T679
Test name
Test status
Simulation time 82061491 ps
CPU time 0.99 seconds
Started Jan 10 12:40:23 PM PST 24
Finished Jan 10 12:41:11 PM PST 24
Peak memory 200764 kb
Host smart-eb728b84-4843-4c82-b95a-a71875bf0f35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609105120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2609105120
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.1875276110
Short name T745
Test name
Test status
Simulation time 21110819117 ps
CPU time 381.93 seconds
Started Jan 10 12:40:25 PM PST 24
Finished Jan 10 12:47:33 PM PST 24
Peak memory 209332 kb
Host smart-0ccb5f12-6c34-4c2e-95f3-9644e12c9fda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1875276110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.1875276110
Directory /workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.clkmgr_trans.4013340708
Short name T866
Test name
Test status
Simulation time 100397222 ps
CPU time 1.14 seconds
Started Jan 10 12:40:25 PM PST 24
Finished Jan 10 12:41:12 PM PST 24
Peak memory 200760 kb
Host smart-2bd2477b-10ed-4c86-9236-18423d196103
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013340708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.4013340708
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.4091921538
Short name T775
Test name
Test status
Simulation time 22419273 ps
CPU time 0.74 seconds
Started Jan 10 12:40:49 PM PST 24
Finished Jan 10 12:41:37 PM PST 24
Peak memory 200644 kb
Host smart-e9f8983e-d2fa-4c4e-a4c5-abe6800d2290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091921538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.4091921538
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.2001885911
Short name T788
Test name
Test status
Simulation time 99624638 ps
CPU time 1.1 seconds
Started Jan 10 12:40:27 PM PST 24
Finished Jan 10 12:41:14 PM PST 24
Peak memory 200764 kb
Host smart-b59b5c7b-fe83-4c1d-a55d-9839734c208a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001885911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.2001885911
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.3845186616
Short name T495
Test name
Test status
Simulation time 68123290 ps
CPU time 0.97 seconds
Started Jan 10 12:40:25 PM PST 24
Finished Jan 10 12:41:12 PM PST 24
Peak memory 200688 kb
Host smart-cb24bba4-7081-478c-8bd1-b6d3baa5608e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845186616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.3845186616
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.3059668345
Short name T335
Test name
Test status
Simulation time 42689756 ps
CPU time 0.82 seconds
Started Jan 10 12:40:32 PM PST 24
Finished Jan 10 12:41:17 PM PST 24
Peak memory 200608 kb
Host smart-4a969ebc-350b-42ab-9940-698460837a70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059668345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3059668345
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.2699313950
Short name T107
Test name
Test status
Simulation time 2503615023 ps
CPU time 11.25 seconds
Started Jan 10 12:40:27 PM PST 24
Finished Jan 10 12:41:24 PM PST 24
Peak memory 201008 kb
Host smart-88fc7f24-0e13-45ce-825e-e5c962edbe79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699313950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.2699313950
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.2062023053
Short name T921
Test name
Test status
Simulation time 658867122 ps
CPU time 2.89 seconds
Started Jan 10 12:40:26 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 200740 kb
Host smart-bbbcb410-9497-4a15-aa5b-93d473f0d502
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062023053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.2062023053
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.1319915083
Short name T514
Test name
Test status
Simulation time 23378371 ps
CPU time 0.85 seconds
Started Jan 10 12:40:25 PM PST 24
Finished Jan 10 12:41:12 PM PST 24
Peak memory 200684 kb
Host smart-68ef6143-d5e1-4386-a3c4-719335fe54e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319915083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.1319915083
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.327916946
Short name T392
Test name
Test status
Simulation time 20199625 ps
CPU time 0.83 seconds
Started Jan 10 12:40:23 PM PST 24
Finished Jan 10 12:41:11 PM PST 24
Peak memory 200776 kb
Host smart-28a23af8-053a-4937-b850-46b010c8a4a7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327916946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_clk_byp_req_intersig_mubi.327916946
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.278232057
Short name T282
Test name
Test status
Simulation time 51972645 ps
CPU time 0.81 seconds
Started Jan 10 12:40:35 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200556 kb
Host smart-a59628b7-6299-468a-b5ed-952c674a4302
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278232057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_ctrl_intersig_mubi.278232057
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.1795064668
Short name T773
Test name
Test status
Simulation time 14725624 ps
CPU time 0.72 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:30 PM PST 24
Peak memory 200612 kb
Host smart-dd6f4bdc-9f78-4285-ad68-bd7a5528665d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795064668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.1795064668
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.1795763342
Short name T582
Test name
Test status
Simulation time 1140362641 ps
CPU time 6.45 seconds
Started Jan 10 12:40:30 PM PST 24
Finished Jan 10 12:41:21 PM PST 24
Peak memory 200980 kb
Host smart-78cd887f-d74f-4f28-a67c-dd24599811d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795763342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.1795763342
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.222918734
Short name T284
Test name
Test status
Simulation time 64956843 ps
CPU time 0.98 seconds
Started Jan 10 12:40:25 PM PST 24
Finished Jan 10 12:41:12 PM PST 24
Peak memory 200744 kb
Host smart-a87904df-7495-446d-8e4a-af18b2c0e33a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222918734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.222918734
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.3883966553
Short name T713
Test name
Test status
Simulation time 8343001835 ps
CPU time 32.83 seconds
Started Jan 10 12:40:27 PM PST 24
Finished Jan 10 12:41:45 PM PST 24
Peak memory 201136 kb
Host smart-c16c02bb-e112-4f36-8045-a01e275ef45a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883966553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.3883966553
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.2694207115
Short name T24
Test name
Test status
Simulation time 8885858313 ps
CPU time 159.32 seconds
Started Jan 10 12:40:25 PM PST 24
Finished Jan 10 12:43:51 PM PST 24
Peak memory 209264 kb
Host smart-3f782c56-bac8-4c66-9b59-1935af233ef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2694207115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.2694207115
Directory /workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.clkmgr_trans.3372300718
Short name T460
Test name
Test status
Simulation time 135944759 ps
CPU time 1.28 seconds
Started Jan 10 12:40:27 PM PST 24
Finished Jan 10 12:41:14 PM PST 24
Peak memory 200680 kb
Host smart-270c8503-a2e2-4930-a84f-c1e290aa2914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372300718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.3372300718
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.380869080
Short name T40
Test name
Test status
Simulation time 36211962 ps
CPU time 0.73 seconds
Started Jan 10 12:40:36 PM PST 24
Finished Jan 10 12:41:20 PM PST 24
Peak memory 200576 kb
Host smart-7ba7894a-2a0e-439c-83fd-8596350a17ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380869080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkm
gr_alert_test.380869080
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.4288963219
Short name T380
Test name
Test status
Simulation time 90719890 ps
CPU time 1.04 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:32 PM PST 24
Peak memory 200628 kb
Host smart-4de6dc07-f665-49c1-9ddf-92cadb4a4d7e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288963219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.4288963219
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.1726022910
Short name T992
Test name
Test status
Simulation time 15181458 ps
CPU time 0.69 seconds
Started Jan 10 12:40:25 PM PST 24
Finished Jan 10 12:41:12 PM PST 24
Peak memory 199544 kb
Host smart-00048e83-4b4c-48a9-b7a4-edbd784304b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726022910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1726022910
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.3589876922
Short name T833
Test name
Test status
Simulation time 23812182 ps
CPU time 0.85 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:33 PM PST 24
Peak memory 200624 kb
Host smart-5181fe0a-00ab-44cb-af68-7ffd528786a8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589876922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.3589876922
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.4219152999
Short name T614
Test name
Test status
Simulation time 42379697 ps
CPU time 0.88 seconds
Started Jan 10 12:40:29 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 200672 kb
Host smart-a91b90c0-d15b-4f51-9d53-4a6524d2695a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219152999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.4219152999
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.1449701746
Short name T448
Test name
Test status
Simulation time 2476161462 ps
CPU time 17.68 seconds
Started Jan 10 12:40:25 PM PST 24
Finished Jan 10 12:41:29 PM PST 24
Peak memory 200976 kb
Host smart-145fa90b-5a41-416c-b02f-a87ff85d3f71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449701746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.1449701746
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.4115898941
Short name T764
Test name
Test status
Simulation time 2417303542 ps
CPU time 16.93 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:49 PM PST 24
Peak memory 200960 kb
Host smart-c7b22a11-2771-4809-9796-126b154f0c2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115898941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.4115898941
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.3115339689
Short name T846
Test name
Test status
Simulation time 75611835 ps
CPU time 0.94 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:30 PM PST 24
Peak memory 200624 kb
Host smart-f8f8678d-82a5-4ec8-acaa-73a8bfcc46e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115339689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.3115339689
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2240942879
Short name T310
Test name
Test status
Simulation time 14928950 ps
CPU time 0.73 seconds
Started Jan 10 12:40:27 PM PST 24
Finished Jan 10 12:41:13 PM PST 24
Peak memory 200760 kb
Host smart-502a82e6-cb35-48e5-a7a1-a4f3a7f18f10
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240942879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.2240942879
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1981291452
Short name T881
Test name
Test status
Simulation time 20223715 ps
CPU time 0.84 seconds
Started Jan 10 12:40:26 PM PST 24
Finished Jan 10 12:41:12 PM PST 24
Peak memory 200592 kb
Host smart-1fbd4845-d061-484a-a481-2f8d4a2361de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981291452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.1981291452
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.4217880943
Short name T365
Test name
Test status
Simulation time 29296766 ps
CPU time 0.72 seconds
Started Jan 10 12:40:32 PM PST 24
Finished Jan 10 12:41:17 PM PST 24
Peak memory 200628 kb
Host smart-ad17e460-da40-49ab-88a1-fb4dc439525d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217880943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.4217880943
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.1787893147
Short name T744
Test name
Test status
Simulation time 197870855 ps
CPU time 1.49 seconds
Started Jan 10 12:40:26 PM PST 24
Finished Jan 10 12:41:13 PM PST 24
Peak memory 200612 kb
Host smart-e6c43d12-fa18-40c4-9097-9358d2bf7795
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787893147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.1787893147
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.499399402
Short name T841
Test name
Test status
Simulation time 21479560 ps
CPU time 0.81 seconds
Started Jan 10 12:40:24 PM PST 24
Finished Jan 10 12:41:11 PM PST 24
Peak memory 200808 kb
Host smart-81fb2b77-2199-47b1-92cb-251c7a9402b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499399402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.499399402
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.3347700569
Short name T958
Test name
Test status
Simulation time 3091768534 ps
CPU time 23.3 seconds
Started Jan 10 12:40:22 PM PST 24
Finished Jan 10 12:41:31 PM PST 24
Peak memory 201028 kb
Host smart-7e5b615b-e135-4498-80b3-6b99d441582a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347700569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.3347700569
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.1667743715
Short name T603
Test name
Test status
Simulation time 86099221575 ps
CPU time 676.73 seconds
Started Jan 10 12:40:41 PM PST 24
Finished Jan 10 12:52:42 PM PST 24
Peak memory 209156 kb
Host smart-e8f30545-c46b-4b90-81b3-3cb067a4d465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1667743715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.1667743715
Directory /workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.clkmgr_trans.2372615332
Short name T417
Test name
Test status
Simulation time 24921595 ps
CPU time 0.84 seconds
Started Jan 10 12:40:34 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200704 kb
Host smart-091cd3a1-4b93-40b2-999d-397ae6742fda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372615332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.2372615332
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.3919995900
Short name T982
Test name
Test status
Simulation time 48946704 ps
CPU time 0.84 seconds
Started Jan 10 12:40:34 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200780 kb
Host smart-e25952b4-a5e6-4e0b-847d-1ae68ef16f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919995900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.3919995900
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.3734322219
Short name T45
Test name
Test status
Simulation time 26583312 ps
CPU time 0.68 seconds
Started Jan 10 12:40:36 PM PST 24
Finished Jan 10 12:41:20 PM PST 24
Peak memory 199420 kb
Host smart-7d3630fd-8f06-4b54-b8a0-00e78daca2cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734322219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.3734322219
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.94860751
Short name T306
Test name
Test status
Simulation time 22313876 ps
CPU time 0.8 seconds
Started Jan 10 12:40:30 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 200724 kb
Host smart-2d48c179-8ea2-422a-bf8c-3b507d49778c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94860751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.clkmgr_div_intersig_mubi.94860751
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.904949532
Short name T860
Test name
Test status
Simulation time 14263189 ps
CPU time 0.71 seconds
Started Jan 10 12:40:38 PM PST 24
Finished Jan 10 12:41:23 PM PST 24
Peak memory 200384 kb
Host smart-3235cc08-17bc-4095-bdfd-d99f388b2da9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904949532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.904949532
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.1587682878
Short name T673
Test name
Test status
Simulation time 2117356101 ps
CPU time 17.04 seconds
Started Jan 10 12:40:26 PM PST 24
Finished Jan 10 12:41:29 PM PST 24
Peak memory 201028 kb
Host smart-122ab0cb-a4f3-4abd-9f5b-0e32eec6c057
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587682878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1587682878
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.4191017113
Short name T555
Test name
Test status
Simulation time 1339782726 ps
CPU time 9.42 seconds
Started Jan 10 12:40:35 PM PST 24
Finished Jan 10 12:41:28 PM PST 24
Peak memory 200684 kb
Host smart-14f9b031-e96b-4a21-8294-c2315bbca3d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191017113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.4191017113
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2186500103
Short name T648
Test name
Test status
Simulation time 46696144 ps
CPU time 0.95 seconds
Started Jan 10 12:40:24 PM PST 24
Finished Jan 10 12:41:11 PM PST 24
Peak memory 200764 kb
Host smart-95a7dfc3-2f56-4f4f-89db-a86de86692be
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186500103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.2186500103
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.2724413003
Short name T540
Test name
Test status
Simulation time 137193930 ps
CPU time 1.08 seconds
Started Jan 10 12:40:29 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 200808 kb
Host smart-8b2ebbca-4074-4c77-b188-0ff1a98c57e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724413003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.2724413003
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.2883148126
Short name T413
Test name
Test status
Simulation time 18431263 ps
CPU time 0.77 seconds
Started Jan 10 12:40:26 PM PST 24
Finished Jan 10 12:41:12 PM PST 24
Peak memory 200780 kb
Host smart-97e5c70a-b4c1-41b8-8965-6ea9d902aa87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883148126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.2883148126
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.3615348728
Short name T543
Test name
Test status
Simulation time 15486732 ps
CPU time 0.71 seconds
Started Jan 10 12:40:35 PM PST 24
Finished Jan 10 12:41:20 PM PST 24
Peak memory 200556 kb
Host smart-085f6eea-2fce-4552-8dbe-18f9ca37aa39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615348728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.3615348728
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.3788604984
Short name T400
Test name
Test status
Simulation time 1927612024 ps
CPU time 6.25 seconds
Started Jan 10 12:40:42 PM PST 24
Finished Jan 10 12:41:34 PM PST 24
Peak memory 200772 kb
Host smart-279123b4-3ddf-4569-b4c2-b1d706bf9ec5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788604984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3788604984
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.807116308
Short name T423
Test name
Test status
Simulation time 24819069 ps
CPU time 0.78 seconds
Started Jan 10 12:40:35 PM PST 24
Finished Jan 10 12:41:20 PM PST 24
Peak memory 200592 kb
Host smart-872c9023-eac9-4057-b59a-747729d85d93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807116308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.807116308
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.3141537291
Short name T580
Test name
Test status
Simulation time 8647766384 ps
CPU time 61.71 seconds
Started Jan 10 12:40:48 PM PST 24
Finished Jan 10 12:42:37 PM PST 24
Peak memory 201088 kb
Host smart-ba85aa3a-252c-442f-9104-63cc63731582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141537291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.3141537291
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.2601662560
Short name T702
Test name
Test status
Simulation time 36849958248 ps
CPU time 661.74 seconds
Started Jan 10 12:40:32 PM PST 24
Finished Jan 10 12:52:18 PM PST 24
Peak memory 211188 kb
Host smart-cc312a42-7a2d-40bc-846f-1f7554dff898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2601662560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.2601662560
Directory /workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.clkmgr_trans.3868114125
Short name T666
Test name
Test status
Simulation time 18109401 ps
CPU time 0.75 seconds
Started Jan 10 12:40:35 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200588 kb
Host smart-6592ef2f-1fb3-43f0-9b11-99ac302cabd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868114125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3868114125
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.637188250
Short name T854
Test name
Test status
Simulation time 15229296 ps
CPU time 0.74 seconds
Started Jan 10 12:40:32 PM PST 24
Finished Jan 10 12:41:17 PM PST 24
Peak memory 200792 kb
Host smart-83f58e5e-aa2b-4984-813a-2c8b86b026c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637188250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkm
gr_alert_test.637188250
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2853722593
Short name T612
Test name
Test status
Simulation time 100518823 ps
CPU time 1.08 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:32 PM PST 24
Peak memory 200644 kb
Host smart-020f440a-08c0-41fc-851e-54058d769172
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853722593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.2853722593
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.702819639
Short name T646
Test name
Test status
Simulation time 73458217 ps
CPU time 0.83 seconds
Started Jan 10 12:40:30 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 199428 kb
Host smart-a5629bcf-8b39-4d0d-8c9d-932a84d9d718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702819639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.702819639
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.1485146098
Short name T534
Test name
Test status
Simulation time 25513984 ps
CPU time 0.82 seconds
Started Jan 10 12:40:49 PM PST 24
Finished Jan 10 12:41:38 PM PST 24
Peak memory 200624 kb
Host smart-34baa97d-f8d5-4a1e-98eb-b0c704b093ce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485146098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.1485146098
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.4257088118
Short name T821
Test name
Test status
Simulation time 30928854 ps
CPU time 0.81 seconds
Started Jan 10 12:40:34 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200728 kb
Host smart-7bfede96-6713-4967-aed1-a926ceee908b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257088118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.4257088118
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.3525440937
Short name T59
Test name
Test status
Simulation time 563421152 ps
CPU time 4.52 seconds
Started Jan 10 12:40:38 PM PST 24
Finished Jan 10 12:41:26 PM PST 24
Peak memory 200620 kb
Host smart-a45306bd-45f6-44ca-80e5-fdf96d3fd63c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525440937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.3525440937
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.372792341
Short name T619
Test name
Test status
Simulation time 2419729676 ps
CPU time 17.43 seconds
Started Jan 10 12:40:45 PM PST 24
Finished Jan 10 12:41:48 PM PST 24
Peak memory 200988 kb
Host smart-89e33239-cb5a-487d-aa9c-2b3248257d15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372792341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_ti
meout.372792341
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.673964634
Short name T931
Test name
Test status
Simulation time 12322608 ps
CPU time 0.66 seconds
Started Jan 10 12:40:51 PM PST 24
Finished Jan 10 12:41:41 PM PST 24
Peak memory 200728 kb
Host smart-ec35b7cd-be4c-4f0c-8165-a2419ba4c740
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673964634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.clkmgr_idle_intersig_mubi.673964634
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.2581467548
Short name T638
Test name
Test status
Simulation time 68432872 ps
CPU time 0.95 seconds
Started Jan 10 12:40:38 PM PST 24
Finished Jan 10 12:41:24 PM PST 24
Peak memory 200692 kb
Host smart-199d5525-cc45-46c5-8cda-ae3ef55af63b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581467548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.2581467548
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.4174252379
Short name T947
Test name
Test status
Simulation time 29729693 ps
CPU time 0.78 seconds
Started Jan 10 12:40:39 PM PST 24
Finished Jan 10 12:41:25 PM PST 24
Peak memory 200556 kb
Host smart-6cf03be8-4b98-4959-a35d-08ae1e10dd15
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174252379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.4174252379
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.2098979105
Short name T466
Test name
Test status
Simulation time 24319967 ps
CPU time 0.73 seconds
Started Jan 10 12:40:34 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200576 kb
Host smart-1e70c949-afaf-4086-8050-bc452d1b90de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098979105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.2098979105
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.2264653485
Short name T718
Test name
Test status
Simulation time 569747866 ps
CPU time 2.62 seconds
Started Jan 10 12:40:38 PM PST 24
Finished Jan 10 12:41:24 PM PST 24
Peak memory 200796 kb
Host smart-14375a0f-0045-49e7-a581-1c02844204b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264653485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.2264653485
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.3289151958
Short name T597
Test name
Test status
Simulation time 15980363 ps
CPU time 0.78 seconds
Started Jan 10 12:40:31 PM PST 24
Finished Jan 10 12:41:16 PM PST 24
Peak memory 200756 kb
Host smart-1b127a54-2952-4e17-a5e3-b922aa90c4a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289151958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3289151958
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.1143821828
Short name T472
Test name
Test status
Simulation time 5744587796 ps
CPU time 22.33 seconds
Started Jan 10 12:40:31 PM PST 24
Finished Jan 10 12:41:38 PM PST 24
Peak memory 201076 kb
Host smart-29d599bc-fd6f-40c3-8d38-4e021c146854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143821828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.1143821828
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.2902368354
Short name T880
Test name
Test status
Simulation time 29893476819 ps
CPU time 266.44 seconds
Started Jan 10 12:40:32 PM PST 24
Finished Jan 10 12:45:43 PM PST 24
Peak memory 209360 kb
Host smart-a02c4e6d-1921-4137-815d-731e32b98a13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2902368354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.2902368354
Directory /workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.clkmgr_trans.362907222
Short name T496
Test name
Test status
Simulation time 53514876 ps
CPU time 0.99 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:30 PM PST 24
Peak memory 200632 kb
Host smart-3a1a9346-effa-4f7b-b790-43d8cfe43335
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362907222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.362907222
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.512615976
Short name T535
Test name
Test status
Simulation time 21107561 ps
CPU time 0.78 seconds
Started Jan 10 12:40:35 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200772 kb
Host smart-53d0fa38-711b-4cd5-8545-40d5a88129c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512615976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkm
gr_alert_test.512615976
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.673235311
Short name T26
Test name
Test status
Simulation time 18978468 ps
CPU time 0.87 seconds
Started Jan 10 12:40:32 PM PST 24
Finished Jan 10 12:41:17 PM PST 24
Peak memory 200972 kb
Host smart-0014863f-1217-43e5-8920-bf9e68ce2711
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673235311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.673235311
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.2982097501
Short name T133
Test name
Test status
Simulation time 16707497 ps
CPU time 0.66 seconds
Started Jan 10 12:40:47 PM PST 24
Finished Jan 10 12:41:36 PM PST 24
Peak memory 199600 kb
Host smart-5bbe0cd3-4978-4c0a-ac1d-ee463e845feb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982097501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.2982097501
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.1826788592
Short name T805
Test name
Test status
Simulation time 114296788 ps
CPU time 1.03 seconds
Started Jan 10 12:40:45 PM PST 24
Finished Jan 10 12:41:32 PM PST 24
Peak memory 200728 kb
Host smart-218862bf-4af0-4155-ac8b-25938cd5c901
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826788592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.1826788592
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.1915516348
Short name T386
Test name
Test status
Simulation time 249840361 ps
CPU time 1.55 seconds
Started Jan 10 12:40:34 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200660 kb
Host smart-60d28c87-eaaa-4de2-8693-816103dfa63e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915516348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.1915516348
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.1348661661
Short name T810
Test name
Test status
Simulation time 1844643275 ps
CPU time 8.39 seconds
Started Jan 10 12:40:45 PM PST 24
Finished Jan 10 12:41:39 PM PST 24
Peak memory 200812 kb
Host smart-52b9634b-8b18-4515-b426-def3b8b7ecf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348661661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1348661661
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.1699630289
Short name T896
Test name
Test status
Simulation time 1828770809 ps
CPU time 9.39 seconds
Started Jan 10 12:40:39 PM PST 24
Finished Jan 10 12:41:33 PM PST 24
Peak memory 200768 kb
Host smart-c8121e0c-3c08-4f64-87c1-88bf5da908d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699630289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.1699630289
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2394737607
Short name T678
Test name
Test status
Simulation time 32610001 ps
CPU time 0.74 seconds
Started Jan 10 12:40:34 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200780 kb
Host smart-35bb2fac-30ad-4b96-9959-45104f57a97b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394737607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.2394737607
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.794078367
Short name T375
Test name
Test status
Simulation time 42626816 ps
CPU time 0.86 seconds
Started Jan 10 12:40:31 PM PST 24
Finished Jan 10 12:41:16 PM PST 24
Peak memory 200664 kb
Host smart-d4a83623-0f19-4a2c-b55a-0ad521f8499d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794078367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.clkmgr_lc_ctrl_intersig_mubi.794078367
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.2847038793
Short name T703
Test name
Test status
Simulation time 14281236 ps
CPU time 0.68 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:33 PM PST 24
Peak memory 200600 kb
Host smart-7574e234-3608-454a-ba66-5d92e341d4d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847038793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2847038793
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.2308869963
Short name T58
Test name
Test status
Simulation time 1697898085 ps
CPU time 5.77 seconds
Started Jan 10 12:40:34 PM PST 24
Finished Jan 10 12:41:23 PM PST 24
Peak memory 200984 kb
Host smart-231a16e8-0d8e-4ab3-8ef7-b36aec81bba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308869963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.2308869963
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.2938666814
Short name T320
Test name
Test status
Simulation time 147768903 ps
CPU time 1.14 seconds
Started Jan 10 12:40:45 PM PST 24
Finished Jan 10 12:41:32 PM PST 24
Peak memory 200640 kb
Host smart-31611fbb-f2df-484d-a255-13238aa4b6ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938666814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2938666814
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.700034111
Short name T533
Test name
Test status
Simulation time 1383826241 ps
CPU time 6.01 seconds
Started Jan 10 12:40:49 PM PST 24
Finished Jan 10 12:41:43 PM PST 24
Peak memory 201000 kb
Host smart-836d876d-cbcf-40e1-8083-7ba861b30db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700034111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.700034111
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.3289130190
Short name T396
Test name
Test status
Simulation time 452383304244 ps
CPU time 1833.49 seconds
Started Jan 10 12:40:33 PM PST 24
Finished Jan 10 01:11:51 PM PST 24
Peak memory 214888 kb
Host smart-bc732d62-86ab-4358-a68d-baab12ec83b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3289130190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.3289130190
Directory /workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.clkmgr_trans.3763144888
Short name T974
Test name
Test status
Simulation time 51149811 ps
CPU time 0.95 seconds
Started Jan 10 12:40:45 PM PST 24
Finished Jan 10 12:41:33 PM PST 24
Peak memory 200588 kb
Host smart-7df0dffc-6b90-4e13-8019-d5714b3ff4a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763144888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.3763144888
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.996755123
Short name T752
Test name
Test status
Simulation time 65699545 ps
CPU time 0.84 seconds
Started Jan 10 12:40:48 PM PST 24
Finished Jan 10 12:41:37 PM PST 24
Peak memory 200740 kb
Host smart-2f019981-b70d-47a7-a4a9-865d5ad44455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996755123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkm
gr_alert_test.996755123
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.4214619723
Short name T381
Test name
Test status
Simulation time 22343952 ps
CPU time 0.81 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:31 PM PST 24
Peak memory 200604 kb
Host smart-ee7d60f5-8986-4ae8-8ba7-e25fdacb35b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214619723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.4214619723
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.947674814
Short name T851
Test name
Test status
Simulation time 20499052 ps
CPU time 0.69 seconds
Started Jan 10 12:40:51 PM PST 24
Finished Jan 10 12:41:41 PM PST 24
Peak memory 199540 kb
Host smart-dd5a38f0-bb64-4c87-a597-3329daa1dcef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947674814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.947674814
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.3460605117
Short name T434
Test name
Test status
Simulation time 119166898 ps
CPU time 1.09 seconds
Started Jan 10 12:40:43 PM PST 24
Finished Jan 10 12:41:30 PM PST 24
Peak memory 200640 kb
Host smart-7b2b94c3-6d0d-4f15-a7d5-cd101840534f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460605117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.3460605117
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.3759950361
Short name T655
Test name
Test status
Simulation time 27804588 ps
CPU time 0.9 seconds
Started Jan 10 12:40:33 PM PST 24
Finished Jan 10 12:41:18 PM PST 24
Peak memory 200708 kb
Host smart-4216266d-da5c-4c8e-99d6-ffcd8d78dc16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759950361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.3759950361
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.4226694177
Short name T998
Test name
Test status
Simulation time 822067187 ps
CPU time 4.05 seconds
Started Jan 10 12:40:41 PM PST 24
Finished Jan 10 12:41:29 PM PST 24
Peak memory 200668 kb
Host smart-1165a758-c40b-4abe-a2c3-cebf4933ee61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226694177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.4226694177
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.2219554232
Short name T807
Test name
Test status
Simulation time 1460402834 ps
CPU time 10.29 seconds
Started Jan 10 12:40:49 PM PST 24
Finished Jan 10 12:41:48 PM PST 24
Peak memory 200720 kb
Host smart-79b429bb-99a2-49b3-8066-0d4f185ec36f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219554232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.2219554232
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.632628869
Short name T410
Test name
Test status
Simulation time 30926470 ps
CPU time 0.7 seconds
Started Jan 10 12:40:49 PM PST 24
Finished Jan 10 12:41:37 PM PST 24
Peak memory 200616 kb
Host smart-03b3b430-3c60-45a6-8e83-f65f24ec81a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632628869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.clkmgr_idle_intersig_mubi.632628869
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.834325171
Short name T538
Test name
Test status
Simulation time 21502595 ps
CPU time 0.82 seconds
Started Jan 10 12:40:34 PM PST 24
Finished Jan 10 12:41:19 PM PST 24
Peak memory 200776 kb
Host smart-41a531b9-c212-4fe0-9f3e-befaec5051dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834325171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.clkmgr_lc_clk_byp_req_intersig_mubi.834325171
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.1360253303
Short name T696
Test name
Test status
Simulation time 24970007 ps
CPU time 0.82 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:33 PM PST 24
Peak memory 200648 kb
Host smart-d9f9d39e-2975-40a7-acf8-37369b6670a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360253303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.1360253303
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.2575115407
Short name T848
Test name
Test status
Simulation time 15368239 ps
CPU time 0.71 seconds
Started Jan 10 12:40:31 PM PST 24
Finished Jan 10 12:41:16 PM PST 24
Peak memory 200728 kb
Host smart-ffd7f0d9-d1d5-4fc0-9e0e-6b0fe2337c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575115407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.2575115407
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.953045450
Short name T322
Test name
Test status
Simulation time 433814377 ps
CPU time 2.23 seconds
Started Jan 10 12:40:50 PM PST 24
Finished Jan 10 12:41:42 PM PST 24
Peak memory 200568 kb
Host smart-21456b72-9c3b-465e-8f69-f22a88de95c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953045450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.953045450
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.4059517417
Short name T689
Test name
Test status
Simulation time 67078932 ps
CPU time 0.92 seconds
Started Jan 10 12:40:45 PM PST 24
Finished Jan 10 12:41:32 PM PST 24
Peak memory 200592 kb
Host smart-80adf9d6-bfb1-41f6-8a00-816622ef2720
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059517417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.4059517417
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.3877912221
Short name T774
Test name
Test status
Simulation time 6833390083 ps
CPU time 47.57 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:42:31 PM PST 24
Peak memory 201100 kb
Host smart-b4ee6de7-c031-4a44-ac9c-2e5d29b7a137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877912221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.3877912221
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.2375829381
Short name T717
Test name
Test status
Simulation time 10271200325 ps
CPU time 140.85 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:43:53 PM PST 24
Peak memory 209212 kb
Host smart-98b27023-bdfa-42b7-b187-aa2fd17106af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2375829381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.2375829381
Directory /workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.clkmgr_trans.1710630826
Short name T280
Test name
Test status
Simulation time 105381270 ps
CPU time 1.11 seconds
Started Jan 10 12:40:36 PM PST 24
Finished Jan 10 12:41:20 PM PST 24
Peak memory 200680 kb
Host smart-3469df43-f6be-4a0b-9918-f68b068345ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710630826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.1710630826
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.1038462497
Short name T301
Test name
Test status
Simulation time 12841053 ps
CPU time 0.7 seconds
Started Jan 10 12:39:45 PM PST 24
Finished Jan 10 12:40:16 PM PST 24
Peak memory 200936 kb
Host smart-527f0ff6-4a01-43bf-9896-2c4c32fa150f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038462497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.1038462497
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1339798387
Short name T984
Test name
Test status
Simulation time 51824888 ps
CPU time 0.88 seconds
Started Jan 10 12:39:44 PM PST 24
Finished Jan 10 12:40:16 PM PST 24
Peak memory 200792 kb
Host smart-ffe602e2-d817-44c5-99bf-ddbde6a2f098
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339798387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.1339798387
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.2836888109
Short name T44
Test name
Test status
Simulation time 18836776 ps
CPU time 0.72 seconds
Started Jan 10 12:39:42 PM PST 24
Finished Jan 10 12:40:12 PM PST 24
Peak memory 199668 kb
Host smart-5c3d7ccc-315a-4809-8dfe-752a51962183
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836888109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.2836888109
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.147098326
Short name T300
Test name
Test status
Simulation time 16611723 ps
CPU time 0.74 seconds
Started Jan 10 12:39:45 PM PST 24
Finished Jan 10 12:40:16 PM PST 24
Peak memory 200808 kb
Host smart-1212b64c-ee27-4db2-9945-a2b1a41e7018
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147098326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_div_intersig_mubi.147098326
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.3106513955
Short name T312
Test name
Test status
Simulation time 16560372 ps
CPU time 0.76 seconds
Started Jan 10 12:39:44 PM PST 24
Finished Jan 10 12:40:15 PM PST 24
Peak memory 200680 kb
Host smart-0fd8519f-bcc7-43af-8f81-7243f58238e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106513955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.3106513955
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.1809119453
Short name T9
Test name
Test status
Simulation time 567441729 ps
CPU time 3.62 seconds
Started Jan 10 12:39:46 PM PST 24
Finished Jan 10 12:40:20 PM PST 24
Peak memory 200756 kb
Host smart-f0a73c74-83c3-490d-b221-bbb90180eca7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809119453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.1809119453
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.2252543916
Short name T727
Test name
Test status
Simulation time 1825896391 ps
CPU time 9.08 seconds
Started Jan 10 12:39:41 PM PST 24
Finished Jan 10 12:40:20 PM PST 24
Peak memory 200784 kb
Host smart-4c228b63-669f-4ee4-889c-350f5634ea77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252543916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.2252543916
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.2525807742
Short name T946
Test name
Test status
Simulation time 76015668 ps
CPU time 1.14 seconds
Started Jan 10 12:39:41 PM PST 24
Finished Jan 10 12:40:12 PM PST 24
Peak memory 200680 kb
Host smart-6d4dc56b-3f4b-4d57-a9e8-1dc5b6f8c586
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525807742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.2525807742
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.906748857
Short name T302
Test name
Test status
Simulation time 58440737 ps
CPU time 0.88 seconds
Started Jan 10 12:39:44 PM PST 24
Finished Jan 10 12:40:15 PM PST 24
Peak memory 200804 kb
Host smart-4a441ff3-8856-4242-a7bb-da9cf95a88a7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906748857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.clkmgr_lc_clk_byp_req_intersig_mubi.906748857
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3724561525
Short name T928
Test name
Test status
Simulation time 101331649 ps
CPU time 1.02 seconds
Started Jan 10 12:39:41 PM PST 24
Finished Jan 10 12:40:12 PM PST 24
Peak memory 200708 kb
Host smart-b4ae203f-315f-4d59-a39e-c66b18b507a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724561525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.3724561525
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.2480046442
Short name T723
Test name
Test status
Simulation time 36244031 ps
CPU time 0.77 seconds
Started Jan 10 12:39:39 PM PST 24
Finished Jan 10 12:40:10 PM PST 24
Peak memory 200724 kb
Host smart-d5524cc2-093f-4ca5-8245-3a2267909f54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480046442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2480046442
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.104948052
Short name T54
Test name
Test status
Simulation time 156289761 ps
CPU time 1.91 seconds
Started Jan 10 12:39:43 PM PST 24
Finished Jan 10 12:40:16 PM PST 24
Peak memory 219184 kb
Host smart-9ab2faeb-b46e-4e48-baa3-8211768d0c3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104948052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr
_sec_cm.104948052
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.69001131
Short name T537
Test name
Test status
Simulation time 189677305 ps
CPU time 1.32 seconds
Started Jan 10 12:39:43 PM PST 24
Finished Jan 10 12:40:15 PM PST 24
Peak memory 200792 kb
Host smart-5586b1ce-cb28-4535-909c-1d9bb70b2704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69001131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.69001131
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.1987353729
Short name T733
Test name
Test status
Simulation time 4292366301 ps
CPU time 29.36 seconds
Started Jan 10 12:39:52 PM PST 24
Finished Jan 10 12:40:56 PM PST 24
Peak memory 201116 kb
Host smart-3638a1d5-f102-41c7-a4e6-fb7d48b27120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987353729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.1987353729
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.2439675017
Short name T146
Test name
Test status
Simulation time 150579755841 ps
CPU time 757.69 seconds
Started Jan 10 12:39:41 PM PST 24
Finished Jan 10 12:52:48 PM PST 24
Peak memory 209336 kb
Host smart-586b73eb-cb7b-40b1-8aa9-704e72e8603b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2439675017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.2439675017
Directory /workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.clkmgr_trans.1564628604
Short name T329
Test name
Test status
Simulation time 513079194 ps
CPU time 2.3 seconds
Started Jan 10 12:39:38 PM PST 24
Finished Jan 10 12:40:10 PM PST 24
Peak memory 200716 kb
Host smart-432d4de7-0c4e-4d55-b935-52c1d497bee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564628604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.1564628604
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.4084868050
Short name T662
Test name
Test status
Simulation time 18517737 ps
CPU time 0.77 seconds
Started Jan 10 12:40:49 PM PST 24
Finished Jan 10 12:41:39 PM PST 24
Peak memory 200804 kb
Host smart-1528de84-a85e-41b5-8637-0109a4323bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084868050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.4084868050
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3820132478
Short name T355
Test name
Test status
Simulation time 27631228 ps
CPU time 0.75 seconds
Started Jan 10 12:40:47 PM PST 24
Finished Jan 10 12:41:35 PM PST 24
Peak memory 200552 kb
Host smart-8087567a-ded6-46c3-a924-523ed81ca05c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820132478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.3820132478
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.1920180325
Short name T436
Test name
Test status
Simulation time 19615315 ps
CPU time 0.68 seconds
Started Jan 10 12:40:47 PM PST 24
Finished Jan 10 12:41:35 PM PST 24
Peak memory 199516 kb
Host smart-69296926-0f63-42a2-b415-987d5adbce46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920180325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1920180325
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.1761839635
Short name T645
Test name
Test status
Simulation time 44572669 ps
CPU time 0.88 seconds
Started Jan 10 12:40:39 PM PST 24
Finished Jan 10 12:41:25 PM PST 24
Peak memory 200768 kb
Host smart-e4b6772d-04c6-46db-b148-2f925a3a598e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761839635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.1761839635
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.4242451988
Short name T379
Test name
Test status
Simulation time 63621537 ps
CPU time 0.84 seconds
Started Jan 10 12:40:48 PM PST 24
Finished Jan 10 12:41:37 PM PST 24
Peak memory 200736 kb
Host smart-a573f22b-6ccd-443e-a580-370cbfb2f40c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242451988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.4242451988
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.1751648144
Short name T459
Test name
Test status
Simulation time 2044856210 ps
CPU time 8.91 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:41:51 PM PST 24
Peak memory 200968 kb
Host smart-e0a26302-4a8a-47b8-8725-5344fad41a77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751648144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.1751648144
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.189630580
Short name T753
Test name
Test status
Simulation time 1102982236 ps
CPU time 7.83 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:40 PM PST 24
Peak memory 200716 kb
Host smart-a826847d-06ea-4921-8a94-3b2d0e35eb1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189630580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_ti
meout.189630580
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.731768864
Short name T488
Test name
Test status
Simulation time 37809646 ps
CPU time 0.84 seconds
Started Jan 10 12:40:47 PM PST 24
Finished Jan 10 12:41:35 PM PST 24
Peak memory 200544 kb
Host smart-9f2efa88-9625-4ae3-9fac-d0c9fcec0583
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731768864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_idle_intersig_mubi.731768864
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.4090740878
Short name T895
Test name
Test status
Simulation time 30261830 ps
CPU time 0.73 seconds
Started Jan 10 12:40:49 PM PST 24
Finished Jan 10 12:41:38 PM PST 24
Peak memory 200552 kb
Host smart-7eb300ba-8c36-4b7b-a57f-0c14e67dc912
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090740878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.4090740878
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.2592888062
Short name T956
Test name
Test status
Simulation time 30365373 ps
CPU time 0.77 seconds
Started Jan 10 12:40:41 PM PST 24
Finished Jan 10 12:41:26 PM PST 24
Peak memory 200636 kb
Host smart-8d164047-ac47-4ba3-82b7-51656ec8c298
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592888062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.2592888062
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.3697291231
Short name T517
Test name
Test status
Simulation time 86958553 ps
CPU time 0.89 seconds
Started Jan 10 12:40:45 PM PST 24
Finished Jan 10 12:41:32 PM PST 24
Peak memory 200448 kb
Host smart-3bf0242e-9b63-4d4f-98dc-0c74808b7e50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697291231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.3697291231
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.1140265018
Short name T671
Test name
Test status
Simulation time 525530656 ps
CPU time 2.3 seconds
Started Jan 10 12:40:48 PM PST 24
Finished Jan 10 12:41:38 PM PST 24
Peak memory 200496 kb
Host smart-f9f96361-a061-4f54-a7aa-f04649a619f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140265018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1140265018
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.4141484857
Short name T800
Test name
Test status
Simulation time 69094585 ps
CPU time 0.93 seconds
Started Jan 10 12:40:50 PM PST 24
Finished Jan 10 12:41:40 PM PST 24
Peak memory 200692 kb
Host smart-97f5918e-ed0a-411e-88df-d7aa66689785
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141484857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.4141484857
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.1920800422
Short name T313
Test name
Test status
Simulation time 1925042517 ps
CPU time 7.7 seconds
Started Jan 10 12:40:47 PM PST 24
Finished Jan 10 12:41:43 PM PST 24
Peak memory 200968 kb
Host smart-5eff7d35-8826-439a-bece-229ad200a26a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920800422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.1920800422
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.1632749222
Short name T787
Test name
Test status
Simulation time 75725693875 ps
CPU time 444.74 seconds
Started Jan 10 12:40:42 PM PST 24
Finished Jan 10 12:48:53 PM PST 24
Peak memory 217412 kb
Host smart-cb06ef31-9dab-4d03-af0e-f9f2571bec89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1632749222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.1632749222
Directory /workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.clkmgr_trans.2323520614
Short name T955
Test name
Test status
Simulation time 31697502 ps
CPU time 0.95 seconds
Started Jan 10 12:40:33 PM PST 24
Finished Jan 10 12:41:17 PM PST 24
Peak memory 200732 kb
Host smart-5d2315ba-9afb-4f28-a4e5-9cb2241c9dfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323520614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.2323520614
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.873046926
Short name T735
Test name
Test status
Simulation time 70086884 ps
CPU time 0.9 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:33 PM PST 24
Peak memory 200808 kb
Host smart-843dff09-9caa-45ff-8ae1-5180dbd0f41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873046926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkm
gr_alert_test.873046926
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3550290004
Short name T550
Test name
Test status
Simulation time 50818896 ps
CPU time 0.8 seconds
Started Jan 10 12:40:48 PM PST 24
Finished Jan 10 12:41:37 PM PST 24
Peak memory 200552 kb
Host smart-87a35eff-5aa8-43b8-b7d6-14ea30ff8b78
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550290004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.3550290004
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.2971419644
Short name T455
Test name
Test status
Simulation time 26895834 ps
CPU time 0.72 seconds
Started Jan 10 12:40:41 PM PST 24
Finished Jan 10 12:41:26 PM PST 24
Peak memory 199648 kb
Host smart-9a8da77e-bd00-4a40-af1b-a0dc3b015db1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971419644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.2971419644
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.2997928213
Short name T426
Test name
Test status
Simulation time 93465563 ps
CPU time 1 seconds
Started Jan 10 12:40:40 PM PST 24
Finished Jan 10 12:41:26 PM PST 24
Peak memory 200600 kb
Host smart-9d5aa8ac-e7a6-4ddf-b917-348c8193aea7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997928213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.2997928213
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.3392213650
Short name T559
Test name
Test status
Simulation time 45198101 ps
CPU time 0.88 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:48 PM PST 24
Peak memory 200640 kb
Host smart-36b2e391-bb04-4be6-aafb-6c011db7e014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392213650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.3392213650
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.2966799753
Short name T15
Test name
Test status
Simulation time 2378048124 ps
CPU time 9.81 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:59 PM PST 24
Peak memory 200948 kb
Host smart-9e77ebfb-832e-4804-83fe-3f59b5856325
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966799753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2966799753
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.2671456074
Short name T369
Test name
Test status
Simulation time 1712929228 ps
CPU time 8.56 seconds
Started Jan 10 12:40:47 PM PST 24
Finished Jan 10 12:41:43 PM PST 24
Peak memory 201012 kb
Host smart-909d6e45-dbc6-4d4a-a92f-92930dcbaffc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671456074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.2671456074
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.1035486275
Short name T814
Test name
Test status
Simulation time 37913181 ps
CPU time 1.02 seconds
Started Jan 10 12:40:43 PM PST 24
Finished Jan 10 12:41:29 PM PST 24
Peak memory 200772 kb
Host smart-64e8e602-c13f-445f-bf9c-eb81f87747ee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035486275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.1035486275
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.486607592
Short name T57
Test name
Test status
Simulation time 48011451 ps
CPU time 0.85 seconds
Started Jan 10 12:40:43 PM PST 24
Finished Jan 10 12:41:29 PM PST 24
Peak memory 200688 kb
Host smart-b0eadf60-8b37-439f-83bc-e1bb3120d832
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486607592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.clkmgr_lc_clk_byp_req_intersig_mubi.486607592
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.128437161
Short name T728
Test name
Test status
Simulation time 16103959 ps
CPU time 0.75 seconds
Started Jan 10 12:40:41 PM PST 24
Finished Jan 10 12:41:27 PM PST 24
Peak memory 200808 kb
Host smart-00a92d0b-eb71-4768-8114-388480ba9e49
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128437161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.clkmgr_lc_ctrl_intersig_mubi.128437161
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.495716802
Short name T340
Test name
Test status
Simulation time 22016763 ps
CPU time 0.74 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:34 PM PST 24
Peak memory 200548 kb
Host smart-a940898f-3d6b-4ff0-a5e8-46502038756a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495716802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.495716802
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.2299793159
Short name T311
Test name
Test status
Simulation time 1055213141 ps
CPU time 3.71 seconds
Started Jan 10 12:40:39 PM PST 24
Finished Jan 10 12:41:27 PM PST 24
Peak memory 200844 kb
Host smart-a42a5595-eca1-4ccc-8975-3f009d4614ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299793159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.2299793159
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.1619860956
Short name T695
Test name
Test status
Simulation time 22015908 ps
CPU time 0.83 seconds
Started Jan 10 12:40:43 PM PST 24
Finished Jan 10 12:41:29 PM PST 24
Peak memory 200664 kb
Host smart-718433e9-d8e1-4a16-86b5-953cd36dc23a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619860956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.1619860956
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.1684097598
Short name T362
Test name
Test status
Simulation time 6551758608 ps
CPU time 28.99 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:59 PM PST 24
Peak memory 201072 kb
Host smart-e285f716-535d-460c-910d-7878e8ed4dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684097598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.1684097598
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.4071623477
Short name T980
Test name
Test status
Simulation time 114815791045 ps
CPU time 807.68 seconds
Started Jan 10 12:40:40 PM PST 24
Finished Jan 10 12:54:52 PM PST 24
Peak memory 217540 kb
Host smart-a2913134-49a0-40db-a53d-89f870aff920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4071623477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.4071623477
Directory /workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.clkmgr_trans.2958989455
Short name T823
Test name
Test status
Simulation time 90904314 ps
CPU time 1.04 seconds
Started Jan 10 12:40:49 PM PST 24
Finished Jan 10 12:41:38 PM PST 24
Peak memory 200536 kb
Host smart-d2c2e9b0-547a-4f8a-85f1-ff5b61143c4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958989455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.2958989455
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.3942988004
Short name T327
Test name
Test status
Simulation time 18598996 ps
CPU time 0.72 seconds
Started Jan 10 12:40:45 PM PST 24
Finished Jan 10 12:41:32 PM PST 24
Peak memory 200836 kb
Host smart-36f3d9e9-6949-46c0-a7aa-c92a530afe10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942988004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.3942988004
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.2379475692
Short name T407
Test name
Test status
Simulation time 66788034 ps
CPU time 0.95 seconds
Started Jan 10 12:40:40 PM PST 24
Finished Jan 10 12:41:26 PM PST 24
Peak memory 200800 kb
Host smart-a067a7b7-6836-4fc4-bf9f-d474a5cab7b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379475692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.2379475692
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.1458730647
Short name T479
Test name
Test status
Simulation time 40657332 ps
CPU time 0.74 seconds
Started Jan 10 12:41:00 PM PST 24
Finished Jan 10 12:41:58 PM PST 24
Peak memory 199540 kb
Host smart-5ad021bb-eb51-49d4-b8f8-cd7ba309f337
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458730647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.1458730647
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.2607734891
Short name T112
Test name
Test status
Simulation time 60707310 ps
CPU time 0.87 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:31 PM PST 24
Peak memory 200700 kb
Host smart-78145cf4-1c12-4d52-87a8-a5883824619f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607734891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.2607734891
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.791551515
Short name T451
Test name
Test status
Simulation time 63735413 ps
CPU time 0.89 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:49 PM PST 24
Peak memory 200612 kb
Host smart-fabf5ec4-180a-4295-ace2-37e7e0ba4c3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791551515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.791551515
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.3046070780
Short name T574
Test name
Test status
Simulation time 2083592567 ps
CPU time 7.77 seconds
Started Jan 10 12:40:42 PM PST 24
Finished Jan 10 12:41:35 PM PST 24
Peak memory 200800 kb
Host smart-9c9fa378-243b-45fb-97d0-fb126848056f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046070780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3046070780
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.1148768449
Short name T873
Test name
Test status
Simulation time 1458374873 ps
CPU time 10.59 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:40 PM PST 24
Peak memory 200816 kb
Host smart-3d259af7-68ee-4e84-a464-ddab25608dea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148768449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.1148768449
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.852500775
Short name T939
Test name
Test status
Simulation time 30260967 ps
CPU time 0.82 seconds
Started Jan 10 12:40:42 PM PST 24
Finished Jan 10 12:41:29 PM PST 24
Peak memory 200764 kb
Host smart-20b83dbd-3529-400b-a48c-bb8671d4093e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852500775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_idle_intersig_mubi.852500775
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.4017262179
Short name T726
Test name
Test status
Simulation time 272141839 ps
CPU time 1.55 seconds
Started Jan 10 12:40:41 PM PST 24
Finished Jan 10 12:41:28 PM PST 24
Peak memory 200700 kb
Host smart-cf058c2f-4bfd-4a50-b22c-e9ac5d0ffc4d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017262179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.4017262179
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.2766953219
Short name T732
Test name
Test status
Simulation time 16739406 ps
CPU time 0.78 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:30 PM PST 24
Peak memory 200708 kb
Host smart-ae087223-76b2-482f-b296-b081f3a5c67e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766953219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.2766953219
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.2118615340
Short name T397
Test name
Test status
Simulation time 115576742 ps
CPU time 0.96 seconds
Started Jan 10 12:40:49 PM PST 24
Finished Jan 10 12:41:39 PM PST 24
Peak memory 200404 kb
Host smart-31e7717a-8997-48d5-8954-27665ec8755b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118615340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.2118615340
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.241921550
Short name T464
Test name
Test status
Simulation time 1312214250 ps
CPU time 5.17 seconds
Started Jan 10 12:40:49 PM PST 24
Finished Jan 10 12:41:43 PM PST 24
Peak memory 200992 kb
Host smart-4ee2645e-01b5-4dff-8b7e-ddd4ecbb92cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241921550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.241921550
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.2654044250
Short name T428
Test name
Test status
Simulation time 23284585 ps
CPU time 0.79 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:33 PM PST 24
Peak memory 200548 kb
Host smart-d2a415b0-5498-4ad9-b1da-34be73fdbe15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654044250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.2654044250
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.3042258527
Short name T377
Test name
Test status
Simulation time 9571881021 ps
CPU time 71.59 seconds
Started Jan 10 12:40:56 PM PST 24
Finished Jan 10 12:43:04 PM PST 24
Peak memory 201116 kb
Host smart-9a0c9d67-8bc8-402c-a709-41cc2b44ce1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042258527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.3042258527
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.4273075640
Short name T653
Test name
Test status
Simulation time 15697247438 ps
CPU time 277.75 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:46:25 PM PST 24
Peak memory 209200 kb
Host smart-44675dc5-8fc3-40b7-a4b5-b7036bf7cad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4273075640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.4273075640
Directory /workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_trans.2198179649
Short name T724
Test name
Test status
Simulation time 45303142 ps
CPU time 0.88 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:50 PM PST 24
Peak memory 200656 kb
Host smart-0476f912-f638-4dca-a49e-bc0bc42a2ecc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198179649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.2198179649
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.737918285
Short name T664
Test name
Test status
Simulation time 39214762 ps
CPU time 0.78 seconds
Started Jan 10 12:40:54 PM PST 24
Finished Jan 10 12:41:47 PM PST 24
Peak memory 200768 kb
Host smart-e9657302-eb2f-43cd-ae96-e2f81ee061f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737918285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkm
gr_alert_test.737918285
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.385789666
Short name T449
Test name
Test status
Simulation time 13432135 ps
CPU time 0.72 seconds
Started Jan 10 12:40:51 PM PST 24
Finished Jan 10 12:41:41 PM PST 24
Peak memory 200816 kb
Host smart-1b58a78f-1311-4340-87a4-dad3a7f522e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385789666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.385789666
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.2268911624
Short name T777
Test name
Test status
Simulation time 28267584 ps
CPU time 0.69 seconds
Started Jan 10 12:40:56 PM PST 24
Finished Jan 10 12:41:51 PM PST 24
Peak memory 200516 kb
Host smart-b995dec6-1dad-484d-a331-2d0a2eb43521
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268911624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.2268911624
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.169054544
Short name T651
Test name
Test status
Simulation time 26805453 ps
CPU time 0.87 seconds
Started Jan 10 12:40:53 PM PST 24
Finished Jan 10 12:41:45 PM PST 24
Peak memory 200676 kb
Host smart-336abdb0-3a5b-4dc4-82c1-3f7e6663ac30
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169054544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.clkmgr_div_intersig_mubi.169054544
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.14092651
Short name T563
Test name
Test status
Simulation time 22934169 ps
CPU time 0.71 seconds
Started Jan 10 12:40:54 PM PST 24
Finished Jan 10 12:41:47 PM PST 24
Peak memory 200464 kb
Host smart-f4e1e145-220b-4608-b9c5-a7626e7247ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14092651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.14092651
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.2884292910
Short name T494
Test name
Test status
Simulation time 2490316102 ps
CPU time 10.57 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:41 PM PST 24
Peak memory 201084 kb
Host smart-2cff271c-7a5e-4179-9953-c8b0ac089671
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884292910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.2884292910
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.380829316
Short name T607
Test name
Test status
Simulation time 2195343627 ps
CPU time 6.91 seconds
Started Jan 10 12:41:01 PM PST 24
Finished Jan 10 12:42:04 PM PST 24
Peak memory 200852 kb
Host smart-17c3cac5-e8d3-4bae-8aac-359ffbc9ed1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380829316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_ti
meout.380829316
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.550992378
Short name T757
Test name
Test status
Simulation time 32079934 ps
CPU time 1 seconds
Started Jan 10 12:40:56 PM PST 24
Finished Jan 10 12:41:51 PM PST 24
Peak memory 200760 kb
Host smart-93808ffd-3e39-4566-b019-d7040e1afd6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550992378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.clkmgr_idle_intersig_mubi.550992378
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1642228895
Short name T877
Test name
Test status
Simulation time 134307909 ps
CPU time 1.05 seconds
Started Jan 10 12:40:54 PM PST 24
Finished Jan 10 12:41:47 PM PST 24
Peak memory 200812 kb
Host smart-1e7f3cd5-9f55-4432-8c6e-e21d8824c320
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642228895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.1642228895
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.1459499837
Short name T596
Test name
Test status
Simulation time 331602136 ps
CPU time 1.68 seconds
Started Jan 10 12:40:58 PM PST 24
Finished Jan 10 12:41:55 PM PST 24
Peak memory 200808 kb
Host smart-f64e7e47-db4a-4ec4-9b89-f04d893bba27
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459499837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.1459499837
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.2945017617
Short name T771
Test name
Test status
Simulation time 38963513 ps
CPU time 0.83 seconds
Started Jan 10 12:41:05 PM PST 24
Finished Jan 10 12:42:03 PM PST 24
Peak memory 200944 kb
Host smart-2440d2da-7705-411d-b77f-c5233c5a7b0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945017617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.2945017617
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.2209344669
Short name T898
Test name
Test status
Simulation time 455802305 ps
CPU time 2.22 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:41:45 PM PST 24
Peak memory 200680 kb
Host smart-feabcfd4-188e-4295-b056-514e9ed3c3fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209344669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.2209344669
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.4253297044
Short name T755
Test name
Test status
Simulation time 52252806 ps
CPU time 0.86 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:34 PM PST 24
Peak memory 200540 kb
Host smart-991bed3c-5111-4f4e-9d82-88b617ca1356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253297044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.4253297044
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.2632620173
Short name T507
Test name
Test status
Simulation time 5875604464 ps
CPU time 21.56 seconds
Started Jan 10 12:40:56 PM PST 24
Finished Jan 10 12:42:11 PM PST 24
Peak memory 201020 kb
Host smart-300e1ba7-58c9-4ef1-8baf-c157b5c43141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632620173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.2632620173
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.9469705
Short name T719
Test name
Test status
Simulation time 22109288885 ps
CPU time 304 seconds
Started Jan 10 12:40:59 PM PST 24
Finished Jan 10 12:46:59 PM PST 24
Peak memory 209256 kb
Host smart-316d0859-7a89-449b-a5d5-9ab46616e6bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=9469705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.9469705
Directory /workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.clkmgr_trans.2788994490
Short name T633
Test name
Test status
Simulation time 32113966 ps
CPU time 0.97 seconds
Started Jan 10 12:40:50 PM PST 24
Finished Jan 10 12:41:41 PM PST 24
Peak memory 200692 kb
Host smart-47c65339-9c13-4e89-9d85-eef651a7034d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788994490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2788994490
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.1320074005
Short name T983
Test name
Test status
Simulation time 17486634 ps
CPU time 0.77 seconds
Started Jan 10 12:40:57 PM PST 24
Finished Jan 10 12:41:53 PM PST 24
Peak memory 200704 kb
Host smart-6c922556-fb56-4085-b048-69a9979257e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320074005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.1320074005
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.867758170
Short name T569
Test name
Test status
Simulation time 19215519 ps
CPU time 0.8 seconds
Started Jan 10 12:40:54 PM PST 24
Finished Jan 10 12:41:46 PM PST 24
Peak memory 200716 kb
Host smart-9e00beba-dff5-43a6-a074-0731852f2bc4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867758170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.867758170
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.3460105150
Short name T5
Test name
Test status
Simulation time 24927134 ps
CPU time 0.71 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 199476 kb
Host smart-778f741a-7d76-4757-a776-0e1b13e9cef5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460105150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.3460105150
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.1424506968
Short name T364
Test name
Test status
Simulation time 45124548 ps
CPU time 0.81 seconds
Started Jan 10 12:41:05 PM PST 24
Finished Jan 10 12:42:04 PM PST 24
Peak memory 200604 kb
Host smart-e7c8b45c-097f-436a-bd8f-6e54bf08b11d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424506968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.1424506968
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.2390744440
Short name T683
Test name
Test status
Simulation time 77859305 ps
CPU time 0.96 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 200868 kb
Host smart-11e27f71-69e9-4cb9-a31c-7d829e607049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390744440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.2390744440
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.3342965474
Short name T11
Test name
Test status
Simulation time 1786160470 ps
CPU time 7.83 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:55 PM PST 24
Peak memory 200892 kb
Host smart-bef22b78-ed86-49c1-a00d-586835b79a6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342965474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3342965474
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.2319968037
Short name T989
Test name
Test status
Simulation time 740504468 ps
CPU time 5.67 seconds
Started Jan 10 12:40:54 PM PST 24
Finished Jan 10 12:41:52 PM PST 24
Peak memory 200868 kb
Host smart-aa612d45-40c3-4d99-afde-c6acc541d596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319968037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.2319968037
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.210087481
Short name T318
Test name
Test status
Simulation time 22963606 ps
CPU time 0.84 seconds
Started Jan 10 12:40:58 PM PST 24
Finished Jan 10 12:41:55 PM PST 24
Peak memory 200680 kb
Host smart-36ff87fc-2655-4fd2-bc63-f2f8747d671b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210087481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.clkmgr_idle_intersig_mubi.210087481
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1442096420
Short name T529
Test name
Test status
Simulation time 42945676 ps
CPU time 0.92 seconds
Started Jan 10 12:40:57 PM PST 24
Finished Jan 10 12:41:54 PM PST 24
Peak memory 200776 kb
Host smart-61faa9b2-1eef-414b-8e9b-90db10d82b99
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442096420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.1442096420
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.553240683
Short name T884
Test name
Test status
Simulation time 52802776 ps
CPU time 0.88 seconds
Started Jan 10 12:40:53 PM PST 24
Finished Jan 10 12:41:45 PM PST 24
Peak memory 200720 kb
Host smart-138559d0-21f8-441c-b841-6cd25613640e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553240683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.clkmgr_lc_ctrl_intersig_mubi.553240683
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.2279033120
Short name T704
Test name
Test status
Simulation time 17842920 ps
CPU time 0.75 seconds
Started Jan 10 12:40:58 PM PST 24
Finished Jan 10 12:41:55 PM PST 24
Peak memory 200608 kb
Host smart-e1d1d349-ca27-4d77-9833-eb0eddb66b4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279033120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.2279033120
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.590274377
Short name T336
Test name
Test status
Simulation time 925722971 ps
CPU time 3.73 seconds
Started Jan 10 12:40:53 PM PST 24
Finished Jan 10 12:41:48 PM PST 24
Peak memory 200912 kb
Host smart-0ba71536-8f06-4f89-8986-fa91a67b76e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590274377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.590274377
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.1419118385
Short name T441
Test name
Test status
Simulation time 16841220 ps
CPU time 0.8 seconds
Started Jan 10 12:40:58 PM PST 24
Finished Jan 10 12:41:54 PM PST 24
Peak memory 200692 kb
Host smart-a0648bf5-0b10-4302-8177-ddc3a84232fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419118385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.1419118385
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.1823776305
Short name T954
Test name
Test status
Simulation time 4939203094 ps
CPU time 20.96 seconds
Started Jan 10 12:41:06 PM PST 24
Finished Jan 10 12:42:26 PM PST 24
Peak memory 200940 kb
Host smart-2cf41308-5de2-4a84-957d-149f81947577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823776305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.1823776305
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.2200044312
Short name T25
Test name
Test status
Simulation time 109895949064 ps
CPU time 1149.91 seconds
Started Jan 10 12:40:53 PM PST 24
Finished Jan 10 01:00:54 PM PST 24
Peak memory 217524 kb
Host smart-dac399a0-36eb-42ab-8570-a5cbb539f2dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2200044312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.2200044312
Directory /workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.clkmgr_trans.2076526369
Short name T573
Test name
Test status
Simulation time 26082956 ps
CPU time 0.73 seconds
Started Jan 10 12:41:03 PM PST 24
Finished Jan 10 12:42:01 PM PST 24
Peak memory 200596 kb
Host smart-99d79687-c630-48c5-aa81-17aca3069a3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076526369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2076526369
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.171330967
Short name T384
Test name
Test status
Simulation time 56705936 ps
CPU time 0.88 seconds
Started Jan 10 12:40:58 PM PST 24
Finished Jan 10 12:41:55 PM PST 24
Peak memory 200784 kb
Host smart-a05133e0-0228-49f9-bed1-af028b4f886b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171330967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkm
gr_alert_test.171330967
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1176918616
Short name T473
Test name
Test status
Simulation time 23469604 ps
CPU time 0.87 seconds
Started Jan 10 12:41:00 PM PST 24
Finished Jan 10 12:41:57 PM PST 24
Peak memory 200644 kb
Host smart-b96a6cf8-29ab-49c0-90dc-92dfbf7976ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176918616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.1176918616
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.2604222361
Short name T937
Test name
Test status
Simulation time 48775597 ps
CPU time 0.82 seconds
Started Jan 10 12:40:53 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 199680 kb
Host smart-fe202ec8-d04a-48ea-b3f6-f6f61eb774ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604222361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.2604222361
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.1306190687
Short name T590
Test name
Test status
Simulation time 25614204 ps
CPU time 0.86 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 200780 kb
Host smart-9cfc77f8-4756-4871-9a0c-9eae6162239b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306190687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_div_intersig_mubi.1306190687
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.3822800054
Short name T871
Test name
Test status
Simulation time 18913753 ps
CPU time 0.8 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 200644 kb
Host smart-8f8dbb8f-0be7-4167-ade7-19c30d8f54b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822800054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3822800054
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.3049236148
Short name T500
Test name
Test status
Simulation time 434649127 ps
CPU time 3.93 seconds
Started Jan 10 12:40:54 PM PST 24
Finished Jan 10 12:41:49 PM PST 24
Peak memory 200732 kb
Host smart-5123d0bf-14b7-4736-8d6b-96a9207fba1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049236148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.3049236148
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.535791079
Short name T501
Test name
Test status
Simulation time 1815806086 ps
CPU time 12.46 seconds
Started Jan 10 12:40:53 PM PST 24
Finished Jan 10 12:41:57 PM PST 24
Peak memory 200884 kb
Host smart-3dcfde3c-0895-4c61-8d62-500392d3321a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535791079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_ti
meout.535791079
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.2347033912
Short name T446
Test name
Test status
Simulation time 38814392 ps
CPU time 1.04 seconds
Started Jan 10 12:41:02 PM PST 24
Finished Jan 10 12:42:00 PM PST 24
Peak memory 200772 kb
Host smart-7b52a130-1b77-404e-9cf7-4f2fd1a2a75c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347033912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.2347033912
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.1287469345
Short name T288
Test name
Test status
Simulation time 42180672 ps
CPU time 0.82 seconds
Started Jan 10 12:40:54 PM PST 24
Finished Jan 10 12:41:47 PM PST 24
Peak memory 200668 kb
Host smart-bec5fe7e-add3-4dd3-9cad-fe10c5c23413
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287469345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.1287469345
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.3623606492
Short name T433
Test name
Test status
Simulation time 35257431 ps
CPU time 0.81 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:49 PM PST 24
Peak memory 200592 kb
Host smart-f918060d-a28a-4137-90b6-d07f31f0f7aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623606492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.3623606492
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.336194057
Short name T587
Test name
Test status
Simulation time 763847475 ps
CPU time 3.14 seconds
Started Jan 10 12:40:54 PM PST 24
Finished Jan 10 12:41:49 PM PST 24
Peak memory 200908 kb
Host smart-28d86e0d-70a8-490e-8a17-6313e8241476
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336194057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.336194057
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.2592951047
Short name T949
Test name
Test status
Simulation time 15878023 ps
CPU time 0.77 seconds
Started Jan 10 12:41:07 PM PST 24
Finished Jan 10 12:42:07 PM PST 24
Peak memory 200608 kb
Host smart-65fdceea-74e0-4be5-bd47-0d4e6bf077f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592951047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2592951047
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.1087715552
Short name T913
Test name
Test status
Simulation time 3041434848 ps
CPU time 22.22 seconds
Started Jan 10 12:40:56 PM PST 24
Finished Jan 10 12:42:13 PM PST 24
Peak memory 201048 kb
Host smart-91547bae-d5a8-4307-ac4c-6039a18d09ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087715552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.1087715552
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.449819584
Short name T790
Test name
Test status
Simulation time 34931477649 ps
CPU time 260.22 seconds
Started Jan 10 12:41:01 PM PST 24
Finished Jan 10 12:46:18 PM PST 24
Peak memory 215804 kb
Host smart-14bb384d-1978-4f7e-a33f-79e4241620a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=449819584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.449819584
Directory /workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.clkmgr_trans.131168165
Short name T308
Test name
Test status
Simulation time 40559563 ps
CPU time 0.89 seconds
Started Jan 10 12:41:02 PM PST 24
Finished Jan 10 12:42:00 PM PST 24
Peak memory 200764 kb
Host smart-833a1782-ea2f-47e4-90f3-565786e562a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131168165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.131168165
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.2410690666
Short name T39
Test name
Test status
Simulation time 28616589 ps
CPU time 0.79 seconds
Started Jan 10 12:41:09 PM PST 24
Finished Jan 10 12:42:10 PM PST 24
Peak memory 200796 kb
Host smart-0df7d83a-d495-43ad-a0c8-e18bdf1037dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410690666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.2410690666
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.1850098374
Short name T307
Test name
Test status
Simulation time 19486313 ps
CPU time 0.8 seconds
Started Jan 10 12:40:52 PM PST 24
Finished Jan 10 12:41:44 PM PST 24
Peak memory 200808 kb
Host smart-cd4e60bf-9110-4747-972d-f0f79c056b60
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850098374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.1850098374
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.3364662165
Short name T513
Test name
Test status
Simulation time 44258168 ps
CPU time 0.76 seconds
Started Jan 10 12:40:56 PM PST 24
Finished Jan 10 12:41:51 PM PST 24
Peak memory 199520 kb
Host smart-c1947ad7-06e9-49ab-bc04-5d27e4be54d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364662165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.3364662165
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.267642489
Short name T137
Test name
Test status
Simulation time 43495286 ps
CPU time 0.9 seconds
Started Jan 10 12:41:10 PM PST 24
Finished Jan 10 12:42:10 PM PST 24
Peak memory 200692 kb
Host smart-34ec2493-2b62-4c49-9c94-c77de49811d7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267642489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_div_intersig_mubi.267642489
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.1989578221
Short name T341
Test name
Test status
Simulation time 43673504 ps
CPU time 0.79 seconds
Started Jan 10 12:40:58 PM PST 24
Finished Jan 10 12:41:54 PM PST 24
Peak memory 200596 kb
Host smart-834b5b7f-06d2-45c5-8b4c-eeca84cf695c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989578221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1989578221
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.568633069
Short name T815
Test name
Test status
Simulation time 1158879490 ps
CPU time 9.13 seconds
Started Jan 10 12:40:57 PM PST 24
Finished Jan 10 12:42:00 PM PST 24
Peak memory 200560 kb
Host smart-2c0dc5dd-3817-40bc-9292-1ff330e8bed4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568633069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.568633069
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.2090175534
Short name T353
Test name
Test status
Simulation time 539395170 ps
CPU time 2.74 seconds
Started Jan 10 12:40:54 PM PST 24
Finished Jan 10 12:41:48 PM PST 24
Peak memory 200776 kb
Host smart-22aa6328-ce10-47e4-9c7e-e177f673c73c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090175534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.2090175534
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.2094103172
Short name T969
Test name
Test status
Simulation time 65999515 ps
CPU time 0.95 seconds
Started Jan 10 12:40:56 PM PST 24
Finished Jan 10 12:41:51 PM PST 24
Peak memory 200760 kb
Host smart-7ae2b5e5-d88a-4e9b-aea9-a45e78afb717
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094103172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.2094103172
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3417795672
Short name T468
Test name
Test status
Simulation time 19307550 ps
CPU time 0.81 seconds
Started Jan 10 12:41:06 PM PST 24
Finished Jan 10 12:42:06 PM PST 24
Peak memory 200612 kb
Host smart-17773c2a-3929-47d6-bacf-eedcb0f41063
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417795672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3417795672
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.4041697630
Short name T838
Test name
Test status
Simulation time 70194565 ps
CPU time 0.9 seconds
Started Jan 10 12:40:53 PM PST 24
Finished Jan 10 12:41:45 PM PST 24
Peak memory 200812 kb
Host smart-7217c290-40df-4059-a27a-521e2a4488be
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041697630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.4041697630
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.1810434187
Short name T844
Test name
Test status
Simulation time 38443226 ps
CPU time 0.75 seconds
Started Jan 10 12:40:50 PM PST 24
Finished Jan 10 12:41:41 PM PST 24
Peak memory 200700 kb
Host smart-11171fc7-08b8-478a-acfa-6e5ee3cbb2f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810434187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.1810434187
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.2876419252
Short name T149
Test name
Test status
Simulation time 965540739 ps
CPU time 3.68 seconds
Started Jan 10 12:41:07 PM PST 24
Finished Jan 10 12:42:11 PM PST 24
Peak memory 200944 kb
Host smart-75c1725b-3f1c-4e7b-babd-210b2e307bfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876419252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.2876419252
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.2285921697
Short name T139
Test name
Test status
Simulation time 22115758 ps
CPU time 0.94 seconds
Started Jan 10 12:40:56 PM PST 24
Finished Jan 10 12:41:50 PM PST 24
Peak memory 200804 kb
Host smart-b586651a-c21c-4c73-b03d-cd3d7b0b3b27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285921697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.2285921697
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.369760369
Short name T621
Test name
Test status
Simulation time 69155631238 ps
CPU time 607.65 seconds
Started Jan 10 12:41:07 PM PST 24
Finished Jan 10 12:52:17 PM PST 24
Peak memory 211444 kb
Host smart-26525942-c059-44d0-9ab9-cd98fd7b40f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=369760369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.369760369
Directory /workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.clkmgr_trans.3464079687
Short name T342
Test name
Test status
Simulation time 34376782 ps
CPU time 0.77 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:50 PM PST 24
Peak memory 200748 kb
Host smart-05d648cc-15d6-4f13-9628-65f985f1672d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464079687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.3464079687
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.3802735864
Short name T575
Test name
Test status
Simulation time 48017246 ps
CPU time 0.84 seconds
Started Jan 10 12:41:07 PM PST 24
Finished Jan 10 12:42:07 PM PST 24
Peak memory 200660 kb
Host smart-0bb0604b-565c-4951-ab27-fcb8801f4ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802735864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.3802735864
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1085763367
Short name T933
Test name
Test status
Simulation time 139017293 ps
CPU time 1.17 seconds
Started Jan 10 12:41:06 PM PST 24
Finished Jan 10 12:42:06 PM PST 24
Peak memory 200648 kb
Host smart-ea67bc45-7f60-4ead-a432-afcac7cf1aad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085763367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.1085763367
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.1035200974
Short name T786
Test name
Test status
Simulation time 18188698 ps
CPU time 0.7 seconds
Started Jan 10 12:41:10 PM PST 24
Finished Jan 10 12:42:11 PM PST 24
Peak memory 200572 kb
Host smart-995b33d5-1ca5-4c87-a33e-d51c87753d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035200974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1035200974
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3162966986
Short name T601
Test name
Test status
Simulation time 72429729 ps
CPU time 0.97 seconds
Started Jan 10 12:41:05 PM PST 24
Finished Jan 10 12:42:04 PM PST 24
Peak memory 200768 kb
Host smart-0bf2222e-6b18-40a7-85df-37ec9b492147
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162966986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3162966986
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.2156756950
Short name T962
Test name
Test status
Simulation time 46720878 ps
CPU time 0.95 seconds
Started Jan 10 12:41:06 PM PST 24
Finished Jan 10 12:42:07 PM PST 24
Peak memory 200580 kb
Host smart-3876f931-f310-429a-b700-cfa4c097768a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156756950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.2156756950
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.1540308365
Short name T692
Test name
Test status
Simulation time 1516457534 ps
CPU time 11.51 seconds
Started Jan 10 12:41:04 PM PST 24
Finished Jan 10 12:42:12 PM PST 24
Peak memory 200808 kb
Host smart-72bae73f-258f-4219-8bb7-a03ac5bb833e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540308365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.1540308365
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.1743172736
Short name T910
Test name
Test status
Simulation time 2209369918 ps
CPU time 8.87 seconds
Started Jan 10 12:41:12 PM PST 24
Finished Jan 10 12:42:22 PM PST 24
Peak memory 201056 kb
Host smart-6679c213-d119-4776-8e6a-a01dbaa23133
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743172736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.1743172736
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.3259009944
Short name T741
Test name
Test status
Simulation time 141291093 ps
CPU time 1.35 seconds
Started Jan 10 12:41:09 PM PST 24
Finished Jan 10 12:42:10 PM PST 24
Peak memory 200696 kb
Host smart-a3eb916b-6997-4f23-91f2-a679642bfb40
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259009944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.3259009944
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.3825667156
Short name T916
Test name
Test status
Simulation time 79853763 ps
CPU time 0.98 seconds
Started Jan 10 12:41:09 PM PST 24
Finished Jan 10 12:42:10 PM PST 24
Peak memory 200728 kb
Host smart-5ed1dfcf-da5b-43c4-a1e1-18069b46669c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825667156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.3825667156
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.959889650
Short name T19
Test name
Test status
Simulation time 39478037 ps
CPU time 0.92 seconds
Started Jan 10 12:41:07 PM PST 24
Finished Jan 10 12:42:08 PM PST 24
Peak memory 200656 kb
Host smart-10ff11e3-12fc-4fde-823f-c2d0eaee5bc8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959889650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.clkmgr_lc_ctrl_intersig_mubi.959889650
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.2268623156
Short name T506
Test name
Test status
Simulation time 13964796 ps
CPU time 0.72 seconds
Started Jan 10 12:41:08 PM PST 24
Finished Jan 10 12:42:09 PM PST 24
Peak memory 200768 kb
Host smart-697e1f42-0b50-4e78-b5e4-c3fad7b69291
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268623156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.2268623156
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.1417429589
Short name T693
Test name
Test status
Simulation time 723128540 ps
CPU time 4.53 seconds
Started Jan 10 12:41:12 PM PST 24
Finished Jan 10 12:42:18 PM PST 24
Peak memory 200912 kb
Host smart-95d6d8f2-cf32-4413-aa6d-86a9efaac829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417429589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1417429589
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.3662938354
Short name T874
Test name
Test status
Simulation time 18951510 ps
CPU time 0.81 seconds
Started Jan 10 12:41:06 PM PST 24
Finished Jan 10 12:42:06 PM PST 24
Peak memory 200660 kb
Host smart-6de06b4d-91a4-4735-a3e3-7d229a43af7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662938354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3662938354
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.41051846
Short name T142
Test name
Test status
Simulation time 1451415326 ps
CPU time 6.55 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:26 PM PST 24
Peak memory 201064 kb
Host smart-5b762e5b-6b15-44c0-9cd9-32aa20938ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41051846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_stress_all.41051846
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.3223362400
Short name T480
Test name
Test status
Simulation time 30954538902 ps
CPU time 491.39 seconds
Started Jan 10 12:41:08 PM PST 24
Finished Jan 10 12:50:19 PM PST 24
Peak memory 209456 kb
Host smart-58cf4584-14c9-4e42-a457-1d7cf94b1e15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3223362400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.3223362400
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_trans.850533152
Short name T801
Test name
Test status
Simulation time 158608734 ps
CPU time 1.31 seconds
Started Jan 10 12:41:07 PM PST 24
Finished Jan 10 12:42:08 PM PST 24
Peak memory 200792 kb
Host smart-d3248e5d-7ace-4fed-8be1-07d7de9aa563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850533152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.850533152
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.1698088342
Short name T739
Test name
Test status
Simulation time 29976443 ps
CPU time 0.79 seconds
Started Jan 10 12:41:08 PM PST 24
Finished Jan 10 12:42:08 PM PST 24
Peak memory 200716 kb
Host smart-bf8f50dd-7da1-4037-9947-543ff207c253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698088342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.1698088342
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.3253068993
Short name T738
Test name
Test status
Simulation time 31948499 ps
CPU time 0.93 seconds
Started Jan 10 12:41:13 PM PST 24
Finished Jan 10 12:42:16 PM PST 24
Peak memory 200692 kb
Host smart-25d9a63b-1500-4d1d-9bd1-888c86d499f3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253068993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.3253068993
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.2236314987
Short name T644
Test name
Test status
Simulation time 16593570 ps
CPU time 0.73 seconds
Started Jan 10 12:41:05 PM PST 24
Finished Jan 10 12:42:03 PM PST 24
Peak memory 199604 kb
Host smart-691b6f09-e59e-422e-b240-8c70daae4b60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236314987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.2236314987
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.3920726801
Short name T351
Test name
Test status
Simulation time 72331248 ps
CPU time 0.94 seconds
Started Jan 10 12:41:13 PM PST 24
Finished Jan 10 12:42:15 PM PST 24
Peak memory 200692 kb
Host smart-6a8307d1-4cc1-43c3-8a55-8d3b5c5e7ef5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920726801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.3920726801
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.3871859095
Short name T994
Test name
Test status
Simulation time 95626741 ps
CPU time 1.06 seconds
Started Jan 10 12:41:14 PM PST 24
Finished Jan 10 12:42:18 PM PST 24
Peak memory 200624 kb
Host smart-22dbffd2-7374-4a2e-a8c9-b74b437e2097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871859095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.3871859095
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.1404470456
Short name T523
Test name
Test status
Simulation time 1484158154 ps
CPU time 6.9 seconds
Started Jan 10 12:41:10 PM PST 24
Finished Jan 10 12:42:17 PM PST 24
Peak memory 200740 kb
Host smart-da3c2453-a7b2-42f2-88bc-ab31a69d7621
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404470456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.1404470456
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.2934724632
Short name T867
Test name
Test status
Simulation time 1517118912 ps
CPU time 5.36 seconds
Started Jan 10 12:41:04 PM PST 24
Finished Jan 10 12:42:08 PM PST 24
Peak memory 200840 kb
Host smart-6d2bdca8-a203-49ce-aa1d-112158160762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934724632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.2934724632
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.264397846
Short name T361
Test name
Test status
Simulation time 88657131 ps
CPU time 1.12 seconds
Started Jan 10 12:41:07 PM PST 24
Finished Jan 10 12:42:10 PM PST 24
Peak memory 200704 kb
Host smart-4cb9c2aa-59e8-45df-9aef-a09f8cc4aa23
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264397846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.clkmgr_idle_intersig_mubi.264397846
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.413676937
Short name T697
Test name
Test status
Simulation time 68166484 ps
CPU time 0.9 seconds
Started Jan 10 12:41:11 PM PST 24
Finished Jan 10 12:42:12 PM PST 24
Peak memory 200800 kb
Host smart-e1311aa2-04bd-4054-87fe-862bf2dfe7db
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413676937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.clkmgr_lc_clk_byp_req_intersig_mubi.413676937
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.2596245466
Short name T558
Test name
Test status
Simulation time 21877637 ps
CPU time 0.83 seconds
Started Jan 10 12:41:06 PM PST 24
Finished Jan 10 12:42:07 PM PST 24
Peak memory 200792 kb
Host smart-ebc10a57-0a9f-4b37-ba56-9deeb9180f66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596245466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.2596245466
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.3588058866
Short name T819
Test name
Test status
Simulation time 631540419 ps
CPU time 3.65 seconds
Started Jan 10 12:41:03 PM PST 24
Finished Jan 10 12:42:04 PM PST 24
Peak memory 200832 kb
Host smart-157206d8-38af-4386-ace2-56f5ceba180f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588058866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.3588058866
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.1432181684
Short name T625
Test name
Test status
Simulation time 22383734 ps
CPU time 0.84 seconds
Started Jan 10 12:41:10 PM PST 24
Finished Jan 10 12:42:11 PM PST 24
Peak memory 200776 kb
Host smart-9d246945-a3c0-4e3c-98f6-e889cc722a75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432181684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.1432181684
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.1580037433
Short name T784
Test name
Test status
Simulation time 6451480435 ps
CPU time 43.2 seconds
Started Jan 10 12:41:05 PM PST 24
Finished Jan 10 12:42:46 PM PST 24
Peak memory 201116 kb
Host smart-82677f63-b283-420a-a8c4-073ebf2c5798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580037433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.1580037433
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.4065639831
Short name T766
Test name
Test status
Simulation time 86598197584 ps
CPU time 761.72 seconds
Started Jan 10 12:41:10 PM PST 24
Finished Jan 10 12:54:52 PM PST 24
Peak memory 209272 kb
Host smart-67d2cadc-6a59-4589-b6d1-458ff9040fe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4065639831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.4065639831
Directory /workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.clkmgr_trans.1542237317
Short name T136
Test name
Test status
Simulation time 36690734 ps
CPU time 1.07 seconds
Started Jan 10 12:41:07 PM PST 24
Finished Jan 10 12:42:13 PM PST 24
Peak memory 200692 kb
Host smart-023900a4-3a4c-4b66-b4b3-6c217d539657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542237317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.1542237317
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.3162030923
Short name T371
Test name
Test status
Simulation time 63813181 ps
CPU time 0.96 seconds
Started Jan 10 12:41:25 PM PST 24
Finished Jan 10 12:42:32 PM PST 24
Peak memory 200712 kb
Host smart-d43d6caf-1cba-49b3-b395-250dd8fc9a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162030923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.3162030923
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.201184420
Short name T927
Test name
Test status
Simulation time 63872870 ps
CPU time 0.94 seconds
Started Jan 10 12:41:09 PM PST 24
Finished Jan 10 12:42:10 PM PST 24
Peak memory 200696 kb
Host smart-b41562c9-65e1-4aca-8c2a-90a255fc8e08
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201184420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.201184420
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.2935912417
Short name T584
Test name
Test status
Simulation time 22252837 ps
CPU time 0.72 seconds
Started Jan 10 12:41:18 PM PST 24
Finished Jan 10 12:42:24 PM PST 24
Peak memory 199572 kb
Host smart-3f9478ed-fa0e-4322-a5d1-7aadf6d0b414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935912417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2935912417
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.276349897
Short name T734
Test name
Test status
Simulation time 42996387 ps
CPU time 0.91 seconds
Started Jan 10 12:41:14 PM PST 24
Finished Jan 10 12:42:18 PM PST 24
Peak memory 200704 kb
Host smart-18332306-4a78-4d3b-bd39-681799f069a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276349897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.clkmgr_div_intersig_mubi.276349897
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.1876528179
Short name T904
Test name
Test status
Simulation time 83410582 ps
CPU time 1.06 seconds
Started Jan 10 12:41:12 PM PST 24
Finished Jan 10 12:42:15 PM PST 24
Peak memory 200668 kb
Host smart-b77a3777-0a99-489a-8a44-04da258b7422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876528179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1876528179
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.3028293967
Short name T772
Test name
Test status
Simulation time 345751019 ps
CPU time 1.92 seconds
Started Jan 10 12:41:08 PM PST 24
Finished Jan 10 12:42:10 PM PST 24
Peak memory 200712 kb
Host smart-ac1f8b94-9855-4b8e-8aa6-61caaf2994a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028293967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.3028293967
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.2197760094
Short name T938
Test name
Test status
Simulation time 381813810 ps
CPU time 3.13 seconds
Started Jan 10 12:41:10 PM PST 24
Finished Jan 10 12:42:13 PM PST 24
Peak memory 200868 kb
Host smart-f085e667-8493-43db-b4dc-445035b8ef2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197760094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.2197760094
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3270756032
Short name T649
Test name
Test status
Simulation time 141142283 ps
CPU time 1.29 seconds
Started Jan 10 12:41:09 PM PST 24
Finished Jan 10 12:42:10 PM PST 24
Peak memory 200768 kb
Host smart-91d9673d-8e6e-4cf0-960f-299646c91209
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270756032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.3270756032
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2534798170
Short name T760
Test name
Test status
Simulation time 71881703 ps
CPU time 0.97 seconds
Started Jan 10 12:41:08 PM PST 24
Finished Jan 10 12:42:09 PM PST 24
Peak memory 200648 kb
Host smart-13c10531-25a0-4190-9ce7-172675e2ad51
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534798170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.2534798170
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.133500528
Short name T748
Test name
Test status
Simulation time 25007975 ps
CPU time 0.86 seconds
Started Jan 10 12:41:04 PM PST 24
Finished Jan 10 12:42:02 PM PST 24
Peak memory 200692 kb
Host smart-829f46e9-bc2e-49a7-bf01-915f4e3a524d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133500528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.clkmgr_lc_ctrl_intersig_mubi.133500528
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.1982035804
Short name T546
Test name
Test status
Simulation time 22847631 ps
CPU time 0.75 seconds
Started Jan 10 12:41:06 PM PST 24
Finished Jan 10 12:42:07 PM PST 24
Peak memory 200564 kb
Host smart-0e8bc358-21e1-4503-b972-915cd898f968
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982035804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.1982035804
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.2333045717
Short name T737
Test name
Test status
Simulation time 646208877 ps
CPU time 3.72 seconds
Started Jan 10 12:41:14 PM PST 24
Finished Jan 10 12:42:21 PM PST 24
Peak memory 200976 kb
Host smart-78cd0a4e-1954-44e6-95ab-53b26ccbc7ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333045717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.2333045717
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.510289625
Short name T690
Test name
Test status
Simulation time 66112896 ps
CPU time 0.95 seconds
Started Jan 10 12:41:11 PM PST 24
Finished Jan 10 12:42:13 PM PST 24
Peak memory 200588 kb
Host smart-eca5761d-484d-4906-b50a-b9b3deee50cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510289625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.510289625
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.4123404496
Short name T566
Test name
Test status
Simulation time 6407341848 ps
CPU time 26.19 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:46 PM PST 24
Peak memory 201040 kb
Host smart-4a09ebcc-b88e-463d-beb6-603fc85c5c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123404496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.4123404496
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.2950443416
Short name T997
Test name
Test status
Simulation time 76678317952 ps
CPU time 535.9 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:51:17 PM PST 24
Peak memory 209348 kb
Host smart-61ef81a7-d14c-4db0-b8df-00f396c4997b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2950443416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.2950443416
Directory /workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.clkmgr_trans.185310156
Short name T471
Test name
Test status
Simulation time 126437031 ps
CPU time 1.2 seconds
Started Jan 10 12:41:08 PM PST 24
Finished Jan 10 12:42:09 PM PST 24
Peak memory 200976 kb
Host smart-10162946-fa58-4a65-8fd1-067123acfd53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185310156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.185310156
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.2952426955
Short name T416
Test name
Test status
Simulation time 15272003 ps
CPU time 0.71 seconds
Started Jan 10 12:40:01 PM PST 24
Finished Jan 10 12:40:45 PM PST 24
Peak memory 200624 kb
Host smart-792ecb79-16a6-44f9-8d05-830b86b0712f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952426955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.2952426955
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.2839990686
Short name T918
Test name
Test status
Simulation time 30676386 ps
CPU time 0.91 seconds
Started Jan 10 12:39:43 PM PST 24
Finished Jan 10 12:40:13 PM PST 24
Peak memory 200828 kb
Host smart-9a80c01b-3a03-4a80-b33e-ab297c1b237e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839990686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.2839990686
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.3287120614
Short name T641
Test name
Test status
Simulation time 17081057 ps
CPU time 0.68 seconds
Started Jan 10 12:39:39 PM PST 24
Finished Jan 10 12:40:10 PM PST 24
Peak memory 199640 kb
Host smart-20dac2c9-52c3-4747-90ab-7097da9486d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287120614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.3287120614
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.22618596
Short name T832
Test name
Test status
Simulation time 106492713 ps
CPU time 1.09 seconds
Started Jan 10 12:39:42 PM PST 24
Finished Jan 10 12:40:12 PM PST 24
Peak memory 200708 kb
Host smart-cf30c3b3-4c65-4107-a658-b4eedde1d05c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22618596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
clkmgr_div_intersig_mubi.22618596
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.2091640214
Short name T439
Test name
Test status
Simulation time 20914415 ps
CPU time 0.78 seconds
Started Jan 10 12:39:43 PM PST 24
Finished Jan 10 12:40:14 PM PST 24
Peak memory 200700 kb
Host smart-89058b87-3ef9-4897-86a3-0a5919b07177
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091640214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.2091640214
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.899753424
Short name T751
Test name
Test status
Simulation time 357844936 ps
CPU time 2.13 seconds
Started Jan 10 12:39:46 PM PST 24
Finished Jan 10 12:40:19 PM PST 24
Peak memory 200752 kb
Host smart-d209767b-76d8-4d53-82e1-39e876ad6d8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899753424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.899753424
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.43088867
Short name T521
Test name
Test status
Simulation time 739982902 ps
CPU time 4.83 seconds
Started Jan 10 12:39:42 PM PST 24
Finished Jan 10 12:40:17 PM PST 24
Peak memory 200720 kb
Host smart-5241dba6-25d9-4573-859c-a939d1cf81c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43088867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_time
out.43088867
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.2948695297
Short name T541
Test name
Test status
Simulation time 110610450 ps
CPU time 1.16 seconds
Started Jan 10 12:39:41 PM PST 24
Finished Jan 10 12:40:12 PM PST 24
Peak memory 200680 kb
Host smart-e3d11202-db8b-4703-8cd5-a596ee3eec3f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948695297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.2948695297
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.66755820
Short name T572
Test name
Test status
Simulation time 40547218 ps
CPU time 0.89 seconds
Started Jan 10 12:39:46 PM PST 24
Finished Jan 10 12:40:18 PM PST 24
Peak memory 200772 kb
Host smart-6cc6b6b8-e8b7-466b-ac8a-9522cda8a22f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66755820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_lc_clk_byp_req_intersig_mubi.66755820
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.2432243196
Short name T290
Test name
Test status
Simulation time 38331856 ps
CPU time 0.8 seconds
Started Jan 10 12:39:46 PM PST 24
Finished Jan 10 12:40:18 PM PST 24
Peak memory 200704 kb
Host smart-419559fb-0d41-452d-891b-e96216f9640a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432243196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.2432243196
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.3342517007
Short name T17
Test name
Test status
Simulation time 23477381 ps
CPU time 0.71 seconds
Started Jan 10 12:39:42 PM PST 24
Finished Jan 10 12:40:13 PM PST 24
Peak memory 200604 kb
Host smart-dbf9462e-fda9-4e8c-aa33-46c10b7314f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342517007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.3342517007
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.4279858614
Short name T457
Test name
Test status
Simulation time 1120791857 ps
CPU time 6.13 seconds
Started Jan 10 12:39:40 PM PST 24
Finished Jan 10 12:40:15 PM PST 24
Peak memory 201000 kb
Host smart-fd3dfe0e-3540-4af1-b699-3ed8064f2057
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279858614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.4279858614
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.3319578365
Short name T64
Test name
Test status
Simulation time 472316670 ps
CPU time 2.62 seconds
Started Jan 10 12:39:39 PM PST 24
Finished Jan 10 12:40:11 PM PST 24
Peak memory 219096 kb
Host smart-91895b7d-18d6-4a7d-becb-accffeca2365
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319578365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.3319578365
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.980923979
Short name T620
Test name
Test status
Simulation time 78876059 ps
CPU time 1.04 seconds
Started Jan 10 12:39:41 PM PST 24
Finished Jan 10 12:40:12 PM PST 24
Peak memory 200820 kb
Host smart-7f7cff18-b38a-4d2f-9921-b6509283d5ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980923979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.980923979
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.295298470
Short name T940
Test name
Test status
Simulation time 8484400444 ps
CPU time 35.07 seconds
Started Jan 10 12:40:02 PM PST 24
Finished Jan 10 12:41:21 PM PST 24
Peak memory 200952 kb
Host smart-8584c7b3-1aae-403d-aba9-fb82b03acdac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295298470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.295298470
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.3841513838
Short name T438
Test name
Test status
Simulation time 139737528254 ps
CPU time 1044.06 seconds
Started Jan 10 12:39:52 PM PST 24
Finished Jan 10 12:57:51 PM PST 24
Peak memory 209352 kb
Host smart-8abd3eb0-8b0a-4139-98ce-d0a6aba21c1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3841513838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.3841513838
Directory /workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.clkmgr_trans.3741931995
Short name T294
Test name
Test status
Simulation time 22858952 ps
CPU time 0.72 seconds
Started Jan 10 12:39:51 PM PST 24
Finished Jan 10 12:40:25 PM PST 24
Peak memory 200656 kb
Host smart-fdacb13d-1e26-48ec-83d3-a1795bc8c2c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741931995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.3741931995
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.2481801387
Short name T865
Test name
Test status
Simulation time 48629916 ps
CPU time 0.85 seconds
Started Jan 10 12:41:19 PM PST 24
Finished Jan 10 12:42:26 PM PST 24
Peak memory 200712 kb
Host smart-00f0e522-ae3e-42e0-96e1-b8d9789d0df6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481801387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.2481801387
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.310734828
Short name T948
Test name
Test status
Simulation time 16134215 ps
CPU time 0.76 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:24 PM PST 24
Peak memory 200976 kb
Host smart-fa035d10-b523-483b-89f4-cf925f0303ee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310734828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.310734828
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.2932977610
Short name T489
Test name
Test status
Simulation time 57808659 ps
CPU time 0.8 seconds
Started Jan 10 12:41:13 PM PST 24
Finished Jan 10 12:42:15 PM PST 24
Peak memory 200596 kb
Host smart-d73c97d6-d672-49cd-8b3b-80b98327cc4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932977610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2932977610
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.1224287667
Short name T592
Test name
Test status
Simulation time 30848666 ps
CPU time 0.9 seconds
Started Jan 10 12:41:14 PM PST 24
Finished Jan 10 12:42:18 PM PST 24
Peak memory 200756 kb
Host smart-2c35daf5-117b-4e42-b2f9-7bde0baa6f0e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224287667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.1224287667
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.4264593094
Short name T531
Test name
Test status
Simulation time 35955773 ps
CPU time 0.86 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:42:22 PM PST 24
Peak memory 200696 kb
Host smart-d5197271-d18a-4bb5-a52a-0279ffef9fdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264593094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.4264593094
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.779800785
Short name T617
Test name
Test status
Simulation time 556858578 ps
CPU time 4.77 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:24 PM PST 24
Peak memory 200728 kb
Host smart-9718790f-8bdf-48b3-911e-ad3f5840336a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779800785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.779800785
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.2879780802
Short name T929
Test name
Test status
Simulation time 741375380 ps
CPU time 4.24 seconds
Started Jan 10 12:41:20 PM PST 24
Finished Jan 10 12:42:30 PM PST 24
Peak memory 200864 kb
Host smart-b75f8cb4-bc6f-4a2f-98d0-fa48c7fda91a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879780802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.2879780802
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.3513112046
Short name T990
Test name
Test status
Simulation time 15649204 ps
CPU time 0.8 seconds
Started Jan 10 12:41:14 PM PST 24
Finished Jan 10 12:42:18 PM PST 24
Peak memory 200736 kb
Host smart-79694117-fdc4-4e6d-9bca-a32730e93e8e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513112046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.3513112046
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.1516732411
Short name T912
Test name
Test status
Simulation time 15799050 ps
CPU time 0.72 seconds
Started Jan 10 12:41:25 PM PST 24
Finished Jan 10 12:42:32 PM PST 24
Peak memory 200704 kb
Host smart-4852f368-a27a-4016-86c6-a71a82836617
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516732411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.1516732411
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.4189406504
Short name T942
Test name
Test status
Simulation time 24275643 ps
CPU time 0.72 seconds
Started Jan 10 12:41:14 PM PST 24
Finished Jan 10 12:42:18 PM PST 24
Peak memory 200740 kb
Host smart-75c2dbcc-af3d-488c-9670-e4f0f0b26bf7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189406504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.4189406504
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.1292158522
Short name T422
Test name
Test status
Simulation time 157003213 ps
CPU time 1.14 seconds
Started Jan 10 12:41:20 PM PST 24
Finished Jan 10 12:42:30 PM PST 24
Peak memory 200640 kb
Host smart-d3e96e0f-9443-4d8f-858f-7388c538b545
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292158522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.1292158522
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.842740549
Short name T677
Test name
Test status
Simulation time 257222941 ps
CPU time 1.98 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:42:24 PM PST 24
Peak memory 200896 kb
Host smart-e9ba9e98-fc11-4bf5-985f-cd54b863201a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842740549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.842740549
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.1730382758
Short name T585
Test name
Test status
Simulation time 95660704 ps
CPU time 1.02 seconds
Started Jan 10 12:41:15 PM PST 24
Finished Jan 10 12:42:20 PM PST 24
Peak memory 200772 kb
Host smart-446a72e1-4c49-49b0-aa5a-1cf19d46499f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730382758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.1730382758
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.4170679134
Short name T484
Test name
Test status
Simulation time 1643003649 ps
CPU time 7.55 seconds
Started Jan 10 12:41:21 PM PST 24
Finished Jan 10 12:42:35 PM PST 24
Peak memory 200672 kb
Host smart-21be34f0-d1b4-4bb6-b9ee-bff0e3170959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170679134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.4170679134
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.4004394417
Short name T855
Test name
Test status
Simulation time 32281548377 ps
CPU time 567.96 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:51:51 PM PST 24
Peak memory 210080 kb
Host smart-c29b1ee8-02b3-4d5f-8d34-8f79d5f0c955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4004394417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.4004394417
Directory /workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.clkmgr_trans.3483526377
Short name T28
Test name
Test status
Simulation time 25761828 ps
CPU time 0.76 seconds
Started Jan 10 12:41:18 PM PST 24
Finished Jan 10 12:42:23 PM PST 24
Peak memory 200772 kb
Host smart-2618e0b3-3ab9-417b-aeb0-64f6f22cedda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483526377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.3483526377
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.1412241908
Short name T470
Test name
Test status
Simulation time 23913335 ps
CPU time 0.86 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:42:22 PM PST 24
Peak memory 200824 kb
Host smart-b355df98-a920-42d3-b236-9b2bb94465c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412241908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.1412241908
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.2801783295
Short name T850
Test name
Test status
Simulation time 34657757 ps
CPU time 0.75 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:42:22 PM PST 24
Peak memory 200676 kb
Host smart-46c278e3-8b48-47b2-82ef-794e99356f0b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801783295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.2801783295
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.2228199160
Short name T444
Test name
Test status
Simulation time 22781632 ps
CPU time 0.7 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:20 PM PST 24
Peak memory 199552 kb
Host smart-1cd0ffee-21be-4c75-b4bf-7dd8c1b6cf27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228199160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.2228199160
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.1387747649
Short name T747
Test name
Test status
Simulation time 135918010 ps
CPU time 1.15 seconds
Started Jan 10 12:41:18 PM PST 24
Finished Jan 10 12:42:25 PM PST 24
Peak memory 200796 kb
Host smart-a6162fde-39de-41a6-a661-e3871f6fde42
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387747649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.1387747649
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.3548093017
Short name T694
Test name
Test status
Simulation time 40611770 ps
CPU time 0.89 seconds
Started Jan 10 12:41:15 PM PST 24
Finished Jan 10 12:42:20 PM PST 24
Peak memory 200644 kb
Host smart-d9da63f7-52f5-4ac0-81eb-75c891f6a93c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548093017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3548093017
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.762499214
Short name T588
Test name
Test status
Simulation time 1045077325 ps
CPU time 5.94 seconds
Started Jan 10 12:41:21 PM PST 24
Finished Jan 10 12:42:33 PM PST 24
Peak memory 200656 kb
Host smart-2e0591e3-bd21-4802-92f6-1b026c41ad3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762499214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.762499214
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.1127830955
Short name T571
Test name
Test status
Simulation time 1018534648 ps
CPU time 4.58 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:25 PM PST 24
Peak memory 200848 kb
Host smart-3a5a6154-f822-4967-807d-5a2f2ef8f1f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127830955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.1127830955
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.2388339772
Short name T385
Test name
Test status
Simulation time 328320548 ps
CPU time 1.84 seconds
Started Jan 10 12:41:15 PM PST 24
Finished Jan 10 12:42:20 PM PST 24
Peak memory 200628 kb
Host smart-4d5baa3a-ae93-4497-9643-9883ce1ccca2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388339772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.2388339772
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.3418122857
Short name T964
Test name
Test status
Simulation time 64995001 ps
CPU time 0.93 seconds
Started Jan 10 12:41:18 PM PST 24
Finished Jan 10 12:42:24 PM PST 24
Peak memory 200672 kb
Host smart-8be8f4d3-95c9-45d5-bf0c-f3813c13b256
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418122857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.3418122857
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2534533759
Short name T406
Test name
Test status
Simulation time 19282460 ps
CPU time 0.78 seconds
Started Jan 10 12:41:15 PM PST 24
Finished Jan 10 12:42:20 PM PST 24
Peak memory 200708 kb
Host smart-e4e5aa1b-d0b4-46db-af11-1429ebdf86f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534533759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.2534533759
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.758406332
Short name T782
Test name
Test status
Simulation time 14218676 ps
CPU time 0.72 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:20 PM PST 24
Peak memory 200696 kb
Host smart-0574f236-0a6f-4b24-ad71-d9a16e67302c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758406332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.758406332
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.916527161
Short name T793
Test name
Test status
Simulation time 1167335429 ps
CPU time 6.65 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:42:28 PM PST 24
Peak memory 200972 kb
Host smart-e0d48492-46db-4f21-9391-367ce14ddc70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916527161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.916527161
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.2915147723
Short name T622
Test name
Test status
Simulation time 38653852 ps
CPU time 0.89 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:42:23 PM PST 24
Peak memory 200664 kb
Host smart-75acd28f-9c07-4072-9809-f045470892dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915147723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.2915147723
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.1498788786
Short name T481
Test name
Test status
Simulation time 9740913596 ps
CPU time 42.17 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:43:04 PM PST 24
Peak memory 201120 kb
Host smart-d4f1ae7b-1213-46f0-bbc8-2215601a3e10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498788786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.1498788786
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.2340792609
Short name T858
Test name
Test status
Simulation time 21263726521 ps
CPU time 378.45 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:48:38 PM PST 24
Peak memory 217324 kb
Host smart-82c66500-7b76-42fc-8db0-ff2de88a86b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2340792609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.2340792609
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.802558854
Short name T889
Test name
Test status
Simulation time 81984098 ps
CPU time 1.09 seconds
Started Jan 10 12:41:19 PM PST 24
Finished Jan 10 12:42:27 PM PST 24
Peak memory 200780 kb
Host smart-dc3ddb2f-c8f4-48d8-bb4d-5a8f43c0deed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802558854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.802558854
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.1644828590
Short name T283
Test name
Test status
Simulation time 39924834 ps
CPU time 0.77 seconds
Started Jan 10 12:41:18 PM PST 24
Finished Jan 10 12:42:25 PM PST 24
Peak memory 200796 kb
Host smart-69b98fce-add9-4401-bbb8-dca4be034dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644828590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.1644828590
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.1680859398
Short name T429
Test name
Test status
Simulation time 23039178 ps
CPU time 0.73 seconds
Started Jan 10 12:41:24 PM PST 24
Finished Jan 10 12:42:31 PM PST 24
Peak memory 200708 kb
Host smart-8faf6e1e-3df0-466d-9460-255d1c3bddeb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680859398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.1680859398
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.4235263663
Short name T953
Test name
Test status
Simulation time 56332340 ps
CPU time 0.8 seconds
Started Jan 10 12:41:22 PM PST 24
Finished Jan 10 12:42:29 PM PST 24
Peak memory 200680 kb
Host smart-6002cd2a-78a6-4fd4-ac92-ca5c4ab2153f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235263663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.4235263663
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.2742960729
Short name T299
Test name
Test status
Simulation time 16385451 ps
CPU time 0.72 seconds
Started Jan 10 12:41:20 PM PST 24
Finished Jan 10 12:42:29 PM PST 24
Peak memory 200796 kb
Host smart-9a6e75ea-9a65-44d7-967c-b12641f6bafb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742960729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.2742960729
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.2510335546
Short name T292
Test name
Test status
Simulation time 28948741 ps
CPU time 0.73 seconds
Started Jan 10 12:41:19 PM PST 24
Finished Jan 10 12:42:25 PM PST 24
Peak memory 200648 kb
Host smart-fea5ee5e-231d-4bf0-b455-bc5ce3caff79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510335546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.2510335546
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.2817481636
Short name T769
Test name
Test status
Simulation time 1014253026 ps
CPU time 4 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:27 PM PST 24
Peak memory 200788 kb
Host smart-1664176c-d54b-4fb6-b541-6100a8900a2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817481636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.2817481636
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.4077790554
Short name T634
Test name
Test status
Simulation time 516940355 ps
CPU time 2.43 seconds
Started Jan 10 12:41:12 PM PST 24
Finished Jan 10 12:42:15 PM PST 24
Peak memory 200720 kb
Host smart-1f21da14-bbbd-4ac7-915b-c162e3b4f39c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077790554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.4077790554
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.299606728
Short name T754
Test name
Test status
Simulation time 43975381 ps
CPU time 0.82 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:21 PM PST 24
Peak memory 200756 kb
Host smart-2bf39a35-a814-4d0f-87f7-d071c3bd61c0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299606728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.clkmgr_idle_intersig_mubi.299606728
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1177175181
Short name T682
Test name
Test status
Simulation time 15595122 ps
CPU time 0.74 seconds
Started Jan 10 12:41:14 PM PST 24
Finished Jan 10 12:42:18 PM PST 24
Peak memory 200700 kb
Host smart-f21198e7-0775-49b4-b274-bf93c19b1616
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177175181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.1177175181
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.3947314797
Short name T698
Test name
Test status
Simulation time 63317674 ps
CPU time 0.9 seconds
Started Jan 10 12:41:20 PM PST 24
Finished Jan 10 12:42:27 PM PST 24
Peak memory 200804 kb
Host smart-fd0f5ed4-6ba3-42f2-87a5-477651e992c1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947314797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.3947314797
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.832307419
Short name T287
Test name
Test status
Simulation time 60679220 ps
CPU time 0.83 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:24 PM PST 24
Peak memory 200756 kb
Host smart-99d60d83-24f9-4777-8dc3-b451373909bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832307419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.832307419
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.3996784898
Short name T560
Test name
Test status
Simulation time 92234464 ps
CPU time 0.98 seconds
Started Jan 10 12:41:20 PM PST 24
Finished Jan 10 12:42:27 PM PST 24
Peak memory 200684 kb
Host smart-c8859a76-7c54-4cdd-8b27-8e72a4a22e26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996784898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3996784898
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.423328597
Short name T490
Test name
Test status
Simulation time 85543851 ps
CPU time 1.04 seconds
Started Jan 10 12:41:19 PM PST 24
Finished Jan 10 12:42:27 PM PST 24
Peak memory 200692 kb
Host smart-b89d51ec-4a91-4955-b0c0-f6232fe80d49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423328597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.423328597
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.146698806
Short name T985
Test name
Test status
Simulation time 3790216722 ps
CPU time 29.54 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:42:51 PM PST 24
Peak memory 201092 kb
Host smart-291338cf-7e75-48ec-894e-b4651829f348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146698806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.146698806
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.1650424668
Short name T354
Test name
Test status
Simulation time 22456915023 ps
CPU time 199.41 seconds
Started Jan 10 12:41:20 PM PST 24
Finished Jan 10 12:45:45 PM PST 24
Peak memory 209336 kb
Host smart-ee4b91dd-43ed-4be0-9d31-9b07be5400f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1650424668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.1650424668
Directory /workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.clkmgr_trans.1024863700
Short name T935
Test name
Test status
Simulation time 17308396 ps
CPU time 0.82 seconds
Started Jan 10 12:41:20 PM PST 24
Finished Jan 10 12:42:27 PM PST 24
Peak memory 200668 kb
Host smart-39dbb7fc-515d-4044-a51e-2d98ec4c0aae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024863700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.1024863700
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.2538719284
Short name T41
Test name
Test status
Simulation time 35034666 ps
CPU time 0.76 seconds
Started Jan 10 12:41:23 PM PST 24
Finished Jan 10 12:42:30 PM PST 24
Peak memory 200604 kb
Host smart-a435c238-dee0-476a-980b-a059ee9ce5be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538719284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.2538719284
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.1278674292
Short name T486
Test name
Test status
Simulation time 25782808 ps
CPU time 0.88 seconds
Started Jan 10 12:41:21 PM PST 24
Finished Jan 10 12:42:27 PM PST 24
Peak memory 200796 kb
Host smart-afe4eca2-dd47-4df7-85cb-61df384c8bd3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278674292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.1278674292
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.2073687665
Short name T462
Test name
Test status
Simulation time 35132121 ps
CPU time 0.74 seconds
Started Jan 10 12:41:20 PM PST 24
Finished Jan 10 12:42:27 PM PST 24
Peak memory 200668 kb
Host smart-0f9522fd-9e99-447a-bd12-f4d72e190a3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073687665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2073687665
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.3477358009
Short name T834
Test name
Test status
Simulation time 84204650 ps
CPU time 1.02 seconds
Started Jan 10 12:41:23 PM PST 24
Finished Jan 10 12:42:30 PM PST 24
Peak memory 200688 kb
Host smart-5f295289-5eec-4c85-a208-31c007ffd47f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477358009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.3477358009
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.1277656426
Short name T925
Test name
Test status
Simulation time 76171307 ps
CPU time 0.97 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:42:23 PM PST 24
Peak memory 200732 kb
Host smart-b32ad161-d6cc-4eb5-9943-bbac8d3c2ab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277656426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.1277656426
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.1518288068
Short name T674
Test name
Test status
Simulation time 2502622946 ps
CPU time 10.41 seconds
Started Jan 10 12:41:29 PM PST 24
Finished Jan 10 12:42:45 PM PST 24
Peak memory 200988 kb
Host smart-cc0e3043-2d86-4a42-bebb-3fbcd696b8a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518288068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.1518288068
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.438765035
Short name T970
Test name
Test status
Simulation time 1461062233 ps
CPU time 10.26 seconds
Started Jan 10 12:41:22 PM PST 24
Finished Jan 10 12:42:38 PM PST 24
Peak memory 200768 kb
Host smart-9fee48bd-354c-417e-9bff-7b9e22ff1efe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438765035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_ti
meout.438765035
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.616807805
Short name T20
Test name
Test status
Simulation time 65768500 ps
CPU time 0.94 seconds
Started Jan 10 12:41:25 PM PST 24
Finished Jan 10 12:42:32 PM PST 24
Peak memory 200772 kb
Host smart-bb25fbde-d392-481d-9b69-184bc9888e31
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616807805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.clkmgr_idle_intersig_mubi.616807805
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.3221394996
Short name T551
Test name
Test status
Simulation time 24598954 ps
CPU time 0.76 seconds
Started Jan 10 12:41:25 PM PST 24
Finished Jan 10 12:42:32 PM PST 24
Peak memory 200700 kb
Host smart-52e69955-70f1-4718-932b-379c5f40d8d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221394996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.3221394996
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3346766376
Short name T610
Test name
Test status
Simulation time 20075243 ps
CPU time 0.78 seconds
Started Jan 10 12:41:21 PM PST 24
Finished Jan 10 12:42:28 PM PST 24
Peak memory 200808 kb
Host smart-0988f8ed-859d-4ed0-a9f9-dfea73342bfa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346766376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.3346766376
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.631251635
Short name T547
Test name
Test status
Simulation time 17230502 ps
CPU time 0.73 seconds
Started Jan 10 12:41:19 PM PST 24
Finished Jan 10 12:42:26 PM PST 24
Peak memory 200744 kb
Host smart-3fd2cb74-d269-433e-9a37-0e339beb51c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631251635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.631251635
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.1599871425
Short name T720
Test name
Test status
Simulation time 816077878 ps
CPU time 3.21 seconds
Started Jan 10 12:41:22 PM PST 24
Finished Jan 10 12:42:31 PM PST 24
Peak memory 200840 kb
Host smart-cd26f422-7d18-43d1-8a56-bdd1e89cf484
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599871425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.1599871425
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.2411237654
Short name T105
Test name
Test status
Simulation time 75408918 ps
CPU time 0.97 seconds
Started Jan 10 12:41:21 PM PST 24
Finished Jan 10 12:42:28 PM PST 24
Peak memory 200700 kb
Host smart-c9287566-517c-4eee-8c19-24f5ca6910da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411237654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.2411237654
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.1906605833
Short name T824
Test name
Test status
Simulation time 4169220114 ps
CPU time 29.69 seconds
Started Jan 10 12:41:21 PM PST 24
Finished Jan 10 12:42:57 PM PST 24
Peak memory 201032 kb
Host smart-9fbf4607-f8af-4cb6-b07a-3e6942e73646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906605833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.1906605833
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.2391247375
Short name T959
Test name
Test status
Simulation time 101021083004 ps
CPU time 569.85 seconds
Started Jan 10 12:41:23 PM PST 24
Finished Jan 10 12:52:00 PM PST 24
Peak memory 209096 kb
Host smart-c559d073-9d7d-40f9-a6a2-f9454d43aed0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2391247375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.2391247375
Directory /workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.clkmgr_trans.598049935
Short name T330
Test name
Test status
Simulation time 49211695 ps
CPU time 0.88 seconds
Started Jan 10 12:41:24 PM PST 24
Finished Jan 10 12:42:31 PM PST 24
Peak memory 200592 kb
Host smart-3fffee15-5ef2-4879-8238-32a8977c2303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598049935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.598049935
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.2597302669
Short name T334
Test name
Test status
Simulation time 21704082 ps
CPU time 0.77 seconds
Started Jan 10 12:41:41 PM PST 24
Finished Jan 10 12:42:48 PM PST 24
Peak memory 200660 kb
Host smart-235b99ec-9ca1-4c9f-af12-2ca880977f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597302669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.2597302669
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3224638534
Short name T545
Test name
Test status
Simulation time 30715285 ps
CPU time 0.85 seconds
Started Jan 10 12:41:19 PM PST 24
Finished Jan 10 12:42:26 PM PST 24
Peak memory 200768 kb
Host smart-96400cc3-a41e-4378-a18d-70ecfa44f6c3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224638534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.3224638534
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.3826156641
Short name T808
Test name
Test status
Simulation time 15316504 ps
CPU time 0.68 seconds
Started Jan 10 12:41:25 PM PST 24
Finished Jan 10 12:42:32 PM PST 24
Peak memory 199560 kb
Host smart-2488c994-725a-42b4-8261-aa30221b4c15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826156641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.3826156641
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.3437738569
Short name T297
Test name
Test status
Simulation time 57904373 ps
CPU time 0.94 seconds
Started Jan 10 12:41:24 PM PST 24
Finished Jan 10 12:42:31 PM PST 24
Peak memory 200768 kb
Host smart-b859eae2-9307-4b6b-b171-276751cbb606
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437738569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.3437738569
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.3707874589
Short name T378
Test name
Test status
Simulation time 75775313 ps
CPU time 0.97 seconds
Started Jan 10 12:41:40 PM PST 24
Finished Jan 10 12:42:48 PM PST 24
Peak memory 200532 kb
Host smart-380e831e-f508-4f78-894a-1e2c15ec93fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707874589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.3707874589
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.761098268
Short name T762
Test name
Test status
Simulation time 2160414999 ps
CPU time 9.83 seconds
Started Jan 10 12:41:26 PM PST 24
Finished Jan 10 12:42:42 PM PST 24
Peak memory 200924 kb
Host smart-42afc7fa-e476-4f59-bf6a-6d86a24c083b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761098268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.761098268
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.1887785756
Short name T564
Test name
Test status
Simulation time 752074937 ps
CPU time 3.28 seconds
Started Jan 10 12:41:30 PM PST 24
Finished Jan 10 12:42:39 PM PST 24
Peak memory 200724 kb
Host smart-8134de90-ecba-4455-9a3f-dd4dbebae47f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887785756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.1887785756
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.297066447
Short name T345
Test name
Test status
Simulation time 15712259 ps
CPU time 0.73 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:24 PM PST 24
Peak memory 200788 kb
Host smart-63297a30-a585-43b7-a454-e6e759d82862
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297066447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.clkmgr_idle_intersig_mubi.297066447
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2600584095
Short name T512
Test name
Test status
Simulation time 29907999 ps
CPU time 0.78 seconds
Started Jan 10 12:41:21 PM PST 24
Finished Jan 10 12:42:28 PM PST 24
Peak memory 200648 kb
Host smart-c011665f-50ac-4453-a130-a86e34fbe73f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600584095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.2600584095
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.3292168886
Short name T632
Test name
Test status
Simulation time 32519425 ps
CPU time 0.88 seconds
Started Jan 10 12:41:31 PM PST 24
Finished Jan 10 12:42:37 PM PST 24
Peak memory 200612 kb
Host smart-db40ddcf-c36f-4582-93cb-3cb5607b8078
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292168886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.3292168886
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.2011224870
Short name T554
Test name
Test status
Simulation time 44204806 ps
CPU time 0.77 seconds
Started Jan 10 12:41:35 PM PST 24
Finished Jan 10 12:42:42 PM PST 24
Peak memory 200492 kb
Host smart-d4bca122-10f9-4c9c-8ec3-d6da8ad29986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011224870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2011224870
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.1660307971
Short name T886
Test name
Test status
Simulation time 830313032 ps
CPU time 4.73 seconds
Started Jan 10 12:41:23 PM PST 24
Finished Jan 10 12:42:34 PM PST 24
Peak memory 200992 kb
Host smart-15e60b66-cf77-465c-9331-087f17c9bbb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660307971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.1660307971
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.3577532607
Short name T557
Test name
Test status
Simulation time 16432025 ps
CPU time 0.77 seconds
Started Jan 10 12:41:24 PM PST 24
Finished Jan 10 12:42:31 PM PST 24
Peak memory 200692 kb
Host smart-e6e355b5-5ac5-49c0-8617-ff1e6a7ad769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577532607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.3577532607
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.1665916723
Short name T615
Test name
Test status
Simulation time 7347206233 ps
CPU time 54.25 seconds
Started Jan 10 12:41:32 PM PST 24
Finished Jan 10 12:43:32 PM PST 24
Peak memory 200960 kb
Host smart-80f33c98-6d39-4e02-8c4e-ef661daf52c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665916723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.1665916723
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.3069678906
Short name T936
Test name
Test status
Simulation time 9993715397 ps
CPU time 153.95 seconds
Started Jan 10 12:41:22 PM PST 24
Finished Jan 10 12:45:02 PM PST 24
Peak memory 214472 kb
Host smart-985e4109-158c-4709-a7b3-0ba81841e862
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3069678906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.3069678906
Directory /workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.clkmgr_trans.1372406226
Short name T798
Test name
Test status
Simulation time 24195735 ps
CPU time 0.81 seconds
Started Jan 10 12:41:30 PM PST 24
Finished Jan 10 12:42:37 PM PST 24
Peak memory 200628 kb
Host smart-cbf01919-d7a1-40e1-8e57-cc466ea39997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372406226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.1372406226
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.3805653845
Short name T893
Test name
Test status
Simulation time 26294071 ps
CPU time 0.77 seconds
Started Jan 10 12:41:27 PM PST 24
Finished Jan 10 12:42:34 PM PST 24
Peak memory 200808 kb
Host smart-1f9faca4-ec0e-45a0-a624-9775735930ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805653845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.3805653845
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.2185026247
Short name T791
Test name
Test status
Simulation time 41192314 ps
CPU time 0.88 seconds
Started Jan 10 12:41:29 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200600 kb
Host smart-d5c332f8-71a1-4a8a-8be8-cf51eeb2cd6d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185026247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.2185026247
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.1203297983
Short name T783
Test name
Test status
Simulation time 15489887 ps
CPU time 0.68 seconds
Started Jan 10 12:41:19 PM PST 24
Finished Jan 10 12:42:25 PM PST 24
Peak memory 199560 kb
Host smart-3fe77fb7-b5d2-4f81-9b9e-0fdad0ca8789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203297983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.1203297983
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.3018922511
Short name T150
Test name
Test status
Simulation time 101066492 ps
CPU time 1.01 seconds
Started Jan 10 12:41:22 PM PST 24
Finished Jan 10 12:42:29 PM PST 24
Peak memory 200776 kb
Host smart-d2d11c4e-66a8-4768-8829-9ac35324dc0a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018922511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.3018922511
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.3370057632
Short name T981
Test name
Test status
Simulation time 67707178 ps
CPU time 0.9 seconds
Started Jan 10 12:41:20 PM PST 24
Finished Jan 10 12:42:27 PM PST 24
Peak memory 200696 kb
Host smart-5f3d4b2d-b7b3-4a65-b189-b3adbf6c6dbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370057632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3370057632
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.3685799097
Short name T797
Test name
Test status
Simulation time 1552350971 ps
CPU time 5.68 seconds
Started Jan 10 12:41:30 PM PST 24
Finished Jan 10 12:42:41 PM PST 24
Peak memory 200660 kb
Host smart-f4b7a15c-2458-4c91-8447-59dd3329700e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685799097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.3685799097
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.4189448956
Short name T714
Test name
Test status
Simulation time 1217506408 ps
CPU time 8.58 seconds
Started Jan 10 12:41:41 PM PST 24
Finished Jan 10 12:42:56 PM PST 24
Peak memory 200724 kb
Host smart-8f19040c-2e5d-4a7f-9c7f-11125e95350e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189448956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.4189448956
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3817354003
Short name T909
Test name
Test status
Simulation time 252768088 ps
CPU time 1.35 seconds
Started Jan 10 12:41:29 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200596 kb
Host smart-4cc48d82-0a06-469b-ad59-8a6b7d89e209
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817354003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.3817354003
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.1629172355
Short name T699
Test name
Test status
Simulation time 89911642 ps
CPU time 0.94 seconds
Started Jan 10 12:41:32 PM PST 24
Finished Jan 10 12:42:39 PM PST 24
Peak memory 200608 kb
Host smart-1b31a04a-3c90-4fc3-91bd-9582b20117dd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629172355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.1629172355
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3983428857
Short name T474
Test name
Test status
Simulation time 17616777 ps
CPU time 0.71 seconds
Started Jan 10 12:41:38 PM PST 24
Finished Jan 10 12:42:44 PM PST 24
Peak memory 200656 kb
Host smart-58619346-bbf9-4b69-a9b1-290431dfa8d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983428857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.3983428857
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.4006961322
Short name T527
Test name
Test status
Simulation time 55599497 ps
CPU time 0.82 seconds
Started Jan 10 12:41:29 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200592 kb
Host smart-05926571-4c12-48c5-b22c-a6fd433b1866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006961322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.4006961322
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.113461643
Short name T485
Test name
Test status
Simulation time 368729020 ps
CPU time 1.87 seconds
Started Jan 10 12:41:18 PM PST 24
Finished Jan 10 12:42:25 PM PST 24
Peak memory 200632 kb
Host smart-868da126-16bd-4ab1-98c5-50413563030a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113461643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.113461643
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.700810509
Short name T721
Test name
Test status
Simulation time 23047514 ps
CPU time 0.84 seconds
Started Jan 10 12:41:19 PM PST 24
Finished Jan 10 12:42:25 PM PST 24
Peak memory 200648 kb
Host smart-eb3ec793-0d83-4ae3-8bee-6daba57e7ccd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700810509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.700810509
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.3355245265
Short name T794
Test name
Test status
Simulation time 9298797671 ps
CPU time 36.8 seconds
Started Jan 10 12:41:18 PM PST 24
Finished Jan 10 12:43:00 PM PST 24
Peak memory 201132 kb
Host smart-58010993-1dce-42a6-9754-f4e94d1fdc8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355245265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.3355245265
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.3946108963
Short name T337
Test name
Test status
Simulation time 10499773140 ps
CPU time 157.3 seconds
Started Jan 10 12:41:19 PM PST 24
Finished Jan 10 12:45:01 PM PST 24
Peak memory 213668 kb
Host smart-ac2717af-2ac5-495d-8266-63c119ef4616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3946108963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.3946108963
Directory /workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.clkmgr_trans.1833945266
Short name T519
Test name
Test status
Simulation time 94305470 ps
CPU time 1.03 seconds
Started Jan 10 12:41:31 PM PST 24
Finished Jan 10 12:42:38 PM PST 24
Peak memory 200624 kb
Host smart-ef21e273-1f49-4e74-8aa1-ba5f18f050c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833945266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1833945266
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.1353373954
Short name T802
Test name
Test status
Simulation time 25697647 ps
CPU time 0.74 seconds
Started Jan 10 12:41:29 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200728 kb
Host smart-8f2024b0-0d92-4578-80ef-647b43313fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353373954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.1353373954
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.3301638708
Short name T440
Test name
Test status
Simulation time 21923046 ps
CPU time 0.83 seconds
Started Jan 10 12:41:30 PM PST 24
Finished Jan 10 12:42:37 PM PST 24
Peak memory 200648 kb
Host smart-29f7cb07-f673-4951-87f3-c4dbc71c93e0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301638708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.3301638708
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.249236093
Short name T944
Test name
Test status
Simulation time 23534047 ps
CPU time 0.71 seconds
Started Jan 10 12:41:24 PM PST 24
Finished Jan 10 12:42:31 PM PST 24
Peak memory 199676 kb
Host smart-946e5e38-c13f-4299-bc22-267baf96b840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249236093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.249236093
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.2870738512
Short name T911
Test name
Test status
Simulation time 22240294 ps
CPU time 0.72 seconds
Started Jan 10 12:41:33 PM PST 24
Finished Jan 10 12:42:39 PM PST 24
Peak memory 200724 kb
Host smart-5247ce54-17ec-4c21-bab9-06009aba76e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870738512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.2870738512
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.1161389208
Short name T973
Test name
Test status
Simulation time 14635834 ps
CPU time 0.73 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:42:22 PM PST 24
Peak memory 200692 kb
Host smart-80f24401-4d2a-4217-b4e5-84bfb1d121fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161389208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.1161389208
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.2373870718
Short name T568
Test name
Test status
Simulation time 2057560824 ps
CPU time 7.32 seconds
Started Jan 10 12:41:18 PM PST 24
Finished Jan 10 12:42:31 PM PST 24
Peak memory 201008 kb
Host smart-5930a7b0-a02e-4c2f-9441-61f3817d8950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373870718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.2373870718
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.1780502145
Short name T926
Test name
Test status
Simulation time 256980193 ps
CPU time 2.47 seconds
Started Jan 10 12:41:18 PM PST 24
Finished Jan 10 12:42:26 PM PST 24
Peak memory 200876 kb
Host smart-d4947c25-2421-4a2e-af86-67fe52d445e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780502145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.1780502145
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.722026679
Short name T382
Test name
Test status
Simulation time 39320662 ps
CPU time 0.87 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:21 PM PST 24
Peak memory 200736 kb
Host smart-8d2e869d-aedd-4308-bbb5-f5bcf6845f85
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722026679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.clkmgr_idle_intersig_mubi.722026679
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.910711657
Short name T435
Test name
Test status
Simulation time 27780491 ps
CPU time 0.79 seconds
Started Jan 10 12:41:27 PM PST 24
Finished Jan 10 12:42:33 PM PST 24
Peak memory 200708 kb
Host smart-0f0159e0-480c-4fb7-b57c-6ad8c1ea609f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910711657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.clkmgr_lc_clk_byp_req_intersig_mubi.910711657
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.317853731
Short name T360
Test name
Test status
Simulation time 15436179 ps
CPU time 0.77 seconds
Started Jan 10 12:41:27 PM PST 24
Finished Jan 10 12:42:34 PM PST 24
Peak memory 200664 kb
Host smart-9c813fef-966b-4213-bec7-85bf76bd7407
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317853731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.clkmgr_lc_ctrl_intersig_mubi.317853731
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.3409787040
Short name T776
Test name
Test status
Simulation time 21705454 ps
CPU time 0.76 seconds
Started Jan 10 12:41:16 PM PST 24
Finished Jan 10 12:42:24 PM PST 24
Peak memory 200612 kb
Host smart-f26f9e23-2bc2-481f-b648-bc4abef5f2aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409787040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.3409787040
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.881716556
Short name T626
Test name
Test status
Simulation time 648078685 ps
CPU time 3.17 seconds
Started Jan 10 12:41:27 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200928 kb
Host smart-abb9e03b-bcde-4e3a-a578-946f9d624356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881716556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.881716556
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.625479077
Short name T870
Test name
Test status
Simulation time 33187794 ps
CPU time 0.84 seconds
Started Jan 10 12:41:17 PM PST 24
Finished Jan 10 12:42:23 PM PST 24
Peak memory 200768 kb
Host smart-fa3d119b-b7e6-4c41-a21a-0a5f4ab165dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625479077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.625479077
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.865971753
Short name T765
Test name
Test status
Simulation time 1696954067 ps
CPU time 8.18 seconds
Started Jan 10 12:41:34 PM PST 24
Finished Jan 10 12:42:48 PM PST 24
Peak memory 201028 kb
Host smart-d0225cfe-747c-456f-b0ff-29f8ee65689f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865971753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.865971753
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.2171349588
Short name T849
Test name
Test status
Simulation time 83757951662 ps
CPU time 491.25 seconds
Started Jan 10 12:41:31 PM PST 24
Finished Jan 10 12:50:48 PM PST 24
Peak memory 211312 kb
Host smart-751062ae-71ec-4a1f-9d15-fb4753db3c93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2171349588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.2171349588
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.1626005829
Short name T503
Test name
Test status
Simulation time 24097829 ps
CPU time 0.83 seconds
Started Jan 10 12:41:24 PM PST 24
Finished Jan 10 12:42:32 PM PST 24
Peak memory 200768 kb
Host smart-3430dc32-69e2-4e1a-8004-1a695502b4bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626005829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1626005829
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.2847550177
Short name T993
Test name
Test status
Simulation time 30332308 ps
CPU time 0.8 seconds
Started Jan 10 12:41:33 PM PST 24
Finished Jan 10 12:42:40 PM PST 24
Peak memory 200812 kb
Host smart-8d10db44-3489-43f6-acb3-dc72edffb754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847550177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.2847550177
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.4116910478
Short name T469
Test name
Test status
Simulation time 77244209 ps
CPU time 1.07 seconds
Started Jan 10 12:41:26 PM PST 24
Finished Jan 10 12:42:34 PM PST 24
Peak memory 200780 kb
Host smart-0346efcc-cacf-4ed8-a34d-e99a077a5ad4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116910478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.4116910478
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.1747675288
Short name T131
Test name
Test status
Simulation time 19014758 ps
CPU time 0.68 seconds
Started Jan 10 12:41:26 PM PST 24
Finished Jan 10 12:42:33 PM PST 24
Peak memory 199500 kb
Host smart-4582ee44-b3f1-466f-950c-f951f7b7d213
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747675288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.1747675288
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.3356613515
Short name T404
Test name
Test status
Simulation time 14825140 ps
CPU time 0.74 seconds
Started Jan 10 12:41:32 PM PST 24
Finished Jan 10 12:42:38 PM PST 24
Peak memory 200648 kb
Host smart-79de03db-f28c-499d-a81b-d628edb64893
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356613515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.3356613515
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.1649476832
Short name T499
Test name
Test status
Simulation time 76587590 ps
CPU time 0.98 seconds
Started Jan 10 12:41:27 PM PST 24
Finished Jan 10 12:42:34 PM PST 24
Peak memory 200552 kb
Host smart-4b5b9388-4178-4824-9f92-d10acf6b5412
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649476832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.1649476832
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.2164448253
Short name T108
Test name
Test status
Simulation time 2354551235 ps
CPU time 18.75 seconds
Started Jan 10 12:41:39 PM PST 24
Finished Jan 10 12:43:03 PM PST 24
Peak memory 201040 kb
Host smart-8f39508f-a932-4be8-8be0-7ca670ba67df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164448253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.2164448253
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.2404148306
Short name T437
Test name
Test status
Simulation time 1114609423 ps
CPU time 5.29 seconds
Started Jan 10 12:41:31 PM PST 24
Finished Jan 10 12:42:42 PM PST 24
Peak memory 200780 kb
Host smart-94ed2bdb-7972-4ea2-8b65-368596b9ecaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404148306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.2404148306
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.3746712656
Short name T461
Test name
Test status
Simulation time 25333646 ps
CPU time 0.78 seconds
Started Jan 10 12:41:25 PM PST 24
Finished Jan 10 12:42:32 PM PST 24
Peak memory 200776 kb
Host smart-8e459a78-41a9-48de-b40f-413e9b9c4261
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746712656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.3746712656
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1281630530
Short name T905
Test name
Test status
Simulation time 81204112 ps
CPU time 0.99 seconds
Started Jan 10 12:41:32 PM PST 24
Finished Jan 10 12:42:39 PM PST 24
Peak memory 200792 kb
Host smart-8c954b05-9207-476e-88ab-b17f88b8206d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281630530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.1281630530
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2993136472
Short name T869
Test name
Test status
Simulation time 94937762 ps
CPU time 1.14 seconds
Started Jan 10 12:41:34 PM PST 24
Finished Jan 10 12:42:41 PM PST 24
Peak memory 200720 kb
Host smart-05eaef66-47f0-41af-b1b8-3373b7cf5ca0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993136472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.2993136472
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.4272637657
Short name T450
Test name
Test status
Simulation time 16101853 ps
CPU time 0.73 seconds
Started Jan 10 12:41:44 PM PST 24
Finished Jan 10 12:42:52 PM PST 24
Peak memory 200556 kb
Host smart-6e7af3e0-07d2-4128-b3d8-e190372a4df8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272637657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.4272637657
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.2966961344
Short name T915
Test name
Test status
Simulation time 1188212879 ps
CPU time 4.37 seconds
Started Jan 10 12:41:25 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200804 kb
Host smart-e3262f82-2051-4893-966e-db87cd233929
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966961344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.2966961344
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.2838801572
Short name T767
Test name
Test status
Simulation time 16910113 ps
CPU time 0.8 seconds
Started Jan 10 12:41:29 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200688 kb
Host smart-186dc84e-31d5-464f-a65c-94514f4e7c04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838801572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.2838801572
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.1547072818
Short name T532
Test name
Test status
Simulation time 8424460168 ps
CPU time 31.7 seconds
Started Jan 10 12:41:30 PM PST 24
Finished Jan 10 12:43:08 PM PST 24
Peak memory 201052 kb
Host smart-85dbad59-da62-4387-b081-87647daa5999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547072818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.1547072818
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.3484721103
Short name T363
Test name
Test status
Simulation time 13845848602 ps
CPU time 260.96 seconds
Started Jan 10 12:41:33 PM PST 24
Finished Jan 10 12:47:00 PM PST 24
Peak memory 209312 kb
Host smart-f17fe729-125c-42db-b983-fbaf317436b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3484721103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.3484721103
Directory /workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.clkmgr_trans.3991266831
Short name T498
Test name
Test status
Simulation time 58232140 ps
CPU time 0.89 seconds
Started Jan 10 12:41:28 PM PST 24
Finished Jan 10 12:42:34 PM PST 24
Peak memory 200752 kb
Host smart-483f9c29-b975-4fcc-b52d-c9b933040c63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991266831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.3991266831
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.3907935555
Short name T681
Test name
Test status
Simulation time 62900878 ps
CPU time 0.9 seconds
Started Jan 10 12:41:33 PM PST 24
Finished Jan 10 12:42:39 PM PST 24
Peak memory 200732 kb
Host smart-30f587fa-7f60-4e02-a8f0-ef714677362e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907935555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.3907935555
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.939670834
Short name T712
Test name
Test status
Simulation time 41385716 ps
CPU time 0.85 seconds
Started Jan 10 12:41:26 PM PST 24
Finished Jan 10 12:42:33 PM PST 24
Peak memory 200808 kb
Host smart-6f3a3489-5d2a-4ebf-9a02-69bdc2d446c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939670834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.939670834
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.1799129571
Short name T705
Test name
Test status
Simulation time 38274290 ps
CPU time 0.73 seconds
Started Jan 10 12:41:34 PM PST 24
Finished Jan 10 12:42:41 PM PST 24
Peak memory 200592 kb
Host smart-734193eb-83ff-4fe6-8a98-132cca7bdefe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799129571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1799129571
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.3018250340
Short name T478
Test name
Test status
Simulation time 23684338 ps
CPU time 0.82 seconds
Started Jan 10 12:41:40 PM PST 24
Finished Jan 10 12:42:46 PM PST 24
Peak memory 200720 kb
Host smart-b0ea49c2-4e23-48f2-829f-11a6616a7a11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018250340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.3018250340
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.2772859631
Short name T684
Test name
Test status
Simulation time 136937175 ps
CPU time 1.08 seconds
Started Jan 10 12:41:25 PM PST 24
Finished Jan 10 12:42:32 PM PST 24
Peak memory 200592 kb
Host smart-78f99e1c-34de-44cc-a014-806a27f2fadd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772859631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.2772859631
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.1974176032
Short name T629
Test name
Test status
Simulation time 2120743803 ps
CPU time 16.3 seconds
Started Jan 10 12:41:33 PM PST 24
Finished Jan 10 12:42:55 PM PST 24
Peak memory 200916 kb
Host smart-0d428e14-0277-4eca-8ed1-c7369969f1ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974176032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1974176032
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.2656422566
Short name T526
Test name
Test status
Simulation time 503301970 ps
CPU time 3.14 seconds
Started Jan 10 12:41:26 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200832 kb
Host smart-c9fa8ee0-a628-4289-8827-b0ceb7050d6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656422566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.2656422566
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.4009710057
Short name T508
Test name
Test status
Simulation time 34389660 ps
CPU time 0.98 seconds
Started Jan 10 12:41:33 PM PST 24
Finished Jan 10 12:42:39 PM PST 24
Peak memory 200688 kb
Host smart-bb5d98d3-cdc8-4473-90c8-5041ccf14b63
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009710057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.4009710057
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1502693807
Short name T691
Test name
Test status
Simulation time 35058097 ps
CPU time 0.79 seconds
Started Jan 10 12:41:26 PM PST 24
Finished Jan 10 12:42:33 PM PST 24
Peak memory 200668 kb
Host smart-331f278c-91c3-4d44-9509-99527e102e6e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502693807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.1502693807
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.208139693
Short name T882
Test name
Test status
Simulation time 38694224 ps
CPU time 0.76 seconds
Started Jan 10 12:41:37 PM PST 24
Finished Jan 10 12:42:43 PM PST 24
Peak memory 200728 kb
Host smart-7f258c3c-2257-4815-b32b-ebc826937607
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208139693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.clkmgr_lc_ctrl_intersig_mubi.208139693
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.3530679279
Short name T661
Test name
Test status
Simulation time 22188511 ps
CPU time 0.74 seconds
Started Jan 10 12:41:30 PM PST 24
Finished Jan 10 12:42:37 PM PST 24
Peak memory 200552 kb
Host smart-662b7b6e-0277-4a2c-ab9b-1c98de809360
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530679279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.3530679279
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.2340640429
Short name T852
Test name
Test status
Simulation time 893631087 ps
CPU time 5.08 seconds
Started Jan 10 12:41:38 PM PST 24
Finished Jan 10 12:42:49 PM PST 24
Peak memory 200888 kb
Host smart-730a4e6f-a7e9-4561-a881-87c25d0ecc7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340640429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.2340640429
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.2255954415
Short name T303
Test name
Test status
Simulation time 132904631 ps
CPU time 1.18 seconds
Started Jan 10 12:41:25 PM PST 24
Finished Jan 10 12:42:32 PM PST 24
Peak memory 200660 kb
Host smart-d0fb7fbd-d4ec-48e6-8f3b-403288e052ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255954415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.2255954415
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.1656786040
Short name T812
Test name
Test status
Simulation time 2170732683 ps
CPU time 8.78 seconds
Started Jan 10 12:41:35 PM PST 24
Finished Jan 10 12:42:50 PM PST 24
Peak memory 201020 kb
Host smart-6dd3248a-c478-4df5-ad9f-ef822722d2e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656786040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.1656786040
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.1645110345
Short name T42
Test name
Test status
Simulation time 391026670331 ps
CPU time 1426.56 seconds
Started Jan 10 12:41:34 PM PST 24
Finished Jan 10 01:06:26 PM PST 24
Peak memory 217500 kb
Host smart-6b0a7a0f-1622-4ba1-9572-1692b5f0e3ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1645110345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.1645110345
Directory /workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.clkmgr_trans.2495934199
Short name T979
Test name
Test status
Simulation time 28552562 ps
CPU time 0.94 seconds
Started Jan 10 12:41:29 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200692 kb
Host smart-a4a47aee-a890-48cb-8f43-fb8df8e3a5dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495934199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.2495934199
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.3410855484
Short name T722
Test name
Test status
Simulation time 51793883 ps
CPU time 0.79 seconds
Started Jan 10 12:41:29 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200664 kb
Host smart-2778bbcd-a913-40ec-b62e-0dd82e399da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410855484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.3410855484
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.854822436
Short name T424
Test name
Test status
Simulation time 14895550 ps
CPU time 0.69 seconds
Started Jan 10 12:41:39 PM PST 24
Finished Jan 10 12:42:45 PM PST 24
Peak memory 200676 kb
Host smart-e64a4c1e-7d53-47a7-957c-61ac6e3e4f8f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854822436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.854822436
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.1398765595
Short name T581
Test name
Test status
Simulation time 31681082 ps
CPU time 0.72 seconds
Started Jan 10 12:41:39 PM PST 24
Finished Jan 10 12:42:46 PM PST 24
Peak memory 199680 kb
Host smart-922afea9-6e54-4e4b-8386-b0fcd2195859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398765595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.1398765595
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.1234701828
Short name T957
Test name
Test status
Simulation time 29176968 ps
CPU time 0.81 seconds
Started Jan 10 12:41:27 PM PST 24
Finished Jan 10 12:42:34 PM PST 24
Peak memory 200800 kb
Host smart-5aec7c45-195a-4ac2-9739-98f8778dad63
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234701828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.1234701828
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.1455142624
Short name T458
Test name
Test status
Simulation time 54493614 ps
CPU time 0.85 seconds
Started Jan 10 12:41:32 PM PST 24
Finished Jan 10 12:42:38 PM PST 24
Peak memory 200652 kb
Host smart-3f2c6100-c072-4e96-bcc2-b29fec371e22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455142624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.1455142624
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.3921745415
Short name T467
Test name
Test status
Simulation time 1275668555 ps
CPU time 10.32 seconds
Started Jan 10 12:41:36 PM PST 24
Finished Jan 10 12:42:53 PM PST 24
Peak memory 200712 kb
Host smart-0351da89-2603-4cc4-8a4e-7bd38204fbae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921745415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.3921745415
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.1262938776
Short name T963
Test name
Test status
Simulation time 862859436 ps
CPU time 4.98 seconds
Started Jan 10 12:41:31 PM PST 24
Finished Jan 10 12:42:41 PM PST 24
Peak memory 200828 kb
Host smart-7e39e04a-303a-4b1b-839f-2b49328a282a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262938776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.1262938776
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.750327866
Short name T570
Test name
Test status
Simulation time 25501609 ps
CPU time 0.81 seconds
Started Jan 10 12:41:33 PM PST 24
Finished Jan 10 12:42:40 PM PST 24
Peak memory 200596 kb
Host smart-55fb2935-4787-423e-9779-eecdfa302d9f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750327866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.clkmgr_idle_intersig_mubi.750327866
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.306706934
Short name T405
Test name
Test status
Simulation time 67360985 ps
CPU time 0.89 seconds
Started Jan 10 12:41:43 PM PST 24
Finished Jan 10 12:42:50 PM PST 24
Peak memory 200644 kb
Host smart-43b39f25-b307-4475-9433-8b69c971defd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306706934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.clkmgr_lc_clk_byp_req_intersig_mubi.306706934
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.309343864
Short name T333
Test name
Test status
Simulation time 18370939 ps
CPU time 0.75 seconds
Started Jan 10 12:41:39 PM PST 24
Finished Jan 10 12:42:45 PM PST 24
Peak memory 200656 kb
Host smart-a51de590-1331-47ae-acd0-4e4e598cee5c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309343864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.clkmgr_lc_ctrl_intersig_mubi.309343864
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.3340991207
Short name T296
Test name
Test status
Simulation time 22576239 ps
CPU time 0.74 seconds
Started Jan 10 12:41:27 PM PST 24
Finished Jan 10 12:42:33 PM PST 24
Peak memory 200668 kb
Host smart-c9e4b8b5-eb1f-4d41-8957-a37445c79d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340991207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.3340991207
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.3412619384
Short name T309
Test name
Test status
Simulation time 199333823 ps
CPU time 1.26 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:42:57 PM PST 24
Peak memory 200752 kb
Host smart-ec7d77a5-7641-47a1-8287-ffb630aabdfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412619384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.3412619384
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.4092115042
Short name T706
Test name
Test status
Simulation time 26125806 ps
CPU time 0.77 seconds
Started Jan 10 12:41:40 PM PST 24
Finished Jan 10 12:42:46 PM PST 24
Peak memory 200648 kb
Host smart-40e71baa-5e62-460a-8895-a5d9efa6cbb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092115042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.4092115042
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.180779381
Short name T862
Test name
Test status
Simulation time 1862810758 ps
CPU time 14.16 seconds
Started Jan 10 12:41:30 PM PST 24
Finished Jan 10 12:42:50 PM PST 24
Peak memory 200960 kb
Host smart-80bd3a2a-e92f-4e30-9af1-3fe543ca4bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180779381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.180779381
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.3267234236
Short name T374
Test name
Test status
Simulation time 46679003532 ps
CPU time 406.92 seconds
Started Jan 10 12:41:34 PM PST 24
Finished Jan 10 12:49:27 PM PST 24
Peak memory 209296 kb
Host smart-f3188ab8-4d7b-4075-99d7-1dcf1f52d971
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3267234236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.3267234236
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.clkmgr_trans.1623670063
Short name T305
Test name
Test status
Simulation time 91191545 ps
CPU time 0.96 seconds
Started Jan 10 12:41:38 PM PST 24
Finished Jan 10 12:42:44 PM PST 24
Peak memory 200640 kb
Host smart-394c4025-9eb6-4331-9b5d-07dab3592b59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623670063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1623670063
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.1787374259
Short name T359
Test name
Test status
Simulation time 21502815 ps
CPU time 0.77 seconds
Started Jan 10 12:40:10 PM PST 24
Finished Jan 10 12:40:57 PM PST 24
Peak memory 200700 kb
Host smart-7ae81ebc-febd-463e-a3fd-7c0819750bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787374259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.1787374259
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1924014704
Short name T401
Test name
Test status
Simulation time 18570886 ps
CPU time 0.84 seconds
Started Jan 10 12:39:48 PM PST 24
Finished Jan 10 12:40:21 PM PST 24
Peak memory 200760 kb
Host smart-3355111e-6a28-4a5e-9b50-92bcccf49e81
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924014704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.1924014704
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.3879214259
Short name T816
Test name
Test status
Simulation time 36508279 ps
CPU time 0.72 seconds
Started Jan 10 12:40:01 PM PST 24
Finished Jan 10 12:40:43 PM PST 24
Peak memory 200508 kb
Host smart-43738dd7-e384-4668-a497-956271930ef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879214259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.3879214259
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.764145375
Short name T746
Test name
Test status
Simulation time 112488532 ps
CPU time 1.1 seconds
Started Jan 10 12:39:47 PM PST 24
Finished Jan 10 12:40:19 PM PST 24
Peak memory 200784 kb
Host smart-47848ef6-032e-4c34-9ab9-a89553ae058c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764145375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.clkmgr_div_intersig_mubi.764145375
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.31587027
Short name T399
Test name
Test status
Simulation time 29004042 ps
CPU time 0.81 seconds
Started Jan 10 12:39:49 PM PST 24
Finished Jan 10 12:40:22 PM PST 24
Peak memory 200592 kb
Host smart-f5707187-bf5e-4adc-aefb-fc8a0403d23c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31587027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.31587027
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.1605429540
Short name T415
Test name
Test status
Simulation time 371214982 ps
CPU time 2.05 seconds
Started Jan 10 12:40:09 PM PST 24
Finished Jan 10 12:40:58 PM PST 24
Peak memory 200672 kb
Host smart-6a05b0a6-1b60-41c2-a554-fcca3a3bf62f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605429540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1605429540
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.653874669
Short name T445
Test name
Test status
Simulation time 2293811453 ps
CPU time 16.11 seconds
Started Jan 10 12:39:50 PM PST 24
Finished Jan 10 12:40:39 PM PST 24
Peak memory 200952 kb
Host smart-189c60ab-7442-4dd5-a3f1-c6139f0e7137
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653874669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_tim
eout.653874669
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.3749454252
Short name T919
Test name
Test status
Simulation time 17349654 ps
CPU time 0.82 seconds
Started Jan 10 12:40:01 PM PST 24
Finished Jan 10 12:40:44 PM PST 24
Peak memory 200732 kb
Host smart-a93a38cf-16cb-4299-85e6-178c48845884
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749454252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.3749454252
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.703915773
Short name T111
Test name
Test status
Simulation time 49931306 ps
CPU time 0.84 seconds
Started Jan 10 12:40:02 PM PST 24
Finished Jan 10 12:40:47 PM PST 24
Peak memory 200636 kb
Host smart-4cd64ef0-9279-4d5d-8e32-435bb588d223
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703915773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.clkmgr_lc_clk_byp_req_intersig_mubi.703915773
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2653023579
Short name T431
Test name
Test status
Simulation time 19162826 ps
CPU time 0.79 seconds
Started Jan 10 12:39:52 PM PST 24
Finished Jan 10 12:40:28 PM PST 24
Peak memory 200744 kb
Host smart-93a8e2c7-e282-4835-b6b8-c748bab9e6f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653023579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.2653023579
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.1138930768
Short name T700
Test name
Test status
Simulation time 40784917 ps
CPU time 0.79 seconds
Started Jan 10 12:39:49 PM PST 24
Finished Jan 10 12:40:23 PM PST 24
Peak memory 200640 kb
Host smart-9b54085b-6552-47f7-ac4e-afdb17cacba8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138930768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.1138930768
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.1084798914
Short name T647
Test name
Test status
Simulation time 690632532 ps
CPU time 4.1 seconds
Started Jan 10 12:39:52 PM PST 24
Finished Jan 10 12:40:30 PM PST 24
Peak memory 200828 kb
Host smart-0f33c7a7-282a-4cfd-a009-acf1bc9d3cc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084798914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.1084798914
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.3138966413
Short name T53
Test name
Test status
Simulation time 459114251 ps
CPU time 3.36 seconds
Started Jan 10 12:40:10 PM PST 24
Finished Jan 10 12:41:00 PM PST 24
Peak memory 216556 kb
Host smart-d065ea56-56c3-4406-9245-8cd73d686b12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138966413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.3138966413
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.3956454544
Short name T725
Test name
Test status
Simulation time 94830328 ps
CPU time 1.09 seconds
Started Jan 10 12:39:49 PM PST 24
Finished Jan 10 12:40:23 PM PST 24
Peak memory 200784 kb
Host smart-ef5629a9-173c-42c7-a004-3953fc6765ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956454544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.3956454544
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.2604204494
Short name T420
Test name
Test status
Simulation time 3683935380 ps
CPU time 26.21 seconds
Started Jan 10 12:40:01 PM PST 24
Finished Jan 10 12:41:09 PM PST 24
Peak memory 201064 kb
Host smart-887bf960-fb04-4bcf-b1ef-e75dd5dbe232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604204494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.2604204494
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.1121333283
Short name T602
Test name
Test status
Simulation time 66514381183 ps
CPU time 414 seconds
Started Jan 10 12:39:50 PM PST 24
Finished Jan 10 12:47:18 PM PST 24
Peak memory 209824 kb
Host smart-e88673cc-156d-4330-b289-d25030bc2039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1121333283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.1121333283
Directory /workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.clkmgr_trans.1178776492
Short name T326
Test name
Test status
Simulation time 22803007 ps
CPU time 0.85 seconds
Started Jan 10 12:39:51 PM PST 24
Finished Jan 10 12:40:26 PM PST 24
Peak memory 200672 kb
Host smart-6120de1b-62a3-4efd-8bb9-05a60f3b7bdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178776492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.1178776492
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.1632592436
Short name T304
Test name
Test status
Simulation time 22817330 ps
CPU time 0.71 seconds
Started Jan 10 12:41:46 PM PST 24
Finished Jan 10 12:42:55 PM PST 24
Peak memory 200616 kb
Host smart-773e0de2-43ba-46d9-909a-48fd96c9b341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632592436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.1632592436
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.4021154628
Short name T930
Test name
Test status
Simulation time 16516158 ps
CPU time 0.72 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200604 kb
Host smart-a465b96d-d1dc-4f0f-8636-09f974d0efa8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021154628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.4021154628
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.1553711940
Short name T130
Test name
Test status
Simulation time 48966221 ps
CPU time 0.8 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 199368 kb
Host smart-6192624f-d63f-49ea-aa19-6acd97ae6853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553711940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1553711940
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.1732356087
Short name T102
Test name
Test status
Simulation time 52904958 ps
CPU time 0.8 seconds
Started Jan 10 12:41:35 PM PST 24
Finished Jan 10 12:42:43 PM PST 24
Peak memory 200776 kb
Host smart-6e1332ef-8e8c-4a2e-b440-1ead11b007bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732356087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.1732356087
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.1677255698
Short name T864
Test name
Test status
Simulation time 33550371 ps
CPU time 0.82 seconds
Started Jan 10 12:41:43 PM PST 24
Finished Jan 10 12:42:50 PM PST 24
Peak memory 200700 kb
Host smart-a99c27f2-e980-4159-b104-20451c154d4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677255698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1677255698
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.127080046
Short name T456
Test name
Test status
Simulation time 686019485 ps
CPU time 4.14 seconds
Started Jan 10 12:41:33 PM PST 24
Finished Jan 10 12:42:43 PM PST 24
Peak memory 200680 kb
Host smart-8d4252b9-9da0-4458-9266-44d6393be4f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127080046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.127080046
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.1554717366
Short name T314
Test name
Test status
Simulation time 1683963153 ps
CPU time 5.88 seconds
Started Jan 10 12:41:38 PM PST 24
Finished Jan 10 12:42:49 PM PST 24
Peak memory 200792 kb
Host smart-bd44e4fc-5c6f-4481-a454-3557a0df129e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554717366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.1554717366
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.76312289
Short name T756
Test name
Test status
Simulation time 15920777 ps
CPU time 0.74 seconds
Started Jan 10 12:41:34 PM PST 24
Finished Jan 10 12:42:40 PM PST 24
Peak memory 200768 kb
Host smart-b1d190de-b2ab-4849-84b8-892ddd3b71a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76312289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.clkmgr_idle_intersig_mubi.76312289
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.2775101196
Short name T668
Test name
Test status
Simulation time 64275563 ps
CPU time 0.93 seconds
Started Jan 10 12:41:39 PM PST 24
Finished Jan 10 12:42:46 PM PST 24
Peak memory 200648 kb
Host smart-2cec1f78-0a67-4dfe-81e7-e4e03ab68824
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775101196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.2775101196
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.4279350468
Short name T367
Test name
Test status
Simulation time 83665968 ps
CPU time 1.03 seconds
Started Jan 10 12:41:36 PM PST 24
Finished Jan 10 12:42:44 PM PST 24
Peak memory 200708 kb
Host smart-4ba5e508-6d6a-4c86-9110-c9eb41968368
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279350468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.4279350468
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.178667074
Short name T966
Test name
Test status
Simulation time 17245009 ps
CPU time 0.76 seconds
Started Jan 10 12:41:35 PM PST 24
Finished Jan 10 12:42:42 PM PST 24
Peak memory 200696 kb
Host smart-cf3f3da6-95f4-4034-a75a-29101cf26dc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178667074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.178667074
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.1433750332
Short name T730
Test name
Test status
Simulation time 581653586 ps
CPU time 2.49 seconds
Started Jan 10 12:41:34 PM PST 24
Finished Jan 10 12:42:42 PM PST 24
Peak memory 200832 kb
Host smart-67eddde3-d7ab-4d64-ad73-b776a803e19d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433750332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.1433750332
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.4031209977
Short name T943
Test name
Test status
Simulation time 25651274 ps
CPU time 0.77 seconds
Started Jan 10 12:41:44 PM PST 24
Finished Jan 10 12:42:52 PM PST 24
Peak memory 200740 kb
Host smart-2719e023-b8f0-4757-bfc8-bf51440ad9cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031209977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.4031209977
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.2285123090
Short name T822
Test name
Test status
Simulation time 852613532 ps
CPU time 4.96 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200720 kb
Host smart-b07cc44a-df0f-419e-9080-cbf00fd00577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285123090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.2285123090
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.4231737949
Short name T14
Test name
Test status
Simulation time 187804733596 ps
CPU time 1313.42 seconds
Started Jan 10 12:41:45 PM PST 24
Finished Jan 10 01:04:46 PM PST 24
Peak memory 209252 kb
Host smart-6965972e-69c1-4876-b15f-29c5342f7eb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4231737949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.4231737949
Directory /workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.clkmgr_trans.2982941968
Short name T971
Test name
Test status
Simulation time 110737175 ps
CPU time 1.12 seconds
Started Jan 10 12:41:34 PM PST 24
Finished Jan 10 12:42:41 PM PST 24
Peak memory 200800 kb
Host smart-748a4b74-a4f2-45ef-9336-9803a198069e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982941968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.2982941968
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.3482766156
Short name T317
Test name
Test status
Simulation time 30154021 ps
CPU time 0.82 seconds
Started Jan 10 12:41:42 PM PST 24
Finished Jan 10 12:42:49 PM PST 24
Peak memory 200772 kb
Host smart-a3cc6ac8-34be-4907-827e-25ac7454d127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482766156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.3482766156
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1807015420
Short name T920
Test name
Test status
Simulation time 196844341 ps
CPU time 1.39 seconds
Started Jan 10 12:41:52 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200528 kb
Host smart-f28a2c6c-0d27-4963-9a5c-092d2a903336
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807015420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.1807015420
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.1076927373
Short name T591
Test name
Test status
Simulation time 23315659 ps
CPU time 0.7 seconds
Started Jan 10 12:41:34 PM PST 24
Finished Jan 10 12:42:41 PM PST 24
Peak memory 200640 kb
Host smart-ab1a162f-4f7d-4445-91f7-08992f0eea31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076927373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.1076927373
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.2288250476
Short name T295
Test name
Test status
Simulation time 27310122 ps
CPU time 0.74 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:42:56 PM PST 24
Peak memory 200744 kb
Host smart-39cbfc24-4322-4266-922e-f4d9f085d748
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288250476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.2288250476
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.2466786405
Short name T688
Test name
Test status
Simulation time 49958842 ps
CPU time 0.92 seconds
Started Jan 10 12:41:52 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200484 kb
Host smart-86f67894-4aa7-4905-8265-3d34c462cab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466786405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.2466786405
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.2094580519
Short name T628
Test name
Test status
Simulation time 1651714574 ps
CPU time 8.94 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:43:06 PM PST 24
Peak memory 200728 kb
Host smart-c1f98354-acd3-40ae-b640-0f414ae108cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094580519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.2094580519
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.1570823830
Short name T427
Test name
Test status
Simulation time 637523389 ps
CPU time 2.83 seconds
Started Jan 10 12:41:35 PM PST 24
Finished Jan 10 12:42:44 PM PST 24
Peak memory 200720 kb
Host smart-45c7b592-0958-4890-b4ea-498d9211c46e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570823830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.1570823830
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.873286308
Short name T18
Test name
Test status
Simulation time 59979693 ps
CPU time 1 seconds
Started Jan 10 12:41:39 PM PST 24
Finished Jan 10 12:42:46 PM PST 24
Peak memory 200632 kb
Host smart-a49aa321-85d3-4bc5-99ac-0176064008fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873286308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.clkmgr_idle_intersig_mubi.873286308
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.1056594311
Short name T843
Test name
Test status
Simulation time 73126616 ps
CPU time 0.94 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200756 kb
Host smart-aa11f4a6-e3b6-4a8b-8439-b98508c5ed25
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056594311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.1056594311
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.177008789
Short name T61
Test name
Test status
Simulation time 24611115 ps
CPU time 0.84 seconds
Started Jan 10 12:41:52 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200528 kb
Host smart-17149498-44e7-4906-991b-27b5d860f0b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177008789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.clkmgr_lc_ctrl_intersig_mubi.177008789
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.3246922010
Short name T637
Test name
Test status
Simulation time 47605615 ps
CPU time 0.79 seconds
Started Jan 10 12:41:51 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200488 kb
Host smart-df4fa901-1253-43a5-b107-64c58f2b96da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246922010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.3246922010
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.1958436645
Short name T356
Test name
Test status
Simulation time 89090104 ps
CPU time 0.95 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200736 kb
Host smart-feaa3b42-28d6-49c7-af61-ec9c7235930a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958436645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.1958436645
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.479499183
Short name T656
Test name
Test status
Simulation time 3228537859 ps
CPU time 17.69 seconds
Started Jan 10 12:41:35 PM PST 24
Finished Jan 10 12:42:59 PM PST 24
Peak memory 201116 kb
Host smart-7b1e2234-5e2b-4848-acfb-7990b1a3be20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479499183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.479499183
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.3202584970
Short name T477
Test name
Test status
Simulation time 244275385154 ps
CPU time 1630.75 seconds
Started Jan 10 12:41:51 PM PST 24
Finished Jan 10 01:10:12 PM PST 24
Peak memory 217312 kb
Host smart-8ad13de0-f99b-44d0-b413-55e097fac367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3202584970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.3202584970
Directory /workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.clkmgr_trans.1284884071
Short name T977
Test name
Test status
Simulation time 24933496 ps
CPU time 0.91 seconds
Started Jan 10 12:41:39 PM PST 24
Finished Jan 10 12:42:45 PM PST 24
Peak memory 200796 kb
Host smart-048e16f9-5013-4e4f-8aa5-83ef1b1d9549
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284884071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.1284884071
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.1930614526
Short name T388
Test name
Test status
Simulation time 125107931 ps
CPU time 0.99 seconds
Started Jan 10 12:41:43 PM PST 24
Finished Jan 10 12:42:50 PM PST 24
Peak memory 200612 kb
Host smart-e7ec53c4-4894-4aeb-b601-47e0113a1d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930614526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.1930614526
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2372043954
Short name T589
Test name
Test status
Simulation time 49296896 ps
CPU time 0.86 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200700 kb
Host smart-3f65b0c8-b396-4b0d-a476-50988255d101
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372043954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.2372043954
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.3907320200
Short name T636
Test name
Test status
Simulation time 26686496 ps
CPU time 0.71 seconds
Started Jan 10 01:20:59 PM PST 24
Finished Jan 10 01:21:04 PM PST 24
Peak memory 199584 kb
Host smart-631f5af8-93ff-47b9-8154-e77be46f4167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907320200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.3907320200
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.1834872889
Short name T906
Test name
Test status
Simulation time 39759731 ps
CPU time 0.86 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200748 kb
Host smart-fd09124d-a052-4794-8ff5-4db82b41fb0a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834872889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.1834872889
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.1135850534
Short name T599
Test name
Test status
Simulation time 24710863 ps
CPU time 0.83 seconds
Started Jan 10 12:41:30 PM PST 24
Finished Jan 10 12:42:36 PM PST 24
Peak memory 200612 kb
Host smart-abc0dec6-6121-468f-8515-bc7afc71e021
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135850534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1135850534
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.3473120493
Short name T845
Test name
Test status
Simulation time 1040405320 ps
CPU time 7.77 seconds
Started Jan 10 12:41:44 PM PST 24
Finished Jan 10 12:42:59 PM PST 24
Peak memory 200580 kb
Host smart-4dc54ad7-6e76-4990-8944-4cbecb9943d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473120493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.3473120493
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.3380471430
Short name T482
Test name
Test status
Simulation time 1911889394 ps
CPU time 8.34 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:43:04 PM PST 24
Peak memory 200820 kb
Host smart-4c479520-cc65-498a-a561-20e25405f4bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380471430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.3380471430
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.1259590848
Short name T828
Test name
Test status
Simulation time 91270126 ps
CPU time 1.11 seconds
Started Jan 10 12:57:02 PM PST 24
Finished Jan 10 12:58:16 PM PST 24
Peak memory 200804 kb
Host smart-0b7864a6-4fe8-489c-961a-2da42bbe8c4e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259590848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.1259590848
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.2237836055
Short name T624
Test name
Test status
Simulation time 27059658 ps
CPU time 0.78 seconds
Started Jan 10 12:41:37 PM PST 24
Finished Jan 10 12:42:44 PM PST 24
Peak memory 200708 kb
Host smart-359fdb64-ee26-4e8a-b42e-330ac9d6c92e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237836055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.2237836055
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.700748523
Short name T778
Test name
Test status
Simulation time 83494168 ps
CPU time 0.96 seconds
Started Jan 10 12:49:06 PM PST 24
Finished Jan 10 12:50:38 PM PST 24
Peak memory 200612 kb
Host smart-9b0f5346-bd07-4e64-812f-a0f638952f92
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700748523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.clkmgr_lc_ctrl_intersig_mubi.700748523
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.3715963529
Short name T763
Test name
Test status
Simulation time 14665041 ps
CPU time 0.74 seconds
Started Jan 10 12:41:37 PM PST 24
Finished Jan 10 12:42:44 PM PST 24
Peak memory 200764 kb
Host smart-707ae8d2-2a76-4436-8d73-3d43d0c6122a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715963529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.3715963529
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.771580436
Short name T323
Test name
Test status
Simulation time 339364491 ps
CPU time 1.65 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 199544 kb
Host smart-c341f828-db9d-4e9a-91a9-82ab3a17389d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771580436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.771580436
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.3516184412
Short name T861
Test name
Test status
Simulation time 31717018 ps
CPU time 0.82 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:42:56 PM PST 24
Peak memory 200740 kb
Host smart-b4b8b0ef-b8ce-4551-8ff3-98112570e81b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516184412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.3516184412
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.636848051
Short name T968
Test name
Test status
Simulation time 11894380344 ps
CPU time 71.6 seconds
Started Jan 10 12:41:51 PM PST 24
Finished Jan 10 12:44:13 PM PST 24
Peak memory 200872 kb
Host smart-62c6e9ca-6fdd-4e06-99f5-18a640f42b66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636848051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.636848051
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.3967206445
Short name T609
Test name
Test status
Simulation time 53562802975 ps
CPU time 308.7 seconds
Started Jan 10 12:41:51 PM PST 24
Finished Jan 10 12:48:10 PM PST 24
Peak memory 209116 kb
Host smart-76f405d4-d6c0-4092-b832-f811ef59a2f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3967206445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.3967206445
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.2830449496
Short name T986
Test name
Test status
Simulation time 73396944 ps
CPU time 0.94 seconds
Started Jan 10 12:41:32 PM PST 24
Finished Jan 10 12:42:38 PM PST 24
Peak memory 200720 kb
Host smart-069a0cd2-a314-476b-ab20-ebc926b072f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830449496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.2830449496
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.2321600056
Short name T875
Test name
Test status
Simulation time 38415082 ps
CPU time 0.75 seconds
Started Jan 10 12:41:46 PM PST 24
Finished Jan 10 12:42:56 PM PST 24
Peak memory 200808 kb
Host smart-7316662b-9234-482d-8977-aa7f83d8d5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321600056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.2321600056
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.3693209921
Short name T343
Test name
Test status
Simulation time 29425802 ps
CPU time 0.87 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200604 kb
Host smart-f6021777-061a-407d-a988-85d41d3bd955
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693209921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.3693209921
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.3417729979
Short name T839
Test name
Test status
Simulation time 29904110 ps
CPU time 0.7 seconds
Started Jan 10 12:41:43 PM PST 24
Finished Jan 10 12:42:50 PM PST 24
Peak memory 199680 kb
Host smart-384e2cf9-31c6-4757-9736-d231bbd7a135
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417729979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.3417729979
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.2877519603
Short name T826
Test name
Test status
Simulation time 26323904 ps
CPU time 0.72 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:42:56 PM PST 24
Peak memory 200564 kb
Host smart-af319edb-5f69-4a90-a12f-7276bb4b5937
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877519603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.2877519603
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.129261716
Short name T522
Test name
Test status
Simulation time 47419599 ps
CPU time 0.85 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200344 kb
Host smart-cd0c5c08-bd6c-4f60-81bf-57da1c4b0969
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129261716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.129261716
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.4015718472
Short name T394
Test name
Test status
Simulation time 675190498 ps
CPU time 5.46 seconds
Started Jan 10 12:41:43 PM PST 24
Finished Jan 10 12:42:55 PM PST 24
Peak memory 200584 kb
Host smart-e30fb55f-8597-443b-b3e5-0cf933a0c59c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015718472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.4015718472
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.1550940050
Short name T879
Test name
Test status
Simulation time 1337446486 ps
CPU time 9.76 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:43:06 PM PST 24
Peak memory 200784 kb
Host smart-1642f249-b138-4190-8f71-889654288848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550940050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.1550940050
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.650938581
Short name T876
Test name
Test status
Simulation time 67138457 ps
CPU time 0.93 seconds
Started Jan 10 12:41:35 PM PST 24
Finished Jan 10 12:42:42 PM PST 24
Peak memory 200732 kb
Host smart-682f257f-96ce-4cbc-be96-853abada442d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650938581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.clkmgr_idle_intersig_mubi.650938581
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2345900293
Short name T675
Test name
Test status
Simulation time 158792491 ps
CPU time 1.15 seconds
Started Jan 10 12:41:37 PM PST 24
Finished Jan 10 12:42:44 PM PST 24
Peak memory 200768 kb
Host smart-771314da-7ab1-4d3c-94a4-aa84663f40df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345900293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.2345900293
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.2585112533
Short name T279
Test name
Test status
Simulation time 17599035 ps
CPU time 0.75 seconds
Started Jan 10 12:41:46 PM PST 24
Finished Jan 10 12:42:55 PM PST 24
Peak memory 200624 kb
Host smart-3884f508-92ab-47fd-a416-12a1abab49a7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585112533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.2585112533
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.3653618948
Short name T885
Test name
Test status
Simulation time 16288591 ps
CPU time 0.76 seconds
Started Jan 10 12:41:42 PM PST 24
Finished Jan 10 12:42:49 PM PST 24
Peak memory 200672 kb
Host smart-11550f59-8a38-425f-8e88-749a1640ff09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653618948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3653618948
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.1514123974
Short name T4
Test name
Test status
Simulation time 395665553 ps
CPU time 1.97 seconds
Started Jan 10 12:41:36 PM PST 24
Finished Jan 10 12:42:45 PM PST 24
Peak memory 200636 kb
Host smart-3f8e5643-79e9-4c8d-90a3-0c2a2845fce5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514123974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.1514123974
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.2395032393
Short name T951
Test name
Test status
Simulation time 153392156 ps
CPU time 1.14 seconds
Started Jan 10 12:41:54 PM PST 24
Finished Jan 10 12:43:05 PM PST 24
Peak memory 200532 kb
Host smart-c3a527ac-8960-467d-8565-bb80dd14f475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395032393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.2395032393
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.1272056140
Short name T414
Test name
Test status
Simulation time 1407954355 ps
CPU time 10.58 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:43:06 PM PST 24
Peak memory 200928 kb
Host smart-24ebce8c-ec49-4fa2-a4b7-3df6a375bbfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272056140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.1272056140
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.1905206378
Short name T10
Test name
Test status
Simulation time 22689695454 ps
CPU time 360.31 seconds
Started Jan 10 12:41:40 PM PST 24
Finished Jan 10 12:48:46 PM PST 24
Peak memory 216048 kb
Host smart-96c9ee7d-26a1-4a61-bea1-e827ad15d156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1905206378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1905206378
Directory /workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.clkmgr_trans.2544153831
Short name T106
Test name
Test status
Simulation time 38444449 ps
CPU time 1.01 seconds
Started Jan 10 12:41:54 PM PST 24
Finished Jan 10 12:43:04 PM PST 24
Peak memory 200652 kb
Host smart-4cefb39b-263e-4777-b2aa-9c6e8f3851df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544153831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2544153831
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.1945656452
Short name T961
Test name
Test status
Simulation time 14067349 ps
CPU time 0.75 seconds
Started Jan 10 12:41:45 PM PST 24
Finished Jan 10 12:42:53 PM PST 24
Peak memory 200768 kb
Host smart-c56f7e9b-4428-441c-a323-627ed08585a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945656452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.1945656452
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.2242670214
Short name T897
Test name
Test status
Simulation time 42349436 ps
CPU time 0.93 seconds
Started Jan 10 12:41:52 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200620 kb
Host smart-c57c4421-2828-4789-adf9-c96842b55b97
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242670214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.2242670214
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.1940460027
Short name T476
Test name
Test status
Simulation time 14477976 ps
CPU time 0.66 seconds
Started Jan 10 12:41:46 PM PST 24
Finished Jan 10 12:42:56 PM PST 24
Peak memory 199472 kb
Host smart-21a2d737-db4a-4eae-bee4-8fa3b3b702fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940460027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.1940460027
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.4219585277
Short name T465
Test name
Test status
Simulation time 18627388 ps
CPU time 0.77 seconds
Started Jan 10 12:41:50 PM PST 24
Finished Jan 10 12:43:01 PM PST 24
Peak memory 200672 kb
Host smart-6c7e7b5d-4a70-46cc-ae78-6e09bae9874f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219585277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.4219585277
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.1115509909
Short name T452
Test name
Test status
Simulation time 58235136 ps
CPU time 0.84 seconds
Started Jan 10 12:41:38 PM PST 24
Finished Jan 10 12:42:44 PM PST 24
Peak memory 200528 kb
Host smart-66fbb753-08b5-4219-bbf1-57365423b0ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115509909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.1115509909
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.1256488566
Short name T711
Test name
Test status
Simulation time 2144285990 ps
CPU time 8.02 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:43:06 PM PST 24
Peak memory 201168 kb
Host smart-814871dc-3958-4d5a-b29b-8b58dc95a7e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256488566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.1256488566
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.4136454612
Short name T421
Test name
Test status
Simulation time 1126047526 ps
CPU time 4.21 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200680 kb
Host smart-df192a36-e17c-4819-9afa-8ce632eb4591
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136454612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.4136454612
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.3865700072
Short name T502
Test name
Test status
Simulation time 13845270 ps
CPU time 0.71 seconds
Started Jan 10 12:41:46 PM PST 24
Finished Jan 10 12:42:54 PM PST 24
Peak memory 200580 kb
Host smart-20209def-a5f9-4bca-9fe9-4590e57fbdfb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865700072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.3865700072
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.2276890595
Short name T493
Test name
Test status
Simulation time 39745652 ps
CPU time 0.75 seconds
Started Jan 10 12:41:44 PM PST 24
Finished Jan 10 12:42:52 PM PST 24
Peak memory 200568 kb
Host smart-b9a8b5fa-9fd4-4d21-aa1a-66ffd14e45ea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276890595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.2276890595
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.100554947
Short name T950
Test name
Test status
Simulation time 15867983 ps
CPU time 0.73 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200596 kb
Host smart-29f407d8-b207-45f9-94ac-5e5bf42bcb30
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100554947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.clkmgr_lc_ctrl_intersig_mubi.100554947
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.3853088089
Short name T842
Test name
Test status
Simulation time 24050236 ps
CPU time 0.8 seconds
Started Jan 10 12:41:52 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200520 kb
Host smart-6446708c-7189-46de-bd5e-54bc8ecdf912
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853088089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.3853088089
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.3673916871
Short name T781
Test name
Test status
Simulation time 1111958877 ps
CPU time 4.1 seconds
Started Jan 10 12:41:50 PM PST 24
Finished Jan 10 12:43:05 PM PST 24
Peak memory 200812 kb
Host smart-be09e52c-5235-4146-9100-cb8ce07d8207
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673916871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.3673916871
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.691784826
Short name T809
Test name
Test status
Simulation time 17829376 ps
CPU time 0.82 seconds
Started Jan 10 12:41:44 PM PST 24
Finished Jan 10 12:42:52 PM PST 24
Peak memory 200788 kb
Host smart-65ea64a6-37f4-482b-ba80-c15d4a87540a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691784826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.691784826
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.1832700776
Short name T556
Test name
Test status
Simulation time 6845871773 ps
CPU time 27.41 seconds
Started Jan 10 12:41:39 PM PST 24
Finished Jan 10 12:43:12 PM PST 24
Peak memory 200580 kb
Host smart-fc98568e-6be7-42c4-b19a-d33581783808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832700776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.1832700776
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.2063162662
Short name T542
Test name
Test status
Simulation time 103038408 ps
CPU time 1.11 seconds
Started Jan 10 12:41:53 PM PST 24
Finished Jan 10 12:43:04 PM PST 24
Peak memory 200588 kb
Host smart-66037ce7-54d2-4e2c-91ac-3e40571ddf46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063162662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.2063162662
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.3627494816
Short name T562
Test name
Test status
Simulation time 109935252 ps
CPU time 1 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200564 kb
Host smart-98e68f73-5447-4a79-a8f4-d1660b5bebdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627494816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.3627494816
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.2714077873
Short name T672
Test name
Test status
Simulation time 58875775 ps
CPU time 0.88 seconds
Started Jan 10 12:41:43 PM PST 24
Finished Jan 10 12:42:49 PM PST 24
Peak memory 200796 kb
Host smart-b068a6ba-0290-4319-9eea-922162737b1a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714077873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.2714077873
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.1008751794
Short name T553
Test name
Test status
Simulation time 14934486 ps
CPU time 0.7 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:57 PM PST 24
Peak memory 199564 kb
Host smart-338a6e80-ea8f-45a6-9671-46e374c6f0bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008751794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1008751794
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.2170283518
Short name T561
Test name
Test status
Simulation time 34769510 ps
CPU time 0.81 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:42:59 PM PST 24
Peak memory 200580 kb
Host smart-9369c509-0c01-456b-940f-d08cd602fe87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170283518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.2170283518
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.832264155
Short name T463
Test name
Test status
Simulation time 85946745 ps
CPU time 1.03 seconds
Started Jan 10 12:41:39 PM PST 24
Finished Jan 10 12:42:46 PM PST 24
Peak memory 200160 kb
Host smart-bf6269b4-f180-4064-b4b7-d5ba5392c8ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832264155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.832264155
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.3310713493
Short name T13
Test name
Test status
Simulation time 807478328 ps
CPU time 5.07 seconds
Started Jan 10 12:41:39 PM PST 24
Finished Jan 10 12:42:50 PM PST 24
Peak memory 200796 kb
Host smart-096da7db-20de-40e2-84fa-26855f77b6e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310713493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3310713493
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.1002512164
Short name T890
Test name
Test status
Simulation time 289481677 ps
CPU time 1.56 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 199748 kb
Host smart-d3538ad4-724c-4ee6-b47f-d9f2c3438e7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002512164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.1002512164
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2633761380
Short name T331
Test name
Test status
Simulation time 25449754 ps
CPU time 0.82 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200588 kb
Host smart-16b02f5f-97fd-45e7-94be-53ef3062cccb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633761380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.2633761380
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1697266610
Short name T657
Test name
Test status
Simulation time 16501996 ps
CPU time 0.75 seconds
Started Jan 10 12:41:54 PM PST 24
Finished Jan 10 12:43:04 PM PST 24
Peak memory 200668 kb
Host smart-51e068ff-2bfa-43b8-88fe-edded3560946
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697266610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1697266610
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.1745618857
Short name T709
Test name
Test status
Simulation time 20840276 ps
CPU time 0.77 seconds
Started Jan 10 12:41:54 PM PST 24
Finished Jan 10 12:43:05 PM PST 24
Peak memory 200600 kb
Host smart-a0530751-5e5d-4423-b610-b5d0f8082207
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745618857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.1745618857
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.2543433080
Short name T291
Test name
Test status
Simulation time 27432371 ps
CPU time 0.74 seconds
Started Jan 10 12:41:41 PM PST 24
Finished Jan 10 12:42:49 PM PST 24
Peak memory 200596 kb
Host smart-833c2712-829e-4200-99e0-65f948b7e755
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543433080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.2543433080
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.1739477336
Short name T759
Test name
Test status
Simulation time 804446208 ps
CPU time 3.19 seconds
Started Jan 10 12:41:52 PM PST 24
Finished Jan 10 12:43:04 PM PST 24
Peak memory 200792 kb
Host smart-a59ee105-d960-442b-bc35-849476c9aba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739477336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.1739477336
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.1227133092
Short name T887
Test name
Test status
Simulation time 51491881 ps
CPU time 0.89 seconds
Started Jan 10 12:41:44 PM PST 24
Finished Jan 10 12:42:52 PM PST 24
Peak memory 200760 kb
Host smart-e8505a52-3482-4175-961b-fc04587f2ca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227133092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.1227133092
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.1796701029
Short name T996
Test name
Test status
Simulation time 6863210524 ps
CPU time 50.13 seconds
Started Jan 10 12:41:40 PM PST 24
Finished Jan 10 12:43:36 PM PST 24
Peak memory 201020 kb
Host smart-270fa1ca-9397-40b5-bc59-15d7daa38360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796701029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.1796701029
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.609327520
Short name T837
Test name
Test status
Simulation time 24573182557 ps
CPU time 350.15 seconds
Started Jan 10 12:41:50 PM PST 24
Finished Jan 10 12:48:49 PM PST 24
Peak memory 209228 kb
Host smart-067a4ec5-066a-4658-908d-9617a549c356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=609327520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.609327520
Directory /workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.clkmgr_trans.2688740795
Short name T412
Test name
Test status
Simulation time 105317357 ps
CPU time 1.16 seconds
Started Jan 10 12:41:45 PM PST 24
Finished Jan 10 12:42:54 PM PST 24
Peak memory 200732 kb
Host smart-cb2736a4-dca6-4c83-8fa0-91764764b392
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688740795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.2688740795
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.820848995
Short name T315
Test name
Test status
Simulation time 25299838 ps
CPU time 0.78 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200776 kb
Host smart-77943917-6e24-4cf1-9137-9393d92696c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820848995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkm
gr_alert_test.820848995
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.680616106
Short name T868
Test name
Test status
Simulation time 31100187 ps
CPU time 0.88 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200840 kb
Host smart-279afc45-d144-40c4-a700-050e5f1f47bf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680616106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.680616106
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.1134058617
Short name T134
Test name
Test status
Simulation time 11642868 ps
CPU time 0.67 seconds
Started Jan 10 12:41:52 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200528 kb
Host smart-388ffd1f-ec7e-4b30-abff-31d0cfc76625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134058617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1134058617
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.734540062
Short name T796
Test name
Test status
Simulation time 155171441 ps
CPU time 1.24 seconds
Started Jan 10 12:41:45 PM PST 24
Finished Jan 10 12:42:54 PM PST 24
Peak memory 200672 kb
Host smart-6c1304eb-8a2e-4258-a33a-7b09f82cff04
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734540062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_div_intersig_mubi.734540062
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.416326264
Short name T907
Test name
Test status
Simulation time 98226180 ps
CPU time 1 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200484 kb
Host smart-052ad27f-60e1-4a44-baa0-1121a57f9a3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416326264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.416326264
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.4249178493
Short name T978
Test name
Test status
Simulation time 2239539919 ps
CPU time 14.78 seconds
Started Jan 10 12:41:45 PM PST 24
Finished Jan 10 12:43:07 PM PST 24
Peak memory 201004 kb
Host smart-4dfacffd-6cfa-400e-8138-1febf88f2398
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249178493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.4249178493
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.2367067270
Short name T710
Test name
Test status
Simulation time 975177905 ps
CPU time 7.09 seconds
Started Jan 10 12:41:51 PM PST 24
Finished Jan 10 12:43:08 PM PST 24
Peak memory 200884 kb
Host smart-3d933154-f6b3-4241-a547-d08b240c0a9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367067270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.2367067270
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1606819148
Short name T152
Test name
Test status
Simulation time 24130192 ps
CPU time 0.89 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:42:57 PM PST 24
Peak memory 200612 kb
Host smart-240273a8-3acc-4cf9-a61c-094b1a50c752
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606819148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.1606819148
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3850754892
Short name T742
Test name
Test status
Simulation time 36349121 ps
CPU time 0.9 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:42:56 PM PST 24
Peak memory 200692 kb
Host smart-f2b09a21-afc3-48d1-80be-1e471983de33
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850754892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.3850754892
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.278814364
Short name T16
Test name
Test status
Simulation time 14620800 ps
CPU time 0.77 seconds
Started Jan 10 12:41:45 PM PST 24
Finished Jan 10 12:42:53 PM PST 24
Peak memory 200700 kb
Host smart-4f148141-777b-40fa-af0c-10e34bf5379a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278814364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.clkmgr_lc_ctrl_intersig_mubi.278814364
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.471218183
Short name T62
Test name
Test status
Simulation time 14072422 ps
CPU time 0.7 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:42:56 PM PST 24
Peak memory 200488 kb
Host smart-49cb7da3-f7fa-4c3c-88ed-f5b42d4d75b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471218183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.471218183
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.224029183
Short name T454
Test name
Test status
Simulation time 1533282969 ps
CPU time 5.71 seconds
Started Jan 10 12:41:53 PM PST 24
Finished Jan 10 12:43:07 PM PST 24
Peak memory 201040 kb
Host smart-613cd98f-9170-459f-bb62-738e37169664
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224029183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.224029183
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.1061940140
Short name T623
Test name
Test status
Simulation time 23482167 ps
CPU time 0.85 seconds
Started Jan 10 12:41:56 PM PST 24
Finished Jan 10 12:43:08 PM PST 24
Peak memory 200704 kb
Host smart-644eea9c-4100-4965-9539-deaa587eeb5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061940140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.1061940140
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.1895963892
Short name T676
Test name
Test status
Simulation time 6251689378 ps
CPU time 21.73 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:43:19 PM PST 24
Peak memory 201044 kb
Host smart-fc3bcab2-2df2-4209-8ac9-34bffd3b9f28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895963892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.1895963892
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.789115913
Short name T43
Test name
Test status
Simulation time 56672632840 ps
CPU time 983.65 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:59:19 PM PST 24
Peak memory 209196 kb
Host smart-ea5240dc-5a30-4eaa-a692-975f420f5090
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=789115913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.789115913
Directory /workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.clkmgr_trans.511730500
Short name T332
Test name
Test status
Simulation time 74495341 ps
CPU time 1.11 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200776 kb
Host smart-99afd9fa-5440-4b6c-8c7e-52e6737c1cd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511730500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.511730500
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.3580019821
Short name T398
Test name
Test status
Simulation time 57673546 ps
CPU time 0.94 seconds
Started Jan 10 12:41:57 PM PST 24
Finished Jan 10 12:43:09 PM PST 24
Peak memory 200816 kb
Host smart-ba542496-c8d4-4e21-bdab-88f43675f390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580019821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.3580019821
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3178647566
Short name T995
Test name
Test status
Simulation time 13049233 ps
CPU time 0.71 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:42:59 PM PST 24
Peak memory 200692 kb
Host smart-49f82e03-437a-4b0a-ae55-50ccb47bc199
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178647566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.3178647566
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.71637448
Short name T856
Test name
Test status
Simulation time 12864122 ps
CPU time 0.73 seconds
Started Jan 10 12:41:51 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 199544 kb
Host smart-e36dd8a9-a673-4f21-a70c-c60098936d5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71637448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.71637448
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.1698508616
Short name T967
Test name
Test status
Simulation time 39274478 ps
CPU time 0.87 seconds
Started Jan 10 12:41:44 PM PST 24
Finished Jan 10 12:42:52 PM PST 24
Peak memory 200596 kb
Host smart-3cab9435-863b-4970-aeb8-e4ee70ba8aa7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698508616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.1698508616
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.697385517
Short name T447
Test name
Test status
Simulation time 22030538 ps
CPU time 0.82 seconds
Started Jan 10 12:41:43 PM PST 24
Finished Jan 10 12:42:50 PM PST 24
Peak memory 200784 kb
Host smart-fbc384d8-a5a1-4e16-885c-ece12a25a8de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697385517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.697385517
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.1628161067
Short name T975
Test name
Test status
Simulation time 316689122 ps
CPU time 3.01 seconds
Started Jan 10 12:41:45 PM PST 24
Finished Jan 10 12:42:55 PM PST 24
Peak memory 200832 kb
Host smart-6c578732-8ba8-43bd-be43-20d9385b4d55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628161067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.1628161067
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.1249487459
Short name T665
Test name
Test status
Simulation time 2196610862 ps
CPU time 8.48 seconds
Started Jan 10 12:41:57 PM PST 24
Finished Jan 10 12:43:19 PM PST 24
Peak memory 201120 kb
Host smart-b06983f3-e1ae-4344-8a48-f444c869d489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249487459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.1249487459
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.669431079
Short name T432
Test name
Test status
Simulation time 45985066 ps
CPU time 0.95 seconds
Started Jan 10 12:41:51 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200600 kb
Host smart-6f9f5e39-884f-40cd-9705-5b278754f22f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669431079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_idle_intersig_mubi.669431079
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.505477679
Short name T549
Test name
Test status
Simulation time 23053500 ps
CPU time 0.86 seconds
Started Jan 10 12:41:50 PM PST 24
Finished Jan 10 12:43:01 PM PST 24
Peak memory 200780 kb
Host smart-26a80547-04df-4465-bc2e-6ab85484da6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505477679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.clkmgr_lc_clk_byp_req_intersig_mubi.505477679
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.1911903849
Short name T373
Test name
Test status
Simulation time 46368817 ps
CPU time 0.97 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:58 PM PST 24
Peak memory 200656 kb
Host smart-a12c898d-a04f-4577-8287-af3f8e83d1da
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911903849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.1911903849
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.2224365085
Short name T328
Test name
Test status
Simulation time 43293856 ps
CPU time 0.79 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:42:56 PM PST 24
Peak memory 200540 kb
Host smart-d8da3554-5273-408a-8ef9-786f34b83e42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224365085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.2224365085
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.1068935567
Short name T903
Test name
Test status
Simulation time 46068806 ps
CPU time 1 seconds
Started Jan 10 12:41:50 PM PST 24
Finished Jan 10 12:43:01 PM PST 24
Peak memory 200676 kb
Host smart-62ade17e-d3fa-419e-93d3-908aeda5f8cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068935567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.1068935567
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.2303413413
Short name T293
Test name
Test status
Simulation time 37976258 ps
CPU time 0.89 seconds
Started Jan 10 12:41:50 PM PST 24
Finished Jan 10 12:42:59 PM PST 24
Peak memory 200756 kb
Host smart-f2e94c26-746d-4bbb-9f89-045f4dcf0115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303413413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.2303413413
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.2819772266
Short name T686
Test name
Test status
Simulation time 174986212 ps
CPU time 2.01 seconds
Started Jan 10 12:41:51 PM PST 24
Finished Jan 10 12:43:03 PM PST 24
Peak memory 200836 kb
Host smart-48dce65c-c810-4a5e-b7ff-b58e0323c8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819772266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.2819772266
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.1623887874
Short name T987
Test name
Test status
Simulation time 53050758284 ps
CPU time 820.28 seconds
Started Jan 10 12:41:46 PM PST 24
Finished Jan 10 12:56:35 PM PST 24
Peak memory 217436 kb
Host smart-2e322497-8f70-4ab6-896a-38be7b58ec2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1623887874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.1623887874
Directory /workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.clkmgr_trans.2880820272
Short name T316
Test name
Test status
Simulation time 26804022 ps
CPU time 0.84 seconds
Started Jan 10 12:41:52 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200740 kb
Host smart-7049581d-ceb1-466c-b650-4e156fdcb25e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880820272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.2880820272
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.2566010314
Short name T595
Test name
Test status
Simulation time 41295718 ps
CPU time 0.8 seconds
Started Jan 10 12:41:56 PM PST 24
Finished Jan 10 12:43:08 PM PST 24
Peak memory 200840 kb
Host smart-419c72ad-b2ca-498c-a878-648672a6ea75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566010314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.2566010314
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2522381221
Short name T811
Test name
Test status
Simulation time 39867839 ps
CPU time 0.78 seconds
Started Jan 10 12:41:52 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200800 kb
Host smart-5374c10c-2cce-48a8-adc3-ce2c3825b2ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522381221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.2522381221
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.500305282
Short name T604
Test name
Test status
Simulation time 11758535 ps
CPU time 0.67 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:42:57 PM PST 24
Peak memory 200680 kb
Host smart-841a8021-0cf7-4017-81b1-7c256d8715aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500305282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.500305282
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.1643784443
Short name T640
Test name
Test status
Simulation time 94095331 ps
CPU time 0.96 seconds
Started Jan 10 12:42:05 PM PST 24
Finished Jan 10 12:43:19 PM PST 24
Peak memory 200796 kb
Host smart-93f012bd-2407-4082-8349-b98577f44e26
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643784443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.1643784443
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.3758562572
Short name T583
Test name
Test status
Simulation time 71111081 ps
CPU time 0.9 seconds
Started Jan 10 12:41:45 PM PST 24
Finished Jan 10 12:42:54 PM PST 24
Peak memory 200672 kb
Host smart-88e9f151-f19e-4fc4-b626-905f97c4e69a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758562572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.3758562572
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.789410563
Short name T492
Test name
Test status
Simulation time 813199974 ps
CPU time 4.8 seconds
Started Jan 10 12:41:51 PM PST 24
Finished Jan 10 12:43:06 PM PST 24
Peak memory 200704 kb
Host smart-0727957e-365d-460a-bf3a-0bd9670923c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789410563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.789410563
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.2384543282
Short name T286
Test name
Test status
Simulation time 139791171 ps
CPU time 1.53 seconds
Started Jan 10 12:41:47 PM PST 24
Finished Jan 10 12:42:57 PM PST 24
Peak memory 200852 kb
Host smart-c8aa3cf6-312d-4ac2-8282-be22b82d258f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384543282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.2384543282
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.2471727287
Short name T847
Test name
Test status
Simulation time 57826496 ps
CPU time 0.97 seconds
Started Jan 10 12:41:45 PM PST 24
Finished Jan 10 12:42:53 PM PST 24
Peak memory 200632 kb
Host smart-7c55ce54-7e46-4d4c-863d-4809cf888dc1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471727287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.2471727287
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.963737148
Short name T393
Test name
Test status
Simulation time 36959657 ps
CPU time 0.85 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:42:59 PM PST 24
Peak memory 200604 kb
Host smart-7eb89295-9217-4888-aa0f-927c58492498
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963737148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.clkmgr_lc_clk_byp_req_intersig_mubi.963737148
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1361744422
Short name T104
Test name
Test status
Simulation time 105967999 ps
CPU time 1.1 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:43:00 PM PST 24
Peak memory 200840 kb
Host smart-a221a3d2-ac38-465a-8a3f-77e599544d74
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361744422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.1361744422
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.454664736
Short name T922
Test name
Test status
Simulation time 35965225 ps
CPU time 0.76 seconds
Started Jan 10 12:41:51 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200616 kb
Host smart-57d693a0-217b-441d-9e55-1e881c021af0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454664736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.454664736
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.863484397
Short name T7
Test name
Test status
Simulation time 1080265501 ps
CPU time 5.9 seconds
Started Jan 10 12:41:58 PM PST 24
Finished Jan 10 12:43:16 PM PST 24
Peak memory 200976 kb
Host smart-37ef14fd-40bb-4a78-b0aa-4ae0c4aa02dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863484397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.863484397
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.2049023743
Short name T319
Test name
Test status
Simulation time 19854560 ps
CPU time 0.85 seconds
Started Jan 10 12:41:44 PM PST 24
Finished Jan 10 12:42:52 PM PST 24
Peak memory 200948 kb
Host smart-3537a6a4-619b-4106-a26f-5fcb9502cb97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049023743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2049023743
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.3106158057
Short name T594
Test name
Test status
Simulation time 4526395022 ps
CPU time 30.68 seconds
Started Jan 10 12:42:03 PM PST 24
Finished Jan 10 12:43:46 PM PST 24
Peak memory 201008 kb
Host smart-d11829c4-4c82-4f09-819f-4dd074ff844e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106158057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.3106158057
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.1314473066
Short name T707
Test name
Test status
Simulation time 17277811144 ps
CPU time 240.01 seconds
Started Jan 10 12:41:52 PM PST 24
Finished Jan 10 12:47:01 PM PST 24
Peak memory 215560 kb
Host smart-33c147ec-faea-452e-a1aa-7c1227bfc5d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1314473066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.1314473066
Directory /workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.clkmgr_trans.1728717201
Short name T483
Test name
Test status
Simulation time 275855015 ps
CPU time 1.52 seconds
Started Jan 10 12:41:44 PM PST 24
Finished Jan 10 12:42:52 PM PST 24
Peak memory 200592 kb
Host smart-27d70b6a-6b5a-4b0d-b815-5820925cb995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728717201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.1728717201
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.1069363326
Short name T768
Test name
Test status
Simulation time 48086053 ps
CPU time 0.81 seconds
Started Jan 10 12:41:55 PM PST 24
Finished Jan 10 12:43:07 PM PST 24
Peak memory 200664 kb
Host smart-9fbb99df-b3a5-4be6-b97a-2fa4dda314f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069363326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.1069363326
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.1062249456
Short name T357
Test name
Test status
Simulation time 23787306 ps
CPU time 0.76 seconds
Started Jan 10 12:41:53 PM PST 24
Finished Jan 10 12:43:04 PM PST 24
Peak memory 200600 kb
Host smart-fed52b47-6274-4442-b1f8-918d23c083ee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062249456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.1062249456
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.3258566837
Short name T487
Test name
Test status
Simulation time 36382512 ps
CPU time 0.78 seconds
Started Jan 10 12:42:09 PM PST 24
Finished Jan 10 12:43:23 PM PST 24
Peak memory 199528 kb
Host smart-d3b65f65-e8b9-437a-a96a-5619c40c0031
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258566837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.3258566837
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2998934967
Short name T901
Test name
Test status
Simulation time 43886369 ps
CPU time 0.87 seconds
Started Jan 10 12:41:58 PM PST 24
Finished Jan 10 12:43:12 PM PST 24
Peak memory 200644 kb
Host smart-0f47a70c-4443-486e-a559-0da443a4e217
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998934967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.2998934967
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.435618311
Short name T383
Test name
Test status
Simulation time 15960510 ps
CPU time 0.76 seconds
Started Jan 10 12:41:58 PM PST 24
Finished Jan 10 12:43:11 PM PST 24
Peak memory 200640 kb
Host smart-dca348b7-ff37-41fd-908d-5bdb626b2407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435618311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.435618311
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.2932293599
Short name T635
Test name
Test status
Simulation time 2396144180 ps
CPU time 9.97 seconds
Started Jan 10 12:41:59 PM PST 24
Finished Jan 10 12:43:22 PM PST 24
Peak memory 201068 kb
Host smart-4ec8e976-4ddc-410f-a2c3-fcae2b43b15a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932293599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.2932293599
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.896994302
Short name T932
Test name
Test status
Simulation time 140123101 ps
CPU time 1.6 seconds
Started Jan 10 12:41:55 PM PST 24
Finished Jan 10 12:43:07 PM PST 24
Peak memory 200888 kb
Host smart-4ccd4a1d-3e26-40cc-a9b5-bd4ae1b96c97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896994302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_ti
meout.896994302
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.2865791142
Short name T605
Test name
Test status
Simulation time 21106618 ps
CPU time 0.72 seconds
Started Jan 10 12:41:53 PM PST 24
Finished Jan 10 12:43:02 PM PST 24
Peak memory 200756 kb
Host smart-a5aafeb0-2f40-4510-a27a-d4c3036f2611
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865791142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.2865791142
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3905835298
Short name T715
Test name
Test status
Simulation time 71786970 ps
CPU time 0.93 seconds
Started Jan 10 12:42:09 PM PST 24
Finished Jan 10 12:43:23 PM PST 24
Peak memory 200664 kb
Host smart-184af461-9951-4426-bc75-ea438034a3bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905835298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.3905835298
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2545822988
Short name T972
Test name
Test status
Simulation time 29611677 ps
CPU time 0.89 seconds
Started Jan 10 12:42:01 PM PST 24
Finished Jan 10 12:43:16 PM PST 24
Peak memory 200712 kb
Host smart-8d32aa4d-63c7-4dac-9437-c91453d3f511
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545822988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.2545822988
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.308371972
Short name T325
Test name
Test status
Simulation time 11737354 ps
CPU time 0.69 seconds
Started Jan 10 12:42:09 PM PST 24
Finished Jan 10 12:43:23 PM PST 24
Peak memory 200516 kb
Host smart-5c370090-78e1-41e4-9ab7-afd792b0144e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308371972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.308371972
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.2908360015
Short name T818
Test name
Test status
Simulation time 1218572613 ps
CPU time 5.57 seconds
Started Jan 10 12:41:53 PM PST 24
Finished Jan 10 12:43:07 PM PST 24
Peak memory 200972 kb
Host smart-a5d0a4eb-19fa-4379-9410-e565adea9153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908360015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.2908360015
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.749318283
Short name T518
Test name
Test status
Simulation time 63599655 ps
CPU time 0.95 seconds
Started Jan 10 12:41:59 PM PST 24
Finished Jan 10 12:43:13 PM PST 24
Peak memory 200660 kb
Host smart-d07bf448-c1b7-4532-89d7-d08adaeb912a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749318283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.749318283
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.980014579
Short name T576
Test name
Test status
Simulation time 1332657706 ps
CPU time 10.77 seconds
Started Jan 10 12:41:54 PM PST 24
Finished Jan 10 12:43:14 PM PST 24
Peak memory 200924 kb
Host smart-20820776-b45a-4933-aa5a-fa95260c22f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980014579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.980014579
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.1577963002
Short name T497
Test name
Test status
Simulation time 55450364223 ps
CPU time 846.34 seconds
Started Jan 10 12:41:54 PM PST 24
Finished Jan 10 12:57:10 PM PST 24
Peak memory 209268 kb
Host smart-81e9f988-e437-4d5f-a45c-8acd31972af5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1577963002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.1577963002
Directory /workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.clkmgr_trans.3607199015
Short name T504
Test name
Test status
Simulation time 53729548 ps
CPU time 0.87 seconds
Started Jan 10 12:41:54 PM PST 24
Finished Jan 10 12:43:05 PM PST 24
Peak memory 200752 kb
Host smart-1fce030f-8327-4551-ba39-ee4454bfabab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607199015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3607199015
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.2666683980
Short name T952
Test name
Test status
Simulation time 32861477 ps
CPU time 0.81 seconds
Started Jan 10 12:40:09 PM PST 24
Finished Jan 10 12:40:57 PM PST 24
Peak memory 200692 kb
Host smart-aaad76fb-eac2-4b23-90ec-ce7a86b656ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666683980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.2666683980
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.2983940853
Short name T941
Test name
Test status
Simulation time 33439974 ps
CPU time 0.86 seconds
Started Jan 10 12:39:57 PM PST 24
Finished Jan 10 12:40:36 PM PST 24
Peak memory 200756 kb
Host smart-3c0f1b74-96e1-43a1-a03f-518750aec994
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983940853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.2983940853
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.3530916361
Short name T524
Test name
Test status
Simulation time 44624315 ps
CPU time 0.81 seconds
Started Jan 10 12:40:10 PM PST 24
Finished Jan 10 12:40:57 PM PST 24
Peak memory 199580 kb
Host smart-b7aaba7b-cedc-40ba-99d9-a8088ad08260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530916361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.3530916361
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.2539560197
Short name T389
Test name
Test status
Simulation time 20174289 ps
CPU time 0.73 seconds
Started Jan 10 12:39:48 PM PST 24
Finished Jan 10 12:40:21 PM PST 24
Peak memory 200692 kb
Host smart-39192421-c680-4d9b-addb-5de5046ba932
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539560197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.2539560197
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.2615520037
Short name T525
Test name
Test status
Simulation time 106540818 ps
CPU time 1.12 seconds
Started Jan 10 12:39:52 PM PST 24
Finished Jan 10 12:40:27 PM PST 24
Peak memory 200600 kb
Host smart-8be57220-869d-4052-b59d-f43ffaa75589
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615520037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.2615520037
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.2912726616
Short name T515
Test name
Test status
Simulation time 2241989550 ps
CPU time 17.27 seconds
Started Jan 10 12:40:03 PM PST 24
Finished Jan 10 12:41:04 PM PST 24
Peak memory 200880 kb
Host smart-79f02009-8efe-4b3e-9f41-0799ba557519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912726616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2912726616
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.2021548523
Short name T22
Test name
Test status
Simulation time 641982645 ps
CPU time 2.99 seconds
Started Jan 10 12:40:02 PM PST 24
Finished Jan 10 12:40:48 PM PST 24
Peak memory 200720 kb
Host smart-c0139bb5-f151-430e-aa6f-a3531eb1b451
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021548523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.2021548523
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.4180671548
Short name T872
Test name
Test status
Simulation time 22556379 ps
CPU time 0.84 seconds
Started Jan 10 12:39:50 PM PST 24
Finished Jan 10 12:40:24 PM PST 24
Peak memory 200688 kb
Host smart-cdff2428-7bb6-4e91-b3ff-f28f5f68cf8d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180671548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.4180671548
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.354246810
Short name T352
Test name
Test status
Simulation time 34867796 ps
CPU time 0.77 seconds
Started Jan 10 12:39:50 PM PST 24
Finished Jan 10 12:40:23 PM PST 24
Peak memory 200768 kb
Host smart-db901eb8-749c-4d9f-a71b-b2242c75388c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354246810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_clk_byp_req_intersig_mubi.354246810
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.1984658198
Short name T516
Test name
Test status
Simulation time 58713912 ps
CPU time 1.04 seconds
Started Jan 10 12:39:50 PM PST 24
Finished Jan 10 12:40:25 PM PST 24
Peak memory 200692 kb
Host smart-98624021-99cd-4991-b1c4-d3ff7d6896a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984658198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.1984658198
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.2147457820
Short name T663
Test name
Test status
Simulation time 42414471 ps
CPU time 0.79 seconds
Started Jan 10 12:39:52 PM PST 24
Finished Jan 10 12:40:28 PM PST 24
Peak memory 200700 kb
Host smart-baba6863-91cd-4f77-8bfe-7dc2e669744a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147457820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.2147457820
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.2721423957
Short name T339
Test name
Test status
Simulation time 1608772790 ps
CPU time 5.69 seconds
Started Jan 10 12:39:51 PM PST 24
Finished Jan 10 12:40:30 PM PST 24
Peak memory 200928 kb
Host smart-ea2c32ba-c841-4a7b-aa5f-0aad27f9159e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721423957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.2721423957
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.2387800966
Short name T27
Test name
Test status
Simulation time 23939383 ps
CPU time 0.93 seconds
Started Jan 10 12:39:51 PM PST 24
Finished Jan 10 12:40:26 PM PST 24
Peak memory 200740 kb
Host smart-202d6b62-970f-4cb3-86da-8097910ec414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387800966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2387800966
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.3034205705
Short name T627
Test name
Test status
Simulation time 2199757222 ps
CPU time 9.18 seconds
Started Jan 10 12:39:52 PM PST 24
Finished Jan 10 12:40:35 PM PST 24
Peak memory 201112 kb
Host smart-fc9755df-8a4e-408f-b96a-53b671e22b6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034205705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.3034205705
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.1358684095
Short name T731
Test name
Test status
Simulation time 29738269713 ps
CPU time 528.89 seconds
Started Jan 10 12:40:10 PM PST 24
Finished Jan 10 12:49:45 PM PST 24
Peak memory 217440 kb
Host smart-5489b430-8842-4b9f-a1a0-5f7f29b1b050
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1358684095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.1358684095
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.clkmgr_trans.3956275532
Short name T892
Test name
Test status
Simulation time 75979816 ps
CPU time 1.17 seconds
Started Jan 10 12:39:55 PM PST 24
Finished Jan 10 12:40:33 PM PST 24
Peak memory 200772 kb
Host smart-285dcdfc-8cf5-4c14-bf57-3f8b5b8c2b47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956275532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.3956275532
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.3959237847
Short name T639
Test name
Test status
Simulation time 157751558 ps
CPU time 1.11 seconds
Started Jan 10 12:40:02 PM PST 24
Finished Jan 10 12:40:46 PM PST 24
Peak memory 200584 kb
Host smart-62b3697e-d3be-424c-a295-9548a99f094c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959237847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.3959237847
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.765675893
Short name T370
Test name
Test status
Simulation time 25073177 ps
CPU time 0.89 seconds
Started Jan 10 12:39:57 PM PST 24
Finished Jan 10 12:40:37 PM PST 24
Peak memory 200712 kb
Host smart-a44eec51-f2d4-4c41-8de5-26f02470d07a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765675893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.765675893
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.149239206
Short name T611
Test name
Test status
Simulation time 25308181 ps
CPU time 0.8 seconds
Started Jan 10 12:40:10 PM PST 24
Finished Jan 10 12:40:57 PM PST 24
Peak memory 200576 kb
Host smart-bb8cd5e7-52cc-40e2-8594-ab17602f79b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149239206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.149239206
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3336630204
Short name T552
Test name
Test status
Simulation time 23833079 ps
CPU time 0.79 seconds
Started Jan 10 12:40:10 PM PST 24
Finished Jan 10 12:40:57 PM PST 24
Peak memory 200684 kb
Host smart-227c10be-cc91-43dc-9d09-7163c15b6b7e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336630204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.3336630204
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.2721474263
Short name T658
Test name
Test status
Simulation time 20685804 ps
CPU time 0.78 seconds
Started Jan 10 12:40:02 PM PST 24
Finished Jan 10 12:40:45 PM PST 24
Peak memory 200528 kb
Host smart-03fee7f6-8d86-4048-8441-00ce8ad594b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721474263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2721474263
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.1853958579
Short name T539
Test name
Test status
Simulation time 1896178203 ps
CPU time 8.59 seconds
Started Jan 10 12:39:55 PM PST 24
Finished Jan 10 12:40:41 PM PST 24
Peak memory 200952 kb
Host smart-67c11de9-f319-4ed0-b998-dfc6385cdbaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853958579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.1853958579
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.1874892475
Short name T324
Test name
Test status
Simulation time 757861485 ps
CPU time 3.39 seconds
Started Jan 10 12:39:55 PM PST 24
Finished Jan 10 12:40:35 PM PST 24
Peak memory 200876 kb
Host smart-fb2004e0-722e-45a9-91c5-20a7cea96349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874892475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.1874892475
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1492992404
Short name T902
Test name
Test status
Simulation time 83544278 ps
CPU time 1.15 seconds
Started Jan 10 12:40:01 PM PST 24
Finished Jan 10 12:40:44 PM PST 24
Peak memory 200732 kb
Host smart-0010d5ae-e77d-4c81-895a-00c2f00b7d58
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492992404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.1492992404
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.4071437530
Short name T729
Test name
Test status
Simulation time 33676339 ps
CPU time 0.75 seconds
Started Jan 10 12:39:50 PM PST 24
Finished Jan 10 12:40:25 PM PST 24
Peak memory 200704 kb
Host smart-4f7c86e1-871b-4150-8f70-1a46add045c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071437530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.4071437530
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.1626502481
Short name T60
Test name
Test status
Simulation time 17458158 ps
CPU time 0.77 seconds
Started Jan 10 12:40:02 PM PST 24
Finished Jan 10 12:40:46 PM PST 24
Peak memory 200632 kb
Host smart-a5315226-d929-491f-9531-df6b9c667513
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626502481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.1626502481
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.1950255309
Short name T510
Test name
Test status
Simulation time 25603435 ps
CPU time 0.74 seconds
Started Jan 10 12:39:50 PM PST 24
Finished Jan 10 12:40:24 PM PST 24
Peak memory 200528 kb
Host smart-525e9f72-2156-4d5f-9f03-279ebd11215c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950255309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1950255309
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.4067628365
Short name T31
Test name
Test status
Simulation time 323452953 ps
CPU time 1.9 seconds
Started Jan 10 12:39:47 PM PST 24
Finished Jan 10 12:40:20 PM PST 24
Peak memory 200644 kb
Host smart-70ba0ec5-4bbf-4b89-b70f-e46a609ac8ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067628365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.4067628365
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.3370090130
Short name T593
Test name
Test status
Simulation time 25594789 ps
CPU time 0.91 seconds
Started Jan 10 12:39:48 PM PST 24
Finished Jan 10 12:40:20 PM PST 24
Peak memory 200704 kb
Host smart-2b2ab262-87f4-416b-8bb4-ff695486d4ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370090130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.3370090130
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.3849525873
Short name T418
Test name
Test status
Simulation time 5862193921 ps
CPU time 30.11 seconds
Started Jan 10 12:40:01 PM PST 24
Finished Jan 10 12:41:13 PM PST 24
Peak memory 200976 kb
Host smart-eae73c36-4300-475f-a9a6-d0d85cb7b572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849525873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.3849525873
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.2093083841
Short name T643
Test name
Test status
Simulation time 110870498383 ps
CPU time 728.85 seconds
Started Jan 10 12:40:02 PM PST 24
Finished Jan 10 12:52:54 PM PST 24
Peak memory 213388 kb
Host smart-3d3bb2c0-43ce-460e-bbe1-b00603a9af2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2093083841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.2093083841
Directory /workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.clkmgr_trans.346757137
Short name T908
Test name
Test status
Simulation time 17867323 ps
CPU time 0.79 seconds
Started Jan 10 12:39:48 PM PST 24
Finished Jan 10 12:40:21 PM PST 24
Peak memory 200760 kb
Host smart-d7b9012b-3fb9-4a55-aa92-97e7bc59ab9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346757137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.346757137
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.3782790416
Short name T631
Test name
Test status
Simulation time 44598130 ps
CPU time 0.87 seconds
Started Jan 10 12:39:57 PM PST 24
Finished Jan 10 12:40:36 PM PST 24
Peak memory 200720 kb
Host smart-879a5014-bfab-4c14-be1d-052c13013dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782790416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.3782790416
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1610723040
Short name T654
Test name
Test status
Simulation time 34762906 ps
CPU time 0.89 seconds
Started Jan 10 12:39:54 PM PST 24
Finished Jan 10 12:40:30 PM PST 24
Peak memory 200684 kb
Host smart-3f68046d-bb5e-4cd5-b264-263b8d68d716
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610723040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.1610723040
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.358515402
Short name T475
Test name
Test status
Simulation time 26425456 ps
CPU time 0.7 seconds
Started Jan 10 12:39:58 PM PST 24
Finished Jan 10 12:40:37 PM PST 24
Peak memory 199476 kb
Host smart-c4758c11-3ebb-44a0-ad86-f6fd0dc4cd25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358515402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.358515402
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.760979652
Short name T853
Test name
Test status
Simulation time 14466696 ps
CPU time 0.73 seconds
Started Jan 10 12:39:54 PM PST 24
Finished Jan 10 12:40:32 PM PST 24
Peak memory 200780 kb
Host smart-f838036a-e0b3-44e4-8d94-6ddb311920be
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760979652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.clkmgr_div_intersig_mubi.760979652
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.2473279527
Short name T21
Test name
Test status
Simulation time 50041588 ps
CPU time 0.84 seconds
Started Jan 10 12:40:01 PM PST 24
Finished Jan 10 12:40:44 PM PST 24
Peak memory 200500 kb
Host smart-0d03f33b-4255-4406-87cb-072a3995684b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473279527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.2473279527
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.429977060
Short name T109
Test name
Test status
Simulation time 2474967115 ps
CPU time 17.94 seconds
Started Jan 10 12:40:00 PM PST 24
Finished Jan 10 12:41:00 PM PST 24
Peak memory 200452 kb
Host smart-29ab64cd-35fe-48fb-aff1-f841231fe09a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429977060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.429977060
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.325103500
Short name T29
Test name
Test status
Simulation time 1341175467 ps
CPU time 9.62 seconds
Started Jan 10 12:40:00 PM PST 24
Finished Jan 10 12:40:52 PM PST 24
Peak memory 200284 kb
Host smart-ad5bf0e0-db1d-40f4-b42d-37a3d20bbeb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325103500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_tim
eout.325103500
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.304379332
Short name T338
Test name
Test status
Simulation time 34122875 ps
CPU time 1.01 seconds
Started Jan 10 12:39:55 PM PST 24
Finished Jan 10 12:40:34 PM PST 24
Peak memory 200800 kb
Host smart-a69b8912-0a99-4447-ae78-83c2bd1823dd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304379332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.clkmgr_idle_intersig_mubi.304379332
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.3773352433
Short name T395
Test name
Test status
Simulation time 29651534 ps
CPU time 0.76 seconds
Started Jan 10 12:39:56 PM PST 24
Finished Jan 10 12:40:34 PM PST 24
Peak memory 200636 kb
Host smart-a431c54d-af76-4fdc-9783-b91a37754767
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773352433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.3773352433
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.2309956152
Short name T616
Test name
Test status
Simulation time 19445732 ps
CPU time 0.79 seconds
Started Jan 10 12:40:11 PM PST 24
Finished Jan 10 12:40:59 PM PST 24
Peak memory 200444 kb
Host smart-f9c7432f-4b09-468b-a923-5a668d5c2f00
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309956152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.2309956152
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.2512280729
Short name T859
Test name
Test status
Simulation time 64389956 ps
CPU time 0.86 seconds
Started Jan 10 12:39:54 PM PST 24
Finished Jan 10 12:40:32 PM PST 24
Peak memory 200516 kb
Host smart-66260e51-db09-4c42-aaac-8d962d46f5cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512280729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.2512280729
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.1925989896
Short name T750
Test name
Test status
Simulation time 555730335 ps
CPU time 2.73 seconds
Started Jan 10 12:39:57 PM PST 24
Finished Jan 10 12:40:37 PM PST 24
Peak memory 200640 kb
Host smart-ed15584f-a7d9-4a3f-909d-d037c9168d54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925989896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.1925989896
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.1374529417
Short name T443
Test name
Test status
Simulation time 39295185 ps
CPU time 0.84 seconds
Started Jan 10 12:40:03 PM PST 24
Finished Jan 10 12:40:47 PM PST 24
Peak memory 200652 kb
Host smart-e675df21-aa74-42d0-afa3-cacd6ed7651f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374529417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.1374529417
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.549785527
Short name T825
Test name
Test status
Simulation time 3161691460 ps
CPU time 23.86 seconds
Started Jan 10 12:39:54 PM PST 24
Finished Jan 10 12:40:55 PM PST 24
Peak memory 200992 kb
Host smart-dad54e71-a25e-406f-89d6-45c227453ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549785527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.549785527
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.411212530
Short name T536
Test name
Test status
Simulation time 22380145708 ps
CPU time 188.44 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:43:57 PM PST 24
Peak memory 215288 kb
Host smart-8bd3d44c-c354-4352-9747-84e174d724ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=411212530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.411212530
Directory /workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.clkmgr_trans.2556411434
Short name T281
Test name
Test status
Simulation time 54191747 ps
CPU time 0.87 seconds
Started Jan 10 12:39:54 PM PST 24
Finished Jan 10 12:40:32 PM PST 24
Peak memory 200704 kb
Host smart-e24ee95e-9fe3-4793-8a6d-6d166b1f6f37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556411434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2556411434
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.2818939349
Short name T863
Test name
Test status
Simulation time 55106593 ps
CPU time 0.88 seconds
Started Jan 10 12:39:55 PM PST 24
Finished Jan 10 12:40:33 PM PST 24
Peak memory 200752 kb
Host smart-3ec59f35-756c-44fe-8111-bfd15d09672d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818939349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.2818939349
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.1317846389
Short name T780
Test name
Test status
Simulation time 28762201 ps
CPU time 0.88 seconds
Started Jan 10 12:39:56 PM PST 24
Finished Jan 10 12:40:37 PM PST 24
Peak memory 200692 kb
Host smart-0b6c710e-10d2-471a-9625-128f7887678e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317846389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.1317846389
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.2006809889
Short name T138
Test name
Test status
Simulation time 11260280 ps
CPU time 0.69 seconds
Started Jan 10 12:39:56 PM PST 24
Finished Jan 10 12:40:37 PM PST 24
Peak memory 199596 kb
Host smart-b878ecba-f630-4bea-baa4-5b496c3d4ae3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006809889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.2006809889
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.4011038971
Short name T917
Test name
Test status
Simulation time 76008139 ps
CPU time 0.94 seconds
Started Jan 10 12:39:54 PM PST 24
Finished Jan 10 12:40:32 PM PST 24
Peak memory 200780 kb
Host smart-89a4edd8-5e23-438a-b531-962020ce8e57
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011038971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.4011038971
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.2209027218
Short name T390
Test name
Test status
Simulation time 26702275 ps
CPU time 0.83 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:40:48 PM PST 24
Peak memory 200584 kb
Host smart-b783517c-144e-4909-ae60-67c562c04978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209027218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.2209027218
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.2770003146
Short name T820
Test name
Test status
Simulation time 2473790716 ps
CPU time 18.96 seconds
Started Jan 10 12:39:58 PM PST 24
Finished Jan 10 12:40:55 PM PST 24
Peak memory 200856 kb
Host smart-4f933019-2043-4500-89d7-6a600ccda91c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770003146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.2770003146
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.1619619735
Short name T795
Test name
Test status
Simulation time 979299046 ps
CPU time 7.16 seconds
Started Jan 10 12:39:58 PM PST 24
Finished Jan 10 12:40:43 PM PST 24
Peak memory 200692 kb
Host smart-ec026946-60b0-496c-af93-63dd32c355fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619619735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.1619619735
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.3898252065
Short name T153
Test name
Test status
Simulation time 198781047 ps
CPU time 1.41 seconds
Started Jan 10 12:40:11 PM PST 24
Finished Jan 10 12:40:59 PM PST 24
Peak memory 200416 kb
Host smart-21190824-7a6e-4bc8-a94e-0c26a619f8e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898252065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.3898252065
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1134333822
Short name T101
Test name
Test status
Simulation time 36493691 ps
CPU time 0.85 seconds
Started Jan 10 12:39:57 PM PST 24
Finished Jan 10 12:40:35 PM PST 24
Peak memory 200700 kb
Host smart-f81eb63b-7689-4762-a572-e78fe4a26f6d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134333822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.1134333822
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.3705413677
Short name T387
Test name
Test status
Simulation time 34052284 ps
CPU time 0.81 seconds
Started Jan 10 12:40:03 PM PST 24
Finished Jan 10 12:40:48 PM PST 24
Peak memory 200660 kb
Host smart-cfa02b70-a18d-4c5d-a782-6ad770bc1b0a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705413677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.3705413677
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.2142784964
Short name T659
Test name
Test status
Simulation time 36260337 ps
CPU time 0.77 seconds
Started Jan 10 12:39:57 PM PST 24
Finished Jan 10 12:40:36 PM PST 24
Peak memory 200500 kb
Host smart-85b51b60-8bad-45b2-a3e7-b2ed67f31957
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142784964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.2142784964
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.501228170
Short name T372
Test name
Test status
Simulation time 128027728 ps
CPU time 1.27 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:40:50 PM PST 24
Peak memory 200584 kb
Host smart-4f11f28b-bb22-45a0-9350-77b58b5f4b9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501228170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.501228170
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.2625403872
Short name T770
Test name
Test status
Simulation time 15527747 ps
CPU time 0.78 seconds
Started Jan 10 12:39:56 PM PST 24
Finished Jan 10 12:40:35 PM PST 24
Peak memory 200644 kb
Host smart-ad4457e0-efde-455e-910e-8c8bb7428841
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625403872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.2625403872
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.1714044244
Short name T544
Test name
Test status
Simulation time 2379310503 ps
CPU time 13.19 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:41:01 PM PST 24
Peak memory 200872 kb
Host smart-1191e83e-e2a8-4072-9e9a-4bfbf9498fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714044244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.1714044244
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.1785182577
Short name T680
Test name
Test status
Simulation time 89891450380 ps
CPU time 759.74 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:53:27 PM PST 24
Peak memory 209228 kb
Host smart-c2f9f7c9-e3d6-4f49-92ef-c68bff551ab5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1785182577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.1785182577
Directory /workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.clkmgr_trans.95239041
Short name T650
Test name
Test status
Simulation time 116240308 ps
CPU time 1.25 seconds
Started Jan 10 12:39:56 PM PST 24
Finished Jan 10 12:40:35 PM PST 24
Peak memory 200696 kb
Host smart-79f50c8c-9b3f-49f4-b033-5bd1ee40e071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95239041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.95239041
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.1977353202
Short name T806
Test name
Test status
Simulation time 54728205 ps
CPU time 0.86 seconds
Started Jan 10 12:40:03 PM PST 24
Finished Jan 10 12:40:48 PM PST 24
Peak memory 200716 kb
Host smart-68a02eb2-ee7f-42b9-a2a3-0c55a5f94929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977353202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.1977353202
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.1874964222
Short name T960
Test name
Test status
Simulation time 152117480 ps
CPU time 1.16 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:40:49 PM PST 24
Peak memory 200716 kb
Host smart-5fa4baed-1738-4eb5-a699-2b4db2d5d681
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874964222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.1874964222
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.970484031
Short name T425
Test name
Test status
Simulation time 16118262 ps
CPU time 0.68 seconds
Started Jan 10 12:40:03 PM PST 24
Finished Jan 10 12:40:47 PM PST 24
Peak memory 199560 kb
Host smart-19a89c0c-7850-4c32-bdc7-a643e312203a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970484031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.970484031
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.1029709001
Short name T991
Test name
Test status
Simulation time 32821003 ps
CPU time 0.85 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:40:53 PM PST 24
Peak memory 200760 kb
Host smart-82632033-4e1e-4b97-9d19-76a776a1459a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029709001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.1029709001
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.2427573915
Short name T606
Test name
Test status
Simulation time 95047846 ps
CPU time 0.93 seconds
Started Jan 10 12:39:56 PM PST 24
Finished Jan 10 12:40:35 PM PST 24
Peak memory 200536 kb
Host smart-4dda2d80-3769-4642-a30f-7aa0c150532b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427573915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.2427573915
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.106207098
Short name T23
Test name
Test status
Simulation time 1287007547 ps
CPU time 7.49 seconds
Started Jan 10 12:39:57 PM PST 24
Finished Jan 10 12:40:42 PM PST 24
Peak memory 200780 kb
Host smart-bc743d89-9bf6-4fa8-9f5a-c78815a18035
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106207098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.106207098
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.636418605
Short name T618
Test name
Test status
Simulation time 1825805474 ps
CPU time 9.77 seconds
Started Jan 10 12:39:53 PM PST 24
Finished Jan 10 12:40:38 PM PST 24
Peak memory 200824 kb
Host smart-63f777f8-3f68-4cbb-8240-9cee91985ac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636418605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_tim
eout.636418605
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.2123422596
Short name T528
Test name
Test status
Simulation time 25422096 ps
CPU time 0.75 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:40:49 PM PST 24
Peak memory 200752 kb
Host smart-d200f4c8-2d5a-47e1-854f-68c6654c84d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123422596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.2123422596
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1827559081
Short name T567
Test name
Test status
Simulation time 24045099 ps
CPU time 0.88 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:40:48 PM PST 24
Peak memory 200696 kb
Host smart-23e22d99-c4a6-43da-a2b1-8be6f8399f99
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827559081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.1827559081
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.1938696682
Short name T411
Test name
Test status
Simulation time 18935378 ps
CPU time 0.81 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:40:52 PM PST 24
Peak memory 200720 kb
Host smart-d4f07c25-afd0-4aeb-bf15-86c5378c8e13
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938696682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.1938696682
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.2699390202
Short name T376
Test name
Test status
Simulation time 43785799 ps
CPU time 0.77 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:40:52 PM PST 24
Peak memory 200620 kb
Host smart-4d61fee5-ae44-478d-b3fb-cb2592ef9b5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699390202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.2699390202
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.1164424826
Short name T660
Test name
Test status
Simulation time 672973581 ps
CPU time 3.53 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:40:54 PM PST 24
Peak memory 200736 kb
Host smart-aebab690-0fd9-4f39-8f4a-e911bb907667
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164424826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1164424826
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.1272441748
Short name T577
Test name
Test status
Simulation time 109750083 ps
CPU time 1.09 seconds
Started Jan 10 12:40:11 PM PST 24
Finished Jan 10 12:40:59 PM PST 24
Peak memory 200648 kb
Host smart-253ac678-87c9-48c3-bfb8-f13905507714
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272441748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1272441748
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.3548521747
Short name T652
Test name
Test status
Simulation time 6853372522 ps
CPU time 51.49 seconds
Started Jan 10 12:40:02 PM PST 24
Finished Jan 10 12:41:37 PM PST 24
Peak memory 201116 kb
Host smart-da42cbf4-8fc2-4427-844e-8aa54a469ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548521747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.3548521747
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.2926014946
Short name T827
Test name
Test status
Simulation time 102345773158 ps
CPU time 763.25 seconds
Started Jan 10 12:40:04 PM PST 24
Finished Jan 10 12:53:32 PM PST 24
Peak memory 213716 kb
Host smart-b348b621-96ba-4685-82be-ed647449389e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2926014946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.2926014946
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.2476727809
Short name T348
Test name
Test status
Simulation time 14429095 ps
CPU time 0.68 seconds
Started Jan 10 12:40:16 PM PST 24
Finished Jan 10 12:41:04 PM PST 24
Peak memory 200660 kb
Host smart-693e1c73-95ef-490a-9c8e-1c2ddcac3839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476727809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.2476727809
Directory /workspace/9.clkmgr_trans/latest
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