Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286217678 1 T6 9970 T7 2060 T8 3618
auto[1] 401086 1 T6 142 T8 788 T1 2338


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286224960 1 T6 9876 T7 2060 T8 3730
auto[1] 393804 1 T6 236 T8 676 T1 1826


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286097958 1 T6 9782 T7 2060 T8 3468
auto[1] 520806 1 T6 330 T8 938 T1 2668


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 272435082 1 T6 8344 T7 2060 T8 328
auto[1] 14183682 1 T6 1768 T8 4078 T1 9328


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 170250884 1 T6 7324 T7 408 T8 1724
auto[1] 116367880 1 T6 2788 T7 1652 T8 2682


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 156850238 1 T6 5510 T7 408 T8 192
auto[0] auto[0] auto[0] auto[0] auto[1] 115242022 1 T6 2650 T7 1652 T33 24
auto[0] auto[0] auto[0] auto[1] auto[0] 27300 1 T1 114 T22 48 T111 20
auto[0] auto[0] auto[0] auto[1] auto[1] 8970 1 T6 4 T1 36 T3 4
auto[0] auto[0] auto[1] auto[0] auto[0] 12805104 1 T6 1608 T8 878 T1 5092
auto[0] auto[0] auto[1] auto[0] auto[1] 1012028 1 T8 2334 T1 1762 T22 98
auto[0] auto[0] auto[1] auto[1] auto[0] 55826 1 T6 10 T8 38 T1 296
auto[0] auto[0] auto[1] auto[1] auto[1] 13470 1 T8 18 T1 74 T110 62
auto[0] auto[1] auto[0] auto[0] auto[0] 29020 1 T1 132 T112 2 T11 2
auto[0] auto[1] auto[0] auto[0] auto[1] 2040 1 T3 2 T15 140 T16 16
auto[0] auto[1] auto[0] auto[1] auto[0] 11138 1 T1 72 T112 48 T11 38
auto[0] auto[1] auto[0] auto[1] auto[1] 3956 1 T3 42 T15 162 T26 62
auto[0] auto[1] auto[1] auto[0] auto[0] 10642 1 T8 8 T1 16 T22 34
auto[0] auto[1] auto[1] auto[0] auto[1] 2414 1 T1 48 T22 28 T11 2
auto[0] auto[1] auto[1] auto[1] auto[0] 20332 1 T1 106 T22 58 T3 108
auto[0] auto[1] auto[1] auto[1] auto[1] 3458 1 T11 60 T147 74 T16 60
auto[1] auto[0] auto[0] auto[0] auto[0] 64314 1 T6 46 T1 210 T22 60
auto[1] auto[0] auto[0] auto[0] auto[1] 3620 1 T6 48 T1 16 T3 20
auto[1] auto[0] auto[0] auto[1] auto[0] 29688 1 T1 178 T111 46 T3 220
auto[1] auto[0] auto[0] auto[1] auto[1] 8048 1 T1 90 T3 62 T13 66
auto[1] auto[0] auto[1] auto[0] auto[0] 30376 1 T8 52 T1 202 T22 54
auto[1] auto[0] auto[1] auto[0] auto[1] 8038 1 T8 14 T1 80 T110 34
auto[1] auto[0] auto[1] auto[1] auto[0] 53060 1 T8 168 T1 268 T22 368
auto[1] auto[0] auto[1] auto[1] auto[1] 12858 1 T8 36 T1 172 T113 104
auto[1] auto[1] auto[0] auto[0] auto[0] 93790 1 T8 34 T1 46 T22 46
auto[1] auto[1] auto[0] auto[0] auto[1] 5824 1 T6 16 T3 16 T114 22
auto[1] auto[1] auto[0] auto[1] auto[0] 44014 1 T8 102 T1 194 T22 240
auto[1] auto[1] auto[0] auto[1] auto[1] 11100 1 T6 70 T3 62 T148 64
auto[1] auto[1] auto[1] auto[0] auto[0] 46612 1 T6 92 T8 50 T1 394
auto[1] auto[1] auto[1] auto[0] auto[1] 11596 1 T8 56 T1 80 T110 32
auto[1] auto[1] auto[1] auto[1] auto[0] 79430 1 T6 58 T8 202 T1 682
auto[1] auto[1] auto[1] auto[1] auto[1] 18438 1 T8 224 T1 56 T111 44

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